Thick Bottom Oxide Growth in High Aspect Ratio Features

Abstract

The present disclosure relates generally to semiconductor device manufacturing, and more particularly to a method for forming a thick bottom oxide layer in a high aspect ratio semiconductor structure. In a particular embodiment, the method includes depositing a non-conformal oxide layer in a feature on a substrate, performing an oxidation process to thermally grow an oxide layer beneath the deposited non-conformal oxide layer in the feature, and selectively stripping the non-conformal oxide layer to expose the thermally grown oxide layer.

Description

[Technical Field]

[0001] TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to semiconductor device manufacturing, and more particularly to methods for forming thick bottom oxide layers in high aspect ratio semiconductor structures. [Background technology]

[0002] 2. Description of Related Art

[0002] In the production of silicon integrated circuits, challenging demands have been placed on the manufacturing process to increase the number of devices while shrinking the minimum feature size on a chip. These demands extend to manufacturing processes that involve depositing layers over challenging topologies while maintaining device reliability. As the number of vertically stacked memory cells in 3D NAND devices increases (e.g., as chip density increases), the aspect ratio of the memory cell strings also increases, creating numerous manufacturing challenges. For example, to help compensate for some of the common integration issues in the processing of 3D NAND devices with high aspect ratio features, it is desirable to form an oxide layer with a greater thickness near the bottom of the high aspect ratio features.

[0003]

[0003] Conventional methods for growing oxide layers on such high-aspect-ratio structures suffer from one or both of two problems. The first problem is the rapid and non-uniform consumption and depletion of oxygen radicals during thermal oxidation growth of high-aspect-ratio features. That is, oxide layers grown on high-aspect-ratio structures are typically thicker at the top because the oxidant flows and is consumed immediately from the top of the feature, thereby causing depletion before the oxidant flows and reaches the bottom of the feature. The second problem is the poor quality of the oxide layers formed by deposition, which may contain defects and traps, leading to reduced device reliability.

[0004]

[0004] Improved processes for growing thick bottom oxide layers in high aspect ratio features are needed because grown oxide layers are known to be of better quality than deposited oxide layers. Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure relate generally to semiconductor device manufacturing, and more particularly to a method for forming a thick bottom oxide layer in a high aspect ratio semiconductor structure. In some embodiments, a method is provided for forming an oxide layer suitable for use in semiconductor manufacturing. The method includes forming a non-conformal oxide layer on a substrate, performing an oxidation process to oxidize the substrate and grow a thermal oxide layer below the non-conformal oxide layer, and selectively removing the non-conformal oxide layer to expose the oxidized portion of the substrate.

[0006] In another embodiment, a method is provided for forming an oxide layer suitable for use in semiconductor manufacturing, the method including forming a non-conformal aluminum oxide layer on a substrate, performing an oxidation process to oxidize the substrate and grow a thermal oxide layer below the non-conformal aluminum oxide layer, and selectively removing the aluminum oxide layer to expose the oxidized portion of the substrate.

[0007] In a further embodiment, a method is provided for forming an oxide layer suitable for use in semiconductor manufacturing, the method including forming a non-conformal aluminum oxide layer on a silicon-containing substrate using a tunable deposition process, performing an oxidation process to oxidize the silicon-containing substrate and grow a thermal oxide layer below the non-conformal aluminum oxide layer, and performing a wet etching process to selectively remove the non-conformal aluminum oxide layer and expose the oxidized portion of the silicon-containing substrate.

[0008]

[0008] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, will be had by reference to embodiments. Some embodiments are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered to limit the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 4 is a schematic diagram of an exemplary process chamber that may be used to perform the method illustrated in FIG. 3, according to certain embodiments of the present disclosure. [Figure 1B]

[0010] 1B is a schematic cross-sectional view of an electrostatic chuck that can be used in the apparatus of FIG. 1A, according to certain embodiments of the present disclosure. [Figure 2]

[0011] FIG. 4 is a schematic diagram of another exemplary process chamber that may be used to implement the method illustrated in FIG. 3, according to certain embodiments of the present disclosure. [Figure 3]

[0012] FIG. 2 is a process flow diagram of a method for forming an oxide layer in a semiconductor structure, in accordance with certain embodiments of the present disclosure. [Figure 4A]

[0013] 4 is a cross-sectional view of an oxide layer formed by the method of FIG. 3 in accordance with certain embodiments of the present disclosure. [Figure 4B] 4 is a cross-sectional view of an oxide layer formed by the method of FIG. 3 in accordance with certain embodiments of the present disclosure. [Figure 4C] 4 is a cross-sectional view of an oxide layer formed by the method of FIG. 3 in accordance with certain embodiments of the present disclosure. [Figure 4D] 4 is a cross-sectional view of an oxide layer formed by the method of FIG. 3 in accordance with certain embodiments of the present disclosure. [Figure 5]

[0014] 1 is a graph showing the observed effect of deposited aluminum oxide on the thermal oxidation of silicon substrates. [Figure 6]

[0015] FIG. 2 is another process flow diagram of a method for forming a silicon oxide layer in a semiconductor structure, in accordance with certain embodiments of the present disclosure. [Figure 7]

[0016] 4 is a schematic top view of a multi-chamber processing system that can be used to perform the method shown in FIG. 3 according to certain embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0017] For ease of understanding, where possible, the same reference numerals have been used to designate identical elements that are common to multiple figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0011]

[0018]

[0001] Embodiments of the present disclosure generally relate to an apparatus and method for forming a thick bottom oxide layer in high aspect ratio features on a substrate. Specific details are set forth in the following description and figures to provide a thorough understanding of various embodiments of the present disclosure. Other details describing well-known methods and systems commonly associated with thin film deposition are not set forth in the following disclosure to avoid unnecessarily obscuring the description of the various embodiments.

[0012]

[0019] Many of the details, components, and other features described herein are illustrative of particular embodiments only. Thus, other embodiments may have other details, components, and features without departing from the spirit or scope of the present disclosure. In addition, further embodiments of the present disclosure may be practiced without some of the details described below.

[0013]

[0020] Other deposition chambers may also benefit from the present disclosure, and the parameters disclosed herein may vary depending on the particular deposition chamber used to form the oxide layers described herein. For example, other deposition chambers may have larger or smaller volumes that require higher or lower gas flow rates than those referenced for the deposition chambers available from Applied Materials.

[0014]

[0021] Embodiments of the present disclosure provide for forming a thick bottom oxide layer in high aspect ratio (HAR) features, such as 3D NAND pillars, without impacting the thermal budget. For an oxidation process to be performed to convert and grow an oxide layer on a substrate, an oxidant must diffuse through an existing oxide layer on the substrate to react with and oxidize the substrate atoms. Such an existing oxide layer on the substrate can act as a delay layer, slowing the oxidation rate of substrate atoms adjacent to the oxide layer through which the oxidant passes. For example, it has been observed that increasing the thickness of the oxide layer on the substrate slows the oxidation rate of substrate atoms adjacent to the oxide layer through which the oxidant must pass, because the distance the oxidant must pass increases. Therefore, by increasing the distance near the top of the HAR feature through which the oxidant must diffuse to oxidize the substrate, such as by providing a thicker oxide layer on the sidewall surfaces near the top of the HAR feature compared to the bottom of the HAR feature, the oxidation rate at the top of the HAR feature can be slowed, allowing a thick bottom oxide layer to grow within the HAR feature. It was also found that by increasing the thickness of the oxide layer near the bottom of the HAR feature, the oxidation rate at the bottom of the HAR feature was further increased, and a catalytic effect was observed that resulted in a thicker oxide layer growing near the bottom of the HAR feature than would otherwise have been formed.

[0015]

[0022] 1A is a schematic cross-sectional side view of an exemplary processing system 132 suitable for performing a deposition process in accordance with at least one embodiment of the present disclosure. A suitable chamber can be obtained from Applied Materials, Inc., located in Santa Clara, California. It should be understood that the system described below is an exemplary process chamber, and that other chambers, including chambers from other manufacturers, can be used with or modified to achieve embodiments of the present disclosure (e.g., method 300 described below). In some embodiments, processing system 132 can be configured to deposit a non-conformal film on a substrate using an atomic layer deposition (plasma-enhanced and / or thermal) process.

[0016]

[0023] The processing system 132 includes a process chamber 100 and a controller 110 coupled to a gas panel 130. The process chamber 100 generally includes a top wall 124, a sidewall 101, and a bottom wall 122, which define a processing space 126. A substrate support assembly 146 is disposed within the processing space 126 of the process chamber 100. The substrate support assembly 146 generally includes an electrostatic chuck 150 supported by a stem 160. The electrostatic chuck 150 may typically be fabricated from aluminum, ceramic, or other suitable materials. The electrostatic chuck 150 may be moved vertically within the process chamber 100 using a displacement mechanism (not shown).

[0017]

[0024] A vacuum pump 102 is connected to a port formed in the bottom of the process chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure within the process chamber 100. The vacuum pump 102 also evacuates post-treatment gases and process by-products from the process chamber 100.

[0018]

[0025] The substrate processing system 132 may further include additional chamber pressure control devices, such as valves (such as throttle valves and isolation valves), positioned between the process chamber 100 and the vacuum pump 102 to control the chamber pressure.

[0019]

[0026] A gas distribution assembly 120 having a plurality of apertures 128 is disposed at the top of the process chamber 100 above the electrostatic chuck 150. The apertures 128 of the gas distribution assembly 120 are utilized to introduce process or precursor gases into the process chamber 100. The apertures 128 may have various sizes, quantities, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for various process requirements. The gas distribution assembly 120 is connected to a gas panel 130, which enables the supply of various gases to the process space 126 during processing. A plasma is formed from the process gas mixture exiting the gas distribution assembly 120 to enhance the thermal decomposition of the process gases, resulting in the deposition of material on the surface 191 of the substrate 190.

[0020]

[0027] The gas distribution assembly 120 and the electrostatic chuck 150 may form a pair of spaced-apart electrodes within the process space 126. To facilitate plasma generation between the gas distribution assembly 120 and the electrostatic chuck 150, one or more RF power sources 140 provide a bias potential to the gas distribution assembly 120 through a matching network 138 (which is optional). Alternatively, the RF power sources 140 and the matching network 138 may be coupled to the gas distribution assembly 120, the electrostatic chuck 150, or both, or may be coupled to an antenna (not shown) located outside the process chamber 100. In some embodiments, the RF power sources 140 may generate power at frequencies of 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz. In one embodiment, the RF power sources 140 may provide power between about 100 Watts and about 3000 Watts at a frequency between about 50 kHz and about 13.6 MHz. In another embodiment, RF power source 140 may provide between about 500 watts and about 1800 watts at a frequency between about 50 kHz and about 13.6 MHz.

[0021]

[0028] The controller 110 includes a central processing unit (CPU) 112, memory 116, and support circuits 114, which are utilized to control process sequences and regulate gas flow from the gas panel 130. The CPU 112 may be any form of general-purpose computer processor available for use in an industrial setting. Software routines may be stored in the memory 116, for example, in random access memory, read-only memory, floppy or hard disk drives, or other forms of digital storage. The support circuits 114 are conventionally coupled to the CPU 112 and may include cache, clock circuits, input / output systems, power supplies, etc. Bidirectional communication between the controller 110 and the various components of the substrate processing system 132 is handled through a number of signal cables (collectively referred to as a signal bus 118, some of which are shown in FIG. 1A ).

[0022]

[0029] 1B shows a schematic cross-sectional view of a substrate support assembly 146 used in the processing system of FIG. 1A. Referring to FIG. 1B, an electrostatic chuck 150 may include a heater element 170 suitable for controlling the temperature of a substrate 190 supported on an upper surface 192 of the electrostatic chuck 150. The heater element 170 may be embedded in the electrostatic chuck 150. The electrostatic chuck 150 may be resistively heated by applying a current from a heater power supply 106 to the heater element 170. The heater power supply 106 may be coupled through an RF filter 158. The RF filter 158 may be used to protect the heater power supply 106 from RF energy. The heater element 170 may be made of nickel-chromium wire enclosed within a sheathed tube of a nickel-iron-chromium alloy (e.g., INCOLOY®). The current supplied by the heater power supply 106 is regulated by the controller 110 to control the heat generated by the heater element 170 and thus maintain the substrate 190 and electrostatic chuck 150 at a substantially constant temperature during film deposition. The current supplied can be adjusted to selectively control the temperature of the electrostatic chuck 150 from about −50° C. to about 600° C.

[0023]

[0030] 1A, in a conventional manner, a temperature sensor 172 (such as a thermocouple) may be embedded in the electrostatic chuck 150 to monitor the temperature of the electrostatic chuck 150. The measured temperature is used by the controller 110 to control the power supplied to the heater element 170 to maintain the substrate at a desired temperature.

[0024]

[0031] The electrostatic chuck 150 includes a chucking electrode 152, which may be a mesh of conductive material. The chucking electrode 152 may be embedded in the electrostatic chuck 150. The chucking electrode 152 is coupled to a chucking power supply 154 and, when energized, electrostatically clamps a substrate 190 to an upper surface 192 of the electrostatic chuck 150.

[0025]

[0032] The chuck electrode 152 may be configured as a monopolar or bipolar electrode, or may have another suitable configuration. The chuck electrode 152 may be coupled to a chuck power supply 154 through an RF filter 156. The chuck power supply 154 provides direct current (DC) power to electrostatically clamp the substrate 190 to the upper surface 192 of the electrostatic chuck 150. The RF filter 156 prevents RF power utilized to form the plasma within the process chamber 100 from damaging or causing electrical interference to electrical equipment outside the chamber. The electrostatic chuck 150 may be fabricated from a ceramic material such as AlN or Al2O3. Alternatively, the electrostatic chuck 150 may be fabricated from a polymer such as polyimide, polyetheretherketone (PEEK), or polyaryletherketone (PAEK).

[0026]

[0033] A power application system 162 is coupled to the substrate support assembly 146. The power application system 162 may include the heater power supply 106, the chuck power supply 154, a first radio frequency (RF) power supply 180, and a second RF power supply 182. Additionally, embodiments of the power application system 162 may include the controller 110, a sensor device 164 in communication with the controller 110, and both the first RF power supply 180 and the second RF power supply 182.

[0027]

[0034] The controller 110 can also be utilized to control a plasma from the processing gas by applying RF power from the first RF power source 180 and the second RF power source 182 to deposit a layer of material on the substrate 190.

[0028]

[0035] As described above, the electrostatic chuck 150 includes a chucking electrode 152, which in one embodiment functions to chuck the substrate 190 while also functioning as a first RF electrode. The electrostatic chuck 150 may also include a second RF electrode 166, which, in conjunction with the chucking electrode 152, may apply RF power to regulate the plasma. The first RF power source 180 may be coupled to the second RF electrode 166, while the second RF power source 182 may be coupled to the chuck electrode 152. A first matching network and a second matching network may be provided for the first RF power source 180 and the second RF power source 182, respectively. The second RF electrode 166 may be a solid metal plate of a conductive material as shown. Alternatively, the second RF electrode 166 may be a mesh of a conductive material.

[0029]

[0036] The first RF power source 180 and the second RF power source 182 can generate power at the same frequency or at different frequencies. In some embodiments, one or both of the first RF power source 180 and the second RF power source 182 can individually generate power at a frequency between about 350 KHz and about 100 MHz (e.g., 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz). In some embodiments, the first RF power source 180 can generate power at a frequency of 13.56 MHz, and the second RF power source 182 can generate power at a frequency of 2 MHz (or vice versa). The RF power from one or both of the first RF power source 180 and the second RF power source 182 can be varied to adjust the plasma. For example, the sensor device 164 can be used to monitor the RF energy from one or both of the first RF power source 180 and the second RF power source 182. Data from the sensor device 164 may be communicated to the controller 110 , which may be utilized to vary the power applied by the first RF power source 180 and the second RF power source 182 .

[0030]

[0037] Other deposition chambers may also benefit from the present disclosure, and the above parameters may vary depending on the particular deposition chamber used to form the amorphous carbon layer. For example, other deposition chambers may have larger or smaller volumes that require higher or lower gas flow rates than those referenced for the deposition chambers available from Applied Materials.

[0031]

[0038] 2 illustrates a process chamber 200, such as a rapid thermal processing (RTP) chamber with a remote plasma source, according to an embodiment. RTP chambers employ radiant heating, such as from incandescent lamps, or radiant energy, such as from a laser annealing system.

[0032]

[0039] The process chamber 200 includes a chamber body 201 that defines a processing space 210 in which a substrate 202 can be thermally processed. The substrate 202 is positioned on a substrate support 212, such as pins or a low-mass edge ring for rapid temperature ramp-up. An energy source 203 is configured to direct radiant energy 205 into the processing space 210. A sensor 208 is positioned at a location for measuring attributes of components within the internal chamber body 201. The sensor 208 is configured to measure the temperature of the substrate 202 by acquiring and measuring radiant energy from the substrate 202. The sensor 208 can be connected to a system controller 209, which can be used to adjust the energy source 203 according to measurements from the sensor 208.

[0033]

[0040] A remote plasma source (RPS) 220 is connected to the processing chamber 200. The RPS 220 employed herein is any suitable RPS capable of forming a remote plasma having at least oxygen. The RPS 220 is fluidly connected to the processing chamber 200 through a first tube 222. An oxygen gas source 226 is also fluidly connected to the RPS 220, such as a microwave, capacitive source, or an inductively coupled remote plasma source. Further embodiments may include an inert gas source 228 coupled to the RPS 220 to generate an oxygen / inert gas plasma that can be delivered to the processing space 210 of the processing chamber 200.

[0034]

[0041] A hydrogen gas source 224 is coupled to the processing chamber 200. The hydrogen gas source 224 delivers hydrogen gas via a second tube 232 to the processing space 210, where the hydrogen gas is activated by the oxygen plasma delivered from the RPS 220.

[0035]

[0042] Temperature control facilitates the formation of high quality silicon oxide. Thus, the process chamber 200 and / or components such as the substrate support 212 used in the embodiments described herein can be controlled to a temperature between about 500° C. and about 1100° C. by rapidly heating and cooling the substrate 202 within the process chamber 200.

[0036]

[0043] Figure 3 shows a flow diagram of a method 300 for forming an oxide layer on a substrate, according to certain embodiments. The processing method 300 described in Figure 3 corresponds to the manufacturing stages (described below) shown in Figures 4A-4D. Figures 4A-4D show cross-sectional views of a workpiece 400 having a substrate 402 with a device structure 408 formed thereon, at different stages of forming an oxide layer within features of the device structure 408 shown in method 300.

[0037]

[0044] Method 300 begins in step 302 by providing a workpiece having a substrate with features formed therein (e.g., workpiece 400 shown in FIG. 4A having substrate 402 with feature 406 formed therein). Workpiece 400 is positioned in a deposition process chamber, such as process chamber 100 shown in FIG. 1. Features 406 may include high aspect ratio features such as pillars, memory holes, vias, trenches, lines, contact holes, etc. Workpiece 400 shown in FIG. 4A includes substrate 402 having device structures 408 formed thereon. It is noted that device structures 408 may be used in three-dimensional (3D) flash memory applications, 3D NAND, DRAM applications, or other suitable applications involving high aspect ratios or other non-standard geometries.

[0038]

[0045] The workpiece 400 includes a silicon-containing layer 404 formed on a substrate 402. The layer 404 includes a feature 406 formed therein with a high aspect ratio (e.g., an aspect ratio greater than 1:1, for example, an aspect ratio greater than about 10:1, such as greater than about 20:1). The feature 406 may be formed into a device structure 408 having a sidewall 412 opposite a bottom surface 414. The feature 406 may form an open channel, exposing the underlying layer 404. In certain embodiments, the silicon-containing layer 404 may be a single silicon or silicon-containing layer, such as a microcrystalline silicon layer, a monocrystalline silicon layer, a doped polysilicon layer, a doped microcrystalline silicon layer, a doped monocrystalline silicon layer, or a silicon nitride layer. In certain embodiments, the silicon-containing layer 404 is a silicon (Si) layer on a silicon nitride (SiN) layer.

[0039]

[0046] In step 304, after transferring the workpiece 400 to a process chamber, a deposition process is performed to deposit a non-conformal oxide layer 416 on the sidewalls 412 of the feature 406, as shown in FIG. 4B. The non-conformal oxide layer 416 generally can slow the oxidation rate of the portion of the layer 404 in contact with the non-conformal oxide layer 416. However, as described further below, it has been observed that, depending on the thickness of the non-conformal oxide layer 416 formed, the non-conformal oxide layer 416 can also increase the oxidation rate of the portion of the sidewalls 412 in contact with the non-conformal oxide layer 416. The non-conformal oxide layer 416 can be deposited in the feature 406 using any suitable tunable deposition process and / or apparatus. For example, physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD) processes can be used to deposit the non-conformal oxide layer 416. Alternatively or additionally, a stand-alone apparatus or a cluster tool can be used to perform the selective atomic layer deposition (ALD) process. Exemplary apparatus that can be configured to perform the above processes include, for example, the OLYMPIA line of ALD apparatus available from Applied Materials.

[0040]

[0047] In certain embodiments, the nonconformal oxide layer 416 can comprise a material that is selectively removable compared to thermal silicon oxide (SiO) or thermal silicon oxynitride (SiN0). In certain embodiments, the nonconformal oxide layer 416 can comprise an aluminum oxide (AlO) layer. Portions of the nonconformal oxide layer 416 can have a thickness that varies within a range from about 0 Å to about 200 Å (e.g., from about 0 Å to about 100 Å, from about 100 Å to about 200 Å, from about 50 Å to about 150 Å, from about 10 Å to about 80 Å, and from about 20 Å to about 50 Å). As shown in FIG. 4B, the nonconformal oxide layer 416 can be deposited thicker on the sidewalls 412 near the substrate surface 411 and thinner near the bottom 414 of the feature 406. In certain embodiments, the portion of nonconformal oxide layer 416 on sidewall 412 near substrate surface 411 can be formed to have a thickness of about 30 Å to about 200 Å (e.g., about 40 Å to about 150 Å, e.g., about 50 Å to about 200 Å). In certain embodiments, the portion of nonconformal oxide layer 416 on sidewall 412 near bottom surface 414 can be formed to have a thickness of about 0 Å to about 50 Å (e.g., about 10 Å to about 30 Å, e.g., about 15 Å to about 20 Å). In one embodiment, nonconformal oxide layer 416 is a nonconformal aluminum oxide layer deposited on sidewall 412 by ALD, having a thickness that increases from about 20 Å near bottom surface 414 to about 50 Å near substrate surface 411.

[0041]

[0048] Deposition of the non-conformal oxide layer 416 on the sidewalls 412 as described above allows for subsequent growth of a thick bottom oxide layer on the sidewalls 412 within the feature 406 by slowing the consumption of oxidant and the oxidation rate in the portion of the sidewalls 412 near the substrate surface 411.

[0042]

[0049] Next, in step 306, the workpiece 400 may be transferred to a process chamber, such as process chamber 200 shown in FIG. 2, where an oxidation process may be performed to oxidize the substrate 402, including the sidewalls 412 of the feature 406, to form an oxide layer 418, as shown in FIG. 4C. The oxide layer 418 may be grown by performing an oxidation process by supplying an oxygen-containing gas or oxygen plasma to the feature 406, such that an oxidant can diffuse through the formed oxide layer 416 and react with the sidewalls 412 to form the oxide layer 418. Due to the non-conformal oxide layer 416 deposited on the sidewalls 412, portions of the sidewalls 412 may oxidize at different rates, such that the oxide layer 418 grows to varying thicknesses, such as being thicker at the bottom near the bottom surface 414. In certain embodiments, the portion of oxide layer 418 that is formed may have a thickness that varies within a range of about 40 Å to about 150 Å (e.g., about 40 Å to about 100 Å, about 100 Å to about 150 Å, 50 Å to about 80 Å, or about 80 Å to about 120 Å). In one embodiment, oxide layer 418 on sidewalls 412 is formed thicker at the bottom, with a thickness that decreases from about 100 Å near bottom surface 414 to about 40 Å near substrate surface 411.

[0043]

[0050] In certain embodiments, the oxidation process can be a thermal oxidation process, a radical plasma oxidation process, a plasma oxidation process, a surface oxidation process, or any suitable oxidation process. In one embodiment, the oxidation process is a thermal oxidation process carried out at a processing temperature of about 500°C to about 1000°C (e.g., about 700°C to about 900°C, e.g., about 800°C). In certain embodiments, the oxidation process is a thermal oxidation process carried out for about 3 minutes to about 120 minutes (e.g., about 3 minutes to about 60 minutes, e.g., about 50 minutes to about 100 minutes, e.g., about 5 minutes to about 20 minutes). In one embodiment, the oxidation process is a thermal oxidation process carried out for about 4 minutes.

[0044]

[0051] In certain embodiments, the oxidation process may be carried out in any suitable chamber configured for radical oxidation, also known as in-situ steam generation (ISSG), etc. Suitable oxidation chambers may include, but are not limited to, RTP process chamber 200 of FIG. 2, small batch high rate ramp thermal furnaces, thermal treatment chambers such as RADIANCE®, plasma immersion ion implantation (P3I), VANTAGE® RADOX™, VANTAGE® RADIANCE® Plus, CENTURA®, and RADOX™ chambers available from Applied Materials, Inc. of Santa Clara, Calif. An exemplary surface oxidation process, also referred to as a radical plasma oxidation process, can be performed using a variety of oxidizing chemistries and may include varying the concentration of a reducing gas, such as one or more of hydrogen (H), ammonia (NH), etc., in an oxidizing gas mixture that includes an oxidizing gas, such as one or more of oxygen (O), nitric oxide (NO), nitrous oxide (NO), etc., and optionally a non-reactive gas, such as one or more of nitrogen gas (N), helium (He), argon (Ar), neon (Ne), and xenon (Xe).

[0045]

[0052] After the oxide layer 418 is formed in step 308, a stripping process is performed that selectively removes the non-conformal oxide layer 416 and exposes the grown oxide layer 418 underneath. In certain embodiments, the non-conformal oxide layer 416 may be selectively removed by a wet etching process using an etching solution such as sulfuric acid, acetic acid, phosphoric acid, nitric acid, piranha solution, combinations thereof, or any suitable chemical etching solution that can selectively remove the non-conformal oxide layer 416 with minimal or no effect on the thermal oxide in the oxide layer 418.

[0046] Example

[0053] A study was conducted using two recipes for growing silicon oxide layers on silicon substrates. The first recipe grew a 50 Å silicon oxide layer on bare silicon substrates. The second recipe grew an 80 Å silicon oxide layer on bare silicon substrates. Each recipe involved performing a thermal oxidation process at approximately 800°C for approximately 4 minutes. The same recipe was then used to grow separate silicon oxide layers on the silicon substrates, when a 20 Å aluminum oxide layer was deposited on each silicon substrate. The same recipe was also used to grow separate silicon oxide layers on the silicon substrates, when a 50 Å aluminum oxide layer was deposited. The thickness of each grown thermal oxide layer was measured after stripping each aluminum oxide layer using a wet etching process using sulfuric acid. The basic method used was aluminum oxide deposition, a thermal oxidation process at approximately 800°C for approximately 4 minutes, and a wet-etch aluminum oxide strip using sulfuric acid to selectively remove the deposited aluminum oxide layer. The results were collected and are shown in the graph in Figure 5.

[0047]

[0054] Figure 5 shows the thickness of silicon oxide grown on silicon substrates using the two different recipes described above when varying the thickness of aluminum oxide: 0 Å (bare silicon substrate), 20 Å, and 50 Å were deposited on the substrate. The two curves show the measured thickness of the thermally grown silicon oxide layer for each of the two recipes used. The recipe used to grow a 50 Å silicon oxide layer on a bare silicon substrate resulted in a silicon oxide layer of approximately 65 Å when 20 Å of aluminum oxide was deposited on the silicon substrate, and a silicon oxide layer of approximately 40 Å when 50 Å of aluminum oxide was deposited. The recipe used to grow an 80 Å silicon oxide layer on a bare silicon substrate resulted in a silicon oxide layer of approximately 130 Å when 20 Å of aluminum oxide was deposited on the silicon substrate, and a silicon oxide layer of approximately 70 Å when 50 Å of aluminum oxide was deposited. In both examples, ellipsometer measurements of the silicon oxide layers grown after stripping off the respective aluminum oxide layers showed that a thinner silicon oxide layer was thermally grown when 50 Å of aluminum oxide was deposited on the substrate compared to when 0 Å and 20 Å of aluminum oxide were deposited.

[0048]

[0055] Without being bound by theory, a catalytic effect on the thermal oxidation of silicon substrates was observed when a 20 Å layer of aluminum oxide was deposited on a silicon substrate compared to 0 Å (bare silicon substrate). As shown in Figure 5, when 20 Å of aluminum oxide was deposited with both recipes, silicon oxide layers of 70 Å and 130 Å were grown, which were thicker than the 50 Å and 80 Å silicon oxide layers grown on bare silicon substrates, respectively.

[0049]

[0056] Thus, depositing a thin oxide layer 416 near the bottom 414 of the feature 406 in addition to depositing a relatively thick oxide layer 416 to slow oxidation on portions of the sidewalls 412 near the substrate surface 411 appears to increase the thickness of the oxide layer near the bottom 414 beyond what would otherwise have grown if the oxide layer 418 had only been deposited on portions of the sidewalls 412 near the substrate surface 411.

[0050]

[0057] 6 illustrates another flow diagram of a method 600 for growing a thick bottom oxide layer in a feature on a substrate, according to certain embodiments. The method 600 provides for growing a thick silicon oxide layer at the bottom of a high aspect ratio feature.

[0051]

[0058] In step 602, a substrate having a single silicon layer and a high aspect ratio feature formed thereon may be placed in a deposition process chamber, such as process chamber 100 shown in Figure 1. In step 604, a non-conformal ALD deposition process is performed to deposit a non-conformal aluminum oxide layer on each sidewall of the feature on the substrate. In particular embodiments, the non-conformal aluminum oxide layer deposited on the sidewalls may have a thickness that increases from about 20 Å near the bottom of the feature to about 50 Å near the opening of the feature and the substrate surface.

[0052]

[0059] In step 606, the substrate may be transferred to a thermal processing chamber, such as the RTP process chamber 200 of FIG. 2, where a thermal oxidation process may be performed to oxidize the substrate and the features formed thereon. The silicon oxide layer is formed when oxygen plasma within the feature diffuses through the aluminum oxide layer and reacts with the silicon on the sidewalls in the presence of heat. The thermal oxidation process may be performed at about 800° C. for about 4 minutes. The oxidation process may form a thick bottom silicon oxide layer beneath the aluminum oxide layer deposited on the sidewalls within the feature. In one embodiment, the thick bottom silicon oxide layer grown on the sidewalls has a thickness that decreases from about 100 Å near the bottom of the feature to about 40 Å at the top near the opening and at the substrate surface.

[0053]

[0060] After the thick bottom silicon oxide layer is grown on the sidewalls within the feature, a wet etching process is performed to selectively remove the aluminum oxide layer and expose the thermally grown silicon oxide layer in step 608. The wet etching process involves exposing the aluminum oxide layer of the feature to an etching solution, such as sulfuric acid, which can remove the aluminum oxide layer with minimal or no effect on the underlying thermally grown silicon oxide layer.

[0054]

[0061] 7 is a schematic top view of a multi-chamber processing system 700 that can be adapted to perform the metal layer deposition processes disclosed herein. In some embodiments, the system 700 can include one or more load lock chambers 722 for transferring workpieces 400 between a processing platform 704 and a factory interface 702. The processing platform 704 includes multiple processing chambers 710, 712, 728, 720, 732 and one or more load lock chambers 722 coupled to a vacuum substrate transfer chamber 736. Two load lock chambers 722 are shown in FIG. 7, and the factory interface 702 is coupled to the transfer chamber 736 via the two load lock chambers 722.

[0055]

[0062] Generally, the system 700 is maintained under vacuum, and one or more load lock chambers 722 may be "pumped down" to facilitate passage of the workpiece 400 between the substantially ambient environment of the factory interface 702 and the vacuum environment of the transfer chamber 736. Disposed within the transfer chamber 736 is a first robot 730. The first robot 730 has a blade 734 capable of transferring a substrate 724 (e.g., the workpiece 400) between the load lock chamber 722 and the processing chambers 710, 712, 728, 720, 732. Each processing chamber 710, 712, 728, 720, 732 may be configured to perform at least one of a substrate deposition process, such as cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, degassing, pre-cleaning, orientation, annealing, and other substrate processes. In one embodiment, processing chamber 710 can be used to perform the aluminum oxide deposition process described herein. The location of processing chamber 710 utilized to perform an atomic layer deposition (ALD) process relative to the other processing chambers 712, 728, 720, 732 is for illustrative purposes only, and the location of processing chamber 710 can optionally be interchanged with any of processing chambers 712, 728, 720, 732 as desired. After the aluminum oxide deposition process is performed in processing chamber 710, workpiece 400 can be further transferred to any of processing chambers 712, 728, 720, 732 of system 700 to perform other processes as needed.

[0056]

[0063] The first robot 730 can also transfer the workpiece 400 between the transfer chambers 722. The transfer chambers 722 and 724 can be used to enable transfer of the workpiece 400 within the system 700 while maintaining ultra-high vacuum conditions. In one or more embodiments, the factory interface 702 includes at least one docking station 708 and one or more second robots 714 to facilitate transfer of the workpiece 400. The docking station 708 is configured to receive one or more front-opening unified pods (FOUPs). In the embodiment of FIG. 7, two FOUPs 706A, 706B are shown. The second robot 714, having a blade 716 located at one end of the robot 714, is configured to transfer one or more substrates from the FOUPSs 706A, 706B through a load lock chamber 722 to the processing platform 704 for processing. The transferred substrates can be at least temporarily stored in the load lock chamber 722.

[0057]

[0064] The microprocessor controller 740 controls the operation of the system 700 using direct control of the process chambers 710, 712, 728, 720, 732 or by controlling a computer (or controller) associated with the process chambers 710, 712, 728, 720, 732 and the system 700. During operation, the microprocessor controller 740 enables data collection and feedback from each chamber and system to optimize the performance of the system 700. The microprocessor controller 740 generally includes a central processing unit (CPU) 738, memory 744, and support circuits 746. The CPU 738 may be one of any form of general-purpose computer processor that can be used in an industrial setting. The support circuits 746 are conventionally coupled to the CPU 738 and may include cache, clock circuits, input / output subsystems, power supplies, etc. Software routines (such as the methods described above) may be stored in the memory 742 and, when executed by the CPU 738, may transform the CPU 738 into a special-purpose computer (microprocessor controller) 740. The software routines may be stored and / or executed by a second controller (not shown) located remotely from the system 700 .

[0058]

[0065] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A method for forming an oxide layer suitable for use in semiconductor manufacturing, said method comprising: forming a non-conformal oxide layer on a substrate; performing an oxidation process to oxidize the substrate and grow a thermal oxide layer under the non-conformal oxide layer; selectively removing the non-conformal oxide layer to expose an oxidized portion of the substrate; A method comprising:

2. 10. The method of claim 1, wherein the substrate comprises a silicon or silicon nitride layer, the silicon or silicon nitride layer including a high aspect ratio feature having a pair of sidewalls defining an opening opposite a bottom surface.

3. 3. The method of claim 2, wherein the non-conformal oxide layer is formed on the sidewalls of the high aspect ratio feature with a thickness that decreases between the opening and the bottom surface, and wherein one or more portions of the non-conformal oxide layer near the opening are thicker than one or more portions of the non-conformal oxide layer near the bottom surface.

4. 3. The method of claim 2, wherein the non-conformal oxide layer comprises aluminum oxide formed with a thickness varying between about 20 Å and about 50 Å between the opening and the bottom surface.

5. 10. The method of claim 1, wherein forming the non-conformal oxide layer comprises exposing the substrate to one or more precursor gases in an atomic layer deposition (ALD) process.

6. 10. The method of claim 1, wherein selectively removing the oxide layer comprises performing a wet etching process using an etching solution capable of selectively removing the non-conformal oxide layer with minimal or no effect on the thermal oxide layer underneath the non-conformal oxide layer.

7. The method of claim 6 , wherein the etching solution comprises sulfuric acid, acetic acid, phosphoric acid, nitric acid, piranha solution, or a combination thereof.

8. 1. A method for forming an oxide layer suitable for use in semiconductor manufacturing, said method comprising: forming a non-conformal aluminum oxide layer on a substrate; performing an oxidation process to oxidize the substrate and grow a thermal oxide layer under the non-conformal aluminum oxide layer; selectively removing the non-conformal aluminum oxide layer to expose an oxidized portion of the substrate; A method comprising:

9. 10. The method of claim 8, wherein the substrate comprises a silicon or silicon nitride layer, the silicon or silicon nitride layer including a high aspect ratio feature having a pair of sidewalls defining an opening opposite a bottom surface.

10. 10. The method of claim 9, wherein the non-conformal aluminum oxide layer is formed on the sidewalls of the high aspect ratio feature with a thickness that decreases between the opening and the bottom surface, and wherein one or more portions of the non-conformal aluminum oxide layer near the opening are thicker than one or more portions of the non-conformal aluminum oxide layer near the bottom surface.

11. 11. The method of claim 10, wherein the non-conformal aluminum oxide layer comprises a thickness between the opening and the bottom surface that varies from about 20 Å to about 50 Å.

12. 10. The method of claim 8, wherein forming the non-conformal aluminum oxide layer comprises exposing the substrate to one or more precursor gases in an atomic layer deposition (ALD) process.

13. 9. The method of claim 8, wherein selectively removing the oxide layer comprises performing a wet etching process using an etching solution capable of selectively removing the non-conformal aluminum oxide layer with minimal or no effect on the thermal oxide layer underneath the non-conformal aluminum oxide layer.

14. 14. The method of claim 13, wherein the etching solution comprises sulfuric acid, acetic acid, phosphoric acid, nitric acid, piranha solution, or a combination thereof.

15. 1. A method for forming an oxide layer suitable for use in semiconductor manufacturing, said method comprising: forming a non-conformal aluminum oxide layer on a silicon-containing substrate using a tunable deposition process; performing an oxidation process to oxidize the silicon-containing substrate and grow a thermal oxide layer under the non-conformal aluminum oxide layer; performing a wet etching process to selectively remove the non-conformal aluminum oxide layer and expose an oxidized portion of the silicon-containing substrate; A method comprising:

16. 16. The method of claim 15, wherein the silicon-containing substrate comprises silicon or silicon nitride, and the silicon-containing substrate includes a high aspect ratio feature having a pair of sidewalls defining an opening opposite a bottom surface.

17. 17. The method of claim 16, wherein the non-conformal aluminum oxide layer is formed on the sidewalls of the high aspect ratio feature with a thickness that decreases between the opening and the bottom surface, and wherein one or more portions of the non-conformal aluminum oxide layer near the opening are thicker than one or more portions of the non-conformal aluminum oxide layer near the bottom surface.

18. 18. The method of claim 17, wherein the non-conformal aluminum oxide layer comprises a thickness between the opening and the bottom surface that varies from about 20 Å to about 50 Å.

19. 16. The method of claim 15, wherein forming the non-conformal aluminum oxide layer using the tunable deposition process comprises exposing the substrate to one or more precursor gases in an atomic layer deposition (ALD) process.

20. 16. The method of claim 15, wherein selectively removing the oxide layer comprises performing a wet etching process using an etching solution comprising sulfuric acid, acetic acid, phosphoric acid, nitric acid, piranha solution, or a combination thereof.

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