Manufacturing method for single crystal silicon wafers for insulated gate bipolar transistors

Abstract

A method for producing single-crystal silicon wafers for use in insulated gate bipolar transistors is disclosed. The method involves determining, for a relatively low-oxygen ingot, a radial profile of the ratio of (i) growth rate v and (ii) axial temperature gradient G. Based on the radial v / G profile, a nitrogen concentration can be selected that widens the v / G window to produce perfect silicon free of COPs and gate oxide defects.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 480,146, filed January 17, 2023, which is incorporated herein by reference in its entirety. [Technical Field]

[0002] The present disclosure relates to a method for manufacturing single crystal silicon wafers used in insulated gate bipolar transistors. [Background technology]

[0003] Single crystal silicon, the starting material for most steps in the manufacturing process of semiconductor electronic components, is commonly produced by the so-called Czochralski method ("Cz method"). In the Czochralski method, polycrystalline silicon ("polysilicon") is placed in a crucible and melted. A seed crystal is brought into contact with the molten silicon and slowly pulled up to grow a single crystal ingot.

[0004] Oxygen is introduced into the silicon melt through a crucible, typically made from quartz (SiO2). During the solidification process, the oxygen in the melt is incorporated into the silicon crystal ingot. This oxygen (sometimes called interstitial oxygen or simply "Oi") can be beneficial to the silicon ingot and the wafers and devices produced from it, but it can also be harmful, causing various defects in the wafers produced from the ingot and potentially reducing the yield of semiconductor devices manufactured using those wafers. For example, insulated gate bipolar transistors (IGBTs) typically require low oxygen concentrations to achieve high resistivity and avoid the formation of pn junctions. Single-crystal silicon wafers used for IGBTs are typically free of crystal-origin particles (COPs) and gate-oxide integrity defects (i.e., what is commonly referred to as "perfect silicon" material). Producing low-oxygen wafers suitable for IGBTs is challenging because reducing the oxygen concentration makes COP-free wafers more difficult to produce (and may require specific heat treatment / growth conditions).

[0005] What is needed is a method for producing single crystal silicon ingots from which wafers can be sliced, which wafers should have a relatively low oxygen concentration, be free of COPs, and be free of gate oxide integrity defects.

[0006] This section is intended to introduce the reader to various aspects of technology that may be related to various aspects of the disclosure described below. This discussion is believed to be helpful in providing the reader with background information to better understand the various aspects of the present disclosure. As such, it should be read in this light, and not as admissions of prior art. Summary of the Invention

[0007] One aspect of the present disclosure relates to a method for manufacturing monocrystalline silicon wafers for insulated gate bipolar transistors (IGBTs). A monocrystalline silicon ingot is manufactured. The monocrystalline silicon ingot has a radial profile defined by the ratio of (i) growth rate v to (ii) axial temperature gradient G. The monocrystalline silicon ingot is manufactured by determining the ingot's radial v / G profile. An ingot nitrogen concentration that does not result in gate oxide integrity defects across the ingot radius is selected based on the ingot's radial v / G profile. Polycrystalline silicon is added to a crucible disposed in a growth chamber of an ingot puller. The polycrystalline silicon is heated to form a silicon melt within the crucible. Nitrogen is added to the silicon melt to achieve a selected ingot nitrogen concentration. A nitrogen-doped monocrystalline silicon ingot is pulled from the melt. A plurality of wafers are cut from the monocrystalline silicon ingot. Each of the plurality of wafers has an oxygen concentration of 2.75×10 17 atoms / cm 3 less than 1000 nm, contains no crystal grains, and has no gate oxide integrity defects.

[0008] Various refinements exist in the features of the above aspects of the present disclosure. Furthermore, additional features may be incorporated into the above aspects of the present disclosure. These refinements and additional features may exist alone or in any combination. For example, the various features discussed below in connection with any of the illustrated embodiments of the present disclosure may be incorporated into the above aspects of the present disclosure alone or in any combination. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional schematic diagram of an insulated gate bipolar transistor (IGBT) device. [Figure 2] FIG. 1 is a cross-sectional view of an ingot pulling apparatus during ingot growth. [Figure 3] FIG. 1 shows ingot defect bands as a function of v / G and nitrogen concentration. [Figure 4]FIG. 1 shows the ingot defect band as a function of v / G and nitrogen concentration, indicating the range within which gate oxide integrity defects ("GOI defects") do not occur for typical oxygen concentrations (e.g., 3×10 atoms / cm to 6×10 atoms / cm). [Figure 5] FIG. 1 shows the ingot defect band as a function of v / G and nitrogen concentration, indicating the range in which gate oxide integrity defects ("GOI defects") do not occur at low oxygen concentrations (e.g., less than 3×10 atoms / cm). [Figure 6] Figure 5 shows the defect bands in the radial direction without nitrogen doping and with nitrogen doping with closely controlled v / G. [Figure 7] FIG. 6 is a diagram showing the defect bands shown in FIG. 5, showing the change in the radial defect bands under low Oi conditions in the cases without and with nitrogen doping. [Figure 8] FIG. 10 shows the v / G ratio between the crystal center and the R / 2 position, and the GOI defect-free area as a function of nitrogen concentration.

[0010] Corresponding reference characters indicate corresponding parts throughout the drawings. DETAILED DESCRIPTION OF THE INVENTION

[0011] Provisions of the present disclosure relate to methods for fabricating monocrystalline silicon wafers used for insulated gate bipolar transistors (IGBTs). An example IGBT device is shown in Figure 1. Such a device may include at least four layers (at least one of the layers is a chip singulated from a wafer fabricated by an embodiment of the method described herein). The transistor may include a gate electrode, a collector electrode, and an emitter.

[0012] The monocrystalline silicon wafers of the present disclosure are sliced ​​from monocrystalline silicon ingots. According to an embodiment of the present disclosure, and with reference to FIG. 2 , an example of an ingot puller (or simply "ingot puller") for producing monocrystalline silicon ingots is generally designated "100." The ingot puller 100 includes a crucible assembly 102 (or simply "crucible") for holding a melt 104 of semiconductor- or solar-grade silicon material. The crucible assembly 102 is supported by a susceptor 106.

[0013] The ingot puller 100 includes a crystal pulling housing 108 that defines a growth chamber 152 for pulling a silicon ingot from a silicon melt 104 along a pulling axis A. The growth chamber 152 includes two portions: a lower growth chamber 155 (also referred to simply as the "lower chamber") and an upper growth chamber 165 (also referred to simply as the "upper chamber") disposed above the lower growth chamber 155. The hot zone (e.g., crucible, reflector assembly, susceptor, heater, etc.) of the ingot puller 100 is disposed within the lower chamber 155. During ingot growth, the ingot 113 is pulled through the lower chamber 155 and continues to be pulled through the upper chamber 165 as the ingot elongates.

[0014] The crystal puller housing 108 includes a domed lower segment 119 that defines a lower chamber 155 and an upper segment 140 that defines an upper chamber 165. The lower domed segment 119 has a dome-shaped portion 169 that tapers in size to the diameter of the upper segment 140. The upper segment 140 is generally cylindrical in shape and has a lower end and an upper end. The upper segment 140 of the crystal puller housing 108 is removably connected (e.g., by fasteners, gaskets, etc.) to the lower segment 119.

[0015] The crucible assembly 102 is disposed within the lower chamber 155. The crucible assembly 102 has sidewalls 131 and a bottom surface 129 and rests on a susceptor 106. The susceptor 106 is supported by a shaft 105. The susceptor 106, the crucible assembly 102, the shaft 105, and the ingot 113 share a common longitudinal axis, or "pull axis," A.

[0016] Within ingot pulling apparatus 100 is a pulling mechanism 114 for growing and pulling an ingot 113 from melt 104. Pulling mechanism 114 includes a pulling cable 118, a seed crystal holder or chuck 120 connected to one end of pulling cable 118, and a seed crystal 122 connected to chuck 120 for initiating crystal growth. One end of pulling cable 118 is connected to a pulley (not shown) or drum (not shown) of pulling mechanism 114, and the other end is connected to chuck 120, which holds seed crystal 122. Pulling mechanism 114 includes a motor that rotates the pulley or drum.

[0017] In operation, the seed crystal 122 is lowered into contact with the surface 111 of the melt 104. The pulling mechanism 114 is activated to raise the seed crystal 122. This causes the single crystal ingot 113 to be pulled from the melt 104.

[0018] A crucible drive unit 107 (e.g., a motor) rotates the crucible assembly 102 and susceptor 106 during heating and crystal pulling. A lift mechanism 112 raises and lowers the crucible assembly 102 along the pulling axis A during the growth process. For example, the crucible assembly 102 may be positioned at a lowest position (near the bottom heater 126) to melt a charge of solid phase silicon 133 that has been pre-added to the crucible assembly 102. Crystal growth is initiated by contacting the melt 104 with the seed crystal 122 and lifting the seed crystal 122 with the pulling mechanism 114.

[0019] The crystal drive unit (not shown) can also rotate the pulling cable 118 and ingot 113 in a direction opposite (e.g., counter-rotation) to the direction in which the crucible drive unit 107 rotates the crucible assembly 102. In embodiments using uniform rotation, the crystal drive unit can rotate the pulling cable 118 in the same direction as the crucible drive unit rotates the crucible assembly 102.

[0020] The ingot pulling apparatus 100 includes bottom insulation 110 and side insulation 124 for retaining heat within the pulling apparatus 100. In the illustrated embodiment, the ingot pulling apparatus 100 includes a bottom heater 126 positioned below a crucible bottom surface 129. The crucible assembly 102 can be moved into relatively close proximity to the bottom heater 126 to melt solid silicon charged into the crucible assembly 102.

[0021] In the Czochralski single crystal growth process, solid silicon, such as polycrystalline silicon (“polysilicon”), is first loaded into the crucible assembly 102. The semiconductor- or solar-grade solid silicon introduced into the crucible assembly 102 is melted by heat provided by one or more heating elements. Once the melt 104 is fully formed, the seed crystal 122 is lowered into contact with the surface 111 of the melt 104. The pulling mechanism 114 is activated, and the seed crystal 122 is pulled out of the melt 104. The resulting ingot 113 includes a crown portion 142 that transitions and slopes outward from the seed crystal 122 until the ingot reaches a target diameter. The ingot 113 includes a constant diameter portion 145, or cylindrical “body” of the crystal, that is grown by increasing the pulling rate. The body 145 of the ingot 113 has a relatively constant diameter. The ingot 113 includes a tail or end cone (not shown) that tapers to a reduced diameter behind the body 145. Once the diameter is sufficiently small, the ingot 113 is separated from the melt 104.

[0022] The crystal growth process can be a batch process, in which solid silicon is initially added to crucible assembly 102 to form a silicon melt, without additional solid silicon being added to crucible assembly 102 during crystal growth. In other embodiments, the crystal growth process is a continuous Czochralski process, in which a constant amount of silicon is added to crucible assembly 102 during ingot growth.

[0023] The ingot pulling apparatus 100 includes side heaters 135 and 106 surrounding the crucible assembly 102 to maintain the temperature of the melt 104 during crystal growth. The side heater 135 is positioned radially outward relative to the crucible sidewall 131 as the crucible assembly 102 moves up and down along the pulling axis A. The side heater 135 and the bottom heater 126 can be any type of heater operable as described herein. In some embodiments, the heaters 135, 126 are resistive heaters. The side heater 135 and the bottom heater 126 can be controlled by a control system (not shown) to control the temperature of the melt 104 throughout the pulling process.

[0024] The ingot pulling apparatus 100 may include a reflector assembly 151 having an opening 157 through which the single crystal silicon ingot 113 is pulled during ingot growth. The ingot pulling apparatus 100 may include an inert gas system for introducing and evacuating an inert gas, such as argon, from the growth chamber 152.

[0025] The illustrated ingot pulling apparatus 100 is an example, and unless otherwise specified, any ingot pulling apparatus 100 suitable for producing single crystal silicon ingots can be used.

[0026] Wafers can be sliced ​​(e.g., by a diamond wire saw) from the single crystal silicon ingot 113. The resulting wafers can have a diameter of 200 mm, greater than 200 mm, 300 mm, or greater than 300 mm. In some embodiments, the wafer diameter is 300 mm. The wafers can be p-type or n-type.

[0027] The wafers preferably have a relatively low oxygen content to make them suitable for use in IGBT devices. For example, the wafers may have an oxygen concentration of 2.75×10 17 atoms / cm 3 Less than or equal to 2.2 × 10 17 atoms / cm 3 The oxygen content may be less than 5.5 ppma, or alternatively less than 5.0 ppma.

[0028] To obtain such a silicon ingot with a relatively low oxygen concentration, various control parameters can be selected during ingot growth. For example, any combination of a high magnetic field strength (e.g., to suppress the flow of the silicon melt), a slow crucible rotation speed (e.g., to increase oxygen evaporation from the melt), and a relatively low crucible bottom temperature (e.g., to reduce melting of the quartz crucible) can be used. In some embodiments, a cusp magnetic field is applied to the melt. In some embodiments, the crystal rotation speed is between 6 rpm and 15 rpm, and / or the crucible rotation speed is between 0.5 rpm and 2.5 rpm, and / or the magnetic field strength is between 0.02 and 0.075 Tesla at the end of the silicon ingot at the melt-solid interface and between 0.05 and 0.20 Tesla at the crucible wall (e.g., parameters may be changed / adjusted in the second stage of ingot growth to maintain a relatively low oxygen concentration throughout the ingot length).

[0029] In another embodiment, a horizontal magnetic field is applied to the silicon melt. It is possible to control several process parameters during the application of the horizontal magnetic field. For example, the position of the maximum Gaussian plane of the horizontal magnetic field can be maintained above the free surface of the melt (e.g., 20 mm to 250 mm above the free surface of the melt). Alternatively, or in addition, the horizontal magnetic field can be applied with a magnetic flux density of 0.1 Tesla to about 0.4 Tesla, and / or the crucible can be rotated (in the opposite direction or the same direction as the ingot) at a speed of 0.1 RPM to 5.0 RPM.

[0030] Growth conditions may be selected from among those disclosed in U.S. Patent Publication No. 2018 / 0355509 and / or U.S. Patent Publication No. 2022 / 0349087, both of which are incorporated by reference herein for all relevant purposes.

[0031] Conditions that promote the growth of low-oxygen ingots can make the growth of perfect silicon material difficult (e.g., the process window in which the ratio of growth rate v to axial temperature gradient G can be controlled to produce perfect silicon is relatively narrow). According to embodiments of the present disclosure, to expand the v / G process window for perfect silicon, the ingot can be nitrogen-doped by adding nitrogen to the silicon melt. Axial v / G control can be achieved by controlling the reflector height (Hr) and controlling the sea drift.

[0032] As shown in Figure 3, adding nitrogen to the ingot decreases the COP region while increasing the oxygen precipitation zone at a certain v / G. Adding nitrogen changes the cause of GOI degradation from COP to a combination of COP and oxygen precipitation (e.g., the high density of oxygen precipitates at high nitrogen additions consumes excess free vacancies, increasing the stress field at the defect-silicon matrix interface). Figure 4 (typical oxygen content: 3 × 10 17 / cm 3 ~6×10 17 / cm 3 ) as shown in Figure 5. 17 / cm3 At temperatures below 1000 K, even with nitrogen doping, the formation and growth of oxygen precipitates is suppressed, reducing leakage problems and expanding the perfect silicon (PS) window.

[0033] Figure 6 shows the radial defect shapes without nitrogen addition and with nitrogen addition to strictly control v / G under the low-oxygen conditions of Figure 5. As shown in Figure 6, the radial defect shapes are not flat but change radially due to the radial variation of v / G.

[0034] Due to the radial defect band structure of the low-oxygen process, the actual process window for low-oxygen growth is narrower than the ideal case shown in Figure 6. The critical v / G for interstitial defects at the midpoint between the center and the edge of the ingot (the "R / 2 position") is larger than that at the crystal center. As shown in the left panel of Figure 7, without nitrogen (N) addition, there is no process window for obtaining a good GOI (interstitial defect) yield. To avoid I defects at the R / 2 position, a higher pull rate is required, resulting in a central core pattern where COPs are detected. The addition of nitrogen expands the deposition region, reducing or eliminating GOI degradation in the deposition region under low-oxygen conditions. In the pull rate range between the R / 2 position and the ingot center, a COP-free window (i.e., a region free of gate oxide integrity defects greater than 8 MVcm) can be formed, as shown in the right panel of Figure 7.

[0035] The concentration of nitrogen can be selected based on the radial v / G profile to obtain a material free of GOI defects throughout the radius of the ingot. In some embodiments, the difference between the v / G ratio at the ingot center and the v / G ratio at the R / 2 location is determined. The nitrogen concentration is selected based on the determined difference between the v / G ratio at the ingot center and the v / G ratio at the R / 2 location, and is tailored to avoid gate oxide integrity defects throughout the radius of the ingot (e.g., nitrogen can be selected according to the function shown in FIG. 8).

[0036] The v / G ratios at the R / 2 position and center of a crystal can be determined empirically using techniques such as axial velocity ramping tests. A full-diameter test ingot is grown in the same ingot puller used to grow the production ingot, with the growth rate gradually increasing during growth. At a given radial location (e.g., the R / 2 position or the ingot center) of the test ingot, the growth rate v at which the transition from interstitial defects begins (i.e., the rate at which the critical v / G occurs) is determined. The ramping axial test indicates the radial location (center, edge, R / 2) at which the I defect region forms. From this information, the v / G ratio between the R / 2 position and the ingot center can be calculated. Because the critical v / G is a predetermined or known parameter (for a given doping level), the axial temperature gradient g at a given radial location within the test ingot can be calculated based on the growth rate v at which the interstitial defect band terminates.

[0037] The transition position from the interstitial defect dominated region at a given radial position can be determined by identifying the position where the I defect band stops using the vertical cut slab method and slab observation, and then specifying the growth rate v at this position. Alternatively, the position where the interstitial defects stop can be determined by slicing wafers from the ingot and observing the wafers to determine the position where the interstitial defects stop.

[0038] After the product ingot is grown by the method of the present disclosure, one or more additional processing steps (e.g., ingot grinding) may be performed as needed, followed by slicing wafers from the single crystal silicon ingot. A separation step may also be performed to divide the wafer into semiconductor chips. Insulated gate bipolar transistors can be fabricated, with at least one of the transistor layers being a semiconductor chip singulated from the wafer.

[0039] Compared to conventional single crystal silicon wafer fabrication for insulated gate bipolar transistors, the method herein has several advantages: the oxygen concentration of the ingot is reduced to 2.75×10 17 atoms / cm 3By controlling the growth parameters so that the v / G ratio is less than 0.01, the resulting wafers are suitable for low-oxygen IGBT applications. By measuring the radial v / G profile of a single-crystal silicon ingot (e.g., at positions R / 2 and the center) and comparing the v / G ratios at the R / 2 and center positions, an appropriate nitrogen concentration can be selected to ensure that the ingot is suitable for IGBT applications without GOI defects. Because the radial defect band variation depends on the hot-zone geometry of the pulling equipment (e.g., heater position, insulation design), and other parameters (e.g., crucible rotation, magnetic field strength, heater power) are set to achieve low oxygen, determining the difference between v / G at the center and the R / 2 position can be correlated to the nitrogen doping amount that should be used to achieve perfect silicon across the wafer radius for a particular ingot pulling equipment and given growth conditions to achieve low oxygen.

[0040] As used herein, the terms "about," "substantially," "essentially," and "approximately," when used in conjunction with ranges of dimensions, concentrations, temperatures, or other physical or chemical properties or characteristics, are intended to encompass variations that may exist at the upper and / or lower limits of the range of such properties or characteristics (including, for example, variations due to rounding error, measurement method, and other statistical variations).

[0041] When introducing elements of this disclosure or embodiments thereof, the articles "a," "an," "the," "said," etc. mean that there are one or more elements. The terms "comprising," "including," "containing," and "having" are inclusive and mean that there may be additional elements other than the listed elements. The use of specific orientational terms (e.g., "top," "bottom," "side," etc.) is for convenience of description and does not require a specific orientation of the described article.

[0042] Because various changes may be made in the above-described structures and methods without departing from the scope of the disclosure, all matter contained in the above description and shown in the accompanying drawings is intended to be interpreted as illustrative and not in a limiting sense.

Claims

1. 1. A method for manufacturing a single crystal silicon wafer for an insulated gate bipolar transistor (IGBT), comprising:

1. A process for producing a single crystal silicon ingot, the single crystal silicon ingot having a radial profile of a ratio of (i) a growth rate v and (ii) an axial temperature gradient G, the single crystal silicon ingot being grown by the following steps: determining a radial v / G profile of the single crystal silicon ingot; selecting an ingot nitrogen concentration based on the radial v / G profile of the ingot that will not result in gate oxide integrity defects across the radius of the ingot; adding polycrystalline silicon to a crucible disposed within a growth chamber of an ingot puller; heating polycrystalline silicon to form a silicon melt in a crucible; adding nitrogen to the silicon melt to achieve a selected ingot nitrogen concentration; and pulling a nitrogen-doped single crystal silicon ingot from the melt; and slicing a plurality of wafers from a single crystal silicon ingot, each of the plurality of wafers having an oxygen concentration of 2.75×10 １７ atoms / cm ３ less than 1000 nm, containing no crystalline particles and no gate oxide integrity defects; and a manufacturing method comprising:

2. Selecting an ingot nitrogen concentration based on the radial v / G profile of the ingot such that the ingot is free of gate oxide integrity defects throughout the ingot's radius comprises the steps of: determining the difference between the v / G ratio at the center of the ingot and the v / G ratio at a location halfway from the center to the periphery of the ingot; and selecting a nitrogen concentration that will result in the ingot having no gate oxide integrity defects throughout the entire radial direction of the ingot based on the difference between the v / G ratio at the center of the ingot and the v / G ratio at a location halfway from the center to the periphery of the ingot; 10. The method of claim 1, comprising:

3. 3. The method of claim 2, wherein the nitrogen concentration throughout the ingot radially free of gate oxide integrity defects is determined based on the ratio of the v / G ratio at the center of the ingot to the v / G ratio at a location halfway from the center to the periphery of the ingot.

4. The radial v / G profile is determined by the following steps: pulling the test ingot with an ingot pulling apparatus and growing the test ingot while changing the growth rate in stages; determining a growth rate v at a predetermined radial position of the test ingot at the transition from interstitial defects; and calculating an axial temperature gradient g at a radial location based on a predetermined critical v / G at the transition from interstitial defects and the growth rate v at which the transition from interstitial defects was observed at that radial location on the test ingot; The method according to any one of claims 1 to 3, wherein the method is empirically determined by a stepwise test method comprising:

5. The method according to claim 4, wherein the radial position is a radial center position (R / 2 position).

6. 6. The method of claim 5, wherein v / G is also determined at the center of the ingot.

7. The method according to any one of claims 4 to 6, wherein the growth rate v at a predetermined radial position of the test ingot at the time of the transition from interstitial defects is determined by identifying the position at which the transition from interstitial defects occurs by a vertical cut slab method and observing the slab, and determining the growth rate v at the position at which the transition from interstitial defects occurs.

8. 7. The method according to claim 4, wherein the growth rate v at the transition from the interstitial defect at a predetermined radial position of the test ingot is determined by slicing a wafer from the ingot, observing the wafer to identify the position at which the transition from the interstitial defect occurs, and determining the growth rate v at the position at which the transition from the interstitial defect occurs.

9. The nitrogen concentration in each wafer is at least 2×10 １３ atoms / cm ３ The method according to any one of claims 1 to 8, wherein

10. The oxygen concentration in each wafer was 2.2×10 １７ atoms / cm ３ The method according to any one of claims 1 to 9, wherein the solubility is less than 100%.

11. The method of any preceding claim, wherein each wafer of the plurality of wafers has an oxygen content of less than 5.5 ppma.

12. The method of any of claims 1 to 10, wherein each wafer of the plurality of wafers has an oxygen content of less than 5.0 ppma.

13. One or more growth parameters selected from crystal rotation speed, crucible rotation speed, and magnetic field strength are adjusted to achieve an oxygen concentration of 2.75×10 in each of the plurality of wafers. １７ atoms / cm ３ The method of any one of claims 1 to 12, wherein the .alpha.-methyl-2-hydroxybenzoate is selected to be less than 100%.

14. A cusp magnetic field is applied to the silicon melt; The crystal rotation speed is between 6 and 15 rpm; The crucible rotation speed is between 0.5 rpm and 2.5 rpm; and 14. The method of claim 13, wherein the magnetic field strength is 0.02 to 0.075 Tesla at the edge of the silicon ingot at the molten-solid interface and 0.05 to 0.20 Tesla at the wall of the crucible.

15. A horizontal magnetic field is applied to the silicon melt, the maximum Gaussian plane of the horizontal magnetic field being maintained 20 mm to 250 mm above the melt free surface; The crucible rotation speed is between 0.1 rpm and 5.0 rpm; and 14. The method of claim 13, wherein the magnetic flux density is from 0.1 Tesla to about 0.4 Tesla.

16. The method of any of claims 1 to 15, wherein the plurality of wafers does not have gate oxide integrity defects greater than 8 MVcm in magnitude.

17. The method according to any one of claims 1 to 16, wherein the single crystal silicon ingot is grown in a batch process in which no silicon is added to the crucible during growth of the single crystal silicon ingot.

18. The method according to any one of claims 1 to 16, wherein the single crystal silicon ingot is grown in a continuous process in which silicon is added to the crucible during growth of the single crystal silicon ingot.

19. 1. A method for manufacturing an insulated gate bipolar transistor, comprising: A step of dividing the wafer manufactured by the method according to any one of claims 1 to 18 into a plurality of semiconductor chips; and A method for forming an insulated gate bipolar transistor having at least four layers, at least one of the layers comprising a semiconductor chip separated from a wafer, the insulated gate bipolar transistor including a gate electrode, a collector electrode, and an emitter.

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