Method for manufacturing an electronic device
By laser-processing the support before attaching the plate, the method reduces cutting line width and prevents component damage, effectively manufacturing electronic devices with precise separation of three-dimensional semiconductor elements.
Patent Information
- Application Number
- JP2025538471
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-12-28
- Filing Date
- 2023-12-07
- Publication Date
- 2026-01-21
- Estimated Expiration
- 2043-12-07
AI Technical Summary
Existing methods for manufacturing electronic devices with three-dimensional semiconductor elements face challenges in reducing the width of cutting lines to minimize material loss and prevent damage to components near the cutting line, especially when using laser processing.
A method involving laser processing the support before attaching the plate with electronic devices to form weakened areas, followed by etching and fracturing to separate the devices, ensuring the laser processing does not damage the electronic components.
The method achieves cutting lines less than 100 μm wide without damaging adjacent components, particularly beneficial for nanometer- or micrometer-sized semiconductor elements in electronic devices like light-emitting diodes.
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Figure 2026502244000001_ABST
Abstract
Description
[Technical Field]
[0001] FIELD OF THE INVENTION The present disclosure relates generally to methods for manufacturing electronic devices, and in particular electronic devices having light emitting diodes. Summary of the Invention [Problem to be solved by the invention]
[0002] In one example of a method for manufacturing electronic devices, a plate containing multiple copies of electronic devices is formed on a support, and then the electronic devices are separated. Separation of the electronic devices can be performed by cutting the plate and the support, particularly by sawing. A disadvantage of this separation method is that the cutting line is wider than 100 μm. In some applications, it is desirable to reduce the width of the cutting line, especially to reduce material loss.
[0003] In the method of separating electronic devices by reducing the width of the cutting line, the support is locally weakened by laser processing, allowing the support to be broken by mechanical action and the electronic devices to be separated. One drawback is that the laser processing may damage components of the electronic device near the cutting line. This drawback may be particularly pronounced when the electronic device includes multiple three-dimensional semiconductor elements of nanometer or micrometer size, each separated by an electrically insulating material. In fact, as the size of the three-dimensional semiconductor elements and the distance separating the three-dimensional semiconductor elements become smaller, the heat dissipation caused by the laser processing may damage the three-dimensional semiconductor elements near the cutting line.
[0004] One embodiment addresses all or some of the shortcomings of known methods for manufacturing electronic devices.
[0005] According to an object of one embodiment, the width of the cutting lines in the plate containing multiple copies of the electronic device is less than 100 μm.
[0006] According to one object of one embodiment, components of the electronic device that are close to the cutting line are not damaged. [Means for solving the problem]
[0007] One embodiment provides a method for manufacturing electronic devices, comprising: manufacturing a plate including multiple copies of electronic devices and attached to a substrate; using a laser to form weakened areas in a support; attaching the plate to the support after forming the weakened areas; removing the substrate after attaching the plate to the support; etching the plate at the extensions of the weakened areas after removing the substrate; and fracturing the support at the weakened areas to separate the electronic devices. Advantageously, the step of laser processing the support to form the weakened areas in the support is performed before the step of attaching the support to the plate including the electronic devices, thereby preventing the laser processing from damaging electronic components of the electronic devices on the plate.
[0008] According to one embodiment, the attachment of the plate to the support is performed by bonding, which may take the form of a bond using a layer of adhesive and can be advantageously performed simply and at low cost. Molecular bonding can also be used, thus avoiding the need for an adhesive layer between the support and the plate.
[0009] According to one embodiment, the method comprises the step of thinning the support after attaching the plate to the support and before breaking the support at the weakened region, which advantageously makes it easier to break the support at the weakened region.
[0010] According to one embodiment, etching of the plate in the extension of the weakened region is carried out by dry or wet etching, so that a trench of reduced thickness can be formed in the plate.
[0011] According to one embodiment, the support is transparent to the laser at least in the weakened area, which advantageously allows localized weakened areas to be formed.
[0012] According to one embodiment, after forming the weakened areas, the step of attaching the plate to the support comprises positioning a first mark on the support relative to a second mark on the plate so that each electronic device to be separated is positioned between two of the weakened areas.
[0013] According to one embodiment, the support is at least partially made of glass, quartz or sapphire, which advantageously allows the use of supports commonly used in laser processing.
[0014] According to one embodiment, the electronic device comprises a light emitting diode. Advantageously, forming the weakened region does not damage the light emitting diode adjacent to the desired cutting line. According to one embodiment, each light emitting diode comprises a nanometer- or micrometer-sized three-dimensional semiconductor element corresponding to a nanometer- or micrometer-sized microwire, nanowire, or pyramidal structure, and an active layer covering the three-dimensional semiconductor element. [Brief explanation of the drawings]
[0015] The foregoing and other features and advantages will be more fully described in the following detailed description of specific embodiments, given by way of illustration and not of limitation, with reference to the accompanying drawings, in which: FIG.
[0016] [Figure 1A] 1A-1C are schematic partial cross-sectional views illustrating structures obtained at different steps in a method for manufacturing an electronic device. [Figure 1B] 1A-1C are schematic partial cross-sectional views illustrating structures obtained at different steps in a method for manufacturing an electronic device. [Figure 1C] 1A-1C are schematic partial cross-sectional views illustrating structures obtained at different steps in a method for manufacturing an electronic device. [Figure 1D]1A-1C are schematic partial cross-sectional views illustrating structures obtained at different steps in a method for manufacturing an electronic device. [Figure 1E] 1A-1C are schematic partial cross-sectional views illustrating structures obtained at different steps in a method for manufacturing an electronic device. [Figure 1F] 1A-1C are schematic partial cross-sectional views illustrating structures obtained at different steps in a method for manufacturing an electronic device. [Figure 1G] 1A-1C are schematic partial cross-sectional views illustrating structures obtained at different steps in a method for manufacturing an electronic device. [Figure 2] FIG. 2 is a schematic partial cross-sectional view showing one embodiment of a support; [Figure 3A] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3B] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3C] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3D] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3E] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3F] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3G] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3H] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3I] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3J] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3K] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3L] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3M] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 3N] 1A-1C are schematic partial cross-sectional views illustrating the structure obtained at different steps of an embodiment of a method for manufacturing an optoelectronic device having a light-emitting diode. [Figure 4] 1 is a schematic partial cross-sectional view illustrating an embodiment of a light-emitting diode. [Figure 5] 1 is a schematic partial cross-sectional view illustrating an embodiment of a light-emitting diode. [Figure 6] 1 is a schematic partial cross-sectional view illustrating an embodiment of a light-emitting diode. DETAILED DESCRIPTION OF THE INVENTION
[0017] In the various drawings, like features are designated by like reference numerals, and in particular, structural and / or functional features common to various embodiments may have the same reference numerals and have the same structural, dimensional, and material characteristics.
[0018] For clarity, only those operations and elements useful for understanding the embodiments described herein are shown and described in detail.
[0019] In the following description, unless otherwise indicated, when reference is made to terms that qualify absolute positions such as "front," "back," "top," "bottom," "left," "right," or relative positions such as "up," "down," "high," "low," or terms that qualify orientations such as "horizontal," "vertical," this refers to the orientation of the drawing or the orientation of the probe during normal use.
[0020] Unless otherwise specified, the terms "about," "approximately," "substantially," and "to the extent of" refer to within 10%, preferably within 5%, of the relevant value. In the case of angles, the terms "about," "approximately," "substantially," and "to the extent of" refer to within 10%, preferably within 5%, of the relevant value. Furthermore, as used herein, the terms "insulating" and "conducting" are considered to refer to "electrically insulating" and "electrically conducting," respectively.
[0021] By optoelectronic device is meant a device adapted to convert electrical signals into electromagnetic radiation or vice versa, in particular a device dedicated to the detection, measurement or emission of electromagnetic radiation.
[0022] The transmittance of a layer corresponds to the ratio of the intensity of radiation leaving the layer through the exit face to the intensity of radiation entering the layer through the entrance face opposite the exit face. For the remainder of this specification, a layer or film will be considered opaque to radiation if the transmittance of radiation through the layer or film is less than 10%. For the remainder of this specification, a layer or film will be considered transparent to radiation if the transmittance of radiation through the layer or film is greater than 10%.
[0023] According to the invention, before the step of attaching the plate containing the multiple copies of the electronic device to the support, a step of laser processing the support to form weakened areas in the support is performed, which advantageously prevents the laser processing from damaging electronic components of the electronic device on the plate.
[0024] 1A, 1B, 1C, 1D, 1E, 1F, and 1G are each schematic partial cross-sectional views illustrating a structure obtained at a step in an embodiment of a method for manufacturing an electronic device.
[0025] FIG. 1A is a schematic partial cross-sectional view illustrating a process for locally weakening a support 5 using a laser processing system 10. As shown in FIG.
[0026] The laser processing system 10 includes a laser source 12 and a focusing optical device 14 having an optical axis D. The laser source 12 is adapted to provide an incident laser beam 16 to the focusing optical device 14, which provides a converging laser beam 18. The focusing optical device 14 may include one optical component, two optical components, or three or more optical components, where one optical component corresponds to, for example, a lens. Preferably, the incident laser beam 16 is substantially parallel along the optical axis D of the focusing optical device 14.
[0027] The support 5 has two opposing surfaces 20 and 22, and the laser beam 18 enters the support 5 through surface 20. According to one embodiment, surfaces 20 and 22 are parallel to each other. According to one embodiment, surfaces 20 and 22 are flat. According to one embodiment, the thickness of the support 5 is in the range of 50 μm to 3 mm. According to one embodiment, the support 5 has a single-layer structure and is formed of a first material, such as glass, quartz, silicon, or sapphire. Therefore, the support 5 is laser-transparent. In another embodiment, the support 5 has a multi-layer structure, and the top layer is formed of a first material. Therefore, at least the top layer is laser-transparent.
[0028] The laser process weakens regions 24 of the support 5 using a laser stealth dicing method, specifically a low-energy laser. By way of example, three weakened regions 24 are shown in FIG. 1A by dotted lines. According to one embodiment, the weakened regions 24 extend into the support 5 from the surface 20 of the support 5 over a thickness in the range of 5 μm to 100 μm. According to one embodiment, the width of each weakened region 24 is in the range of 0.5 μm to 5 μm. Each weakened region 24 corresponds to a localized melting of the support 5 without shrinkage of the material.
[0029] According to one embodiment, the wavelength of the laser beam 18 provided by the processing system 10 is in the range of 100 nm to 3,000 nm, depending on the material to be weakened. According to one embodiment, the laser beam 18 is emitted by the processing system 10 in the form of one pulse, two pulses, or three or more pulses, each pulse having a duration in the range of 0.1 ps to 1,000 ps. The laser beam energy per pulse is in the range of 1 μJ to 100 μJ.
[0030] FIG. 1B is a schematic partial cross-sectional view illustrating the structure obtained after fabricating a plate 30 containing multiple copies of electronic devices 34 on a substrate 32, with two copies of the electronic devices 34 shown in FIG. 1B as an example. The plate 30 has a top surface 36 and a bottom surface 38 opposite the top surface 36. The bottom surface 38 is in contact with the substrate 32. The top surface 36 is preferably flat. According to one embodiment, the plate 30 has a thickness in the range of 1 μm to 100 μm. The electronic devices 34 include electronic components 40, 42, and 44; FIG. 1B shows three electronic components 40, 42, and 44 per electronic device 34 as an example. According to one embodiment, the electronic devices 34 are optoelectronic devices. As such, the electronic components 40, 42, and 44 may include light sources, particularly light-emitting diodes.
[0031] 1C is a schematic partial cross-sectional view showing the structure obtained after the step of attaching the structure shown in FIG. 1B to face 20 of support 5 shown in FIG. 1A. Plate 30 is attached to support 5 by face 36. According to one embodiment, attachment of plate 30 to support 5 is performed by adhesive bonding using a layer of adhesive 50. In another embodiment, not shown, attachment of plate 30 to support 5 is performed by molecular bonding. In this case, face 36 of plate 30 is in direct physical contact with face 20 of support 5.
[0032] The weakened areas 24 are positioned in extensions of the desired separation lines between the electronic devices 34. The separation lines correspond to the portions of the plate 30 that will be removed to separate the electronic devices 34. The desired separation lines between the electronic devices and the weakened areas 24 are superimposed, and the desired separation lines overlap the weakened areas 24. Accurate positioning of the plate 30 relative to the support 5 is performed, for example, using marks on the plate 30 and marks on the support 5 (marks not shown).
[0033] 1D is a schematic partial cross-sectional view showing the structure obtained after a step of removing the substrate 32, for example by dry etching, in particular plasma etching, wet etching, or chemical mechanical polishing (CMP), after which additional steps can be performed to continue the fabrication of the electronic devices 34 on the plate 30, in particular the formation of the conductive pads.
[0034] 1E is a schematic partial cross-sectional view showing the structure obtained after a step of etching trenches 52 in the plate 30 at the desired separation lines of the electronic devices 34. The etching is carried out, for example, by dry etching, in particular by plasma etching. The trenches 52 may extend into the adhesion layer 50 until they reach the surface 20 of the support 5 at the weakened area 24. According to one embodiment, the trenches 52 do not extend into the support 5. The trenches 52 can be obtained by chemical etching. According to one embodiment, the width of each trench 52 is in the range of 1 μm to 20 μm.
[0035] 1F is a schematic partial cross-sectional view showing the structure obtained after a step of thinning the support 5 from the surface 22. Depending on the nature of the material or materials constituting the support 5, the thinning may be carried out by grinding and / or CMP. The CMP step may comprise mechanical polishing and chemical etching steps, either simultaneously or sequentially. At the end of the thinning step, the thickness of the support 5 is in the range of 50 μm to 200 μm. According to one embodiment, the thickness of the plate 30 is smaller than the thickness of the support 5 after thinning, in particular by at least a factor of two.
[0036] 1G is a schematic partial cross-sectional view showing the structure obtained after a step of mechanically breaking the support 5 at the weakened areas 24, thus obtaining a separate electronic device 34. According to an embodiment not shown, in the breaking step, a mechanically stretchable adhesive film is attached to the support 5 on the side of the support 5 facing the electronic device 34, the adhesive film is stretched in the plane of the adhesive film, and then the electronic device 34 is separated, but remains attached to the adhesive film, from which the electronic device is released.
[0037] The method may include subsequent steps, in particular removing part of the support 5 and adhesive layer 50 from underneath each electronic device 34. If the support 5 is to be retained for future use of the electronic devices 34, it is advantageous for the support 5 to be transparent to the radiation emitted by the electronic devices 34.
[0038] Advantageously, in an embodiment of the manufacturing method, the laser machining of the support 5 is performed before the plate 30 is attached to the support 5, so that the laser machining of the support 5 to form the weakened areas 24 cannot damage the electronic components 40, 42, 44 of the plate 30.
[0039] FIG. 2 is a cross-sectional view illustrating an embodiment of the support 5. According to one embodiment, the support 5 has a multi-layer structure, including a layer 56 of a first material covering a substrate 58 of a second material different from the first material. The weakened region 24 is formed in the layer 56. The substrate 58 is laser-transparent. According to one embodiment, the second material is a semiconductor material. The semiconductor material may be silicon, germanium, or a mixture of at least two of these compounds. The substrate 58 is preferably formed of silicon, more preferably monocrystalline silicon. Alternatively, the substrate 58 may be at least partially formed of a non-semiconductor material, such as an electrically insulating or conductive material. The thickness of the layer 56 is in the range of 50 μm to 200 μm. The second material constituting the substrate 58 is advantageously selected to facilitate the thinning process described above in connection with FIG. 1F. In particular, the end of the thinning process corresponds to the complete removal of the substrate 58, making it easier to determine the end of the thinning process.
[0040] A more detailed embodiment will be described in which the electronic device 34 is an optoelectronic device and the electronic components 40, 42, 44 comprise three-dimensional semiconductor elements of nanometer or micrometer size, in particular light-emitting diodes with microwire or nanowire or pyramidal structures covered with an active layer. Indeed, in such optoelectronic devices 34, if the plate containing the optoelectronic devices 34 is attached to a support and the optoelectronic devices 34 are separated by laser machining to form weakened areas in the support, the light-emitting diodes adjacent to the desired cutting line will be significantly degraded.
[0041] The term "microwire" or "nanowire" refers to a three-dimensional structure that is elongated in a desired direction, having at least two dimensions, referred to as minor dimensions, in the range of 5 nm to 5 μm, preferably in the range of 100 nm to 2 μm, and more preferably in the range of 200 nm to 1.5 μm, and a third dimension, referred to as major dimension or height, that is equal to or greater than the largest of the minor dimensions, preferably equal to or greater than three times the largest, and more preferably equal to or greater than five times the largest. In certain embodiments, the height of each microwire or nanowire may be equal to or greater than 500 nm, preferably in the range of 1 μm to 50 μm. In the remainder of the specification, the term "wire" is used to mean "microwire or nanowire."
[0042] The cross section of the wire can have various shapes, for example oval, circular or polygonal, in particular triangular, rectangular, square or hexagonal. The term "average diameter" used in connection with the cross section of a wire is understood to denote a quantity related to the surface area of the wire in this cross section, which corresponds for example to the diameter of a disk having the same surface area as the cross section of the wire.
[0043] In the remainder of the specification, the term "pyramid" refers to a three-dimensional structure, a portion of which has the shape of a pyramid or an elongated cone. This pyramidal structure can be truncated, i.e., the top of the pyramid is absent, leaving a plateau. The base of the pyramid is inscribed within a square whose side dimensions are in the range of 100 nm to 10 μm, preferably in the range of 0.2 μm to 2 μm. The polygon forming the base of the pyramid may be a hexagon. The height of the pyramid between the base and the apex or top plateau is in the range of 100 nm to 20 μm, preferably in the range of 200 nm to 2 μm.
[0044] In the remainder of the specification, embodiments are described for optoelectronic devices comprising light-emitting diodes with microwires or nanowires, however, it is clear that these embodiments may also relate to optoelectronic devices comprising light-emitting diodes with micrometer- or nanometer-sized cones.
[0045] The wire preferably comprises more than 60% by weight, more preferably more than 80% by weight, of at least one semiconductor material, which may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound, or a combination of at least two of these compounds.
[0046] Examples of group III elements include gallium (Ga), indium (In), or aluminum (Al). Examples of III-N compounds include GaN, AlN, InN, InGaN, AlGaN, or AlInGaN. Other group V elements, such as phosphorus or arsenic, can also be used. Generally, elements within a III-V compound can be combined in various mole fractions. Examples of group II elements include group IIA elements, particularly beryllium (Be) and magnesium (Mg), and group IIB elements, particularly zinc (Zn), cadmium (Cd), and mercury (Hg). Examples of group VI elements include group VIA elements, particularly oxygen (O) and tellurium (Te). Examples of II-VI compounds include ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe, or HgTe. In general, the elements in the II-VI compounds can be combined in various mole fractions. The semiconductor material of the wire can include dopants, such as silicon to provide N-type doping of the III-N compounds, or magnesium to provide P-type doping of the III-N compounds.
[0047] Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, 3M, and 3N are each schematic partial cross-sectional views showing a structure obtained at one step in an embodiment of a method for manufacturing an optoelectronic device 34.
[0048] 3A, 3B, 3C, 3D, 3E, and 3F illustrate the fabrication of a plate 30 on a substrate 32 where the plate 30 contains multiple copies of nanowire or microwire optoelectronic devices 34.
[0049] Figure 3A shows - forming on a substrate 60 having opposite faces 62 and 64, face 62 being preferably flat at least at the level of the light-emitting diodes, a seed layer 66 made of a wire growth-promoting material and disposed on face 62; forming a stack of two insulating layers 68 and 70 over the seed layer 66, with an opening 72 exposing a portion of the seed layer 66; and growing a light-emitting diode LED in each opening 72, the LED contacting the seed layer 66 through the opening 72; 3A is a schematic partial cross-sectional view showing the structure obtained after , in which six light-emitting diodes LED 1 of one optoelectronic device 34 are shown as an example, and the light-emitting diodes LED 1 are arranged in groups of light-emitting diodes LED 2 .
[0050] Figure 3B shows forming an insulating layer 74 extending laterally over the lower portion of each light-emitting diode LED and over the insulating layer 70 between the light-emitting diodes LED; forming an electrode layer 76 covering each light emitting diode LED and further extending onto the insulating layer 74 between the light emitting diodes LED; forming a protective dielectric layer 78 extending over the electrode layer 76; and forming a planarization layer 80 extending over the protective dielectric layer 78 and having a flat free surface 81; FIG. 1 is a schematic partial cross-sectional view showing the structure obtained after
[0051] Figure 3C shows - attaching a handle 82 to the free surface 81; and removing the substrate 60 and seed layer 66 by any known method; FIG. 1 is a schematic partial cross-sectional view showing the structure obtained after
[0052] Figure 3D is a schematic partial cross-sectional view showing the structure obtained after forming an interconnect structure 83 having a stack of insulating layers 84 and conductive tracks 86 of different metallization levels on the insulating layer 68, whereby conductive tracks 86 of two metallization levels are shown as an example in Figure 3D, and conductive vias 88 extend through the stack of insulating layers 84, insulating layer 68, and insulating layer 74, connecting the electrode layer 76 to the conductive tracks 86, and the interconnect structure 83 preferably has a flat free surface 90.
[0053] FIG. 3E is a schematic partial cross-sectional view showing the structure obtained after a step of attaching the substrate 32 to the free surface 90, for example by molecular bonding.
[0054] Figure 3F shows - removing the handle 82 by any known method; - etching away the insulating layer 80 at certain pairs of light emitting diodes LED to expose these pairs of light emitting diodes and maintaining the insulating layer 80 between these pairs of light emitting diodes LED for other pairs of light emitting diodes LED; forming photoluminescent blocks 94, 96 covering the exposed pairs of light-emitting diodes LED (two photoluminescent blocks 94, 96 are shown as an example in FIG. 3F); - forming a reflective wall 98 between the photoluminescent blocks 94, 96; forming an encapsulation layer 100 covering each photoluminescent block 94, 96 and the protective dielectric layer 78 between the photoluminescent blocks 94, 96, the encapsulation layer 100 including the unetched portions of the insulating layer 80; and forming at least one color filter 102, e.g., one yellow filter, in the encapsulation layer 100, covering at least a portion of the photoluminescent blocks 94, 96 (FIG. 3F shows an example of one filter 102 covering both photoluminescent blocks 94, 96); FIG. 1 is a schematic partial cross-sectional view showing the structure obtained after
[0055] The structure resting on the substrate 32 forms the plate 30 mentioned above, and the free surface 36 of the sealing layer 100 corresponds to the surface 36 mentioned above.
[0056] Figure 3G is a schematic partial cross-sectional view illustrating the step previously described with respect to Figure 1C of attaching surface 36 to support 5 with layer of adhesive 50. In Figure 3G, support 5, now having two weakened areas 24, is shown with an opaque layer 104 on the opposite side of plate 30. Opaque layer 104 does not have to be provided; it makes support 5 opaque, facilitating machine detection and handling of the structure.
[0057] FIG. 3H is a schematic partial cross-sectional view illustrating the step described above with respect to FIG. 1D of removing substrate 32.
[0058] FIG. 3I is a schematic partial cross-sectional view showing the resulting structure after the step of forming openings 106 in the stack of insulating layers 84 to expose the conductive tracks 86.
[0059] Figure 3J is a schematic partial cross-sectional view showing the resulting structure after the step of removing opaque layer 104. Alternatively, opaque layer 104 can be removed at a later step in the manufacturing method, particularly after the step described below with respect to Figure 3L.
[0060] 3K is a schematic partial cross-sectional view showing the structure obtained after the step of forming conductive pads 108 in contact with the conductive tracks 86 exposed through the openings 106, with one conductive pad 108 shown as an example in FIG. 3K. Each conductive pad 108 may have a single layer structure or a multi-layer structure.
[0061] FIG. 3L is a schematic partial cross-sectional view illustrating the step described above in connection with FIG. 1E of etching trenches 52 in plate 30 at the desired separation lines of electronic devices 34.
[0062] FIG. 3M is a schematic partial cross-sectional view illustrating the step of thinning support 5, described above in connection with FIG. 1F.
[0063] FIG. 3N is a schematic partial cross-sectional view illustrating the step described above in connection with FIG. 1G of breaking the support 5 at the weakened regions 24 to separate the optoelectronic devices 34.
[0064] FIG. 4 illustrates an embodiment of a light-emitting diode (LED). According to one embodiment, each light-emitting diode (LED) includes a wire 110 that contacts the seed layer 66 through one of the openings 72 and a shell 112 that includes a stack of semiconductor layers that covers the sidewalls and top of the wire 110. This configuration is referred to as a radial. The aggregate formed by each wire 110 and its associated shell 112 constitutes a light-emitting diode (LED). FIG. 4 also illustrates a reflective layer 114, e.g., made of metal, that covers the electrode layer 76 between the wires 110 and is in direct physical contact with the electrode layer 76.
[0065] Shell 112 may include a stack of layers, including, among others, active layer 116 and bonding layer 118. Active layer 116 is the layer from which most, preferably all, of the light emitted by the light emitting diode (LED) is emitted. By way of example, active layer 116 may include a confinement mechanism such as a single quantum well or multiple quantum wells. Bonding layer 118 may include a stack of semiconductor layers of the same III-V materials as wire 110, but of the opposite conductivity type to wire 110.
[0066] Figure 5 shows an example of a light emitting diode LED. The light emitting diode LED shown in Figure 5 has all the elements of the light emitting diode LED shown in Figure 4, except that a shell 112 is provided only on top of the wire 110. This configuration is called axial.
[0067] For example, a light emitting diode LED can be formed by growing wire 110 in opening 72 and forming a shell 112 covering wire 110 by metal organic chemical vapor deposition (MOCVD) or any other suitable method.
[0068] Figure 6 illustrates an embodiment of a light emitting diode (LED). The light emitting diode (LED) illustrated in Figure 6 has a two-dimensional structure in that it is fabricated by forming a substantially planar stack of semiconductor layers on a substrate 60 and then defining the light emitting diode, for example, by etching a trench in the stack of semiconductor layers. The light emitting diode illustrated in Figure 6 has a semiconductor layer 120 doped with a first conductivity type and covered by an active layer 122, which is itself covered by a semiconductor layer 124 doped with a second conductivity type.
[0069] The substrate 60 may be a monolithic structure or a layer covering a support formed of another material. The substrate 60 is preferably a semiconductor substrate, for example, silicon, germanium, silicon carbide, a substrate formed of a III-V compound such as GaN or GaAs, or a ZnO substrate. The substrate 60 is preferably a monocrystalline silicon substrate. The substrate 60 may also be a multilayer structure of the silicon-on-insulator type, also known as SOI.
[0070] The seed layer 66 is formed of a material that promotes wire growth. By way of example, the material comprising the seed layer 66 may be a nitride, carbide, or boride of a transition metal from columns IV, V, or VI of the periodic table of the elements, or a combination of these compounds.
[0071] According to another embodiment, the seed layer 66 may not be provided. According to another embodiment, the seed layer 66 may be replaced by a seed pad formed, for example, at the bottom of the opening 72.
[0072] Each of the insulating layers 68, 70, 74, 78, 80 and the sealing layer 100 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si x N y , where x is approximately 3 and y is approximately 4, e.g., Si3N4), silicon oxynitride (e.g., SiO x N y The insulating layers 68, 70, 74, 78, and 80 may be formed of, for example, Si2ON2, aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium dioxide (TiO2), or diamond, which have the general formula: Each insulating layer 68, 70, 74, 78, and 80 may be a single layer structure or a stack of two or more layers.
[0073] The electrode layer 76 is adapted to pass electromagnetic radiation emitted by the light-emitting diode. The material forming the electrode layer 76 may be a transparent conductive material such as indium tin oxide (ITO), zinc oxide doped with aluminum or gallium, or graphene. The thickness of the electrode layer 76 may be in the range of 0.01 μm to 10 μm.
[0074] According to one embodiment, each photoluminescent block 94, 96 is positioned opposite one of the light emitting diodes LED or a set of light emitting diodes LED, and each photoluminescent block 94, 96 comprises a phosphor adapted to emit light at a wavelength different from the wavelength of the light emitted by the associated light emitting diode LED when excited by the light emitted by the associated light emitting diode LED.
[0075] Various embodiments and variations have been described, and those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily occur to those skilled in the art.
[0076] Finally, the actual implementation of the embodiments and variations described herein is within the skill of those skilled in the art based on the functional representations given above.
[0077] This patent application claims priority from French Patent Application No. 22 / 14577, which is considered an integral part of this specification.
Claims
1. A method for manufacturing an electronic device (34), comprising: - manufacturing a plate (30) containing multiple copies of an electronic device (34) and attached to a substrate (32); - using a laser to create weakened areas (24) in the support (5), - after forming said weakened areas (24), attaching said plate (30) to said support (5); - removing the base plate (32) after attaching the plate (30) to the support (5); - after removing said substrate (32), etching said plate in the extension of said weakened area (24); - breaking the support (5) at the weakened area (24) and separating the electronic device (34).
2. 2. A method as claimed in claim 1, wherein the attachment of the plate (30) to the support (5) is performed by bonding.
3. 3. A method according to claim 2, wherein the attachment of the plate (30) to the support (5) is carried out by bonding with an adhesive layer (50).
4. 3. A method as claimed in claim 2, wherein the attachment of the plate (30) to the support (5) is carried out by molecular bonding.
5. 5. The method according to claim 1, further comprising the step of thinning the support (5) after attaching the plate (30) to the support (5) and before breaking the support (5) at the weakened area (24).
6. A method according to any one of claims 1 to 5, wherein the etching of the plate (30) in the extension of the weakened area (24) is carried out by dry etching or wet etching.
7. 7. The method according to claim 1, wherein the step of attaching the plate (30) to the support (5) after forming the weakened areas (24) comprises the step of aligning a first mark on the support (5) with a second mark on the plate (30) so that each electronic device (34) to be separated is located between two of the weakened areas (24).
8. A method according to any one of the preceding claims, wherein the support (5) is laser transparent at least in the weakened areas (24).
9. A method according to any one of the preceding claims, wherein the support (5) is at least partly made of glass, quartz or sapphire.
10. The method of any one of claims 1 to 9, wherein the electronic device (34) comprises a light emitting diode (LED).
11. 11. The method of claim 10, wherein each light emitting diode (LED) comprises a nanometer- or micrometer-sized three-dimensional semiconductor element (110) corresponding to a nanometer- or micrometer-sized microwire, nanowire, or pyramidal structure, and an active layer (112) covering the three-dimensional semiconductor element (110).
Citation Information
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