Systems and methods for operating a low density parity check bit-flip decoder

Abstract

Disclosed herein are systems and methods for operating a low-density parity-check (LDPC) bit-flip decoder. An LDPC codeword is received, and each bit of the LDPC codeword is classified as either a high-reliability bit or a low-reliability bit based on at least one criterion. The LDPC codeword is iteratively processed through multiple iterations based on a parity-check equation associated with each bit of the LDPC codeword, thereby generating a processed LDPC codeword. For each iteration of the multiple iterations, the iterative processing includes inverting at least one bit of the LDPC codeword, such that for the first n iterations of the multiple iterations, no more than 33% of the total number of flipped bits are classified as high-reliability bits. The processed LDPC codeword is decoded.

Description

[Technical Field]

[0001] The present disclosure relates to low-density parity-check (LDPC) bit-flip decoders, and more particularly to improved systems and methods for operating LDPC bit-flip decoders that correct bit errors in LDPC codewords. Summary of the Invention

[0002] According to the present disclosure, a method for operating an LDPC bit-flip decoder that corrects bit errors in an LDPC codeword using bit reliability information (e.g., soft reliability information) is provided. The method includes receiving an LDPC codeword, classifying each bit of the LDPC codeword as either a high-reliability bit or a low-reliability bit based on at least one criterion, and iteratively processing the LDPC codeword through multiple iterations to generate a processed LDPC codeword based on a parity check equation associated with each bit of the LDPC codeword. For each iteration of the multiple iterations, the iterative processing includes inverting at least one bit of the LDPC codeword, such that for the first n iterations of the multiple iterations, bits classified as high-reliability bits do not account for more than 33% of the total number of flipped bits. The method further includes decoding the processed LDPC codeword.

[0003] In some embodiments, the first n iterations may be equal to six.

[0004] In some embodiments, the at least one criterion may include soft confidence information indicating the likelihood that the bit value of each bit in the LDPC codeword is correct.

[0005] In some embodiments, the soft reliability information may be obtained by performing a NAND soft bit read on the storage cells storing the LDPC codewords.

[0006] In some embodiments, the iterative process may include storing bits of the LDPC codeword in a buffer for use in implementing a bit-flipping algorithm, with each bit of the LDPC codeword as a separate variable node, and determining, for each iteration of a plurality of iterations, whether one or more check nodes associated with the separate variable nodes are unfilled based on separate parity check equations for the one or more check nodes calculated during the iteration, identifying bits to be inverted from among the stored bits of the LDPC codeword in response to determining that one or more check nodes are unfilled, and inverting the identified bits, unless the current iteration is less than or equal to n iterations and unless the identified bit is a high-reliability bit and inverting the bit would result in more than 33% of the total number of bits being inverted.

[0007] In some embodiments, decoding the processed LDPC codeword may include determining that all check nodes associated with distinct variable nodes are filled.

[0008] In some embodiments, identifying bits to invert from among the stored bits of the LDPC codeword may include determining that more than half of the check nodes associated with the variable nodes storing the bits are unfilled.

[0009] In some embodiments, receiving the LDPC codeword may include receiving the LDPC codeword from a NAND flash memory.

[0010] In some embodiments, the method may further include obtaining an initial syndrome for the LDPC codeword, and setting the n iterations based on the obtained initial syndrome.

[0011] In some embodiments, an error correction control (ECC) decoder is provided. The ECC decoder includes a buffer and circuitry. The circuitry is configured to receive an LDPC codeword, classify each bit of the LDPC codeword as either a high-reliability bit or a low-reliability bit based on at least one criterion, and iteratively process the LDPC codeword through multiple iterations to generate a processed LDPC codeword based on a parity check equation associated with each bit of the LDPC codeword. For each iteration of the multiple iterations, the circuitry is configured to iteratively process the LDPC codeword by flipping at least one bit of the LDPC codeword, such that for a first n iterations of the multiple iterations, no more than 33% of the total number of flipped bits comprise bits classified as high-reliability bits. The circuitry is further configured to decode the processed LDPC codeword.

[0012] In some embodiments, a non-transitory computer-readable medium is provided having instructions encoded thereon that, when executed by a circuit, cause the circuit to receive an LDPC codeword, classify each bit of the LDPC codeword as either a high-reliability bit or a low-reliability bit based on at least one criterion, and iteratively process the LDPC codeword through multiple iterations based on a parity check equation associated with each bit of the LDPC codeword to generate a processed LDPC codeword. For each iteration of the multiple iterations, the instructions cause the circuit to iteratively process the LDPC codeword by inverting at least one bit of the LDPC codeword, such that for the first n iterations of the multiple iterations, no more than 33% of the total number of inverted bits include bits classified as high-reliability bits. The instructions also cause the circuit to decode the processed LDPC codeword. [Brief explanation of the drawings]

[0013] The following description includes illustrations of figures that illustrate exemplary implementations of embodiments of the present disclosure. These figures are to be understood as examples, not as limitations. References herein to one or more "embodiments" should be understood to describe particular features, structures, and / or characteristics present in at least one implementation. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" appearing herein may describe various embodiments and implementations, and do not necessarily all refer to the same embodiment. However, these phrases are not necessarily mutually exclusive.

[0014] [Figure 1] FIG. 2 illustrates an exemplary block diagram of a storage device in accordance with some embodiments of the present disclosure.

[0015] [Figure 2] 2 illustrates an example probability distribution of threshold voltages for storage cells of the memory of FIG. 1 in accordance with some embodiments of the present disclosure.

[0016] [Figure 3] FIG. 2 illustrates an example block diagram of a graph for implementing an iterative bit-flipping algorithm, in accordance with some embodiments of the present disclosure.

[0017] [Figure 4] FIG. 10 illustrates an example flowchart of a control process for decoding LDPC codewords in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] Error correction codes (ECCs) may be used to protect data or recover from errors associated with the medium (e.g., flash memory) on which the data is stored. ECC-encoded data read from a storage device (e.g., a NAND solid-state drive) may be able to identify and correct multiple such errors. In one example, the ECC-encoded data may include a codeword, which includes a combination of data and parity data (e.g., parity bits). Errors in the resulting codeword may be referred to as the raw bit error rate (RBER). To mitigate the effects of a higher RBER (e.g., due to increased storage device density), additional spare bytes may be added to the data (e.g., in NAND flash memory) or the data may be encoded into larger codewords that include multiple parity bytes. However, as the number of spare bytes added increases or the size of the codeword increases, the complexity of the algorithm for decoding the codeword also increases.

[0019] In some examples, data is encoded using an LDPC code (e.g., an LDPC codeword). The LDPC codeword can provide a relatively high level of error correction capability when decoded by a decoder implementing an algorithm such as a sum-product algorithm (SPA) or a min-sum (MS) algorithm. However, decoders using SPA or MS require large circuitry (e.g., millions of gates) to maintain throughput when decoding the LDPC codeword. Therefore, in some examples, it may be advantageous to use a smaller, less complex LDPC bit-flipping decoder that implements a bit-flipping algorithm. However, an LDPC bit-flipping decoder that implements a bit-flipping algorithm and has lower error correction capabilities may result in a high uncorrectable bit error rate (UBER) or a reduced useful life (e.g., based on an RBER requirement) of a storage device storing the LDPC codeword.

[0020] In accordance with the present disclosure, improved systems and methods are provided for operating an LDPC bit-flipping decoder that uses soft reliability information to correct bit errors in LDPC codewords.

[0021] The subject matter of this disclosure may be better understood with reference to FIGS.

[0022] 1 illustrates an exemplary block diagram of a storage device 101 in accordance with some embodiments of the present disclosure. As illustrated, the storage device 101 may include a controller 102 and a memory 108. The controller 102 may include an ECC encoder 104 that generates and stores codewords in the memory 108, and an ECC decoder 106 that corrects errors in the ECC-encoded data using a bit-flipping algorithm. In some embodiments, the controller 102 may include circuitry, including memory, and one or more processors configured to execute instructions stored in the memory (e.g., a non-transitory computer-readable medium) to perform the functions described herein (e.g., to implement the ECC encoder 104 and the ECC decoder 106). In some embodiments, the circuitry may include one or more application-specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In one embodiment, storage device 101 may be a NAND solid state drive (SSD), and memory 108 may include NAND flash memory. However, this is merely one example, and memory 108 may include any suitable type of non-volatile or volatile memory, such as random-access memory (RAM), dynamic RAM (DRAM), double data rate synchronous dynamic RAM (DDR SDRAM), static random-access memory (SRAM), thyristor RAM (T-RAM) or zero-capacitor RAM (Z-RAM), multi-threshold level NAND flash memory, NOR flash memory, etc.

[0023] ECC encoder 104 (e.g., an LDPC encoder) may encode data 103 (e.g., corresponding to a write request) using an LDPC code. The resulting LDPC codeword 105 may then be stored in memory 108. The stored LDPC codeword 105 may then be read from memory 108 (e.g., corresponding to a read request). However, because the obtained LDPC codeword 105 may contain errors, the obtained LDPC codeword 105 may be transferred to memory 110 of ECC decoder 106 (e.g., an LDPC decoder) and stored in LDPC codeword buffer 114. ECC decoder 106 may also obtain bit reliability information (e.g., soft reliability information 109), which indicates the reliability of bits in the obtained LDPC codeword 105, as described in more detail below with reference to FIG. 2. The soft reliability information 109 may be stored in soft reliability information buffer 112. In some embodiments, memory 110 may include a volatile memory such as an SRAM.

[0024] Correction module 116 of ECC decoder 106 may decode the obtained LDPC codeword 105 stored in LDPC codeword buffer 114. For example, limiting circuit 118 may implement a bit-flipping algorithm that uses soft reliability information 109 stored in soft reliability information buffer 112 to selectively flip bits of the obtained LDPC codeword 105 to identify and attempt to correct any errors and successfully decode the obtained LDPC codeword 105, as described in more detail below. In some embodiments, a working copy of the obtained LDPC codeword 105 may be stored in a separate buffer. After ECC decoder 106 successfully decodes the obtained LDPC codeword 105, ECC decoder 106 may output decoded data 111 (e.g., to a device that requested the data).

[0025] FIG. 2 illustrates an example probability distribution 200 of threshold voltages for storage cells of memory 108 of FIG. 1, according to some embodiments of the present disclosure. As shown, the x-axis is the threshold voltage (V t ), with the y-axis representing probability. In some embodiments, memory 108 of FIG. 1 may be a NAND flash memory. While FIG. 2 shows a single-level cell (SLC), it should be understood that the NAND flash memory may be a multi-level cell. When a NAND flash memory is read, the expected threshold V t A read reference voltage at may be applied to the control gate of the storage cell. In one example, if current flows through the storage cell (e.g., a transistor), the value stored in the storage cell is detected as a logic 1. Otherwise, if no current flows, the value stored in the storage cell is detected as a logic 0. In another example, the logic 0 and logic 1 may be reversed.

[0026] However, the threshold voltages may not always fall within the expected distribution. In this case, some transistors may be on the wrong side of the read reference voltage, resulting in an incorrect logic bit value being read. For example, as shown, if either L0 or L1 straddles read voltage 202, an incorrect logic bit value may be read. Therefore, to obtain soft confidence information 109, a soft read of the storage cells storing LDPC codeword 105 may be performed by applying additional read voltages (e.g., read strobes) on either side of read voltage 202. For example, as shown, a three-strobe read may be performed by also applying read voltages 204 and 206. The read reference voltages (e.g., 202, 204, and 206) may define "bins" or "zones" within which threshold voltages may exist (below the lowest read reference voltage at which current flows through the transistor cell and above the highest read reference voltage at which current does not flow through the transistor cell). The bins may be assigned log-likelihood ratio (LLR) values ​​based on assumptions about normal Gaussian distributions expected based on test data. Based on the LLR value, each bit may be classified as a high-reliability bit (e.g., a reliable bit) or a low-reliability bit (e.g., an unreliable bit). For example, in the illustrated example, the "middle bin" of the three-strobe read may be classified as a low-reliability bit. However, this is just one example, and any suitable soft read with any suitable number of strobe reads may be used by the ECC decoder 106 to classify each bit of the LDPC codeword 105 as a high-reliability bit or a low-reliability bit.

[0027] 3 illustrates an example block diagram of a graph 300 for implementing an iterative bit-flipping algorithm in accordance with some embodiments of the present disclosure. Graph 300 may be a modified Tanner graph and illustrates how an LDPC codeword may be represented using variable nodes and check nodes. For example, as illustrated, a retrieved LDPC codeword 105 may be loaded into multiple variable nodes 302A-302G (collectively referred to as variable nodes 302). Seven variable nodes 302 may represent seven bits of an LDPC codeword retrieved from memory 108 during a read operation. While seven-bit LDPC codewords are discussed, it should be understood that much larger LDPC codewords (e.g., LDPC codewords ranging from 100 bits to 140,000 bits) may be decoded by ECC decoder 106.

[0028] Bit information (“information”) 304A-304G (collectively referred to as bit information 304) may include classification information for each bit (e.g., whether it is a high-reliability bit or a low-reliability bit) determined from the soft reliability information 109. Check nodes 306A-306E (collectively referred to as check nodes 306) may represent one or more parity check equations. As shown, each individual check node 306 may include a check node bit (CNB) 308A-308E to maintain the node's check node information. During operation, if one or more parity check equations associated with a check node 306 fail or are not satisfied, the CNB 308 of the check node 306 may be assigned a binary value of 1. In some examples, an ECC decoder 106 implementing a bit-flipping algorithm may use an iterative decoding scheme for the 7-bit LDPC codeword shown in graph 300. In some embodiments, the original input values ​​of each of the seven variable nodes 302 may be stored so that if a variable node 302 is inverted, a copy of the original input value may be retained.

[0029] 4 illustrates an example flowchart 400 of a control process for decoding an LDPC codeword in accordance with some embodiments of the present disclosure. In some embodiments, the LDPC codeword may be a 7-bit LDPC codeword represented by graph 300 of FIG. 3, where a bit-flipping algorithm is implemented and soft reliability information is used. For ease of explanation, elements of ECC decoder 106 of FIG. 1 and graph 300 of FIG. 3 may be used to describe various portions of the control process.

[0030] At 402, the ECC decoder 106 receives the LDPC codeword 105. For example, the ECC decoder 106 may retrieve the LDPC codeword 105 from the memory 108 (e.g., in response to receiving a read request).

[0031] At 404, ECC decoder 106 receives soft reliability information for LDPC codeword 105. In some embodiments, the soft reliability information (e.g., soft reliability information 109) may be obtained by performing a NAND soft bit read on storage cells of memory 108 that store LDPC codeword 105. In some embodiments, the soft bit read may be a 3-strobe read, a 5-strobe read, or a 7-strobe read (e.g., based on the decoding requirements of the LDPC codeword).

[0032] At 406, the ECC decoder 106 may classify each bit of the LDPC codeword 105 as either a high-reliability bit or a low-reliability bit based on at least one criterion (e.g., soft reliability information 109). In one example, if a three-strobe read is used, bits classified as "middle bits" (e.g., assigned to the inner two bins of the three-strobe read) may be classified as low-reliability bits, and other bits (e.g., assigned to the outer bins of the three-strobe read) may be classified as high-reliability bits. In some embodiments, 10% of the bits based on the soft bit read may be classified as low-reliability bits. However, it should be understood that any suitable method of classifying bits based on soft reliability information may be used.

[0033] At 408, ECC decoder 106 stores the bits of LDPC codeword 105 in a buffer (e.g., LDPC codeword buffer 114) for use in implementing the bit-flipping algorithm, with each bit of the LDPC codeword as a separate variable node. For example, as shown in FIG. 3, each bit of LDPC codeword 105 may be stored in a variable node of variable nodes 302A-302G. Furthermore, ECC decoder 106 may store bit information 304A-304G in separate buffers associated with variable nodes 302A-302G, respectively. Bit information 304A may include information indicating the classification of each bit (e.g., determined at 406).

[0034] At 410, the ECC decoder 106 may determine whether one or more check nodes 306A-306E associated with distinct variable nodes 302 are unsatisfied based on distinct parity check equations for the one or more check nodes 306 calculated during the iterations of the bit-flipping algorithm. In some embodiments, the ECC decoder 106 may determine an initial syndrome for the LDPC codeword 105 based on the initial number of unsatisfied check nodes 306. As described above, a CNB 308 of a check node 306 having a binary value of 0 may indicate that the parity check equation for the check node 306 is satisfied. Thus, at 412, the limiting circuit 118 may determine whether all check nodes 306 are satisfied by examining the CNBs 308 and determining whether all CNBs 308 have a binary value of 0. If all check nodes 306 are satisfied (“yes” at 412), control proceeds to 414, and the LDPC codeword is successfully decoded. After LDPC codeword 105 is successfully decoded, correction module 116 may forward the data (e.g., data 111) encoded in LDPC codeword 105 for transmission to the originator of the request (e.g., a read request). Otherwise (No at 412), control proceeds to 416.

[0035] At 416, the ECC decoder 106 determines whether the maximum number of iterations of the bit-flipping algorithm has been reached. In some embodiments, the maximum number of bit-flipping iterations may be based on the number of times that correction of the LDPC codeword 105 can be attempted (iterated) before the LDPC codeword 105 is deemed to have an uncorrectable error by the bit-flipping algorithm. In one embodiment, the maximum number of bit-flipping iterations is set to a fixed number (e.g., 30). In another embodiment, the maximum number of bit-flipping iterations is set based on the probability of correctly decoding the LDPC codeword (e.g., based on the number of unfilled check nodes 306 after n iterations). In response to a determination that the maximum number of iterations has been reached ("yes" at 416), control proceeds to 418. Otherwise ("no" at 416), control proceeds to 420.

[0036] At 418, if the maximum number of iterations has been reached and the LDPC codeword 105 has not been successfully decoded, the correction module 116 may indicate the decoding failure (e.g., by sending a decode failure notification to the originator of the read request). In some embodiments, the LDPC codeword 105 may be decoded by an SPA or MS decoder.

[0037] At 420, the ECC decoder 106 may identify one or more bits of the LDPC codeword 105 to invert. For example, the limiting circuit 118 may identify one or more bits to invert based on the number of unfilled check nodes 306 associated with each variable node 302. For example, any suitable bit-flip algorithm may be used to identify whether a bit should be inverted. In some embodiments, a bit may be identified to be inverted if more than 50% of the check nodes 306 associated with a variable node 302 are unfilled. In some embodiments, additional information (e.g., whether the bit has been inverted before) may be used to identify the bit to invert.

[0038] At 422, the ECC decoder 106 determines, for each of one or more bits identified to be inverted, whether the identified bit to be inverted is a high-reliability bit. For example, the limiting circuit 118 may examine the bit information 304 associated with each identified bit. For convenience of explanation, this control process describes one bit identified to be inverted herein; however, it should be understood that more than one bit may be identified to be inverted during each iteration of the bit-flipping algorithm. In response to a determination that the identified bit is not a high-reliability bit ("No" at 422), control proceeds to 428. Otherwise ("Yes" at 422), control proceeds to 424.

[0039] At 424, the ECC decoder 106 determines whether the current iteration of the iterative bit-flipping algorithm is less than or equal to n iterations. In some embodiments, n may be equal to 6. However, this is merely one example, and n may be set to any suitable number. For example, n may be adjusted based on the initial syndrome weight values ​​(e.g., n may be set to a smaller value for lower syndrome weight values ​​or to a larger value for higher syndrome weight values). That is, as the number of unfilled check nodes 306 decreases, the value of n may also decrease. By preventing certain high-reliability bits from being flipped during the first n iterations based on soft reliability information by the control process, the UBER of the ECC decoder 106 may be improved. In response to a determination that the current iteration of the bit-flipping algorithm is less than or equal to n iterations (“yes” at 424), control proceeds to 426. Otherwise (“no” at 424), control proceeds to 428.

[0040] At 426, the ECC decoder 106 determines whether flipping the identified bit would result in high-confidence bits comprising more than 33% (e.g., a threshold flip percentage) of the total number of flipped bits. For example, as bits are flipped, the limiting circuit 118 may track the ratio of the number of high-confidence bits flipped to the total number of flipped bits (e.g., across all iterations of the bit-flipping algorithm). In response to a determination that flipping the bit would result in high-confidence bits comprising more than 33% of the total number of flipped bits ("yes" at 426), control may proceed to 430. Otherwise ("no" at 426), control may proceed to 428.

[0041] In some embodiments, the threshold flip percentage for determining whether to flip a bit may be set to a value between 0% (e.g., not allowing any high-confidence bit flips during the first n iterations of the bit-flipping algorithm) and 33% (e.g., limiting high-confidence bit flips to less than 33% of the total number of flipped bits). In some embodiments, the threshold flip percentage may be set based on characteristics of one or more LDPC codes being decoded by ECC decoder 106, syndrome weights of the LDPC codewords, or RBER. In one example, the threshold flip percentage may be set to 10%. However, this is merely one example, and the threshold flip percentage may be set to any appropriate percentage within the range of 0 to 33%, and may be set based on characteristics of one or more LDPC codewords being decoded by ECC decoder 106, syndrome weights of the LDPC codewords, RBER, etc.

[0042] In some embodiments, the ECC decoder 106 may prevent flipping of any high-confidence bits during the first n iterations of the bit-flipping algorithm, unless the variable node 302 associated with the identified high-confidence bit is connected to a large number of unfilled check nodes 306 (e.g., indicating a high probability that the bit should be flipped). In some embodiments, if the weight of the initial syndrome is low (e.g., there are very few unfilled check nodes 306), the ECC decoder 106 may allow the identified high-confidence bit to be flipped. For example, the ECC decoder 106 may exclude the bit information 304 associated with that bit. In some embodiments, the bit value of the flipped erasure bit may not be included in the count of the total number of flipped bits.

[0043] At 428, the ECC decoder 106 may invert the identified bits. For example, the limiting circuit 118 may cause the bit inversion circuit 122 to invert the respective bit of the variable node 302 to which the identified bits belong (e.g., from a binary value of 1 to a binary value of 0). Control then returns to 410 for the next iteration of the bit-flipping algorithm to generate a decodable processed LDPC codeword.

[0044] At 430, the ECC decoder 106 may prevent the identified bits from being inverted. For example, the limiting circuit 118 may prevent the bit inversion circuit 122 from inverting the respective bits of the variable node 302 to which the identified bits belong. Control then returns to 410 for the next iteration of the bit-flipping algorithm to generate a decodable processed LDPC codeword.

[0045] The processes described above are intended to be illustrative and not limiting, and those skilled in the art will appreciate that steps of the processes discussed herein may be omitted, modified, combined, and / or rearranged, and any additional steps may be performed without departing from the scope of the present invention.

[0046] The foregoing merely illustrates the principles of the present disclosure, and various modifications may be made by those skilled in the art without departing from the scope of the present disclosure. The above-described embodiments are presented for purposes of illustration and not limitation. The present disclosure may take many forms other than those expressly described herein. It is therefore emphasized that the present disclosure is not limited to the methods, systems, and apparatuses expressly disclosed, but is intended to include all such modifications and variations, including those within the spirit of the following claims.

Claims

1. receiving a low-density parity check (LDPC) codeword; classifying each bit of the LDPC codeword as either a high reliability bit or a low reliability bit based on at least one criterion; iteratively processing the LDPC codeword for a plurality of iterations to generate a processed LDPC codeword based on a parity check equation associated with each bit of the LDPC codeword, wherein for each iteration of the plurality of iterations, the iterative processing inverts at least one bit of the LDPC codeword, such that for a first n iterations of the plurality of iterations, no more than 33% of the total number of inverted bits include bits classified as reliable bits; and decoding the processed LDPC codeword; A method for providing the above.

2. The method of claim 1 , wherein the first n iterations equal six.

3. The method of claim 1 , wherein the at least one criterion is soft confidence information indicating the likelihood that a bit value of each bit in the LDPC codeword is correct.

4. The method of claim 3 , wherein the soft reliability information is obtained by performing a NAND soft bit read on a storage cell storing the LDPC codeword.

5. The repeating process storing bits of the LDPC codeword in a buffer for use in implementing a bit-flipping algorithm, with each bit of the LDPC codeword as a separate variable node; and For each iteration of said plurality of iterations, determining whether the one or more check nodes associated with the distinct variable nodes are unsatisfied based on distinct parity check equations for one or more check nodes calculated during the iteration; identifying bits to invert from among the stored bits of the LDPC codeword in response to determining that one or more check nodes are not filled; and inverting the identified bit, if the current iteration is less than or equal to said n iterations; and If the identified bit is a high-reliability bit, and if the bit is inverted, the bits classified as high-reliability bits will be included in more than 33% of the total number of inverted bits. Excluding The method of claim 1 , comprising:

6. 6. The method of claim 5, wherein decoding the processed LDPC codeword comprises determining that all check nodes associated with the distinct variable node are filled.

7. 6. The method of claim 5, wherein identifying the bit to invert from among the stored bits of the LDPC codeword comprises determining that more than half of the check nodes associated with the variable node storing the bit are unfilled.

8. The method of claim 1 , wherein receiving the LDPC codeword comprises receiving the LDPC codeword from a NAND flash memory.

9. obtaining an initial syndrome of the LDPC codeword; and setting the n iterations based on the obtained initial syndromes The method of claim 1 , further comprising:

10. a buffer; and A circuit comprising: receiving a low-density parity check (LDPC) codeword; classifying each bit of the LDPC codeword as either a high-reliability bit or a low-reliability bit based on at least one criterion; iteratively processing the LDPC codeword through a plurality of iterations to generate a processed LDPC codeword based on a parity check equation associated with each bit of the LDPC codeword, wherein for each iteration of the plurality of iterations, the circuitry is configured to iteratively process the LDPC codeword by flipping at least one bit of the LDPC codeword, such that for a first n iterations of the plurality of iterations, no more than 33% of a total number of flipped bits include bits classified as reliable bits; and Decode the processed LDPC codeword. The circuit is configured as follows: An error correction control (ECC) decoder comprising:

11. 11. The ECC decoder of claim 10, wherein the first n iterations equal six.

12. 11. The ECC decoder of claim 10, wherein the at least one criterion is soft confidence information indicating the likelihood that a bit value of each bit in the LDPC codeword is correct.

13. 13. The ECC decoder of claim 12, wherein the soft reliability information is obtained by performing a NAND soft bit read on storage cells storing the LDPC codeword.

14. The circuit storing bits of the LDPC codeword in the buffer for use in implementing a bit-flipping algorithm, with each bit of the LDPC codeword as a separate variable node; and For each iteration of said plurality of iterations, determining whether the one or more check nodes associated with the distinct variable nodes are unsatisfied based on distinct parity check equations for one or more check nodes calculated during the iteration; In response to determining that one or more check nodes are not filled, identifying bits to invert among the stored bits of the LDPC codeword; and inverting the identified bit, if the current iteration is less than or equal to said n iterations; and If the identified bit is a high-reliability bit, and if the bit is inverted, the bits classified as high-reliability bits will be included in more than 33% of the total number of inverted bits. Excluding 11. The ECC decoder of claim 10, configured to iteratively process the LDPC codeword by

15. 15. The ECC decoder of claim 14, wherein the circuitry is configured to decode the processed LDPC codeword by determining that all check nodes coupled to the distinct variable node are filled.

16. 15. The ECC decoder of claim 14, wherein the circuitry is configured to identify the bit to invert among the stored bits of the LDPC codeword by determining that more than half of the check nodes coupled to the variable node storing that bit are unfilled.

17. 17. An ECC decoder according to any one of claims 10 to 16, wherein the circuitry is configured to receive the LDPC codeword by receiving the LDPC codeword from a NAND flash memory.

18. A computer program encoded with instructions that, when executed by a circuit, cause the circuit to: receiving a low-density parity check (LDPC) codeword; classifying each bit of the LDPC codeword as either a high-reliability bit or a low-reliability bit based on at least one criterion; iteratively processing the LDPC codeword through a plurality of iterations to generate a processed LDPC codeword based on a parity check equation associated with each bit of the LDPC codeword, wherein for each iteration of the plurality of iterations, the instructions cause the circuit to iteratively process the LDPC codeword by inverting at least one bit of the LDPC codeword such that, for a first n iterations of the plurality of iterations, no more than 33% of a total number of inverted bits comprise bits classified as reliable bits; and Decode the processed LDPC codeword. A computer program that makes things happen.

19. 20. The computer program of claim 18, wherein the first n iterations equal six.

20. 20. The computer program of claim 18 or 19, wherein the at least one criterion is soft confidence information indicating the likelihood that a bit value of each bit in the LDPC codeword is correct.

Images