Semiconductor device manufacturing method and semiconductor device

Abstract

In at least one embodiment, the method is for manufacturing a semiconductor device (1) and includes, in the order listed, the following steps: A) providing a semiconductor body (2) having a top surface (20), the semiconductor body (2) being based on SiC; B) producing a first layer (21) of the semiconductor body (2) adjacent the top surface (20) by doping with a dopant (4); C) applying a carbon-containing layer (3) to the top surface (20); D) implanting C into the first layer (21) through the carbon-containing layer (3); and E) performing a temperature treatment of the semiconductor body (2) while the carbon-containing layer (3) is still present on the top surface (20).

Description

[Technical Field]

[0001] A method for manufacturing a semiconductor device is provided, as well as a corresponding semiconductor device. [Background technology]

[0002] The reference L. Storasta et al., "Reduction of traps and improvement of carrier lifetime in 4H-SiC," Appl. Phys. Lett. 90, 062116 (2007); https: / / doi.org / 10.1063 / 1.2472530, mentions the reduction of deep level defects.

[0003] The literature HMAyedh et al., "Elimination of carbon vacancies in 4H-SiC epi-layers by near-surface ion implantation: Influence of the species", Journal of Applied Physics 118, 175701 (2015); https: / / doi.org / 10.1063 / 1.4934947, mentions methods to address carbon vacancies.

[0004] K. Hamada et al., U.S. Patent Application Publication No. 2016 / 0247894, discloses a method for manufacturing a semiconductor device capable of reducing on-resistance, which includes forming a drift layer on a substrate and forming an ion-implanted layer on the surface of the drift layer. An excess carbon region is formed in the drift layer. The drift layer is then heated.

[0005] The literature B. Zippelius et al., "High Temperature annealing of n-type 4H-SiC: Impact on intrinsic defects and carrier lifetime," J. Appl. Phys. 111, 033515 (2012); http: / / dx.doi.org / 10.1063 / 1.3681806, mentions the carrier lifetime of SiC. Summary of the Invention [Problem to be solved by the invention]

[0006] The object is to provide a semiconductor device with improved electrical behavior. [Means for solving the problem]

[0007] This object is achieved, inter alia, by a power semiconductor device and a method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0008] In at least one embodiment, a method for manufacturing a semiconductor device comprises the following steps, which may be performed in the listed order: A) providing a semiconductor body having a top surface, the semiconductor body being based on SiC; B) producing a first layer of semiconductor body, for example next to the top surface, by doping with a dopant; C) applying a carbon-containing layer to the top surface; D) injecting C into the first layer through the carbon-containing layer; E) performing a temperature treatment of the semiconductor body while the carbon-containing layer is still present on top.

[0009] This method can efficiently achieve carbon vacancy removal by low dose C implantation using a carbon-containing layer, also called a C-cap, thus enabling the removal of carbon vacancies during device fabrication.

[0010] Carbon vacancy (V C V:carbon vacancy) is one of the most important point defects in n-type 4H silicon carbide (4H-SiC). C is the conduction band edge (E C Z, located at 0.65 eV and 1.6 eV below the conduction band edge, respectively. 1 / 2 and E.H. 6 / 7 This gives rise to two electrically active levels in the band gap, labeled Z. 1 / 2 are recombination centers, which affect the charge carrier lifetime in bipolar devices and increase the leakage current in unipolar devices.

[0011] V C Methods for reducing the concentration [V C [See the above citation] was presented by Storasta et al. This involves shallow box-profile C ion implantation into a SiC epilayer with a depth of 100 nm to 2000 nm at an implantation energy of 10 keV to 10 MeV, followed by annealing at high temperatures of 1200 °C to 2200 °C. In this way, the C-interstitials (C i :C-interstitial) diffuses into the epilayer, and V C and recombines with [V C Another method based on annealing at low temperatures, i.e., below 1500 °C, with a C cap was proposed by Ayedh et al. (see above citation). Both methods involve the reduction of C i +V C →φ, and finally V in the drift layer C C recombines with i The term "epilayer" refers to an epitaxially grown layer. For example, an epilayer is grown on a substrate, which may be the same base material, such as SiC.

[0012] However, p +When fabricating in diodes, by using an epilayer processed according to one of the two methods described above, Al implantation for anode formation and subsequent annealing can be performed at V C This results in the regeneration of

[0013] Referring to the above citation, Hamada et al. 13 cm -2 suggests using a high implant dose exceeding 1000 nm to achieve a deep C implant in the epilayer within 500 nm of the Al box profile. i C diffuses into the epilayer from these deeply implanted regions. However, such high implant doses can result in amorphization of the epilayer crystalline structure. i is also an acceptor for n-type 4H-SiC, and high concentration C i Similarly, if a high dose of C is implanted into the anode layer, i.e., the first layer, p + This results in the formation of implantation-related defects that can compensate for the doping. In the method described herein, the C dose is low, so the p + Doping compensation is avoided or its effect is greatly reduced. A low C dose also prevents a decrease in the hole injection efficiency from the anode, which is due to the p + This is because the degradation may occur due to the presence of defects in the region.

[0014] In the methods described herein, p + After implanting C into the implanted region, i.e., the anode, a C cap is used for annealing. This uses lower implant doses and energies than those of, for example, Hamada et al., and unlike Ayedh et al., + in V in the diode C The latter has the advantage of removing V by C cap annealing. C It has been shown that the concentration of C is reduced, but some is still present. The method described herein provides additional C by implanting a low dose of C into the anode layer. i Therefore, C coming from the C cap is supplied.i and C derived from injected C i These C are present in the anode layer. i are all, for example, V C is completely or substantially completely removed from the drift layer.

[0015] Thus, the methods herein include, among other things, a low dose implant of C, for example, into an Al box profile, followed by annealing with a C cap.

[0016] According to at least one embodiment, the concentration of the dopant provided and activated in step B) is at least three times or at least six times the concentration of C implanted in step D). Alternatively or additionally, the concentration of the final activated dopant is up to 30 times or up to 15 times the implanted C concentration. That is, the concentration of activated dopant in the finished semiconductor device is on the order of 10 times the C concentration implanted in step B).

[0017] It should be noted that not all of the implanted dopant is activated, i.e., available for charge carrier conduction in the completed device. For example, when using Al as the dopant, only about 2% of the implanted Al is actually activated; i.e., about 1×10 20 cm -3 The Al implantation concentration is 2×10 18 cm -3 This results in a concentration of activated Al of about 1000 kJ / cm.

[0018] According to at least one embodiment, in step E), the temperature treatment comprises applying a first temperature. For example, the first temperature is at least 1400° C. or at least 1500° C. Alternatively or additionally, the first temperature is at most 1800° C., or at most 1700° C., or at most 1650° C. At such a first temperature, in step E), the pre-implanted C can diffuse from the carbon-containing layer, i.e., the C-cap, into the first layer and possibly also into a second layer of the semiconductor body, such as an intrinsically doped layer.

[0019] According to at least one embodiment, the method further comprises step B2). For example, step B2) is performed after step B) and before step D). In step B2), the dopant is activated by applying a second temperature. For example, the second temperature is at least 1400°C, or at least 1500°C, or at least 1600°C. Alternatively or additionally, the first temperature is at most 1900°C, or at most 1800°C, or at most 1750°C. The second temperature can be 50°C to 150°C higher than the first temperature.

[0020] For example, both temperature treatments at the first and second temperatures are performed during the method. According to at least one embodiment, in step E), C diffuses from the carbon-containing layer into the first layer and / or the second layer, activating the dopant. For example, in step E), the temperature treatment includes applying a third temperature. For example, the third temperature is at least 1400°C, or at least 1500°C, or at least 1550°C. Alternatively or additionally, the third temperature is at most 1900°C, or at most 1800°C, or at most 1750°C, or at most 1650°C. When the third temperature is applied, the temperature treatment with the first or second temperature may not be present.

[0021] According to at least one embodiment, between steps A) and E), the temperature of the semiconductor body (2) is maintained below 800° C., or below 500° C., or below 300° C., or below 100° C. This is the case, for example, when a temperature treatment at a third temperature is performed. In other words, in this case, C diffusion and dopant activation can be performed in the same temperature treatment step without the need for an intermediate temperature step.

[0022] According to at least one embodiment, the dopant is aluminum (Al). Alternatively, the dopant may be B, Ga, or In. In the case of an n-doped first layer, other dopants such as P, As, Sb, and / or Bi may be used as well. It is also possible that co-doping is used, i.e., at least two different dopants are used. Thus, in step B), at least one dopant is introduced into the first layer of the semiconductor body either by implantation, thermal diffusion, or epitaxial growth, or any combination thereof.

[0023] According to at least one embodiment, in step B), the doping is provided by ion implantation. For example, different ion implantation energies are used to achieve a box profile of at least one dopant. The ion implantation energy may be, for example, between 10 keV and 10 MeV, for example, between 30 keV and 300 keV.

[0024] According to at least one embodiment, the first layer is p-doped. According to at least one embodiment, at least one dopant is at least 1×10 13 cm -2 or at least 1×10 14 cm -2 or at least 2×10 14 cm -2 Alternatively or additionally, the implant dose is up to 1×10 16 cm -2 or up to 1×10 15 cm -2 or up to 6×10 14 cm -2 or up to 4×10 14 cm -2 is.

[0025] According to at least one embodiment, C is at least 5×10 8 cm -2 or at least 1×10 9 cm-2 or at least 2×10 9 cm -2 Alternatively or additionally, the injection volume is up to 1×10 12 cm -2 or up to 1×10 11 cm -2 or up to 5×10 10 cm -2 or up to 1×10 10 cm -2 is.

[0026] According to at least one embodiment, the first layer is fabricated adjacent to the top surface by doping with at least one dopant. Thus, the first layer can be disposed directly on the top surface, such that the top surface is partially or completely formed by the first layer. Alternatively, the first layer can be at least partially embedded within the semiconductor body, such that the top layer can be partially or completely separated from the top surface.

[0027] According to at least one embodiment, the carbon-containing layer is applied directly to the top surface, e.g., directly to the first layer. Alternatively, there may be at least one intermediate layer between the carbon-containing layer and the top surface and / or between the carbon-containing layer and the first layer.

[0028] For example, the carbon-containing layer is a continuous, hole-free layer. The carbon-containing layer may extend over the entire semiconductor body. The carbon-containing layer can be used in the applied method steps D) and E), i.e., without material removal or structuring of the carbon-containing layer between them. Thus, the carbon-containing layer can be used in steps D) and E) with the coverage of the semiconductor body that it had when it was first placed on the semiconductor body.

[0029] According to at least one embodiment, in step D), the first implantation energy is at least 10 keV and / or at most 300 keV.

[0030] According to at least one embodiment, the at least one dopant and / or C is applied in a box profile, which may also be referred to as a multi-energy implant profile, i.e., the concentration of each dopant and / or C is approximately constant along the depth direction.

[0031] According to at least one embodiment, after step D) or after step E), the first box profile depth of the at least one dopant is greater than the second box profile depth of C. For example, the respective depths refer to the depths at which the concentration drops to 1 / e of the maximum concentration of the respective dopant or C, where e≈2.7183 is Euler's number. For example, the second box profile depth is at least 30% or at least 45%, and / or at most 80% or at most 60% of the first box profile depth.

[0032] According to at least one embodiment, the first box profile depth is at least 0.1 μm, or at least 0.2 μm, or at least 0.3 μm. Alternatively or additionally, the first box profile depth is at most 1.5 μm, or at most 1.2 μm, or at most 0.7 μm.

[0033] According to at least one embodiment, the method further includes step B1). For example, step B1 is performed after step B) and before step C). In step B1), the semiconductor body is etched. This etching forms, for example, a mesa. A mesa is a raised portion of the semiconductor body, and the semiconductor body adjacent to the mesa portion is removed. Step B1) can be performed between steps B) and B2).

[0034] According to at least one embodiment, the etching depth in step B1) is greater than the thickness of the first layer, i.e., the first box profile depth, for example, the etching depth exceeds the first box profile depth by at least 1.2 times and / or by at most 3 times.

[0035] According to at least one embodiment, in step C), the carbon-containing layer is applied over the entire semiconductor body or over only a portion of the semiconductor body. If a mesa is present, the carbon-containing layer may completely cover the top surface of the mesa and the sidewalls of the mesa.

[0036] According to at least one embodiment, the carbon-containing layer comprises or consists of at least one of graphite, graphitic material, and diamond-like carbon (DLC), i.e., the carbon-containing layer can consist of or consist essentially of C.

[0037] According to at least one embodiment, the carbon-containing layer comprises or consists of a photoresist, for example, the photoresist has been developed and / or baked to become a carbon-containing layer, i.e., the carbon-containing layer may contain, in addition to C, further elements such as H and / or O and / or N.

[0038] According to at least one embodiment, the carbon-containing layer has a thickness of at least 0.1 μm or at least 0.2 μm. Alternatively or additionally, the thickness is at most 1.5 μm, or at most 0.9 μm, or at most 0.6 μm.

[0039] According to at least one embodiment, in the completed semiconductor device, the semiconductor body further comprises a second layer. For example, the second layer is directly away from the top surface of the first layer. If a mesa is present, the second layer may be exposed in places and / or the etching may terminate at the second layer.

[0040] According to at least one embodiment, the second layer is doped at a lower doping concentration than the first layer or is undoped. Thus, the second layer can be an intrinsically doped layer. For example, the doping concentration of the second layer can be up to 1×10 15 cm -3 or up to 5×10 14 cm-3 or up to 1×10 14 cm -3 or up to 5×10 13 cm -3 is.

[0041] According to at least one embodiment, the second layer has a thickness of at least 10 μm. Alternatively or additionally, said thickness is at most 100 μm or at most 50 μm.

[0042] According to at least one embodiment, the first layer or the entire semiconductor body is 4H—SiC. According to at least one embodiment, in the completed semiconductor device, the first layer is an anode layer. For example, the first layer may be in direct contact with a semiconductor contact layer, such as a plug, which may be in direct contact with an electrode, such as a metal electrode or a poly-Si electrode. Although the semiconductor contact layer may have a higher doping concentration than the rest of the first layer, the semiconductor contact layer can be considered part of the first layer because of the same conductivity type, such as p-conductivity.

[0043] A semiconductor device is also provided. The semiconductor device can be manufactured by the method described in relation to at least one of the above-described embodiments. Accordingly, features of the semiconductor device are also disclosed for the method, and vice versa.

[0044] In at least one embodiment, a semiconductor device comprises a semiconductor body having a first layer of 4H—SiC directly on a top surface of the semiconductor body. The first layer has a surface area of ​​at least 2×10 17 cm -3 and / or up to 8x10 18 cm -3 The concentration of carbon vacancies in the first layer adjacent the top surface is at most 2×10 11 cm -3 is.

[0045] According to at least one embodiment, the semiconductor device is a pin diode, or an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), or a metal-insulator-semiconductor field-effect transistor (MISFET), or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0046] The semiconductor device is, for example, a power device or part of a power device for converting direct current from a battery into alternating current for an electric motor in a vehicle such as a hybrid vehicle or a plug-in electric vehicle, or in a railway vehicle such as a commuter train.

[0047] For example, the semiconductor device is configured such that the maximum voltage between its two electrodes, or between the source or emitter electrode and the drain or collector electrode, is at least 0.2 kV, or at least 0.6 kV, or at least 1.2 kV. Alternatively or additionally, the semiconductor device is configured for a current between its two electrodes, or between the source or emitter electrode and the drain or collector electrode, of at least 0.01 kA, or at least at least 0.1 kA, or at least 1 kA, and / or up to 100 kA, or up to 10 kA.

[0048] The method and semiconductor device described herein will be described in more detail below by way of exemplary embodiments with reference to the drawings. In the individual figures, the same elements are designated by the same reference numerals. However, the relationships between the elements are not shown to scale, and rather, the individual elements may be exaggerated to facilitate understanding. [Brief explanation of the drawings]

[0049] [Figure 1] 1 is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 2] 1 is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 3] FIG. 1 is a schematic illustration of a doping profile provided by the method described herein. [Figure 4] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 5] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 6] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 7] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 8] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 9] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 10] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 11] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 12] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 13] 1A-1C are diagrams of deep level transient spectroscopy data for exemplary embodiments of semiconductor devices described herein and comparative examples. DETAILED DESCRIPTION OF THE INVENTION

[0050] Figures 1 and 2 are schematic illustrations of a method for manufacturing a semiconductor device 1. In method step S1, a semiconductor body 2 is provided, see also the description of figures 4 to 9 below. For example, the semiconductor body is SiC.

[0051] Next, in method step S2, the first layer 21 of the semiconductor body 2 is produced by doping the respective regions of the semiconductor body 2 with a dopant 4. For example, the first layer 21 is p-doped in step S2. This can be achieved, for example, by ion implantation of the dopant 4. The dopant 4 is, for example, Al.

[0052] Next, in step S3, a carbon-containing layer 3 is applied to the top surface 20 of the semiconductor body 2. The top surface 20 may be partly or completely formed by a first layer 21.

[0053] In the subsequent step S4, C is implanted into the first layer at a concentration lower than that of the dopant 4. According to Fig. 1, in step S5, a temperature treatment is performed at a third temperature. In this step, both dopants are activated and C can diffuse from the carbon-containing layer 3 into the semiconductor body 2, for example into and / or through the first layer 21. Thus, in the method of Fig. 1 in the relevant method steps, there is only one temperature treatment of the semiconductor body 2 at a high temperature, for example above 1000°C.

[0054] In contrast, FIG. 2 shows the presence of step S31, which involves a temperature treatment at a second temperature during which the dopant 4 is activated. After step S4, there is also step S5, in which C diffusion occurs at the first temperature. Therefore, in the method of FIG. 2, activation and diffusion can be performed separately. The first temperature can be lower than the second temperature.

[0055] Figure 3 shows the resulting doping profiles of a dopant 4, such as Al, and implanted C. Both profiles are box profiles. Note that Figure 3 shows the implanted concentration c of dopant 4, but not the concentration of activated dopant 4. The concentration of activated dopant 4 is about two orders of magnitude lower than the actual implanted concentration c of dopant 4. Therefore, the maximum implanted concentration c of dopant 4 is about three orders of magnitude higher than the maximum implanted concentration c of C.

[0056] As can be seen from Figure 3, the box profile of the dopant 4 has a depth T of about 0.3 µm to 0.4 µm. The box profile of the implanted C has a depth T of about 0.2 µm. Next to the top surface 20, the doping concentration c is relatively low compared to the maximum implant concentration in both cases.

[0057] For example, the methods of FIGS. 1 and 2 can be performed as follows. First, an anode, i.e., the first layer 21, is formed by Al ion implantation. For example, the energy is set to 30 keV, 60 keV, 110 keV, and 180 keV, and the total implantation dose is 10 15 cm -2 When Al implantation is performed at a temperature of at least 100°C, the Al concentration [Al] is about 10 20 cm -3 A plateau is reached and the box profile depth is 0.4 μm. After this, Al activation is performed at a temperature of 1700°C for 30 minutes.

[0058] Next, p + region, i.e., part of the first layer 21, is C-implanted through the previously applied C-cap, i.e., carbon-containing layer 3, e.g., about 0.15 μm thick. The C-implantation energy should be selected so that the C-implantation profile is within 0.1 μm of the Al box profile tail region, located at T≈0.4 μm. The implanted C dose is determined by the implanted C after activation. i The concentration should be chosen to be lower than the implantation [Al]. If the activation rate of dopant 4 is 2%, then the implantation [C i ] is, for example, 1017 cm -3 is less than or equal to [Al] / [C i ]>10. For example, in the profile in Figure 3, C is 5 × 10 at 80 keV. 9 cm -2 It is injected at an injection volume of .

[0059] Finally, annealing is performed at temperatures up to 1600°C. i Diffuses the C coming from the C cap. i are also implanted into a second layer of the semiconductor body 2, such as the drift layer. Their concentration is below the detection limit, e.g., about 10 10 cm -3 until it falls below [Z 1 / 2 ] is not enough to reduce the injected C i compensates for them.

[0060] Alternatively, referring to FIG. 2, C implantation can be performed before Al activation. In this case, the activation temperature is also C i Allows for diffusion.

[0061] Longer annealing times, for example, at least 30 minutes, may result in thicker second layer 22 having a thickness on the order of 100 μm. i can be chosen to spread

[0062] As a result, [V C ] falls below the detection limit. Two other levels, called ON1 and ON2, can be detected; see B. Zippelius et al., supra. These levels do not affect device performance. For example, standard p + In the in diode, p + Upon activation, a certain amount of V C Note that is always detected.

[0063] For example, deep-level transient spectroscopy (DLTS) can be used to detect the presence of p + n diode V C(Z 1 / 2 ) can be demonstrated, and the presence of p + V in n-diode C The absence of ON1 and the appearance of ON2 can also be demonstrated.

[0064] 4 to 9 show an example for producing a semiconductor device 1, which is a pin diode. According to FIG. 4, a semiconductor body 2 is provided. The semiconductor body 2 has a third layer 23 on a second layer 22. The second layer 22 is, for example, intrinsically doped or only very weakly n-doped. The third layer 23 is, for example, n-doped. A top surface 20 is on the second layer 22. The third layer 23 and / or the second layer 22 may be provided by epitaxy.

[0065] 5, a first layer 21 is shown formed by doping the semiconductor body 2 next to the top surface 20 with a dopant 4, for example Al. The thickness of the first layer 21 is, for example, on the order of 0.4 μm.

[0066] The mesas 5 are then formed by etching (see FIG. 6). The etching ends at the second layer 22 so that the first layer 21 is completely removed in places.

[0067] 7, another implant, again with Al, is performed for field protection or to form a junction termination extension (JTE) as a fourth layer 24 of the semiconductor body. A carbon-containing layer 3 is also applied to the entire top surface 20, i.e., mesa 5, as well as to the second layer 22 and the fourth layer 24. The fourth layer 24 may not completely span the second layer 22 but may terminate laterally near the mesa 5. Otherwise, the same may apply to the fourth layer 24 as to the first layer 21.

[0068] The implanted region is activated, for example, at 1700°C, after which C is implanted through the carbon-containing layer 3 (see Figure 8). The carbon-containing layer 3 may be a continuous, hole-free, and therefore uninterrupted layer. For example, the thickness of the carbon-containing layer 3 is constant.

[0069] 8 also shows that first layer 21 may optionally be composed of two regions that are generally separated from each other by a horizontal line in first layer 21 in FIG. 8. In the upper region adjacent top surface 20, there may be a higher maximum p-doping concentration than in the lower region. Thus, the upper region may have a p + The lower region may be p-doped and may act as a contact layer, this also applies to all other examples of the semiconductor device 1.

[0070] After this, referring to Figure 9, C i A low temperature anneal is performed at a temperature below 1600° C. to diffuse V. This causes the second layer 22, which is a drift layer, to diffuse V. C There will be less.

[0071] After the temperature treatment, the carbon-containing layer 3 can be completely removed before applying, for example, an electrode or an electrical insulating layer.

[0072] An example of the completed semiconductor device 1 is shown in Fig. 10. The semiconductor device 1 is a SiC-p + In the mesa 5, for example, + There may be a fifth layer 25 of the semiconductor body 2, which is a contact layer. Also, the first layer 21 is within the mesa 5. Starting from the first layer 21, the fourth layer 24 may extend laterally adjacent the mesa 5 so that a JTE is formed. The layers 24, 25 may be considered special portions of the first layer 21 or may be considered separate layers.

[0073] Below Mesa 5, for example, there are approximately 1 × 10 15 cm -3 At a concentration of -There is a second layer 22 which is doped and may have a thickness of about 70 μm. A third layer 23 is made of, for example, SiC with a doping concentration of 5×10 18 cm -3 degree of n + The third layer 23 is a doped substrate. The thickness of the third layer 23 is, for example, about 0.25 mm. The sides of the mesa and the exposed areas of the second layer 22 and the fourth layer 24 are covered with an electrically insulating layer 6, for example, silicon dioxide.

[0074] The fifth layer 25 on the mesa 5 has a first electrode 71, such as an anode, and the third layer 23 has a second electrode 72, such as a cathode. + There may be a sixth layer 26 in the circumferential direction of the semiconductor body 2, which is doped and acts as a channel stop. In top view, the mesa 5 may be surrounded all around by the fourth layer 24 and the sixth layer 26, for example, in a rotationally symmetric manner.

[0075] Otherwise, the same applies to Figure 10 as to Figures 1 to 9, and vice versa.

[0076] The semiconductor device 1 of FIG. 11 is also a 4H-SiC based pin diode, but in contrast to the semiconductor device 1 of FIG. 10, it is planar, with a flat top surface 20 without a mesa. In the design of FIG. 11, the first electrode 71 is disposed on the side edge of the device 1. The first layer 21 is well-shaped and is disposed within the second layer 22. The thickness of the second layer 22 is, for example, on the order of 10 μm. For example, the second layer 22 and the third layer 23 each have a thickness of about 9×10 15 cm -3 and 1 × 10 19 cm -3 It is n-doped to a concentration of

[0077] Otherwise, the same applies to Figure 11 as to Figures 1 to 10, and vice versa.

[0078] 12, the semiconductor device 1 is shown to be an insulated-gate bipolar transistor (IGBT). Therefore, the first layer 21 is a well region. In the well region, a first electrode 71, which is, for example, an emitter electrode, is provided with, for example, a p + There is a fifth layer, which is a plug. Also in the well region there is a seventh layer of the semiconductor body 2, which is configured as an emitter region. Therefore, the second layer 22 is n - The second layer 22 is a substrate having a thickness of between 50 μm and 200 μm. The doping concentration of the drift layer is, for example, 2×10 14 cm -3 That's about it.

[0079] The second layer 22 extends, in cross section, between the two well regions to the top surface 20. At the top surface 20 above the well regions and said central portion of the second layer 22 is an insulating layer 6 that separates the third electrode 73 from the semiconductor body 2. The third electrode 73 is a gate electrode.

[0080] Optionally, below the second layer 22 is a layer 28 of the semiconductor body 2 which may be a buffer layer. For example, the buffer layer may be about 1×10 18 cm -3 The buffer layer may be n-doped with a maximum doping concentration of 0.1 μm or more and 10 μm or less.

[0081] The third layer 23 is located on the side of the second layer 22 far from the top surface 20 or on the side of the eighth layer 28 far from the top surface 20. The third layer 23 is a collector region. The third layer 23 has a density of, for example, 1×10 19 cm -3 The third layer 23 has a doping concentration of about 1000 .mu.m. The thickness of the third layer 23 is, for example, 2 .mu.m or more and 10 .mu.m or less. The second electrode 72 of the third layer 23 is a collector electrode.

[0082] Similarly, the semiconductor device 1 may be a metal-insulator-semiconductor field-effect transistor (MISFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, the eighth layer 28 may be omitted, and the third layer 23 may have a thickness of, for example, at least 1×10 18 cm -3 or at least 5×10 18 cm -3 or at least 1×10 19 cm -3 and / or up to 5×10 20 cm -3 or up to 2×10 20 cm -3 or up to 1×10 20 cm -3 In this case, the seventh layer 27 is the source region, and the first electrode 71 and the second electrode 72 are the source and drain electrodes, respectively.

[0083] Other than as shown, the IGBT or MISFET or MOSFET does not have to be of planar design, but may be of trench design in which the gate electrode 73 is housed in a trench not shown.

[0084] Otherwise, the same applies to FIG. 12 as to FIGS. 1 to 11, and vice versa.

[0085] The data in Figure 13 for Comparative Example 9 and the semiconductor device 1 described herein were obtained by Deep Level Transient Spectroscopy (DLTS). The measurements were taken at a reverse bias V of -5V. r and a pulse voltage of 5V, V pThe fill pulse length was 1 ms with a periodic width of 0.2 seconds. The semiconductor device 1 was processed as described in connection with FIGS. 4-9, but in the case of Comparative Example 9, there was no low dose C ion implantation through the carbon-containing layer. In Comparative Example 9, Z 1 / 2 As shown by the peak V C On the other hand, in the example of the semiconductor device 1, Z 1 / 2 There is no peak, instead there are peaks corresponding to states ON1 and ON2.

[0086] Typically, V in as-grown n-type 4H-SiC C The concentration is 10 11 cm -3 ~10 12 cm -3 At such a concentration, the minority carrier lifetime is about 1 μs. This value is quite low and is not suitable for SiC bipolar devices. C ] is, for example, 10 11 cm -3 High voltage SiC bipolar devices can be achieved with low doping concentrations, i.e., less than 10 14 cm -3 Since it depends on the region of [V C The threshold for detection of ] is approximately 10 10 cm -3 Therefore, V C The threshold limit of detection is about four orders of magnitude lower than the doping concentration. 14 cm -3 and 5×10 10 cm -3 ~8×10 10 cm -3 or even lower [V C ] performs well.

[0087] The method described herein has the following advantages, for example: -C i is supplied by the C cap and injected C, so by performing C injection into the anode through the C cap, the effective V CRemoval becomes possible.

[0088] Unlike Hamada et al., the C implant can be performed at a low dose, thus avoiding amorphization of the drift layer.

[0089] -Again, unlike Hamada et al., C i Since C is an acceptor in n-type SiC, C implantation is performed at the anode rather than the drift layer, thus avoiding doping compensation.

[0090] - Unlike Storasta et al., no structuring, such as etching, of the C-containing layer is required. -Unlike Ayedh et al., C i is provided not only by the C-cap but also by the injection process, so the residual V C will not remain.

[0091] The low dose C implant avoids excessive defect formation in the anode layer, i.e., the first layer, thus maintaining implant efficiency.

[0092] 7) Reverse engineering is possible in the final product, for example by secondary-ion mass spectrometry (SIMS) to detect C in the anode layer.

[0093] -Reverse engineering is also possible in the final product, for example by DLTS, to detect ON1 and ON2 states.

[0094] The anode layer can be formed to any thickness. Components shown in the figures are illustratively positioned directly on top of each other in the order specified, unless otherwise indicated. Components that are not touching in the figures are illustratively spaced apart from each other. Where lines are drawn parallel to each other, corresponding surfaces may be oriented parallel to each other. Similarly, unless otherwise indicated, the positions of the drawn components relative to each other are accurately reproduced in the figures.

[0095] The invention described herein is not limited by the description based on the exemplary embodiments, but rather the invention encompasses any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly named in the claims or exemplary embodiments. [Explanation of symbols]

[0096] List of Reference Numbers 1. Semiconductor device 2. Semiconductor body 20 top surface of semiconductor body 21 first layer of semiconductor body 22 second layer of semiconductor body 23 Third layer of semiconductor body 24 Fourth layer of semiconductor body 25 fifth layer of semiconductor body 26 Sixth layer of semiconductor body 27 Seventh layer of semiconductor body 28 Eighth layer of semiconductor body 3 Carbon-containing layer 4 Dopant 5. Mesa 6 insulating layer 71 First electrode 72 Second electrode 9 Comparative Example A Absolute temperature (K) Al Aluminum ion implantation c cm -3 Concentration of C Carbon ion implantation DLTS pF Deep Level Transient Spectroscopy Data ON1: First other level in the band structure ON2 Second other level in the band structure S.. Method Step T depth into the semiconductor body from the top surface Z 1 / 2 Activity levels within the band gap

Claims

1. A method for manufacturing a semiconductor device (1), comprising the following steps: A) providing a semiconductor body (2) having a top surface (20), the semiconductor body (2) being based on SiC; B) producing a first layer (21) of said semiconductor body (2) next to said top surface (20) by doping with a dopant (4); C) applying a carbon-containing layer (3) to said upper surface (20); D) implanting C into the first layer (21) through the carbon-containing layer (3); E) subjecting the semiconductor body (2) to a temperature treatment while the carbon-containing layer (3) is still present on the upper surface (20); in the order listed.

2. The concentration of the dopant (4) provided and activated in step B) is at least 3 times and at most 30 times the concentration of C implanted in step D); The method of claim 1.

3. In step E), the temperature treatment comprises applying a first temperature; the first temperature is equal to or higher than 1400°C and equal to or lower than 1800°C, In step E), C diffuses from the carbon-containing layer (3) into the first layer (21).

10. A method according to any one of the preceding claims.

4. Further comprising step B2) between step B) and step D), B2) activating said dopant (4) by applying a second temperature, The second temperature is 1400°C or more and 1800°C or less, and further includes activating.

10. A method according to any one of the preceding claims.

5. In step E), C diffuses from the carbon-containing layer (3) into the first layer (21) and the dopant (4) is activated; In step E), the temperature treatment comprises applying a third temperature; In step E), the third temperature is 1400°C or higher and 1800°C or lower, Between steps A) and E), the temperature of the semiconductor body (2) is maintained below 800°C, 3. The method according to claim 1 or 2.

6. In step B), the doping is provided by ion implantation; 10. A method according to any one of the preceding claims.

7. The dopant (4) is Al, The dopant (4) is 10 １３ cm －２ ~10 １６ cm －２ provided in an injection volume between 10. A method according to any one of the preceding claims.

8. In step D), the first implantation energy is at least 10 keV and at most 300 keV; 10. A method according to any one of the preceding claims.

9. After step D), the first box profile depth of the dopant (4) is greater than the second box profile depth of C; The first box profile depth is equal to or greater than 0.1 μm and equal to or less than 1.2 μm.

10. A method according to any one of the preceding claims.

10. Step B1) is added between step B) and step C), B1) etching the semiconductor body (2) to form a mesa (5), the etching depth being greater than the thickness of the first layer (21); 10. A method according to any one of the preceding claims.

11. In step C), the carbon-containing layer (3) is applied over the entire semiconductor body (2), The carbon-containing layer (3) includes at least one of graphite and photoresist, and the thickness of the carbon-containing layer (3) is at least 0.1 μm and at most 0.9 μm.

10. A method according to any one of the preceding claims.

12. In the completed semiconductor device (1), the semiconductor body (2) further comprises a second layer (22) directly on the side of the first layer (21) remote from the top surface (20), the second layer (23) is doped at a lower doping concentration than the first layer (21); The thickness of the second layer (23) is 10 μm to 100 μm.

10. A method according to any one of the preceding claims.

13. the first layer (21) is 4H—SiC; In the completed semiconductor device (1), the first layer (21) is an anode layer.

10. A method according to any one of the preceding claims.

14. A semiconductor device (1) comprising a semiconductor body (2), - said semiconductor body (2) comprises a first layer (21) of 4H-SiC directly on the top surface (20) of said semiconductor body (2); - said first layer (21) has a density of at least 2 x 10 １７ cm －３ and up to 8 x 10 １８ cm －３ a dopant (4) having a concentration of said activating dopant (4) of - the concentration of carbon vacancies in said first layer (21) adjacent to said top surface (20) is at most 2 x 10 １１ cm －３ That is, Semiconductor device (1).

15. a pin diode, an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT); A semiconductor device (1) according to claim 1.

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