Substrate Encapsulation

Abstract

As used herein, SiO, SiO 2 , SiO 3 , SiO 4 , SiO 5 , SiO 6 , SiO 7 , SiO 8 , SiO 9 , SiO 10 , SiO 11 , SiO 12 , SiO 13 , SiO 14 , SiO 15 , SiO 16 , SiO 17 , SiO 18 , SiO 19 , SiO 20 , SiO 21 , SiO 22 , SiO 23 , SiO 24 , SiO 25 , SiO 26 , SiO 27 , SiO 28 , SiO 29 ... x / SiN y and device structures and methods using SiN structures are provided.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 478,797, filed January 6, 2023, the entire contents of which are incorporated herein by reference.

[0002] Statement of Federally Funded Research Not applicable

[0003] The present invention generally relates to the field of creating encapsulation structures on glass or glass-ceramic surfaces to prevent migration or cross-contamination from the glass or glass-ceramic to semiconductor devices that may be in direct contact with the glass or glass-ceramic substrate, and these active semiconductor devices are used in systems used in RF microwave, millimeter wave, high speed computing, and optical interconnect applications. The encapsulation prevents damage from mobile ions, moisture, and gases from affecting performance and device / system lifetime. [Background technology]

[0004] Without limiting the scope of the present invention, its background is described in the context of encapsulating active semiconductor devices in glass, ceramic, or glass / ceramic substrates to prevent damage from physical diffusion of mobile ions and / or exposure to moisture and gases.

[0005] Glass, ceramic, or glass / ceramic materials are used in the construction of substrates in printed circuit board and advanced packaging applications. Glass, ceramic, or glass / ceramic substrates are composed of elements that can consume or reduce the lifetime of semiconductor devices. Over the lifetime of the system, these elements / ions can migrate from the substrate to the semiconductor device interface due to electric fields or thermal gradients between the substrate and vias and other structures used in RF microwave, millimeter wave, high-speed computing, and optical connection applications. A fundamental issue is that metal interconnects for high-speed electronics and computers are typically copper and require an adhesion layer to the PCB, PTFE, glass, glass composite, or ceramic substrate.

[0006] Even copper has been evaluated as a performance / lifetime-limiting contaminant in silicon devices; see, for example, "First-principles study of copper contamination in silicon semiconductors" by Chen et al. (www.sciencedirect.com / science / article / abs / pii / S2468023022003522). Copper (Cu) is widely used as an interconnect material in the semiconductor industry due to its high electrical and thermal conductivity, excellent electromigration resistance, and low cost. Cu is highly reactive, and contamination, such as physical diffusion from Cu into silicon (Si) and chemical bonding between Cu and Si, is commonly observed and is detrimental to Si semiconductor devices. Cu / Si has also been shown to have interfacial diffusion mechanisms, including vacancy diffusivity and interstitial diffusion.

[0007] New structures and methods are needed to prevent the physical diffusion of mobile ions between semiconductor devices and / or between substrates of semiconductor devices, as well as to protect these devices from exposure to moisture and gases. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] "First-principles study of copper contamination in silicon semiconductor" by Chen et al.(www.sciencedirect.com / science / article / abs / pii / S2468023022003522) Summary of the Invention [Means for solving the problem]

[0009] The novel encapsulation layer of the present invention provides a barrier against the diffusion of mobile ions, gases, and moisture that can damage electronic devices / semiconductors, for example, in a System in a Package (SiP). The encapsulation layer can be co-located with active devices and combined to form a wide range of RF, high-speed computer, optical, electro-optical, and MEMS systems and subsystems, including, but not limited to, gain antennas, RF circulators, RF isolators, RF combiners, RF couplers, RF splitters, transformers, high-speed CPUs, high-speed analog-to-digital converters, high-speed digital-to-analog converters, optical couplers, optical modulators, laser diodes, VECSLSs, switches, multiplexers, duplexers, memory, and / or diplexers, all connected to each other, electrical power, optical power, and / or electrical ground planes by vias and / or metal lines. The present invention provides a general solution for making electrical connections from metal layers to via metal or conductors, eliminating random device performance and parasitics across the substrate, thereby reducing SiP size and improving performance.

[0010] Aspects of the present disclosure, as embodied and broadly described herein, include the use of a SiO2, SiO2, or SiO3 film for encapsulating a substrate to isolate constituents of the substrate from contaminating semiconductor materials and / or semiconductor devices. x / SiN yand a device structure comprising a SiN structure. In one embodiment, the substrate is selected from at least one of borosilicate glass, photosensitive glass, glass / ceramic composite, or ceramic. In another embodiment, the thickness of the SiO2 layer is greater than 20 Å and less than 10 μm. In another embodiment, the SiO2 layer is x / SiN y The thickness of the layer is greater than 20 Å and less than 10,000 Å. x In the layer, x is in the range of 0.5 to 3. In another embodiment, SiN y In the layer, y ranges from 0.5 to 2. In another aspect, the thickness of the SiN layer is greater than 20 Å and less than 10,000 Å. In another aspect, the substrate comprises an electrically and thermally conductive structure. In another aspect, the semiconductor device comprises RF circuitry that removes at least 10% of RF parasitic signals associated with transfer from the substrate to the electrically and thermally conductive structure. In another aspect, the electrically and thermally conductive structure comprises a through-hole via, a blind via, an interconnect, or a heat spreader element. In another aspect, the through-hole via, the blind via, the interconnect, or the heat spreader element comprises copper or another metal. In another aspect, the device structure is stacked or layered to form the equivalent of a multilayer PCB structure. In another aspect, the semiconductor device comprises at least one of a microprocessor / CPU, optical, electro-optical, MEMS device, antenna, RF circulator, RF isolator, RF combiner, RF coupler, RF splitter, transformer, AD converter, high speed DA converter, optical coupler, optical modulator, laser diode, VECSLS, switch, multiplexer, duplexer, diplexer, memory and / or diplexer, RF filter, RF circulator, RF isolator, antenna, impedance matching element, 50 ohm termination element, integrated ground plane, RF shielding element, EMI shielding element, RF combiner, RF splitter, transformer, switch, power splitter, power combiner, memory chip, or microcontroller.

[0011] An aspect of the present disclosure, as embodied and broadly described herein, is a method for encapsulating a substrate to isolate constituents of the substrate from contaminating semiconductor materials and / or semiconductor devices in a device structure, the method comprising the steps of cleaning the surface of the substrate using a plasma or other surface treatment process, the substrate having a thickness in the range of 25 μm to 2500 μm; depositing an adhesion layer of SiO in the range of 20 Å to 40,000 Å, and during deposition of the adhesion layer, reducing the oxygen gas and replacing the oxygen gas with nitrogen gas until the nitrogen gas is 100% of the gas. x / SiN y It forms a transition layer with a thickness of 20 Å to 40,000 Å, and when the gas becomes 100% nitrogen gas, SiO x / SiN y SiN (z) forming a via mask pattern and etching the encapsulation layer to expose metal connectors and a heat spreader; and attaching or forming one or more semiconductors, passive devices, or MEMS devices on the substrate. In one aspect, the one or more semiconductors, passive devices, or MEMS devices attached to the substrate are an integral part of the substrate. In another aspect, the deposited adhesion layer, transfer layer, and final layer are formed of SiO, SiO x / SiN y and a SiN structure. In another aspect, the thickness of the substrate is 100 to 200 μm. In another aspect, the thickness of each of the adhesion layer, the transition layer, and the final layer is 100 to 200 μm. In another aspect, the thickness of each of the adhesion layer, the transition layer, and the final layer is 100 to 200 μm. In another aspect, the deposition conditions of temperature and plasma density / energy are SiN (z) is selected to be stoichiometrically SiN. In another aspect, the substrate is selected from at least one of borosilicate glass, photosensitive glass, glass / ceramic composite, or ceramic. In another aspect, the thickness of the SiO layer is greater than 20 Å and less than 10 μm. In another aspect, the thickness of the SiO layer is greater than 20 Å and less than 10 μm. x / SiN yThe thickness of the layer is greater than 20 Å and less than 10,000 Å. x In the layer, x is in the range of 0.5 to 3. In another embodiment, SiN y In the layer, y ranges from 0.5 to 2. In another aspect, the thickness of the SiN layer is greater than 20 Å and less than 10,000 Å. In another aspect, the substrate comprises an electrically and thermally conductive structure. In another aspect, the semiconductor device comprises RF circuitry that removes at least 10% of RF parasitic signals associated with transfer from the substrate to the electrically and thermally conductive structure. In another aspect, the electrically and thermally conductive structure comprises a through-hole via, a blind via, an interconnect, or a heat spreader element. In another aspect, the through-hole via, the blind via, the interconnect, or the heat spreader element comprises copper or another metal. In another aspect, the device structure is stacked or layered to form the equivalent of a multilayer PCB structure. In another aspect, the semiconductor device comprises at least one of a microprocessor / CPU, optical, electro-optical, MEMS device, antenna, RF circulator, RF isolator, RF combiner, RF coupler, RF splitter, transformer, AD converter, high speed DA converter, optical coupler, optical modulator, laser diode, VECSLS, switch, multiplexer, duplexer, diplexer, memory and / or diplexer, RF filter, RF circulator, RF isolator, antenna, impedance matching element, 50 ohm termination element, integrated ground plane, RF shielding element, EMI shielding element, RF combiner, RF splitter, transformer, switch, power splitter, power combiner, memory chip, or microcontroller.

[0012] An aspect of the present disclosure, as embodied and broadly described herein, is a method for preventing contamination of a semiconductor device, comprising cleaning a surface of a substrate using a plasma or other surface treatment process by encapsulating the substrate, the substrate having a thickness in the range of 25 μm to 2500 μm, and depositing an adhesion layer of SiO in the range of 20 Å to 40,000 Å, during deposition of the adhesion layer, by reducing oxygen gas and replacing oxygen gas with nitrogen gas until nitrogen gas is 100% of the gas. x / SiN y It forms a transition layer with a thickness of 20 Å to 40,000 Å, and when the gas becomes 100% nitrogen gas, SiO x / SiN y SiN (z) forming a via mask pattern and etching the encapsulation layer to expose metal connectors and a heat spreader; and attaching or forming one or more semiconductor, passive, or MEMS devices on the substrate, thereby isolating one or more components of the substrate from contaminating semiconductor material and / or semiconductor devices of the device structure, whereby the substrate is protected from contamination. [Brief explanation of the drawings]

[0013] For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention taken in conjunction with the accompanying drawings. [Figure 1] FIG. 1 shows a glass / glass ceramic / ceramic substrate with deposited SiO, SiO / SiN, and SiN layers. [Figure 2] Schematic diagram of substrate encapsulation structures (SiO2, SiOx / SiNy, and SiN) on glass, glass-ceramic, or ceramic substrates with conductive through-hole vias, conductive blind vias, and conductive heat spreaders / sinks. [Figure 3] 1 is a flowchart of an example of a method of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] While the making and use of various embodiments of the invention are discussed in detail below, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention, and do not delimit the scope of the invention.

[0015] To facilitate understanding of the present invention, a number of terms are defined below. Terms defined herein have the meanings commonly understood by one of ordinary skill in the art to which the present invention pertains. Terms such as "a," "an," and "the" are intended to refer not only to a single entity but also to encompass the general class of which a specific example may be used for illustration. While terminology herein is used to describe particular embodiments of the present invention, its use is not intended to limit the present invention, except as provided for in the claims.

[0016] In one embodiment, the present invention provides a method for producing SiO2, SiO x / SiN y and a method for encapsulating a substrate having a SiN layer, wherein the substrate is borosilicate glass.

[0017] In another embodiment, the present invention provides a method for producing a SiO2, SiO x / SiN y and a method for encapsulating a substrate having a SiN layer, the substrate being a type of Gorilla Glass.

[0018] In another embodiment, the present invention provides a method for producing a SiO2, SiO x / SiN y and a method for encapsulating a substrate having a SiN layer, the substrate being a type of photosensitive glass.

[0019] In another embodiment, the present invention provides a method for producing a SiO2, SiO x / SiN y and a method for encapsulating a substrate having a SiN layer, the substrate being a type of glass-ceramic composite.

[0020] In another embodiment, the present invention provides a method for producing a SiO2, SiO x / SiN y and a method for encapsulating a substrate with a SiN layer, the substrate being a type of ceramic composite.

[0021] In another embodiment, the present invention provides a method for producing a SiO2, SiO x / SiN y and a method for encapsulating a substrate having a SiN layer, the substrate being borosilicate glass with copper filled vias and contactors.

[0022] Non-limiting examples of substrates for use in the present invention include glass-ceramics (APEX® glass-ceramics). This substrate material is compatible with semiconductors, RF electronics, microwave electronics, and optical imaging devices. APEX® glass-ceramics are processed using first-generation semiconductor devices in a simple three-step process. The final material can be formed into either glass, ceramic, or a material containing both glass and ceramic regions. APEX® glass-ceramics offer several advantages over current materials, including easy fabrication of high-density vias, demonstration of microfluidic functionality, microlens or microlens array functionality, high Young's modulus for rigid packaging, halogen-free manufacturing, and economical manufacturing. Photosensitive glasses such as APEX® offer several advantages for fabricating a wide variety of microsystem components. These glasses allow for relatively inexpensive production of microstructures using conventional semiconductor processing equipment.

[0023] Generally, glass has high-temperature stability, good mechanical and electrical properties, and chemical resistance superior to plastics and many metals. An example of a glass-ceramic is 75 to 85 wt% silicon oxide (SiO2), 7 to 11 wt% lithium oxide (Li2O), 3 to 6 wt% aluminum oxide (Al2O3), 1 to 2 wt% sodium oxide (Na2O), 0.2 to 0.5 wt% antimony trioxide (Sb2O3), arsenic oxide (As2O3), or 0.05 to 0.15 wt% silver oxide (Ag2O), and 0.01 to 0.04 wt% cerium oxide (CeO2). As used herein, the terms "APEX® glass ceramic," "APEX® glass," or simply "APEX®" are used to refer to one embodiment of a glass ceramic composition for constructing a device having one or more electronic devices on or within a photosensitive glass substrate having blind or through openings etched or machined into the photosensitive glass substrate, where the electronic circuits and openings are filled using standard materials and processes.

[0024] Any exposed portions of a photosensitive glass substrate in the form of an aperture structure are transformed into a crystalline material by heating the glass substrate to a temperature close to the glass transformation temperature. When etching a glass substrate in an etchant such as hydrofluoric (HF) acid, the anisotropic etch ratio of the exposed portion to the unexposed portion is at least 30:1 upon exposure of the glass to a broad-spectrum mid-ultraviolet (approximately 308-312 nm) flood lamp. The exposed glass is typically fired in a two-step process. First, the exposed glass is heated at 420-520°C for 10 minutes to 2 hours to fuse silver ions to the silver nanoparticles. Second, the exposed glass is heated at 520-620°C for 10 minutes to 2 hours to form lithium oxide around the silver nanoparticles. The glass plate is then etched. The glass substrate is typically etched in an etchant of 5-10% by volume HF solution, where the etch ratio of the exposed portion to the unexposed portion can reach, for example, at least 30:1.

[0025] FIG. 1 shows the SiO2, SiO x / SiN y 1 is a schematic side cross-sectional view of a glass / glass ceramic / ceramic main substrate having a SiN layer deposited thereon. A SiO2 layer is formed on the surface of the glass / glass ceramic / ceramic main substrate by PECVD or other deposition methods in the presence of oxygen gas. Nitrogen gas is added to the oxygen gas during the deposition of the SiO2 layer to increase the SiO2 concentration. x / SiN y A transition layer of 100% nitrogen is formed, and finally, when the gas reaches 100% nitrogen gas, a SiN layer is formed.

[0026] FIG. 2 illustrates a substrate encapsulation structure (SiO2, SiO2) on a glass, glass ceramic, or ceramic substrate with conductive through-hole vias, conductive blind vias, and conductive heat spreaders / sinks and metal interconnects formed on a glass / glass ceramic / ceramic main substrate. x / SiN y 1A and 1B are schematic side cross-sectional views of SiO, SiO , and SiN) for various interconnects including exemplary conductive through-hole vias, conductive blind vias, metal interconnects, and conductive heat spreaders / sinks. x / SiN y , and the position of SiN are shown.

[0027] Table 1 shows the step-by-step method for constructing the device of the present invention. The process flow for creating an encapsulated glass, glass / ceramic, or ceramic substrate is as follows: [Table 1]

[0028] FIG. 3 illustrates an exemplary method of the present invention. In step 10, the surface of the substrate is cleaned using a plasma or other surface treatment process. The substrate can range from 25 μm to 2500 μm. In step 20, an adhesion layer of SiO2 is deposited using plasma-enhanced chemical vapor deposition (PECVD) or another deposition method. The deposited layer can range from 20 Å to 40,000 Å. In step 30, during the deposition of SiO2, the oxygen gas is reduced and replaced with nitrogen gas until pure nitrogen gas is obtained. This allows the SiO2 to be deposited. x / SiN y The transition layer can range from 20 Å to 40,000 Å. In step 40, when the gas becomes pure nitrogen gas, the SiO x / SiN y SiN (z) Depending on the deposition conditions (temperature and plasma density / energy), (z) will be stoichiometrically SiN. In step 50, the encapsulation layer is etched using a via mask pattern to expose the metal connectors and heat spreader. Finally, in step 60, the semiconductor and passive devices are attached. In some cases, the passive devices and / or MEMS devices may be an integral part of the substrate.

[0029] It will be understood that the specific embodiments described herein are provided by way of example and not by way of limitation. By way of example, metal interconnects may be formed of SiO2, SiO x / SiN y, and SiN structures may be extended onto the surface of the substrate below, which can be stacked / layered to form the equivalent of multi-layer PCB structures for RF systems, high speed computers, optical, electro-optical, and MEMS systems and subsystems, including, but not limited to, gain antennas, RF circulators, RF isolators, RF combiners, RF couplers, RF splitters, transformers, high speed CPUs, high speed AD converters, high speed DA converters, optical couplers, optical modulators, laser diodes, VECSLS, switches, multiplexers, duplexers, memories, and / or diplexers.

[0030] In one embodiment, the device structure comprises a SiO, SiO 2 , SiO 3 , SiO 4 , SiO 5 , SiO 6 , SiO 7 , SiO 8 , SiO 9 , SiO 10 , SiO 11 , SiO 12 , SiO 13 , SiO 14 , SiO 15 , SiO 16 , SiO 17 , SiO 18 , SiO 19 , SiO 20 , SiO 21 , SiO 22 , SiO 23 , SiO 24 , SiO 25 , SiO 26 , SiO 27 , SiO 28 , SiO 29 ... x / SiN y , and SiN structure, SiO2, SiO x / SiN y , and SiN structure, or SiO2, SiO x / SiN y , and SiN structure. In one aspect, the substrate comprises, consists essentially of, or consists of borosilicate glass. In another aspect, the substrate comprises, consists essentially of, or consists of photosensitive glass. In another aspect, the substrate comprises, consists essentially of, or consists of a glass / ceramic composite. In another aspect, the substrate comprises, consists essentially of, or consists of a ceramic. In another aspect, the thickness of the SiO2 layer is greater than 20 Å and less than 10 μm. In another aspect, the SiO x / SiN y The thickness of the layer is greater than 20 Å and less than 10,000 Å. x In the layer, x is in the range of 0.5 to 3. In another embodiment, SiN yIn the layer, y ranges from 0.5 to 2. In another aspect, the thickness of the SiN layer is greater than 20 Å and less than 10,000 Å. In another aspect, the substrate comprises an electrically and thermally conductive structure. In another aspect, the semiconductor device comprises RF circuitry that removes at least 10% of RF parasitic signals associated with transfer from the substrate to the electrically and thermally conductive structure. In another aspect, the electrically and thermally conductive structure comprises a through-hole via, a blind via, an interconnect, or a heat spreader element. In another aspect, the through-hole via, the blind via, the interconnect, or the heat spreader element comprises copper or another metal. In another aspect, the device structure is stacked or layered to form the equivalent of a multilayer PCB structure. In another aspect, the semiconductor device comprises a microprocessor / CPU, optical, electro-optical, MEMS device, antenna, RF circulator, RF isolator, RF combiner, RF coupler, RF splitter, transformer, AD converter, high speed DA converter, optical coupler, optical modulator, laser diode, VECSLS, switch, multiplexer, duplexer, diplexer, memory and / or diplexer, RF filter, RF circulator, RF isolator, antenna, impedance matching element, 50 ohm termination element, integrated ground plane, RF shielding element, EMI shielding element, RF combiner, RF splitter, transformer, switch, power splitter, power combiner, memory chip, or microcontroller.

[0031] An aspect of the present disclosure, as embodied and broadly described herein, is a method for encapsulating a substrate to isolate constituents of the substrate from contaminating semiconductor materials and / or semiconductor devices in a device structure, the method comprising the steps of cleaning the surface of the substrate using a plasma or other surface treatment process, the substrate having a thickness in the range of 25 μm to 2500 μm; depositing an adhesion layer of SiO in the range of 20 Å to 40,000 Å, and during deposition of the adhesion layer, reducing the oxygen gas and replacing the oxygen gas with nitrogen gas until the nitrogen gas is 100% of the gas. x / SiN yIt forms a transition layer with a thickness of 20 Å to 40,000 Å, and when the gas becomes 100% nitrogen gas, SiO x / SiN y The present invention relates to a method comprising, consisting essentially of, or consisting of transferring a silicon nitride (SiN) layer onto a SiN(z) substrate, forming a via mask pattern and etching the encapsulation layer to expose metal connectors and a heat spreader, and attaching or forming one or more semiconductors, passive devices, or MEMS devices on the substrate. In one aspect, the one or more semiconductors, passive devices, or MEMS devices attached to the substrate are an integral part of the substrate. In another aspect, the deposited adhesion layer, transfer layer, and final layer are formed of SiO, SiO x / SiN y and a SiN structure. In another aspect, the thickness of the substrate is 100 to 200 μm. In another aspect, the thickness of each of the adhesion layer, the transition layer, and the final layer is 100 to 200 μm. In another aspect, the thickness of each of the adhesion layer, the transition layer, and the final layer is 100 to 200 μm. In another aspect, the deposition conditions of temperature and plasma density / energy are SiN (z) is selected to be stoichiometrically SiN. In another aspect, the substrate is selected from at least one of borosilicate glass, photosensitive glass, glass / ceramic composite, or ceramic. In another aspect, the thickness of the SiO layer is greater than 20 Å and less than 10 μm. In another aspect, the thickness of the SiO layer is greater than 20 Å and less than 10 μm. x / SiN y The thickness of the layer is greater than 20 Å and less than 10,000 Å. x In the layer, x is in the range of 0.5 to 3. In another embodiment, SiN yIn the layer, y ranges from 0.5 to 2. In another aspect, the thickness of the SiN layer is greater than 20 Å and less than 10,000 Å. In another aspect, the substrate comprises an electrically and thermally conductive structure. In another aspect, the semiconductor device comprises RF circuitry that removes at least 10% of RF parasitic signals associated with transfer from the substrate to the electrically and thermally conductive structure. In another aspect, the electrically and thermally conductive structure comprises a through-hole via, a blind via, an interconnect, or a heat spreader element. In another aspect, the through-hole via, the blind via, the interconnect, or the heat spreader element comprises copper or another metal. In another aspect, the device structure is stacked or layered to form the equivalent of a multilayer PCB structure. In another aspect, the semiconductor device comprises at least one of a microprocessor / CPU, optical, electro-optical, MEMS device, antenna, RF circulator, RF isolator, RF combiner, RF coupler, RF splitter, transformer, AD converter, high speed DA converter, optical coupler, optical modulator, laser diode, VECSLS, switch, multiplexer, duplexer, diplexer, memory and / or diplexer, RF filter, RF circulator, RF isolator, antenna, impedance matching element, 50 ohm termination element, integrated ground plane, RF shielding element, EMI shielding element, RF combiner, RF splitter, transformer, switch, power splitter, power combiner, memory chip, or microcontroller.

[0032] An aspect of the present disclosure, as embodied and broadly described herein, is a method for preventing contamination of a semiconductor device, comprising cleaning a surface of a substrate using a plasma or other surface treatment process by encapsulating the substrate, the substrate having a thickness in the range of 25 μm to 2500 μm, and depositing an adhesion layer of SiO in the range of 20 Å to 40,000 Å, during deposition of the adhesion layer, by reducing oxygen gas and replacing oxygen gas with nitrogen gas until nitrogen gas is 100% of the gas. x / SiN yIt forms a transition layer with a thickness of 20 Å to 40,000 Å, and when the gas becomes 100% nitrogen gas, SiO x / SiN y to SiN(z), forming a via mask pattern and etching the encapsulation layer to expose metal connectors and heat spreaders, and attaching or forming one or more semiconductor, passive, or MEMS devices on the substrate, thereby isolating one or more components of the substrate from contaminating semiconductor material and / or semiconductor devices of the device structure, wherein the substrate is protected from contamination.

[0033] The principal features of this invention can be employed in various embodiments without departing from the scope of the invention. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of this invention and are covered by the claims.

[0034] All publications and patent applications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

[0035] The use of the word "a" or "an" in the claims and / or this specification when used in conjunction with the word "comprising" can mean "one," but is also consistent with the meanings of "one or more," "at least one," and "one or more." The use of the word "or" in the claims is used to mean "and / or" unless expressly specified to represent alternatives only or where the alternatives are mutually exclusive, although this disclosure supports both alternative and "and / or" definitions. Throughout this application, the term "about" is used to indicate that a value includes the inherent variation of error for the device, the inherent variation of error for the method employed to determine the value, or the variation that exists among study subjects.

[0036] As used herein and in the claims, the words "comprising" (and any form of "comprising," such as "comprise" and "comprises"), "having" (and any form of "having," such as "have" and "has"), "including" (and any form of "including," such as "includes" and "include"), or "containing" (and any form of "containing," such as "contains" and "contain") are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. In any embodiment of the compositions and methods provided herein, "comprising" is interchangeable with "consisting essentially of" or "consisting of." As used herein, the phrase "consisting essentially of" requires certain entities or steps, as well as entities or steps that do not materially affect the characteristics or function of the claimed invention. As used herein, the term "comprising" is used to indicate only the presence of a listed entity (e.g., feature, element, attribute, property, method / process step, or limitation) or group of entities (e.g., feature, element, attribute, property, method / process step, or limitation).

[0037] As used herein, the term "or combinations thereof" refers to all permutations and combinations of the items listed before the term. For example, "A, B, C, or combinations thereof" is intended to include at least one of A, B, C, AB, AC, BC, or ABC, and, where order is important in the particular context, also includes BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing this example, combinations containing repeats of one or more items or terms are expressly included, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABAB, etc. One of ordinary skill in the art will understand that there is generally no limit to the number of items or terms in any combination unless otherwise clear from the context.

[0038] As used herein, approximation words, including but not limited to "about," "substantial," or "substantially," when so modified, are understood not to be necessarily absolute or complete, but express conditions that would be considered close enough for one of ordinary skill in the art to justify as existing. The degree to which an expression may vary depends on the magnitude of the change that may occur and whether a person of ordinary skill in the art would still recognize that the modified feature still possesses the desired characteristics and functionality of the unmodified feature. Following the foregoing discussion, generally, numerical values ​​modified herein by approximation words such as "about" may vary by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12, or 15% from the stated value.

[0039] All of the structures and / or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the structures and methods of the present invention have been described in terms of preferred embodiments, it will be apparent to those skilled in the art that variations can be made to the structures and / or methods, and in the steps or sequence of steps of the methods, described herein without departing from the concept, spirit, and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope, and concept of the invention as defined by the appended claims.

[0040] All of the devices and / or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the devices and / or methods of the present invention have been described in terms of preferred embodiments, it will be apparent to those skilled in the art that variations can be made to the structures and / or methods, and in the steps or sequence of steps of the methods, described herein without departing from the concept, spirit, and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope, and concept of the invention as defined by the appended claims.

[0041] Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore to be understood that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the present disclosure. Accordingly, the protection sought herein is as set forth in the following claims.

[0042] Modifications, additions, or omissions may be made to the systems and devices described herein without departing from the scope of the invention. System and device components may be integrated or separated. Furthermore, system and device operations may be performed by more, fewer, or other components. Methods may include more, fewer, or other steps. Steps may also be performed in any suitable order.

[0043] As an aid to the Patent Office and any reader of any patent issued to this application in interpreting the claims appended hereto, Applicants wish to note that the appended claims as they existed on the filing date of this specification are not intended to invoke the sixth paragraph of 35 U.S.C. § 112, paragraph 35, except where the words "means for" or "step for" are expressly used in a particular claim.

[0044] For each claim, each dependent claim may depend on both the independent claim and each preceding dependent claim, for each and every claim, so long as the preceding claim provides a proper antecedent basis for a claim term or element.

Claims

1. SiO for encapsulating the substrate to isolate the constituents of the substrate from contaminating semiconductor materials and / or semiconductor devices. ２ , SiO ｘ / SiN ｙ and a device structure comprising a SiN structure.

2. The device structure of claim 1 , wherein the substrate is selected from at least one of borosilicate glass, photosensitive glass, glass / ceramic composite, or ceramic.

3. The SiO ２ 10. The device structure of claim 1, wherein the layer has a thickness greater than 20 Å and less than 10 μm.

4. The SiO ｘ / SiN ｙ 10. The device structure of claim 1, wherein the layer has a thickness greater than 20 Å and less than 10,000 Å.

5. The SiO ｘ 5. The device structure of claim 4, wherein in the layer, x ranges from 0.5 to 3.

6. The SiN ｙ 5. The device structure of claim 4, wherein in the layer, y is in the range of 0.5 to 2.

7. 10. The device structure of claim 1, wherein the thickness of the SiN layer is greater than 20 Å and less than 10,000 Å.

8. The device structure of claim 1 , wherein the substrate comprises an electrically and thermally conductive structure.

9. 10. The device structure of claim 8, wherein the semiconductor device comprises an RF circuit that removes at least 10% of RF parasitic signals associated with transfer from the substrate to the electrically and thermally conductive structure.

10. The device structure of claim 8 , wherein the electrically and thermally conductive structure comprises a through-hole via, a blind via, an interconnect, or a heat spreader element.

11. The device structure of claim 10 , wherein the through-hole via, blind via, interconnect, or heat spreader element comprises copper or another metal.

12. The device structure of claim 1 , wherein the device structure is stacked or layered to form the equivalent of a multi-layer PCB structure.

13. 10. The device structure of claim 1, wherein the semiconductor device comprises a microprocessor / CPU, optical, electro-optical, MEMS device, antenna, RF circulator, RF isolator, RF combiner, RF coupler, RF splitter, transformer, analog-to-digital converter, high speed digital-to-analog converter, optical coupler, optical modulator, laser diode, VECSS, switch, multiplexer, duplexer, diplexer, memory and / or diplexer, RF filter, RF circulator, RF isolator, antenna, impedance matching element, 50 ohm termination element, integrated ground plane, RF shielding element, EMI shielding element, RF combiner, RF splitter, transformer, switch, power splitter, power combiner, memory chip, or microcontroller.

14. 1. A method for encapsulating a substrate to isolate constituents of the substrate from contaminating semiconductor materials and / or semiconductor devices of a device structure, comprising: cleaning the surface of the substrate using a plasma or other surface treatment process, the substrate having a thickness in the range of 25 μm to 2500 μm; SiO in the range of 20 Å to 40,000 Å ２ and depositing an adhesion layer of SiO 2 by reducing the oxygen gas and replacing it with nitrogen gas until nitrogen gas is 100% of the gas during the deposition of the adhesion layer. ｘ / SiN ｙ and forms a transition layer having a thickness of 20 Å to 40,000 Å. When the gas becomes 100% nitrogen gas, the SiO ｘ / SiN ｙ SiN （ｚ） and transferring the forming a via mask pattern and etching the encapsulation layer to expose the metal connector and the heat spreader; attaching or forming one or more semiconductor, passive, or MEMS devices on the substrate; The method comprising:

15. The method of claim 14 , wherein the one or more semiconductor, passive, or MEMS devices attached to the substrate are an integral part of the substrate.

16. The deposited adhesion layer, transfer layer, and final layer are preferably SiO ２ , SiO ｘ / SiN ｙ and a SiN structure.

17. The method of claim 14, wherein the substrate has a thickness of 100 to 200 μm.

18. 15. The method of claim 14, wherein the adhesive layer, transfer layer, and final layer each have a thickness of 100 to 200 μm.

19. 15. The method of claim 14, wherein the adhesive layer, transfer layer, and final layer have a thickness of 100 to 200 μm.

20. The deposition conditions of temperature and plasma density / energy are （ｚ） The method of claim 14 , wherein is selected to be stoichiometrically SiN.

21. 15. The method of claim 14, wherein the substrate is selected from at least one of borosilicate glass, photosensitive glass, glass / ceramic composite, or ceramic.

22. The SiO ２ 15. The method of claim 14, wherein the layer has a thickness greater than 20 Å and less than 10 μm.

23. The SiO ｘ / SiN ｙ 15. The method of claim 14, wherein the layer has a thickness greater than 20 Å and less than 10,000 Å.

24. The SiO ｘ The method of claim 14, wherein in the layer, x ranges from 0.5 to 3.

25. The SiN ｙ The method of claim 14, wherein in the layer, y is in the range of 0.5 to 2.

26. 15. The method of claim 14, wherein the thickness of the SiN layer is greater than 20 Å and less than 10,000 Å.

27. The method of claim 14 , wherein the substrate comprises an electrically and thermally conductive structure.

28. 15. The method of claim 14, wherein the semiconductor device comprises an RF circuit that removes at least 10% of RF parasitic signals associated with transfer from the substrate to the electrically and thermally conductive structure.

29. 30. The method of claim 28, wherein the electrically and thermally conductive structure comprises a through-hole via, a blind via, an interconnect, or a heat spreader element.

30. 30. The method of claim 29, wherein the through-hole via, blind via, interconnect, or heat spreader element comprises copper or another metal.

31. 15. The method of claim 14, wherein the device structure is stacked or layered to form the equivalent of a multi-layer PCB structure.

32. 15. The method of claim 14, wherein the semiconductor device comprises a microprocessor / CPU, optical, electro-optical, MEMS device, antenna, RF circulator, RF isolator, RF combiner, RF coupler, RF splitter, transformer, analog-to-digital converter, high speed digital-to-analog converter, optical coupler, optical modulator, laser diode, VECSS, switch, multiplexer, duplexer, diplexer, memory and / or diplexer, RF filter, RF circulator, RF isolator, antenna, impedance matching element, 50 ohm termination element, integrated ground plane, RF shielding element, EMI shielding element, RF combiner, RF splitter, transformer, switch, power splitter, power combiner, memory chip, or microcontroller.

33. 1. A method for preventing contamination of a semiconductor device, comprising: By encapsulating the substrate, cleaning the surface of the substrate using a plasma or other surface treatment process, wherein the thickness of the substrate is in the range of 25 μm to 2500 μm; SiO in the range of 20 Å to 40,000 Å ２ and during said deposition of said adhesion layer, reducing the oxygen gas and replacing said oxygen gas with said nitrogen gas until nitrogen gas is 100% of the gas, thereby forming a SiO ｘ / SiN ｙ and forms a transition layer having a thickness of 20 Å to 40,000 Å. When the gas becomes 100% nitrogen gas, the SiO ｘ / SiN ｙ SiN （ｚ） and transferring it to forming a via mask pattern and etching the encapsulation layer to expose the metal connectors and the heat spreader; attaching or forming one or more semiconductor, passive, or MEMS devices on said substrate; isolating one or more constituents of the substrate from contaminating semiconductor material and / or semiconductor devices of device structures by protecting the substrate from contamination.

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