Dry etching of boron-containing materials

Abstract

An exemplary semiconductor processing method can include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate can be contained within the processing region. The substrate can include a boron-containing material overlying a carbon-containing material. The method can include generating plasma effluents of the fluorine-containing precursor. The method can include contacting the substrate with the plasma effluents of the fluorine-containing precursor. The method can include removing the boron-containing material from the substrate.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 18 / 098,791, filed January 19, 2023, entitled "DRY ETCH OF BORON-CONTAINING MATERIAL," which is incorporated herein by reference in its entirety.

[0002] Technical Field The present technology relates to semiconductor processes and materials, and more particularly to removing boron-containing materials overlying other materials. [Background technology]

[0003] Integrated circuits are made possible by processes that fabricate intricately patterned layers of material on a substrate surface. Fabricating patterned materials on a substrate requires controlled methods for the formation and removal of exposed material. Stacked memory, such as vertical or 3D NAND, can involve the formation of a series of alternating layers of dielectric material, through which multiple memory holes or openings can be etched. The material properties of the layers of material, as well as the process conditions and materials for etching, can affect the uniformity of the resulting structures. Resistance to etchants can lead to non-uniformity in the pattern formation, which can further affect the uniformity of the resulting structures.

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0005] An exemplary semiconductor processing method can include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate can be contained within the processing region. The substrate can include a boron-containing material overlying a carbon-containing material. The method can include generating plasma effluents of the fluorine-containing precursor. The method can include contacting the substrate with the plasma effluents of the fluorine-containing precursor. The method can include removing the boron-containing material from the substrate.

[0006] In embodiments, the fluorine-containing precursor may be or include nitrogen trifluoride (NF3). The boron-containing material may be characterized by a boron content of greater than or equal to about 20 atomic percent. The boron-containing material may further include nitrogen. The boron-containing material and the carbon-containing material may define at least one opening extending through both the boron-containing material and the carbon-containing material. The temperature within the semiconductor processing chamber may be maintained at about 100°C or less. The pressure within the semiconductor processing chamber may be maintained at about 1 Torr or less. When generating plasma effluents of the fluorine-containing precursor, plasma power may be maintained at about 1,000 W or more. The boron-containing material may be removed from the substrate at a rate of greater than or equal to about 5,000 Å / min. The removal selectivity of the boron-containing material over the carbon-containing material may be greater than or equal to about 10:1.

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing hard mask material. The boron-containing material and the carbon-containing hard mask material may define at least one opening extending through both the boron-containing material and the carbon-containing hard mask material. The method may include generating plasma effluents of the fluorine-containing precursor. The method may include contacting a substrate with the plasma effluents of the fluorine-containing precursor. The method may include removing the boron-containing material from the substrate.

[0008] In embodiments, the fluorine-containing precursor can be or include nitrogen trifluoride (NF3). The flow rate of the fluorine-containing precursor can be about 1,000 sccm or less. The boron-containing material can be characterized by a thickness of about 250 nm or more. The fluorine-containing precursor can be delivered to a processing region of a semiconductor processing chamber without a carrier gas. The method can include etching a carbon-containing hard mask material to form at least one opening extending through the carbon-containing hard mask material before delivering the fluorine-containing precursor. Removal of the boron-containing material from the substrate can be performed in the same semiconductor processing chamber as etching the carbon-containing hard mask material.

[0009] Some embodiments of the present technology may include a semiconductor processing method. The method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The fluorine-containing precursor may be or include nitrogen trifluoride (NF3). A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing material. The method may include generating plasma effluents of the fluorine-containing precursor. In generating the plasma effluents of the fluorine-containing precursor, plasma power may be maintained between about 500 W and about 3,000 W. The method may include contacting a substrate with the plasma effluents of the fluorine-containing precursor. The method may include removing the boron-containing material from the substrate.

[0010] In embodiments, the boron-containing material can be removed from the substrate in about 10 minutes or less. The carbon-containing material can define at least one opening. Removing the boron-containing material from the substrate can preserve sidewalls and a bottom surface of the at least one opening.

[0011] Such techniques can provide many advantages over conventional systems and techniques. For example, the processes and structures can selectively remove boron-containing materials relative to carbon-containing materials and other materials during etching operations. Furthermore, operation of embodiments of the present techniques can improve etch rates and eliminate undercut profiles in underlying materials, such as carbon-containing materials, and other underlying materials, such as silicon oxide and / or silicon nitride. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the following description and accompanying figures.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic top view of an exemplary processing system in accordance with some embodiments of the present technique; [Figure 2] 1 is a schematic cross-sectional view of an exemplary processing system in accordance with some embodiments of the present technique; [Figure 3] 1 illustrates selected operations of a forming method in accordance with some embodiments of the present technique. [Figure 4A] 1A-1C are schematic cross-sectional views of substrate material performing selected operations in accordance with some embodiments of the present technique; [Figure 4B] 1A-1C are schematic cross-sectional views of substrate material performing selected operations in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0014] Some figures are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically and explicitly stated to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include unnecessary or exaggerated material for illustrative purposes.

[0015] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numerals, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0016] As 3D NAND structures grow with the number of cells formed, the aspect ratios of memory holes and other structures increase, sometimes dramatically. During 3D NAND processing, a stack of placeholder layers and dielectric materials can be first formed, within which memory cells can be formed. These placeholder layers can have various operations performed to position the structures before the material is completely removed and replaced with metal. This layer is often formed over a conductive layer, such as polysilicon. Once the memory holes are formed, openings can extend through all of the alternating layers of material before accessing the polysilicon or other material substrate. Subsequent processing can form stair-like structures for contacts or can laterally excavate the placeholder material.

[0017] A reactive ion etching ("RIE") operation can be performed to create high aspect ratio memory holes. The RIE process can often involve a combination of chemical and physical removal of alternating layers. As one non-limiting example, if the alternating layers can include silicon oxide and silicon nitride, the silicon oxide may be removed more by physical bombardment of the layers during RIE, and the silicon nitride may be removed more by chemical reaction of the RIE precursor with the nitride material.

[0018] Conventional techniques can struggle with uniformity and control during memory hole formation due to material differences between the two layer types, as well as the RIE process and materials. Furthermore, memory holes can expand outward during etching, widening the critical dimension within the stack structure where RIE can be performed to create the memory holes. Bowing can occur anywhere throughout the structure and can be caused by multiple issues. For example, bowing can be caused by limited passivation on the sidewalls, which can result in a certain amount of lateral etching. Bowing can also occur due to changes in the hard mask material or other structural features. For example, if the edge of the hard mask can erode during the RIE process, ions can be projected into the feature or memory hole at a direction or angle different from normal to the substrate, which can result in additional lateral etching in some areas of the structure until the taper of the hard mask is removed or etched. Furthermore, memory holes can become partially or completely blocked due to redeposition of etched material. Partial blocking can affect the circularity of the memory hole. Partial or complete blockage can adversely affect the electrical performance of the final device. In some technologies, the hard mask may not be perfectly uniform due to openings in the hard mask.

[0019] To address these issues, conventional techniques limit the number of stacked layers that can be etched at one time. As the number of layers increases, many conventional techniques fabricate structures in two separate cycles. For example, conventional techniques may fabricate a first set of layers and then etch those layers. Memory holes may be plugged, and a second set of layers may be formed over the first set. The second set of layers can then be etched, similar to the first set of plugs, to fully form the structure. However, hole alignment between sets is not nearly perfect, resulting in offsets that can impact fabrication and cell formation. Furthermore, stopping fabrication between sets can result in material differences due to different exposure and processing levels.

[0020] The present technique overcomes these problems by using a boron-containing material as a mask to open a hard mask overlying the alternating layers. The boron-containing material is less likely to clog during hard mask opening, potentially resulting in more uniform features or openings in the hard mask. Furthermore, intermittent flashing during etching can prevent clogging and therefore improve uniformity. More uniform features or openings can result in more uniform etching of the alternating layers underlying the hard mask. However, unlike conventional techniques, conventional wet etching may be unable to remove the boron-containing material or may have slow removal rates and poor selectivity for the boron-containing material. The present technique also overcomes these problems by using a fluorine-containing precursor to remove the boron-containing material. The removal operation can remove different thicknesses of the boron-containing material across the substrate while minimizing impact on underlying materials, such as the hard mask.

[0021] While the remaining disclosure routinely identifies particular materials and semiconductor structures utilizing the disclosed technology, it will be readily understood that the systems, methods, and materials are equally applicable to many other structures that can benefit from aspects of the technology. Thus, the technology should not be considered limited to use with only 3D NAND processes or materials. Furthermore, while an exemplary chamber is described to provide a foundation for the technology, it should be understood that the technology can be applied to any semiconductor processing chamber that can enable the described operations.

[0022] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and / or cure chamber processing system 10, according to embodiments. The tool or processing system 10 illustrated in FIG. 1 may include multiple processing chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The processing chambers may include any number of structures or components and any number or combination of processing chambers.

[0023] To transfer substrates between chambers, the transfer chamber 20 can include a robotic transport mechanism 22. The transport mechanism 22 can each have a pair of substrate transport blades 22a attached to the distal end of an extendable arm 22b. The blades 22a can be used to transport individual substrates into and out of the processing chambers. In operation, one of the substrate transport blades, such as blade 22a of the transport mechanism 22, can retrieve a substrate W from one of the load lock chambers, such as chambers 16a-b, and transport the substrate W to a first processing stage, such as a processing process described below for chambers 24a-d. Chambers can be included to perform individual or combinations of the described techniques. For example, one or more chambers can be configured to perform deposition or etching operations, while one or more other chambers can be configured to perform pre-processing operations and / or one or more of the described post-processing operations. Various configurations are encompassed within the present technology, and various additional fabrication operations typically performed in semiconductor processing can also be performed.

[0024] If a chamber is occupied, the robot can wait until processing is complete, then remove the processed substrate from the chamber using one blade 22a and insert a new substrate using a second blade. Once the substrate has been processed, it can then be moved to a second stage of processing. At each move, the transport mechanism 22 can generally have one blade carrying the substrate and one empty blade to perform the substrate swap. The transport mechanism 22 can wait at each chamber until the swap is accomplished.

[0025] Once processing is completed in a processing chamber, the transport mechanism 22 can remove the substrate W from the last processing chamber and transport the substrate W to a cassette in the load lock chambers 16a-b. From the load lock chambers 16a-b, the substrate can be moved to the factory interface 12. The factory interface 12 can operate to transfer substrates between the pod loaders 14a-d and the load lock chambers 16a-b in a generally atmospheric clean environment. The clean environment within the factory interface 12 can generally be provided through an air filtration process, such as HEPA filtration. The factory interface 12 can also include a substrate orienter / aligner that can be used to properly align substrates prior to processing. At least one substrate robot, such as robots 18a-b, can be positioned within the factory interface 12 to transport substrates between various locations within the factory interface 12 and to other locations in communication therewith. The robots 18a-b may be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0026] The processing system 10 may further include an integrated metrology chamber 28 for providing control signals, which may provide adaptive control for any of the processes being performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices for measuring various film properties, such as thickness, roughness, composition, etc., which may further characterize lattice parameters, such as critical dimensions, sidewall angle, and feature height under vacuum, in an automated manner.

[0027] Each of the processing chambers 24a-d can be configured to perform one or more processing steps in the fabrication of semiconductor structures, and any number and combination of processing chambers can be used on the multichamber processing system 10. For example, any of the processing chambers can be configured to perform many substrate processing operations, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and any number of deposition processes, including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, alignment, and other substrate processes. Some specific processes that can be performed in any of the chambers or any combination of chambers can be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma treatment. Any other processes can be similarly performed in a specific chamber incorporated within the multichamber processing system 10, including any of the processes described below, as will be readily recognized by those skilled in the art.

[0028] FIG. 2 illustrates a schematic cross-sectional view of an exemplary processing chamber 200 suitable for patterning a material layer disposed on a substrate 202 therein. While the exemplary processing chamber 200 is suitable for performing a patterning process, it should be understood that aspects of the present technique can be practiced in a variety of chambers, and that substrate support according to the present technique can be included in an etch chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 200 can include a chamber body 205 defining a chamber volume 201 in which a substrate can be processed. The chamber body 205 can have sidewalls 212 and a bottom 218 connected to a ground 226. The sidewalls 212 can have a liner 215 to protect the sidewalls 212 and extend the maintenance interval of the plasma processing chamber 200. The dimensions of the chamber body 205 and associated components of the plasma processing chamber 200 are not limited and can generally be increased in proportion to the size of the substrate 202 to be processed. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, among others, such as display substrates or solar cell substrates.

[0029] The chamber body 205 can support a chamber lid assembly 210 that surrounds the chamber volume 201. The chamber body 205 can be fabricated from aluminum or other suitable materials. A substrate access port 213 can be formed through a sidewall 212 of the chamber body 205 to facilitate transfer of the substrate 202 into and out of the plasma processing chamber 200. This access port 213 can be coupled to a transfer chamber and / or other chambers of a substrate processing system, as described above. A pumping port 245 can be formed through the sidewall 212 of the chamber body 205 and connected to the chamber volume 201. A pumping device can be connected to the chamber volume 201 through the pumping port 245 to evacuate and control the pressure within the processing volume. The pumping device can include one or more pumps and a throttle valve.

[0030] The gas panel 260 can be connected to the chamber body 205 by gas lines 267 to supply process gases to the processing volume 201. The gas panel 260 can include one or more process gas sources 261, 262, 263, 264, and can further include inert, non-reactive, and reactive gases for various processes. Examples of process gases that can be provided by the gas panel 260 include, but are not limited to, hydrocarbon gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon gas, chlorine, nitrogen, helium, or oxygen gas, as well as various additional materials. Additionally, the process gas may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases, such as BCl, C2F, C4F, C4F, CHF, CH2F, CH3F, NF, NH, CO, SO, CO, N2, NO, N2O, and H2, among various additional precursors.

[0031] A valve 266 can control the flow rate of process gases from the sources 261, 262, 263, and 264 of the gas panel 260 and can be managed by a controller 265. The flow of gas supplied from the gas panel 260 to the chamber body 205 can include a combination of gases from one or more sources. The lid assembly 210 can include a nozzle 214. The nozzle 214 can be one or more ports for introducing process gases from the sources 261, 262, 264, and 263 of the gas panel 260 into the chamber volume 201. After the process gases are introduced into the plasma processing chamber 200, the gases are excited to form a plasma. An antenna 248, such as one or more inductor coils, can be provided adjacent to the plasma processing chamber 200. An antenna power supply 242 can power the antenna 248 via a matching circuit 241 that inductively couples energy (e.g., RF energy) to the process gases to maintain a plasma formed from the process gases in the chamber volume 201 of the plasma processing chamber 200. Alternatively, or in addition to the antenna power supply 242, a process electrode below the substrate 202 and / or above the substrate 202 may be used to capacitively couple RF power to the process gas to maintain a plasma within the chamber volume 201. The operation of the power supply 242 may be controlled by a controller (e.g., controller 265) that also controls the operation of other components within the plasma processing chamber 200.

[0032] A substrate support pedestal 235 may be disposed within the chamber volume 201 to support the substrate 202 during processing. The substrate support pedestal 235 may include an electrostatic chuck 222 for holding the substrate 202 during processing. The electrostatic chuck ("ESC") 222 holds the substrate 202 to the substrate support pedestal 235 using electrostatic attraction. The ESC 222 is powered by an RF power supply 225 integrated with a matching circuit 224. The ESC 222 may include an electrode 221 embedded in a dielectric. The electrode 221 may be coupled to the RF power supply 225 to provide a bias that attracts plasma ions formed by the process gases in the chamber volume 201 toward the ESC 222 and the substrate 202 positioned on the pedestal. The RF power supply 225 may be cycled on and off or pulsed during processing of the substrate 202. The ESC 222 may include an isolator 228 to reduce the plasma's attraction to the sidewalls of the ESC 222 to extend the maintenance lifecycle of the ESC 222. Additionally, the substrate support pedestal 235 may include a cathode liner 236 to protect the sidewalls of the substrate support pedestal 235 from the plasma gases and extend the maintenance intervals of the plasma processing chamber 200.

[0033] The electrode 221 may be connected to a power supply 250. The power supply 250 may provide a chucking voltage of about 200 volts to about 2000 volts to the electrode 221. The power supply 250 may also include a system controller for controlling the operation of the electrode 221 by inducing a DC current to the electrode 221 to chuck and dechuck the substrate 202. The ESC 222 may include a heater disposed within the pedestal and connected to a power supply for heating the substrate, while the cooling base 229 supporting the ESC 222 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 222 and the substrate 202 disposed thereon. The ESC 222 may be configured to operate within a temperature range required by the thermal budget of a device fabricated on the substrate 202. For example, the ESC 222 may be configured to maintain the substrate 202 at a temperature of about −150° C. or lower to about 500° C. or higher, depending on the process being performed.

[0034] A cooling base 229 may be provided to assist in controlling the temperature of the substrate 202. To mitigate process drift and time, the temperature of the substrate 202 may be maintained substantially constant by the cooling base 229 while the substrate 202 is in the chamber. In some embodiments, the temperature of the substrate 202 may be maintained at a temperature between about −150° C. and about 500° C. throughout subsequent processes, although any temperature may be utilized. A cover ring 230 may be disposed on the ESC 222 along the periphery of a substrate support pedestal 235. The cover ring 230 may be configured to contain etching gases to desired portions of the exposed upper surface of the substrate 202 while shielding the upper surface of the substrate support pedestal 235 from the plasma environment within the plasma processing chamber 200. Lift pins may be selectively moved through the substrate support pedestal 235 to lift the substrate 202 above the substrate support pedestal 235 and facilitate access to the substrate 202 by a transfer robot or other suitable transfer mechanism, as previously described.

[0035] The controller 265 can be utilized to control process sequences and regulate gas flow rates and other process parameters from the gas panel 260 to the plasma processing chamber 200. The software routines, when executed by the CPU, can transform the CPU into a special-purpose computer, such as a controller, and control the plasma processing chamber 200 to perform processes according to the present disclosure. The software routines can also be stored and / or executed by a second controller that can be associated with the plasma processing chamber 200.

[0036] As described above, the present technique can open a carbon-containing material, such as a carbon-containing hard mask material, using a boron-containing material as a mask overlying the carbon-containing material. FIG. 3 illustrates exemplary operations in a semiconductor processing method 300 according to embodiments of the present technique. Method 300 can include one or more operations prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or other operations that can be performed before the described operations. For example, the method can begin after multiple layers of material overlying the boron-containing material have been patterned and / or removed, and the method includes patterning the boron-containing material. However, as discussed above, it should be understood that the illustration illustrates only one exemplary process that can be employed for patterning a carbon-containing material according to embodiments of the present technique, and the description herein is not intended to limit the present technique to only this process. Some or all of the operations can be performed in a chamber or system tool, as described above, or can be performed in different chambers on the same system tool, which can include a chamber that can perform the operations of method 300.

[0037] Method 300 may include several optional operations that may or may not be specifically associated with some embodiments of methods according to the present technology, as illustrated. For example, while many of the operations are described to provide a broader range of structure formations, they are not critical to the technology or may be performed by alternative methodologies discussed further below. Method 300 describes operations shown generally in FIGS. 4A-4B, examples of which are described in conjunction with the operations of method 300. It should be understood that FIGS. 4A-4B show only partial schematic views, and that a substrate may include various structural sections having the aspects shown in the figures, as well as alternative structural aspects that can still benefit from the operations of the present technology.

[0038] Method 300 may or may not include optional operations to develop the semiconductor structure for a particular manufacturing operation. It should be understood that method 300 can be performed on a variety of semiconductor structures, and FIGS. 4A-4B illustrate one exemplary structure on which the etching process can be performed. As shown in FIG. 4A, the processed semiconductor structure 400 can include a substrate 405, which can have multiple layers stacked over the substrate, which can be silicon-containing materials such as polysilicon, silicon germanium, or other substrate materials, and can be conductors for contact with subsequent metallization. As a non-limiting example, these layers can include an IPD layer that includes alternating layers of dielectric material 410, which can be silicon oxide, and placeholder material 415, which can be silicon nitride. Placeholder material 415 can be or can include a material that will be removed to create individual memory cells in a subsequent operation. In the illustrated example, only four layers of material are shown, but it should be understood that the exemplary structure may include any number of layers as previously described (possibly including tens or hundreds of layers), and the illustration is merely a schematic representation of aspects of the present technology.

[0039] The exposed boron-containing material 425, in embodiments, can be characterized by a thickness of about 250 nm or greater, and can be characterized by a thickness of about 300 nm or greater, about 350 nm or greater, about 400 nm or greater, about 450 nm or greater, about 500 nm or greater, or greater. Conventional techniques can struggle to remove boron-containing material 425 characterized by a thickness of about 250 nm or greater because the etch selectivity between the boron-containing material 425 and the mask material 420 can be poor. Furthermore, conventional techniques can undercut or damage the mask material 420 during removal of the boron-containing material 425 and / or can damage underlying materials such as silicon oxide and / or silicon nitride. In embodiments, the boron-containing material can be characterized by a boron content of about 20 atomic % or greater, e.g., about 22 atomic % or greater, about 24 atomic % or greater, about 26 atomic % or greater, about 28 atomic % or greater, about 30 atomic % or greater, about 32 atomic % or greater, about 34 atomic % or greater, about 36 atomic % or greater, about 38 atomic % or greater, about 40 atomic % or greater, or greater.

[0040] In embodiments, the boron-containing material 425 and the mask material 420 can be characterized by a cell region, a peripheral region, and combinations thereof. The cell region can include a narrower width of the mask material 420, and therefore the width of the overlying boron-containing material 425 can also be narrower. The peripheral region can include a wider width of the mask material 420, and therefore the width of the overlying boron-containing material 425 can also be wider. The boron-containing material 425 overlying the mask material 420 in the peripheral region can be thicker than the boron-containing material 425 overlying the mask material 420 in the cell region. As described below, the present techniques can enable the removal of the boron-containing material 425 from the cell region and the peripheral region without damaging the underlying mask material 420 and without leaving any residue of the boron-containing material 425.

[0041] The mask material 420 may be formed over the IPD layer and may be a carbon-containing material, such as an amorphous carbon carbon-containing hard mask material, or other carbon-containing material that may be formed on an underlying layer during subsequent cleaning and / or etching operations. A boron-containing material 425 may be disposed over the mask material 420. In embodiments, the boron-containing material 425 may also include nitrogen and may be a boron-nitrogen-containing material. The boron-containing material 425 may include a plurality of openings or apertures 430. The openings or apertures 430 may extend through the entire thickness of the boron-containing material 425, exposing the underlying mask material 420. The carbon-containing material of the mask material 420 may also include a plurality of openings or apertures 440. The openings or apertures 440 may extend through the entire thickness of the carbon-containing material of the mask material 420, exposing the underlying stack of the dielectric material 410 and the placeholder material 415.

[0042] As shown, multiple materials may be present and may be exposed to etchant materials that may be used in an etching process. Method 300 may be performed to etch or remove boron-containing material 425 to allow subsequent processing to proceed, while minimizing or eliminating etching or damage to the carbon-containing material of mask material 420 and / or underlying materials such as silicon oxide and / or silicon nitride. Utilizing process conditions and precursors according to embodiments of the present technology may limit or prevent etching of mask material 420 during etching and removal of boron-containing material 425.

[0043] As discussed above, the boron-containing material 425 may be discontinuous such that the material includes openings or apertures 430. The mask material 420 may be exposed in recessed features, such as the openings or apertures 430, and may include openings or apertures 440 aligned with the openings or apertures 430 in the boron-containing material 425. In an embodiment, the method 300 may include, in optional operation 305, etching the mask material 420 to form the openings or apertures 440. The mask material 420 may be etched using any etching method, such as using an oxygen-containing precursor or its plasma effluent. The boron-containing material 425 may function as a mask to open the openings 440 in the mask material 420. The etching in optional operation 305 may form features 440 (sometimes referred to as holes) in the mask material 420. The aspect ratio of the features or openings 440 can be about 10:1 or greater, about 20:1 or greater, about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, or greater.

[0044] The method 300 may include supplying a fluorine-containing precursor to a processing region of a semiconductor processing chamber in operation 310. The processing region may contain a substrate, such as the processed semiconductor structure 400, which may have exposed boron-containing material 425, such as a boron-nitrogen-containing material, and exposed carbon-containing material (e.g., mask material 420), such as a carbon-containing hard mask and / or underlying material (e.g., silicon oxide and / or silicon nitride). Removal of the boron-containing material 425 may be necessary for continued processing, such as etching an overlying material, such as mask material 420. If present on the substrate 405, the boron-containing material 425 may adversely affect subsequent operations or increase the likelihood of defects. The fluorine-containing precursor may be supplied to the processing region to selectively remove the boron-containing material 425 relative to the underlying mask material 420.

[0045] The fluorine-containing precursor used in method 300 can include any fluorine-containing precursor. An exemplary fluorine-containing precursor can include nitrogen trifluoride (NF), which can be flowed into the processing region without passing through a plasma. Other fluorine sources can be used in conjunction with or in place of nitrogen trifluoride. Generally, a fluorine-containing precursor is flowed into the processing region and can include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride (CF), hydrogen fluoride (HF), sulfur hexafluoride (SF), xenon difluoride (XeF), and various other fluorine-containing precursors used or useful in semiconductor processing. The precursor can include various carrier gases, which can include nitrogen, helium, argon, or other noble gases, inert gases, or useful precursors. The carrier gas can be used to dilute the fluorine-containing precursor, thereby reducing the etch rate and allowing for better etching control. However, it is contemplated that the fluorine-containing precursor can be delivered without other gases.

[0046] The flow rate of one or more of the fluorine-containing precursors can also be adjusted along with other process conditions. For example, the flow rate of the fluorine-containing precursor can be reduced, maintained, or increased during the performance of method 300. During any operation of method 300, the flow rate of the fluorine-containing precursor can be between about 2 sccm and about 1,000 sccm. Furthermore, the flow rate of the fluorine-containing precursor can be about 900 sccm or less, about 800 sccm or less, about 700 sccm or less, about 600 sccm or less, about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, about 150 sccm or less, about 100 sccm or less, etc. Additionally, the flow rate can be between any of these recited flow rates or within a narrower range encompassed by any of these values.

[0047] The method 300 may include forming a plasma in a processing region of the semiconductor processing chamber in operation 315. The plasma may produce plasma effluents of a fluorine-containing precursor. Operations 310 and 315 may be performed sequentially or substantially simultaneously in some embodiments. Furthermore, the plasma may be formed first from the fluorine-containing precursor, or, if present, may be formed from one or more inert precursors prior to adding the fluorine-containing precursor in different embodiments.

[0048] The localized plasma formed from the fluorine-containing precursor can provide a directional flow of plasma effluents toward the boron-containing material 425, resulting in efficient removal of the boron-containing material 425. The plasma can be a low-level plasma to limit the amount of bombardment, sputtering, and surface modification. In embodiments, the plasma power can be about 5,000 W or less, about 4,500 W or less, about 4,000 W or less, about 3,500 W or less, about 3,000 W or less, about 2,500 W or less, about 2,000 W or less, about 1,500 W or less, about 1,000 W or less, or less. Utilizing a plasma power of, for example, about 4,000 W or less can provide better control of plasma effluents and reduce profiling and / or damage to exposed surfaces, such as the mask material 420. However, if the plasma power is too low, for example, about 500 W or less, the etch rate of the boron-containing material 425 can be sacrificed, resulting in reduced throughput and increased wait times. In embodiments, the plasma power can be about 500 W or more, about 600 W or more, about 700 W or more, about 800 W or more, about 900 W or more, about 1,000 W or more, about 1,250 W or more, about 1,500 W or more, about 1,750 W or more, about 2,000 W or more, or more. Thus, the plasma power can be maintained between about 500 W and about 3,000 W, or any range therebetween.

[0049] The semiconductor structure 400 may be contacted by plasma effluents in operation 320, which may perform etching or removal of the boron-containing material 425 in operation 325. As shown in FIG. 4B , the plasma effluents may contact the semiconductor structure 400 and may contact all exposed surfaces, including surfaces to be etched, such as the boron-containing material 425, and surfaces to be maintained, such as the mask material 420, the placeholder material 415, and / or the dielectric material 410, which may include the sidewalls and / or bottom surface of the opening 440 in the mask material. During operation 325, the sidewalls and / or bottom surface of the opening 440 in the mask material may be maintained with minimal or no alteration or damage.

[0050] Embodiments of the present technology can remove the boron-containing material 425 relative to the mask material 420 or other materials at a rate of at least about 10:1, and can etch the boron-containing material 425 relative to the mask material 420 or other materials with a selectivity of about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 50:1 or greater, about 100:1 or greater, about 150:1 or greater, about 200:1 or greater, about 250:1 or greater, about 300:1 or greater, about 350:1 or greater, about 400:1 or greater, about 450:1 or greater, about 500:1 or greater, or greater. For example, etches performed according to some embodiments of the present technology can etch the boron-containing material 425 while substantially or essentially preserving the mask material 420 or other materials.

[0051] Embodiments of the present technology can rapidly and efficiently remove boron-containing material 425. Many conventional techniques, such as wet etching processes, can require significant operating times to completely remove the boron-containing material. The precursors and / or operating conditions of the present embodiments can provide enhanced removal rates. In embodiments, the boron-containing material 425 can be removed from the substrate 405 at rates of about 5,000 Å / min or greater, about 5,500 Å / min or greater, about 6,000 Å / min or greater, about 6,500 Å / min or greater, about 7,000 Å / min or greater, about 7,500 Å / min or greater, about 8,000 Å / min or greater, about 8,500 Å / min or greater, about 9,000 Å / min or greater, or even faster.

[0052] Thus, in some embodiments, the etching operation can be performed in a single cycle, although multiple cycles of etching can also be performed. Further, the process can completely remove the boron-containing material 425 in about 10 minutes or less, about 9 minutes or less, about 8 minutes or less, about 7 minutes or less, about 6 minutes or less, about 5 minutes or less, about 4 minutes or less, about 3 minutes or less, about 2 minutes or less, about 1 minute or less, or less.

[0053] Process conditions can affect the operations performed in method 300. While each operation of method 300 can be performed at a constant temperature in embodiments, in some embodiments, the temperature can be adjusted during different operations. For example, the temperature of the substrate, pedestal, or chamber during processing can be maintained at about 100° C. or less, about 90° C. or less, about 80° C. or less, about 70° C. or less, about 60° C. or less, or about 50° C. or less, and in some embodiments, the temperature can be maintained at about 40° C. or less, about 30° C. or less, about 20° C. or less, about 10° C. or less, about 0° C. or less, about −10° C. or less, about −20° C. or less, about −30° C. or less, or less. Maintaining the substrate, pedestal, or chamber temperature at a relatively low temperature can minimize damage to the semiconductor structure 400, such as the sidewalls and / or bottom of the opening 440 in the mask material 420, during removal of the boron-containing material 425. However, a lower temperature can decrease the etch rate, which can increase overall throughput. Thus, the temperature of the substrate, pedestal, or chamber during processing can be maintained at a temperature between about -30°C and about 100°C.

[0054] The pressure in the processing chamber can be controlled during method 300. For example, the pressure in the processing chamber can be maintained at about 1 Torr or less. Furthermore, in embodiments, the pressure in the processing chamber can be maintained at about 750 mTorr or less, about 500 mTorr or less, about 250 mTorr or less, about 100 mTorr or less, about 80 mTorr or less, about 60 mTorr or less, about 50 mTorr or less, about 40 mTorr or less, about 30 mTorr or less, about 20 mTorr or less, or less, although the pressure may be within a range between any two of these recited values ​​or any smaller range encompassed within any of the recited ranges. Pressure can affect removal uniformity. For example, increasing pressure results in decreased removal uniformity of the boron-containing material 425. Furthermore, decreasing the pressure, such as below 1 mTorr, can also decrease plasma density. Low plasma density can result in decreased removal rate and decreased throughput time.

[0055] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0056] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. In addition, while a method or process may be described sequentially or stepwise, it should be understood that operations may be performed simultaneously or in an order different from that described.

[0057] Where a range of values ​​is presented, unless the context clearly dictates otherwise, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value within that stated range is also encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded from the range, and each range where either, neither, or both limits are included in the smaller range is also encompassed within the scope, subject to any specifically excluded limits in the stated range. When one or both limits are included in a stated range, ranges excluding either or both of those included limits are also included.

[0058] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the material" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0059] Additionally, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and the appended claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, the processing region containing a substrate, the substrate including a boron-containing material overlying a carbon-containing material; generating a plasma effluent of said fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor; and removing the boron-containing material from the substrate; A semiconductor processing method comprising:

2. The fluorine-containing precursor is nitrogen trifluoride (NF ３ 10. The semiconductor processing method of claim 1, comprising:

3. 10. The semiconductor processing method of claim 1, wherein said boron-containing material is characterized by a boron content of greater than or equal to about 20 atomic percent.

4. The semiconductor processing method of claim 1 , wherein the boron-containing material further comprises nitrogen.

5. 10. The semiconductor processing method of claim 1, wherein said boron-containing material and said carbon-containing material define at least one opening extending through both said boron-containing material and said carbon-containing material.

6. 10. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained at about 100[deg.] C. or less.

7. 10. The semiconductor processing method of claim 1, wherein the pressure within the semiconductor processing chamber is maintained at about 1 Torr or less.

8. 10. The semiconductor processing method of claim 1, wherein plasma power is maintained at about 1,000 W or greater when generating plasma effluents of the fluorine-containing precursor.

9. 10. The semiconductor processing method of claim 1, wherein the boron-containing material is removed from the substrate at a rate of about 5,000 Å / min or greater.

10. 10. The semiconductor processing method of claim 1, wherein the removal selectivity of the boron-containing material to the carbon-containing material is greater than or equal to about 10:

1.

11. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, the processing region containing a substrate, the substrate including a boron-containing material overlying a carbon-containing hard mask material, the boron-containing material and the carbon-containing hard mask material defining at least one opening extending through both the boron-containing material and the carbon-containing hard mask material; generating a plasma effluent of said fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor; and removing the boron-containing material from the substrate; A semiconductor processing method comprising:

12. The fluorine-containing precursor is nitrogen trifluoride (NF ３ 12. The semiconductor processing method of claim 11, comprising:

13. 12. The semiconductor processing method of claim 11, wherein the flow rate of the fluorine-containing precursor is less than or equal to about 1,000 sccm.

14. 12. The semiconductor processing method of claim 11, wherein the boron-containing material is characterized by a thickness of about 250 nm or greater.

15. 12. The semiconductor processing method of claim 11, wherein the fluorine-containing precursor is delivered to the processing region of the semiconductor processing chamber without a carrier gas.

16. etching the carbon-containing hard mask material to form at least one opening extending through the carbon-containing hard mask material before delivering the fluorine-containing precursor; 12. The semiconductor processing method of claim 11, further comprising:

17. 17. The semiconductor processing method of claim 16, wherein removing the boron-containing material from the substrate is performed in the same semiconductor processing chamber as etching the carbon-containing hard mask material.

18. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, the fluorine-containing precursor being nitrogen trifluoride (NF ３ ), wherein a substrate is accommodated in the processing region, and the substrate is provided with a fluorine-containing precursor comprising a boron-containing material overlying a carbon-containing material; generating a plasma effluent of the fluorine-containing precursor, wherein a plasma power is maintained between about 500 W and about 3,000 W when generating the plasma effluent of the fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor; and removing the boron-containing material from the substrate; A semiconductor processing method comprising:

19. 20. The semiconductor processing method of claim 18, wherein the boron-containing material is removed from the substrate in about 10 minutes or less.

20. the carbon-containing material defines at least one opening; and removing the boron-containing material from the substrate preserves sidewalls and a bottom surface of the at least one opening; 20. The semiconductor processing method of claim 18.

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