Memory and its control method, electronic device

Abstract

The present invention provides a memory, a control method thereof, and electronic equipment, wherein in a first chip of the memory, each local bit line is coupled to a common bit line on one side via a respective bit line selector, and each local bit line is coupled to a common bit line on the other side via a respective precharge switch, the bit line selector is configured to receive a sub-word line drive signal and selectively bring the connected local bit line and the connected common bit line into conduction based on the sub-word line drive signal, and the precharge switch is configured to receive a complementary sub-word line drive signal and selectively bring the connected local bit line and the connected common bit line into conduction based on the complementary sub-word line drive signal.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on December 29, 2023, bearing application number 202311869141.2 and entitled "Memory and its control method, electronic device," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of semiconductors, and in particular to memories and control methods thereof, and electronic devices. [Background technology]

[0003] With the development of semiconductor technology, semiconductor memory is widely applied to electronic devices. DRAM (Dynamic Random Access Memory) is a type of volatile memory that is often used as cache memory due to its fast access speed.

[0004] DRAM mainly consists of two parts: the peripheral circuit (periphery) and the memory array (core). To further improve memory density, three-dimensional DRAM (3D DRAM) places the peripheral circuit (periphery) and the memory array (core) on two separate chips, which are connected by bonding. This makes the three-dimensional structure of the memory array more complex, requiring additional control logic. Summary of the Invention

[0005] The embodiments of the present invention provide a memory, a control method thereof, and an electronic device.

[0006] The technical solution of the present invention is realized as follows:

[0007] In a first aspect, the present invention provides a memory comprising a first chip, the first chip comprising a plurality of memory array tiles, each of the memory array tiles including a plurality of local bit lines and a plurality of common bit lines, the local bit lines extending along a first direction and the common bit lines extending along a second direction, one common bit line on each side of the local bit lines along the first direction, the first direction and the second direction intersecting; each said local bit line is coupled to said common bit line on one side through a respective bit line selector, and each said local bit line is coupled to said common bit line on the other side through a respective precharge switch; the bit line selector is configured to receive a sub-word line drive signal and selectively conduct between a connected local bit line and a connected common bit line based on the sub-word line drive signal; The precharge switch is configured to receive a sub-word line drive complementary signal and selectively conduct a connected local bit line and a connected common bit line based on the sub-word line drive complementary signal, and the sub-word line drive signal and the sub-word line drive complementary signal are both generated by decoding a row address signal in a command address signal received by the memory.

[0008] In some embodiments, each of the memory array tiles includes a plurality of subarray tiles sequentially arranged along a second direction, each of the subarray tiles including a plurality of storage areas sequentially stacked along a third direction, each of the storage areas including two storage layer groups arranged along a first direction, each of the storage layer groups including a plurality of local bit lines, a first common bit line provided on an outer side of each of the storage layer groups away from the other storage layer group in the same storage area, and a second common bit line provided on an inner side of each of the storage layer groups close to the other storage layer group in the same storage area; For each of the memory layer groups, each of the local bit lines is coupled to the second common bit line via a respective one of the bit line selectors, and each of the local bit lines is coupled to the first common bit line via a respective one of the precharge switches.

[0009] In some embodiments, each of the memory array tiles includes a plurality of subarray tiles sequentially arranged along a second direction, each of the subarray tiles including a plurality of storage areas sequentially stacked along a third direction, each of the storage areas including two storage layer groups arranged along a first direction, each of the storage layer groups including a plurality of local bit lines, a first common bit line provided on an outer side of each of the storage layer groups away from the other storage layer group in the same storage area, and a second common bit line provided on an inner side of each of the storage layer groups close to the other storage layer group in the same storage area; For the same sub-array tile, the storage areas are numbered along a third direction; for odd-numbered said storage areas, each said local bit line is coupled to said first common bit line through a respective said bit line selector, and each said local bit line is coupled to said second common bit line through a respective said precharge switch; For even-numbered storage areas, each of the local bit lines is coupled to the second common bit line via a respective one of the bit line selectors, and each of the local bit lines is coupled to the first common bit line via a respective one of the precharge switches.

[0010] In some embodiments, the memory array tile further includes a plurality of local word lines, each of the local word lines passing through the stacked plurality of storage layer groups along a third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction; a plurality of the local word lines that pass through the same memory layer group and are aligned along a first direction form one sub-word line group; one of the local bit lines corresponds to one of the sub-word line groups, and one memory cell is formed at an intersection of the local bit line and each of the corresponding local word lines; All local word lines within the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal, the bit line selector of the local bit line receives the sub-word line drive signal of the corresponding sub-word line group, and the precharge switch of the local bit line receives the sub-word line drive complementary signal of the corresponding sub-word line group.

[0011] In some embodiments, each of the memory array tiles further includes a plurality of common word lines extending along a second direction; In each of the subarray tiles, the local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal.

[0012] In some embodiments, in the memory array tile, the common word lines are numbered sequentially along a first direction, and N consecutively numbered common word lines form one main word line group; The memory comprises a decoding unit and a plurality of sub-word line driving units, where N is a positive integer; the decoding unit is configured to encode the row address signal to generate a main word line drive signal, the sub-word line drive signal, and a complementary sub-word line drive signal for each of the common word lines; the sub-word line drive unit is coupled to one of the common word lines, and is configured to receive a corresponding main word line drive signal, a corresponding sub-word line drive signal, and a corresponding complementary sub-word line drive signal, and turn on or off the common word line coupled thereto based on the received signal; The two memory layer groups in each memory area are treated sequentially along a first direction as the first memory layer group and the second memory layer group, the main word line drive signal is used to select one main word line group from each of the first memory layer group and the second memory layer group, and the sub-word line drive signal and the sub-word line drive complementary signal are used to select one common word line from the main word line group selected in the first memory layer group or to select one common word line from the main word line group selected in the second memory layer group.

[0013] In some embodiments, the sub-word line drive unit comprises a first switch transistor, a second switch transistor, and a third switch transistor; Control terminals of the first switch transistor and the second switch transistor all receive the main word line driving signal, a first terminal of the first switch transistor receives the sub-word line driving signal, a second terminal of the first switch transistor, a first terminal of the second switch transistor, and a first terminal of the third switch transistor are all connected to the common word line, a second terminal of the second switch transistor and a second terminal of the third switch transistor are all connected to a power supply terminal, and a control terminal of the third switch transistor receives the sub-word line driving complementary signal.

[0014] In some embodiments, the memory further comprises a second chip, the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip; the second chip includes a sense amplification region; In the first chip, a step contact structure is provided between two adjacent memory layer groups along a first direction, and the common bit line directly connected to the bit line selector is coupled to the sense amplification region via the step contact structure.

[0015] In a second aspect, an embodiment of the present invention provides a method for controlling a memory, wherein a first chip in the memory comprises a plurality of memory array tiles, each of the memory array tiles including a plurality of local bit lines and a plurality of common bit lines, each of the local bit lines being coupled to a common bit line on one side via a bit line selector, and each of the local bit lines being coupled to a common bit line on the other side via a respective precharge switch; The memory control method includes: receiving a command address signal and decoding a row address signal in the command address signal to generate a plurality of main word line drive signals, a plurality of sub-word line drive signals, and a plurality of complementary sub-word line drive signals; controlling whether the corresponding bit line selector conducts between the connected local bit line and the connected common bit line based on each of the sub-word line drive signals; and controlling, based on each of the complementary sub-word line drive signals, whether or not the corresponding precharge switch conducts between the connected local bit line and the connected common bit line.

[0016] In some embodiments, each of the memory array tiles includes a plurality of sub-array tiles sequentially arranged along a second direction, each of the sub-array tiles includes a plurality of storage areas sequentially stacked along a third direction, each of the storage areas includes two storage layer groups arranged along a first direction, each of the storage layer groups is provided with a plurality of the local bit lines, and each of the storage layer groups is provided with one of the common bit lines on each side along the first direction; the memory array tile further includes a plurality of local word lines, each of which penetrates a plurality of stacked memory layer groups along a third direction, the plurality of local word lines which penetrate the same memory layer group and are aligned along the first direction form one sub-word line group, all the local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal, one local bit line corresponds to one of the sub-word line groups, and one memory cell is formed at an intersection of the local bit line and each corresponding one of the local word lines, Each of the sub-word line groups has a sub-word line drive signal and a complementary sub-word line drive signal, and the method for controlling the memory includes: transmitting sub-word line drive signals of the sub-word line groups to bit line selectors of corresponding local bit lines; The method further includes transmitting complementary sub-word line drive signals of the sub-word line group to precharge switches of the corresponding local bit lines.

[0017] In some embodiments, in each of the subarray tiles, local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal; in the memory array tile, the common word lines are numbered along a first direction, and consecutively numbered N common word lines form one main word line group; The two storage layer groups of each of the storage areas are sequentially treated as a first storage layer group and a second storage layer group along a first direction, and the memory control method includes: selecting one main word line group from each of the first memory layer group and the second memory layer group based on the main word line drive signal; selecting one of the common word lines from the main word line group selected in the first memory layer group or the main word line group selected in the second memory layer group based on the sub-word line drive signal and the complementary sub-word line drive signal; and turning on the selected common word line to perform the operation indicated by the command address signal.

[0018] In a third aspect, an embodiment of the present invention provides an electronic device, the electronic device including the memory of the first aspect.

[0019] Embodiments of the present invention provide a memory, a control method thereof, and electronic equipment, and by using a sub-word line drive signal and a complementary sub-word line drive signal generated by decoding a row address signal to control the operating states of precharge switches and bit line selectors of local bit lines, even if additional precharge switches and bit line selectors are introduced into the three-dimensional memory, there is no need to introduce additional control information or extra decoding logic, thereby improving control efficiency and reducing redundant devices. [Brief explanation of the drawings]

[0020] [Figure 1A] FIG. 2 is a schematic diagram showing the configuration of a memory array tile in a first chip. [Figure 1B] FIG. 2 is a schematic diagram showing the configuration of a memory array tile in a first chip. [Figure 2] FIG. 2 is a schematic diagram showing a cross-sectional configuration of a memory array tile. [Figure 3] FIG. 10 is a schematic diagram showing a cross-sectional configuration of another memory array tile. [Figure 4] 1 is a schematic diagram showing a configuration of a subarray tile according to an embodiment of the present invention; [Figure 5] 1 is a schematic diagram showing a stacked structure of a memory according to an embodiment of the present invention; [Figure 6] FIG. 2 is a schematic diagram illustrating a configuration of a subarray tile according to an embodiment of the present invention. [Figure 7] FIG. 10 is a schematic diagram illustrating another memory array tile configuration according to an embodiment of the present invention. [Figure 8A] 1 is a schematic diagram showing a cross-sectional configuration of a memory array tile according to an embodiment of the present invention; [Figure 8B] 1 is a schematic diagram showing a cross-sectional configuration of a memory array tile according to an embodiment of the present invention; [Figure 9] FIG. 2 is a schematic diagram showing a circuit configuration of a first chip according to an embodiment of the present invention. [Figure 10] FIG. 2 is a schematic diagram showing a configuration of a sub-word line drive unit according to an embodiment of the present invention. [Figure 11] 3 is a flowchart of a control method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings. The described embodiments do not limit the present invention, and all other embodiments that can be obtained by those skilled in the art without any creative efforts are included in the protection scope of the present invention.

[0022] In the following, references to "some embodiments" describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without contradiction.

[0023] The term "first / second" in this application is explained as follows: In the following description, the terms "first / second / third" do not limit a particular order but distinguish between similar objects. It is understood that "first / second / third" can be used to interchange a particular order or order when appropriate, so that the embodiments of the invention described herein can be performed in orders other than those shown or described herein.

[0024] Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the present invention. The terms used herein are used only to describe the embodiments of the present invention and are not intended to limit the present invention.

[0025] Explanation of terms: WL (WordLine): Word line, BL(BitLine): Bit line, CMOS (Complementary Metal Oxide Semiconductor): Complementary metal oxide semiconductor TSV (Through-Silicon-Via): Silicon through hole, Mat(Memory Array Tile):Memory array tile.

[0026] Before describing the embodiments of the present invention, three directions are defined to describe the three-dimensional structure relative to a plane in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0027] The semiconductor chip may include a top surface located on the front side and a bottom surface located on the back side opposite the front side, and assuming that the flatness of the top surface and the bottom surface is not taken into consideration, the direction in which the top surface and the bottom surface of the semiconductor chip intersect (e.g., perpendicularly) is defined as a third direction, the extension direction of the local bit lines within the semiconductor chip is defined as a first direction, and the extension direction of the local word lines within the semiconductor chip is defined as a second direction, and the first direction and the second direction intersect.

[0028] The 3D DRAM includes a first chip and a second chip stacked along a third direction, with a memory array (Core) distributed in the first chip and a peripheral control region (Periphery), sense amplification region, etc. distributed in the second chip. In the first chip, the memory array (Core) includes a large number of memory cells, which are divided into multiple memory array tiles (Mat), which allows for better control and management.

[0029] 1A is a schematic diagram showing the configuration of a memory array tile 11 in a first chip. As shown in FIG. 1A, each memory array tile 11 includes a plurality of subarray tiles (Sub Mat 0, Sub Mat 1, Sub Mat 2, ...) arranged sequentially along a second direction. Each subarray tile includes a plurality of memory areas stacked sequentially along a third direction. Each memory area includes two memory layer groups, a first memory layer group and a second memory layer group, arranged along the first direction. A staircase contact structure 14 is provided between the first memory layer group and the second memory layer group. FIG. 1B shows the locations of a local bit line (Local BL), a common bit line (Common BL), a local word line (Local WL), and a common word line (Common WL). As shown in FIG. 1B, the local word lines penetrate the multiple memory layer groups along the third direction, and in each subarray tile, the local word lines are numbered along the second direction, and local word lines with the same number in different subarray tiles are coupled to the same common word line, which extends along the second direction, and each memory layer group includes multiple local bit lines extending along the first direction, and one common bit line is provided on each of the left and right sides of each memory layer group.

[0030] 2 and 3, which are schematic cross-sectional views of a memory array tile along the third direction, illustrate a memory array tile including 20 subarray tiles (Sub Mat 0, Sub Mat 1...Sub Mat 19). As shown in FIG. 2, a first common bit line is provided on the outside of each memory layer group (meaning the side away from other memory layer groups in the same memory region), and a second common bit line is provided on the inside of each memory layer group (meaning the side closer to other memory layer groups in the same memory region). As shown in FIG. 3, all local bit lines within a memory layer group are connected to the first common bit line via a precharge switch Eq, and all local bit lines within the memory layer group are connected to a second common bit line via a bit line selector Se. A stepped contact structure is provided between the first memory layer group and the second memory layer group, and each second common bit line is coupled to a sense amplifier in the sense amplification region via the stepped contact structure.

[0031] For example, when reading data, a common word line is opened to turn on multiple groups of target memory cells, each group of which is aligned along the third direction, and the bit line selectors Se of the local bit lines connected to the target memory cells of each group are turned on. At this time, each target memory cell is connected to a corresponding second common bit line, and the second common bit lines of a group aligned along the third direction share charge with the respective target memory cells and are sense-amplified. After the sense-amplified state, the second common bit lines are set to a high or low potential (depending on the data stored in the target memory cells). The bit line selectors Se of unselected local bit lines are turned off, and the precharge switches Eq are turned on, charging all first common bit lines to the precharge potential, thereby setting all unselected local bit lines to the precharge potential. Here, the precharge potential may be an intermediate potential, which may be half the memory array power supply voltage (Vblh), i.e., the intermediate potential = 1 / 2 Vblh.

[0032] Simply put, in a three-dimensional memory 3D DRAM, local bit lines of the same memory layer group share one first common bit line and the same second common bit line, and the bit line selector Se selects whether to access the second common bit line, and the precharge switch Eq selects whether to access the first common bit line, so it is necessary to additionally design control logic for the bit line selector Se / precharge switch Eq.

[0033] Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings.

[0034] In one embodiment of the present invention, a memory is provided, the memory comprising a first chip, the first chip comprising a plurality of memory array tiles 11, and referring to Figure 4, Figure 4 is a schematic diagram of a local structure of a memory array tile 11 according to an embodiment of the present invention, specifically a diagram showing the remaining part of one sub-array tile (e.g., Sub Mat0, Sub Mat1 ...) omitting the stepped contact structure. As shown in Figure 4, each memory array tile includes a plurality of local bit lines and a plurality of common bit lines (e.g., the first common bit line 12 and the second common bit line 13 in Figure 4), the local bit lines extend along a first direction, the common bit lines extend along a second direction, and there is one common bit line on each side of the local bit lines along the first direction, and the first direction and the second direction intersect; Each local bit line is coupled to a common bit line on one side via a respective bit line selector Se, and each local bit line is coupled to a common bit line on the other side via a respective precharge switch Eq; The bit line selector Se receives the sub-word line drive signal Phdec (i is a positive integer) and receives the sub-word line drive signal Phdec and selectively conducting the connected local bit line and the connected common bit line based on the The precharge switch Eq receives the sub-word line driving complementary signal PhdecN. (i is a positive integer) and receives the sub-word line driving complementary signal PhdecN. The bit line driver is configured to selectively conduct between the connected local bit line and the connected common bit line based on the signal.

[0035] Here, the sub-word line driving signal Phdec and sub-word line drive complementary signal PhdecN are generated by decoding the row address signal in the command address signal received by the memory. is the sub-word line driving signal Phdec In some embodiments, the complementary sub-word line driving signal PhdecN is obtained by performing an inversion process on the complementary sub-word line driving signal PhdecN. is the sub-word line driving signal Phdec The sub-word line driving signal Phdec is obtained by performing an inversion process and a delay process on the and sub-word line drive complementary signal PhdecN are not exactly mutually inverted states.

[0036] It should be understood that the row address signal is used to indicate word line information to be selected (i.e., turned on) in the current operation, that is, in the embodiment of the present invention, the word line information is multiplexed to control the operating states of the precharge switches Eq and bit line selectors Se of the local bit lines, and the specific principle thereof can be referred to later in the description. As a result, even if additional precharge switches Eq and bit line selectors Se are introduced in the three-dimensional memory, there is no need to introduce additional control information or extra decoding logic, thereby improving control efficiency and reducing redundant devices.

[0037] It should be noted that although FIG. 4 shows an example in which each storage layer group includes four local bit lines, this does not constitute a relevant limitation.

[0038] 1A and 1B, each memory array tile includes a plurality of subarray tiles (Sub Mat0, Sub Mat1, Sub Mat2, ...) arranged sequentially along the second direction, and each subarray tile includes a plurality of storage areas stacked sequentially along the third direction. Although both Fig. 1A and Fig. 1B show an example in which each subarray tile includes five storage areas, the number of storage areas may be greater. Each storage area includes a first storage layer group and a second storage layer group arranged along the first direction.

[0039] In some embodiments, as shown in FIG. 4, multiple local bit lines are provided in each memory layer group, and in each memory layer group, a first common bit line 12 is provided on the outside, away from the other memory layer group in the same memory area, and a second common bit line 13 is provided on the inside, close to the other memory layer group in the same memory area.

[0040] For each storage layer group, each local bit line is coupled to a second common bit line 13 via a respective bit line selector Se, and each local bit line is coupled to a first common bit line 12 via a respective precharge switch Eq.

[0041] In some embodiments, the memory further comprises a second chip, the first chip and the second chip are stacked along a third direction, the first chip is bonded to the second chip, and the second chip includes a sense amplification region; In the first chip, a step contact structure is provided between two adjacent memory layer groups along the first direction, and a common bit line directly connected to the bit line selector Se is coupled to the sense amplification region via the step contact structure.

[0042] The first and second chips are connected by bonding. The bonding connection refers to the electrical connection between the two chips through a hybrid bonding structure (also called a bonding pillar). Hybrid bonding is a process that creates permanent bonds between dissimilar or homogeneous chips. The term "hybrid" refers to the formation of dielectric-dielectric and metal-metal bonds between two surfaces. Specifically, hybrid bonding offers the following advantages: (1) Shorter interconnect distance: Interconnection is achieved simply by connecting the back-channel copper contacts, eliminating the need for lead wires or the need to penetrate the entire CMOS layer with TSVs. (2) Higher interconnect density: The area of ​​the copper contacts is very small. Compared to solder balls or TSVs, which have a diameter of 100 microns, the spacing between copper contacts in the hybrid bonding process is less than 10 microns, which ensures higher interconnect density. (3) Lower cost: Undoubtedly, performing interconnections individually for each chip would take more time. Wafer bonding allows for high-density interconnections over a large area, dramatically improving production capacity. Naturally, this also reduces production costs.

[0043] The sense amplification region includes multiple sense amplifiers (SAs), also called sense amplifiers, which sense and amplify the electrical signal of the common bit line connected to the selected memory cell, ultimately causing the potential of the common bit line to become low or high, thereby achieving the purpose of reading data from or writing data to the selected memory cell.

[0044] Here, in 3D DRAM, since the memory structure is often formed by vertically stacking multiple memory cells (i.e., multiple memory layer groups), in order to enable the sense amplifier to smoothly connect to the common bit line in each memory layer group, it is necessary to form a 3D staircase contact structure, in which different staircases of the staircase contact structure are electrically isolated, and each staircase is connected to one corresponding common bit line (connected to the bit line connector Se), thereby connecting the common bit line to the sense amplifier SA in the sense amplification region, thereby realizing the sense amplification process.

[0045] In this way, the local bit lines in each memory layer group are coupled via the bit line selector Se to a second common bit line 13 provided in the center of the memory area to which it belongs, and a step contact structure is further provided in the center of the memory area, i.e., the second common bit line 13 of each memory layer group can be externally connected to a sense amplifier in the sense amplification area via the step contact structure provided in the center of the memory area.

[0046] In some other embodiments, referring to FIG. 6, for the same subarray tile, the storage areas are numbered along the third direction as storage area 0, storage area 1, storage area 2, storage area 3, storage area 4, etc.

[0047] For odd-numbered storage areas 1 and 3, each local bit line is coupled to a first common bit line 12 via a respective bit line selector Se, and each local bit line is coupled to a second common bit line 13 via a respective precharge switch Eq, and for even-numbered storage areas 0, 2 and 4, each local bit line is coupled to a second common bit line 13 via a respective bit line selector Se, and each local bit line is coupled to a first common bit line 12 via a respective precharge switch Eq.

[0048] That is, the first common bit lines 12 of two adjacent memory layer groups are adjacent in the third direction, and the second common bit lines 13 of two adjacent memory layer groups are adjacent in the third direction, but no first common bit line 12 and no second common bit line 13 are adjacent in the third direction. Also, for odd-numbered memory areas 1 and 3, the local bit lines are connected to the first common bit line 12 via bit line selector Se and connected to the second common bit line 13 via precharge switch Eq, and for even-numbered memory areas 0, 2, and 4, the local bit lines are connected to the second common bit line 13 via bit line selector Se and connected to the first common bit line 12 via precharge switch Eq. Therefore, during the sense amplification process, for the selected memory layer groups, one of the two adjacent first common bit lines 12 is necessarily in the sense amplification state (after the sense amplification state ends, it becomes high or low depending on the specific data value), and the other first common bit line 12 is at the precharge potential; for the two adjacent second common bit lines 13, one of the second common bit lines 13 is necessarily in the sense amplification state (after the sense amplification state ends, it becomes high or low depending on the specific data value), and the other second common bit line is at the precharge potential, where low potential < precharge potential < high potential. However, since two adjacent common bit lines along the third direction do not perform the sense amplification process at the same time, the two adjacent common bit lines along the third direction do not enter the sense amplification state at the same time, and therefore the coupling between the two adjacent common bit lines is obviously weakened, improving the sense amplification margin.

[0049] Of course, no matter how the positions of the precharge switch Eq and the bit line selector Se change, the control signals they receive remain the same, and the complementary sub-word line drive signal PhdecN generated by the row address signal remains unchanged. and the sub-word line driving signal Phdec It is sufficient to control it by using multiple of these.

[0050] Also, referring to Figure 7, a stepped contact structure is located at the center of each memory area and outside each memory area, in this case, for the even-numbered memory areas 0, 2, and 4, the local bit lines are connected to the inner second common bit lines 13 and further coupled to the sense amplifiers via the inner stepped contact structures, and for the odd-numbered memory areas 1 and 3, the local bit lines are connected to the outer first common bit lines 12 and further coupled to the sense amplifiers via the outer stepped contact structures.

[0051] 1B , in some embodiments, the memory array tile further includes a plurality of local word lines, each of which penetrates the stacked memory layer groups along a third direction, and a memory cell is formed at the intersection of a local bit line and a corresponding local word line, where it should be noted that the local bit line and the local word line are not directly connected. Exemplarily, the memory cell has a 1T1C structure and includes a transistor and a capacitor, where the gate of the transistor is connected to the local word line, and the source and drain of the transistor are connected to the local bit line and the capacitor, respectively, and the third direction is perpendicular to the first direction and the second direction.

[0052] 8A, which illustrates control logic for local word lines and local bit lines using a cross section of sub-array tile Sub Mat 0 along the third direction as an example. As shown in FIG. 8A, multiple local word lines that pass through the same memory layer group and are aligned along the first direction form one sub-word line group. All local word lines in the same sub-word line group share the same sub-word line drive signal and the same complementary sub-word line drive signal.

[0053] For example, for the first memory layer group, the local word line WL <0> , W.L. <4> ...WL <1592> , W.L. <1596> form one sub-word line group, and this sub-word line group is <0> and PhdecN <0> Shares the local word line WL <1> , W.L. <5> ...WL <1593> , W.L. <1597> form one sub-word line group, and this sub-word line group is <1> and PhdecN <1> Shares the local word line WL <2> , W.L. <6> ...WL <1594> , W.L. <1598> form one sub-word line group, and this sub-word line group is <2> and PhdecN <2> Shares the local word line WL <3> , W.L. <7> ...WL <1595> , W.L. <1599> form one sub-word line group, and this sub-word line group is <3> and PhdecN <3> Share.

[0054] For the second memory layer group, the local word line WL <1600> , W.L. <1604> ...WL <3192> , W.L. <3196> form one sub-word line group, and this sub-word line group is <4> and PhdecN <4> Shares the local word line WL <1601> , W.L. <1605> ...WL <3193> , W.L. <3197> form one sub-word line group, and this sub-word line group is <5> and PhdecN <5> Shares the local word line WL <1602> , W.L. <1606> ...WL <3194> , W.L. <3198> form one sub-word line group, and this sub-word line group is <6> and PhdecN <6> Shares the local word line WL <1603> , W.L. <1607> ...WL <3195> , W.L. <3199> form one sub-word line group, and this sub-word line group is <7> and PhdecN <7> Share.

[0055] One local bit line corresponds to one sub-word line group, and one memory cell is formed at the intersection of the local bit line and the corresponding local word line. For example, the local bit line BL0 corresponds to the local word line WL <0> , W.L. <4> ...WL <1592> , W.L. <1596> , the local bit line BL0 and the local word line WL <0> There is one memory cell at the intersection of the local bit lines BL0 and WL <4> There is one memory cell at the intersection of the local bit lines BL0 and WL <1596> At the intersection of

[0056] The bit line selector Se of the local bit line receives a sub-word line drive signal of the corresponding sub-word line group, and the precharge switch Eq of the local bit line receives a complementary sub-word line drive signal of the corresponding sub-word line group. For example, the control signal Sel <0> =Phdec <0> The control signal Eq of the precharge switch Eq of the local bit line BL0 <0> =PhdecN <0> is.

[0057] In some embodiments, as shown in FIG. 8B , each memory array tile further includes a plurality of common word lines (Common WL) extending along the second direction, and in each subarray tile, the local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal.

[0058] That is, the local word lines WL in each sub-array tile Sub Mat 0, Sub Mat 1 ... Sub Mat 19 <0> , W.L. <4> ...WL <1596> are the sub-word line driving signals Phdec <0> and sub-word line drive complementary signal PhdecN <0> Share.

[0059] Specifically, the local word lines WL in each of the sub-array tiles Sub Mat 0, Sub Mat 1, ... Sub Mat 19 <0> is common word The local word line WL0 is connected to the common line WL1 in each sub-array tile, Sub Mat0, Sub Mat1...Sub Mat19. <4> is common word Connected to the line Common WL4 is the local word line WL in each sub-array tile Sub Mat 0, Sub Mat 1, ... Sub Mat 19. <1596> is common word Common line connected to WL1596, but common word Lines Common WL0, Common WL4, Common WL1596 are the sub-word line drive signals Phdec <0> and sub-word line drive complementary signal PhdecN <0> Share.

[0060] Also, the bit line selector Se of the first local bit line BL0 in each storage area in each sub-array tile is connected to the sub-word line drive signal Phdec <0> The precharge switch Eq of the local bit line BL0 in each storage area in each sub-array tile receives the sub-word line drive signal PhdecN. <0> Receive.

[0061] In some embodiments, as shown in FIG. 8B, in a memory array tile, the common word lines are numbered sequentially along the first direction, and N consecutively numbered common word lines form one main word line group, and FIG. 8B shows an example where N=4, i.e., WL <0> ~WL <3> is one main word line group, and WL <4> ~WL <7> is one main word line group...

[0062] Referring to FIG. 9, the memory includes a decoding unit 21 and a plurality of sub-word line driving units 22, where N is a positive integer; The decoding unit 21 is configured to encode the row address signal to generate a main word line driving signal GrDec<399:0>, a sub-word line driving signal Phdec<7:0> and a complementary sub-word line driving signal PhdecN<7:0> for each common word line.

[0063] the sub-word line driving unit 22 is coupled to one common word line, and is configured to receive a corresponding main word line driving signal, a corresponding sub-word line driving signal, and a corresponding complementary sub-word line driving signal, and turn on or off the coupled common word line according to the received signals; Here, the main word line drive signal is used to select one main word line group from each of the first memory layer group and the second memory layer group, and the sub-word line drive signal and the sub-word line drive complementary signal are used to select one common word line from the main word line group selected in the first memory layer group or to select one common word line from the main word line group selected in the second memory layer group.

[0064] For example, the main word line driving signal GrDec <0> =0, GrDec <1> ~GrDec <399> =1 (indicates that the main word line is selected when the main word line driving signal is at a low level, and indicates that the main word line is not selected when the main word line driving signal is at a high level), and the sub-word line driving signal Phdec <0> =1, Phdec <1> ~Phdec <7> =0, sub-word line drive complementary signal PhdecN <0> =0, PhdecN <1> ~PhdecN <7> If =1, then common word Common WL <0> is selected, that is, the WL in each subarray tile Sub Mat0, Sub Mat1...Sub Mat19 <0> At the same time, for each storage area of ​​each sub-array tile Sub Mat 0, Sub Mat 1, ... Sub Mat 19 (FIG. 8B is a cross-sectional view, i.e., only one storage area of ​​each sub-array tile Sub Mat 0, Sub Mat 1, ... Sub Mat 19 is shown), the bit line selector Se of the local bit line BL0 therein is made conductive (its control signal Sel <0> =Phdec <0> =1), the precharge switch Eq is cut off (its control signal Eq <0> =PhdecN <0> =0), while the bit line selectors Se of the local bit lines BL1 to BL4 are cut off and the precharge switches Eq are turned on. word Common WL <0> is turned on, BL0 is connected to the adjacent common bit line through the bit line selector Se, and the common bit line is coupled to the sense amplifier through the stepped contact structure, so that each WL <0> The memory cells formed at the intersections of WL and BL0 share charge with the corresponding common bit lines (through BL0 and bit line selector Se), and the potential of the common bit lines is amplified under the action of the sense amplifier. <1> ~WL <4> is not turned on, BL1 to BL4 are electrically connected to adjacent common bit lines via precharge switches Eq, and the common bit lines are controlled to a precharge potential, which may be an intermediate potential 1 / 2 Vblh, where Vblh is the power supply potential of the memory array (or sense amplifier).

[0065] In some embodiments, referring to FIG. 10, the sub-word line driver unit 22 includes a first switch transistor 301, a second switch transistor 302, and a third switch transistor 303; The control terminals of the first switch transistor 301 and the second switch transistor 302 both receive the main word line driving signal Grdec, the first terminal of the first switch transistor 301 receives the sub-word line driving signal Phdec, the second terminal of the first switch transistor 301, the first terminal of the second switch transistor 302, and the first terminal of the third switch transistor 303 are all connected to the common word line Common WL, the second terminal of the second switch transistor 302 and the second terminal of the third switch transistor 303 are all connected to a power supply terminal, and the control terminal of the third switch transistor 303 receives the sub-word line driving complementary signal PhdecN.

[0066] The power supply terminal may be a ground terminal, the first switch transistor 301 is P-type doped, and the second switch transistor 302 and the third switch transistor 303 are both N-type doped.

[0067] Thus, in one case, Grdec=0 means that the main word line group to which the corresponding common word line belongs is selected, and the first switch transistor 301 is conductive. Phdec=1 means that the corresponding common word line is selected, and at this time, the common word line Common WL is high (i.e., selected / on), turning on the transistors in the connected memory cells. In another case, Grdec=0 and Phdec=0 means that the main word line group to which the corresponding common word line belongs is selected, but the corresponding common word line itself is not selected, and the common word line Common WL is low, and the transistors in the connected memory cells are not turned on. In yet another case, Grdec=1 means that the entire main word line group to which the corresponding common word line belongs is not selected, and the first switch transistor 301 is not conductive, the common word line Common WL is low, and the transistors in the connected memory cells are not turned on.

[0068] In addition, the third switch transistor 303 is used to quickly turn off the corresponding common word line after the corresponding common word line is selected and the corresponding operation is completed.

[0069] As described above, an embodiment of the present invention provides a three-dimensional memory, which includes a first chip and a second chip, stacked along a third direction and connected by hybrid bonding. The first chip is mainly used to create a memory array (Core), which is further divided into multiple memory array tiles (Mat) for better control and management. The second chip is mainly used to create a peripheral control region (Periphery), a sense amplification region, etc. In the first chip, each memory array tile includes a plurality of sub-array tiles sequentially arranged along the second direction, each sub-array tile includes a plurality of storage areas sequentially stacked along a third direction, each storage area includes two storage layer groups arranged along the first direction, each storage layer group includes a plurality of local bit lines, each storage layer group is provided with one common bit line on each side along the first direction, each local bit line is coupled to the common bit line on one side via a respective bit line selector, each local bit line is coupled to the common bit line on the other side via a respective precharge switch, the bit line selectors operate based on a sub-word line drive signal, and the precharge switches operate based on a complementary sub-word line drive signal. Thus, in this embodiment of the present invention, word line information is multiplexed to control the operating states of the precharge switches Eq and the bit line selectors Se of the local bit lines, thereby eliminating the need to introduce additional control information or extra decoding logic even when additional precharge switches Eq and bit line selectors Se are introduced, thereby improving control efficiency and reducing redundant devices.

[0070] In another embodiment of the present invention, referring to Figure 11, a flowchart of a memory control method according to an embodiment of the present invention is shown. The memory control method is applied to the above-mentioned memory, and referring to Figure 1A, the memory includes a first chip and a second chip stacked along a first direction, the first chip includes a plurality of memory array tiles, each memory array tile includes a plurality of sub-array tiles arranged sequentially along the second direction, each sub-array tile includes a plurality of storage areas stacked sequentially along a third direction, each storage area includes two storage layer groups arranged along the first direction, each storage layer group includes a plurality of local bit lines, one common bit line is provided on each side of each storage layer group along the first direction, each local bit line is coupled to the common bit line on one side via a respective bit line selector, and each local bit line is coupled to the common bit line on the other side via a respective pre-charge switch.

[0071] As shown in FIG. 11, the memory control method includes the following steps:

[0072] In step S501, a command address signal is received, and a row address signal in the command address signal is decoded to generate a plurality of main word line driving signals, a plurality of sub-word line driving signals, and a plurality of complementary sub-word line driving signals.

[0073] In step S502, based on each sub-word line drive signal, the corresponding bit line selector controls whether to connect the connected local bit line and the connected common bit line to each other.

[0074] In step S503, based on each complementary sub-word line driving signal, the corresponding precharge switch controls whether to connect the connected local bit line and the connected common bit line to each other.

[0075] In some embodiments, referring to FIG. 8B , the memory array tile further includes a plurality of local word lines, each of which penetrates the stacked plurality of storage layer groups along a third direction, and a plurality of local word lines which penetrate the same storage layer group and are aligned along the first direction form a sub-word line group, and all of the local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal, and one local bit line corresponds to one sub-word line group, and one memory cell is formed at an intersection of the local bit line and each corresponding local word line; Each sub-word line group has a sub-word line drive signal and a complementary sub-word line drive signal, and the method for controlling the memory includes: transmitting sub-word line drive signals for the sub-word line groups to bit line selectors for corresponding local bit lines; The method further includes transmitting complementary sub-word line drive signals of the sub-word line group to precharge switches of corresponding local bit lines.

[0076] In some embodiments, in each subarray tile, the local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal; in the memory array tile, the common word lines are numbered sequentially along the first direction, and N consecutively numbered common word lines form one main word line group; The two storage layer groups of each of the storage areas are sequentially treated as a first storage layer group and a second storage layer group along a first direction, and the memory control method includes: selecting one main word line group from each of the first memory layer group and the second memory layer group based on a main word line drive signal; selecting one common word line from the main word line group selected in the first memory layer group or the main word line group selected in the second memory layer group based on the sub-word line drive signal and the complementary sub-word line drive signal; and turning on the selected common word line to perform the operation indicated by the command address signal.

[0077] In this manner, in an embodiment of the present invention, word line information is multiplexed to control the operating states of the precharge switches Eq and bit line selectors Se of the local bit lines, thereby improving control efficiency and reducing redundant devices because even if additional precharge switches Eq and bit line selectors Se are introduced, there is no need to introduce additional control information or extra decoding logic.

[0078] In yet another embodiment of the present invention, there is further provided an electronic device, the electronic device comprising a memory as shown in FIG. 4, the memory comprising a first chip and a second chip stacked along a third direction, the first chip and the second chip being bonded together.

[0079] Referring to FIG. 1A, in a first chip, each memory array tile includes a plurality of subarray tiles sequentially arranged along a second direction, each subarray tile including a plurality of storage regions sequentially stacked along a third direction, each storage region including two storage layer groups arranged along a first direction, each storage layer group including a plurality of local bit lines, each storage layer group including a common bit line on each side along the first direction, each local bit line coupled to one common bit line via a respective bit line selector, and each local bit line coupled to the other common bit line via a respective precharge switch. Referring to FIG. 4, the bit line selectors operate based on sub-word line drive signals, and the precharge switches operate based on complementary sub-word line drive signals. In this manner, in this embodiment of the present invention, word line information is multiplexed to control the operating states of the precharge switches Eq and bit line selectors Se of the local bit lines. Therefore, even if additional precharge switches Eq and bit line selectors Se are introduced, additional control information and extra decoding logic are not required, improving control efficiency and reducing redundant devices.

[0080] It should be noted that, as used herein, the terms "comprises," "includes," or any other variation thereof, are intended to cover a non-exclusive inclusion, whereby a process, method, article, or apparatus comprising a set of elements includes not only those elements but also other elements not expressly listed or inherent in such process, method, article, or apparatus. Unless otherwise limited, an element defined as "comprising" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises that element.

[0081] The sequence numbers of the above embodiments of the present invention are for illustrative purposes only and do not represent the relative merits of the embodiments. Methods disclosed in some method embodiments provided by the present invention can be combined in any manner without contradiction to obtain new method embodiments. Features disclosed in some product embodiments provided by the present invention can be combined in any manner without contradiction to obtain new product embodiments. Features disclosed in some method or apparatus embodiments provided by the present invention can be combined in any manner without contradiction to obtain new method or apparatus embodiments.

[0082] The above content is merely an embodiment of the present invention, and the protection scope of the present invention is not limited thereto. Any modifications or replacements that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A memory comprising a first chip, the first chip including a plurality of memory array tiles, each of the memory array tiles including a plurality of local bit lines and a plurality of common bit lines, the local bit lines extending along a first direction, the common bit lines extending along a second direction, one common bit line on each side of the local bit lines along the first direction, the first direction and the second direction intersecting, Each of the local bit lines is coupled to one of the common bit lines via a respective bit line selector (Se), and each of the local bit lines is coupled to the other of the common bit lines via a respective precharge switch (Eq); the bit line selector (Se) is configured to receive a sub-word line drive signal, and selectively make the connected local bit line and the connected common bit line conductive based on the sub-word line drive signal; the precharge switch (Eq) is configured to receive a sub-word line drive complementary signal and selectively conduct a connected local bit line and a connected common bit line based on the sub-word line drive complementary signal, and the sub-word line drive signal and the sub-word line drive complementary signal are both generated by decoding a row address signal in a command address signal received by the memory.

2. each of the memory array tiles includes a plurality of subarray tiles sequentially arranged along a second direction, each of the subarray tiles includes a plurality of storage areas sequentially stacked along a third direction, each of the storage areas includes two storage layer groups arranged along a first direction, each of the storage layer groups is provided with a plurality of the local bit lines, a first common bit line is provided on an outer side of each of the storage layer groups away from the other storage layer group in the same storage area, and a second common bit line is provided on an inner side of each of the storage layer groups close to the other storage layer group in the same storage area; for each of the storage layer groups, each of the local bit lines is coupled to the second common bit line via a respective one of the bit line selectors, and each of the local bit lines is coupled to the first common bit line via a respective one of the precharge switches; The memory of claim 1 .

3. each of the memory array tiles includes a plurality of subarray tiles sequentially arranged along a second direction, each of the subarray tiles includes a plurality of storage areas sequentially stacked along a third direction, each of the storage areas includes two storage layer groups arranged along a first direction, each of the storage layer groups is provided with a plurality of the local bit lines, a first common bit line is provided on an outer side of each of the storage layer groups away from the other storage layer group in the same storage area, and a second common bit line is provided on an inner side of each of the storage layer groups close to the other storage layer group in the same storage area; For the same sub-array tile, the storage areas are numbered along a third direction; for odd-numbered said storage areas, each said local bit line is coupled to said first common bit line through a respective said bit line selector, and each said local bit line is coupled to said second common bit line through a respective said precharge switch; for even-numbered storage areas, each of the local bit lines is coupled to the second common bit line through a respective one of the bit line selectors, and each of the local bit lines is coupled to the first common bit line through a respective one of the precharge switches; The memory of claim 1 .

4. the memory array tile further includes a plurality of local word lines, each of the local word lines passing through the stacked plurality of memory layer groups along a third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction; a plurality of the local word lines that pass through the same memory layer group and are aligned along a first direction form one sub-word line group; one local bit line corresponds to one of the sub-word line groups, and one memory cell is formed at an intersection of the local bit line and each corresponding one of the local word lines; all local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal, a bit line selector of the local bit line receives the sub-word line drive signal of the corresponding sub-word line group, and a precharge switch of the local bit line receives the sub-word line drive complementary signal of the corresponding sub-word line group; 4. The memory according to claim 2 or 3.

5. Each of the memory array tiles further includes a plurality of common word lines extending along a second direction; In each of the sub-array tiles, local word lines are numbered sequentially and independently, and local word lines with the same number in different sub-array tiles are electrically connected to the same common word line and share the same sub-word line drive signal and the same complementary sub-word line drive signal. The memory of claim 4.

6. In the memory array tile, the common word lines are numbered sequentially along a first direction, and N consecutively numbered common word lines form one main word line group; The memory comprises a decoding unit (21) and a plurality of sub-word line driving units (22), where N is a positive integer; the decoding unit (21) is configured to encode the row address signal to generate a main word line drive signal, a sub-word line drive signal, and a complementary sub-word line drive signal for each of the common word lines; the sub-word line drive unit (22) is coupled to one of the common word lines, and is configured to receive a corresponding main word line drive signal, a corresponding sub-word line drive signal, and a corresponding complementary sub-word line drive signal, and turn on or off the coupled common word line based on the received signals; two memory layer groups in each of the memory areas are treated as a first memory layer group and a second memory layer group sequentially along a first direction, the main word line drive signal is used to select one main word line group from each of the first memory layer group and the second memory layer group, and the sub-word line drive signal and the complementary sub-word line drive signal are used to select one common word line from the main word line group selected in the first memory layer group or to select one common word line from the main word line group selected in the second memory layer group; The memory of claim 5 .

7. The sub-word line drive unit (22) comprises a first switch transistor (301), a second switch transistor (302), and a third switch transistor (303); control terminals of the first switch transistor and the second switch transistor all receive the main word line driving signal, a first terminal of the first switch transistor receives the sub-word line driving signal, a second terminal of the first switch transistor, a first terminal of the second switch transistor, and a first terminal of the third switch transistor are all connected to the common word line, a second terminal of the second switch transistor and a second terminal of the third switch transistor are all connected to a power supply terminal, and a control terminal of the third switch transistor receives the sub-word line driving complementary signal; The memory of claim 6.

8. the memory further includes a second chip, the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip; the second chip includes a sense amplification region; In the first chip, a step contact structure is provided between two adjacent memory layer groups along a first direction, and the common bit line directly connected to the bit line selector is coupled to the sense amplification region via the step contact structure. The memory of claim 7.

9. A method for controlling a memory, comprising: a first chip in the memory comprising a plurality of memory array tiles, each of the memory array tiles including a plurality of local bit lines and a plurality of common bit lines, each of the local bit lines being coupled to a common bit line on one side via a bit line selector, and each of the local bit lines being coupled to a common bit line on the other side via a respective precharge switch; The memory control method includes: receiving a command address signal and decoding a row address signal in the command address signal to generate a plurality of main word line drive signals, a plurality of sub-word line drive signals, and a plurality of complementary sub-word line drive signals; controlling whether the corresponding bit line selector conducts between the connected local bit line and the connected common bit line based on each of the sub-word line drive signals; and controlling, based on each of the sub-word line drive complementary signals, whether or not the corresponding precharge switch conducts between the connected local bit line and the connected common bit line.

10. each of the memory array tiles includes a plurality of sub-array tiles sequentially arranged along a second direction, each of the sub-array tiles includes a plurality of storage areas sequentially stacked along a third direction, each of the storage areas includes two storage layer groups arranged along a first direction, each of the storage layer groups is provided with a plurality of the local bit lines, and each of the storage layer groups is provided with one of the common bit lines on each side along the first direction; the memory array tile further includes a plurality of local word lines, each of which penetrates a plurality of stacked memory layer groups along a third direction, the plurality of local word lines which penetrate the same memory layer group and are aligned along the first direction form one sub-word line group, all the local word lines in the same sub-word line group share the same sub-word line drive signal and the same sub-word line drive complementary signal, one local bit line corresponds to one of the sub-word line groups, and one memory cell is formed at an intersection of the local bit line and each corresponding one of the local word lines, Each of the sub-word line groups has a sub-word line drive signal and a complementary sub-word line drive signal, and the method for controlling the memory includes: transmitting sub-word line drive signals of the sub-word line groups to bit line selectors of corresponding local bit lines; transmitting complementary sub-word line drive signals of the sub-word line group to precharge switches of the corresponding local bit lines; The memory control method according to claim 9.

11. In each of the subarray tiles, local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same sub-word line drive signal and the same sub-word line drive complementary signal; in the memory array tile, the common word lines are numbered along a first direction, and N consecutively numbered common word lines form one main word line group; The two storage layer groups of each of the storage areas are sequentially treated as a first storage layer group and a second storage layer group along a first direction, and the memory control method includes: selecting one main word line group from each of the first memory layer group and the second memory layer group based on the main word line drive signal; selecting one of the common word lines from the main word line group selected in the first memory layer group or the main word line group selected in the second memory layer group based on the sub-word line drive signal and the complementary sub-word line drive signal; turning on the selected common word line to perform an operation indicated by the command address signal. The memory control method according to claim 10.

12. An electronic device comprising the memory according to any one of claims 1 to 8.

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