CAPACITOR ARRAYS, MEMORY CELL ARRAYS, AND METHODS USED IN FORMING CAPACITOR ARRAYS - Patent application

Abstract

Provided are capacitor arrays, memory cell arrays, and methods for use in forming capacitor arrays, the disclosed methods include forming horizontally spaced openings through a sacrificial material and an insulating material (comprising at least one of silicon nitride, silicon boron nitride, and silicon carbonitride, and including an insulating horizontal grid), depositing an insulating lining (comprising at least one of silicon oxide and silicon oxynitride) in the openings and directly over the sacrificial material, intermittently exposing the insulating lining to a nitrogen-containing plasma during deposition, forming first capacitor electrodes horizontally over the insulating lining and in each of the openings, removing the sacrificial material, forming a capacitor insulator on the first capacitor electrodes and the insulating horizontal grid, and forming a second capacitor electrode material on the capacitor insulator.

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION The embodiments disclosed herein relate to capacitor arrays, memory cell arrays, and methods used in forming capacitor arrays. [Background technology]

[0002] A memory is a type of integrated circuit used in computer systems to store data. A memory may be fabricated in one or more arrays of individual memory cells. The memory cells may be written to or read from using digit lines (sometimes called bit lines, data lines, or sense lines) and access lines (sometimes called word lines). The digit lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressable by a combination of a digit line and an access line.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time in the absence of power. Non-volatile memory is conventionally defined as memory with a retention time of at least about 10 years. Volatile memory loses its memory and must therefore be refreshed / rewritten to maintain data storage. Volatile memory may have retention times of milliseconds or less. Regardless of the above, memory cells are configured to maintain or store memory in at least two different selectable states. In a binary system, a state is considered a "0" or a "1." In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

[0004] A capacitor is a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, as an electric field, can be stored electrostatically within this insulating material. Depending on the composition of the insulating material, the stored electric field can be volatile or nonvolatile. For example, a capacitor containing only SiO2 is volatile. A type of nonvolatile capacitor is a ferroelectric capacitor, which contains a ferroelectric material as at least a portion of its insulating material. Ferroelectric materials have the property of having two stable polarization states, making them suitable for use as the programmable material in capacitors and / or memory cells. The polarization state of a ferroelectric material can be changed by applying an appropriate programming voltage, and the polarization state is retained (at least for a certain period of time) after the programming voltage is removed. Each polarization state has a different capacitance from the others, and ideally, it can be used to write (i.e., store) and read memory states without reversing the polarization state until a need arises. Unfortunately, in some memories with ferroelectric capacitors, the act of reading the memory state can reverse the polarization state. Therefore, immediately after determining the polarization state, the memory cell is rewritten to return it to its pre-read state. Nevertheless, memory cells with ferroelectric capacitors are ideally nonvolatile due to the bistable properties of the ferroelectric material that forms part of the capacitor. However, other programmable materials can also be used as the capacitor insulator to make the capacitor nonvolatile.

[0005] A field-effect transistor is another type of electronic component that can be used in memory cells. This type of transistor includes a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Application of an appropriate voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, little or no current can flow through the channel region. Field-effect transistors may also include additional structures, such as a reversibly programmable charge storage region, as part of the gate structure between the gate insulator and the conductive gate. Regardless, the gate insulator may be programmable, e.g., ferroelectric. Summary of the Invention [Means for solving the problem]

[0006] Embodiments of the present invention include methods used in forming capacitor arrays, such as may be used in memories or other integrated circuits. Embodiments of the present invention also include methods used to form memory cell arrays, such as capacitors over transistors. Embodiments of the present invention also include capacitor arrays and memory cell arrays independent of fabrication methods. Exemplary method embodiments for forming memory cell arrays are described with reference to FIGS. 1 through 15. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of a DRAM memory array and peripheral circuitry according to the prior art and one embodiment of the present invention; [Figure 2] FIG. 2 is an enlarged view of a portion of FIG. [Figure 3] 1 is a perspective view of a portion of a substrate during processing, according to one embodiment of the present invention. [Figure 4]1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 5] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 6] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 7] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 8] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 9] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 10]1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 11] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 12] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 13] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 14] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. [Figure 15] 1 and 3 , or portions thereof, or partial hybrid or partial schematics thereof, and / or alternative embodiments of the process, according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] 1 and 2 show exemplary DRAM circuit schematics according to the prior art and embodiments of the present invention. FIG. 2 illustrates an exemplary memory cell MC, each comprising a transistor T and a capacitor C, where the transistor T includes a pair of source / drain regions, and the capacitor C includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator therebetween. One electrode of the capacitor C is directly electrically coupled to an appropriate potential (e.g., ground), and the other capacitor electrode is in contact with or includes one of the source / drain regions of the transistor T. The other source / drain region of the transistor T is electrically (e.g., directly) coupled to a digit line 130 or 131 (individually labeled DL). The gate of the transistor T is directly electrically coupled to a word line WL (e.g., includes a portion of the word line WL). 1 shows digit lines 130 and 131 extending from one of opposing sides 100 and 200 of memory array region 10 to a peripheral circuit region 113 located to the side of memory array region 10. Digit lines 130 and 131 are individually directly electrically coupled to sensing amplifiers SA on opposing sides 100 and 200 of array region 10 (memory array region 10) within peripheral circuit region 113. Thus, in one embodiment, transistors T are arranged in rows 85 and columns 90, with gate lines (e.g., WL) interconnecting multiple transistors T along each of the rows. Digit lines DL interconnect multiple transistors T along each of the columns.

[0009] 3-5 illustrate a portion of a structure 8, including an array or array region 10 (memory array region 10) in which a capacitor array is fabricated. The structure 8 includes a base substrate 11 having any one or more of conductive / conductor / conductive, semiconductive / semiconductive, or insulating / insulating / insulating (i.e., electrically) materials. The materials may be located to the side, within the height, or outside the height of the materials illustrated in FIGS. 3-5. For example, other partially or fully fabricated components of an integrated circuit may be located above, around, or within the base substrate (not shown). Control and / or other peripheral circuitry for operating the components in the memory array may also be fabricated and may or may not be located completely or partially within the array or sub-array. Multiple sub-arrays may also be fabricated and may operate independently, in conjunction, or in other manners relative to one another. As used herein, a "sub-array" may also be considered an array.

[0010] Transistor T (e.g., an access device) is shown schematically in FIG. 3 and may be formed as part of base substrate 11. By way of example only, transistor T may include a field-effect transistor for controlling access to an individual capacitor, such as used in a DRAM circuit in which transistor T and capacitor C (not yet formed) comprise a memory cell (e.g., a one-transistor-one-capacitor [1T / 1C] memory cell). However, other memory and non-memory circuits, both existing and later developed, are encompassed by the present invention. The exemplary base substrate 11 is shown as including insulating material 16 (e.g., doped and / or undoped silicon dioxide) having conductive vias 17 extending therethrough to transistor T. One of the source / drain regions of each pair of source / drain regions of each transistor T is electrically coupled (e.g., directly) to a respective digit line DL. The other of the source / drain region of each pair of source / drain regions of each transistor T is electrically coupled (e.g., directly, e.g., via a respective conductive via 17) to one of the capacitor electrodes (e.g., a first capacitor electrode herein).

[0011] A stack 18 is formed directly above the base substrate 11 and includes a sacrificial material 20 and an insulating material 22 (e.g., at least initially as a continuous layer). The insulating material 22 is between a top 24 and a bottom 26 of the sacrificial material 20. In one embodiment, the insulating material 22 may be at least predominantly (i.e., greater than 50% to 100% by volume) comprised of at least one of silicon nitride, silicon boronitride, and silicon carbonitride (i.e., regardless of stoichiometry / non-stoichiometry). For illustrative purposes only, only one layer of insulating material 22 is shown between the top 24 and bottom 26, although one or more additional layers of insulating material 22 may be provided therebetween (not shown). A layer 25 of insulating material 22 may also be present below the sacrificial material 20, as shown. This layer 25 may be the same or a different thickness as the insulating material 22 above. The sacrificial material 20 and the insulating material 22 are preferably of compositions having different etching properties. Exemplary sacrificial materials 20 include doped and undoped silicon dioxide and doped and undoped polysilicon. A hard mask material 28 (e.g., silicon dioxide) may be formed over the stack 18, as shown.

[0012] Horizontally spaced openings 30 are formed, for example, by anisotropic etching, through sacrificial material 20 and insulating material 22 between top 24 and bottom 26. Openings 30 also are formed through hard mask material 28 (if present) and layer 25, down to conductive vias 17 (if present). The insulating material 22 between top 24 and bottom 26 with openings 30 therethrough comprises insulating horizontal grid 32. More grids may be formed if there are one or more layers of insulating material 22 between top 24 and bottom 26 (not shown). In one embodiment, insulating horizontal grid 32 and its insulating material 22 comprise at least primarily at least two of silicon nitride, silicon boron nitride, and silicon carbonitride. In one embodiment, insulating horizontal grid 32 and its insulating material 22 comprise at least primarily silicon nitride, and in one embodiment, silicon boron nitride, and in one embodiment, silicon carbonitride. In one such latter embodiment, the carbon content in the silicon carbonitride is 0.1 atomic percent to 30.0 atomic percent, and in one embodiment, 5.0 atomic percent to 7.0 atomic percent. The openings 30 may taper inward and / or outward (either desired or as a by-product of manufacturing) as they extend deeper into the stack 18. The exemplary openings 30 are widest at their top and taper inward over only a portion of the height of the openings 30 (e.g., as an undesirable by-product of manufacturing).

[0013] 6-8, an insulating lining 34 is deposited within the horizontally spaced openings 30 and directly over the sacrificial material 20. The insulating lining 34 comprises at least primarily silicon oxide and / or silicon oxynitride (i.e., regardless of stoichiometry / non-stoichiometry; for example, SiO2 is a silicon oxide). In one embodiment, the insulating lining 34 comprises at least primarily silicon oxide, and in another embodiment, at least primarily silicon oxynitride. In one embodiment, the insulating lining 34 is not deposited on the sides of the insulating horizontal grid 32 (as shown), while in another embodiment, the insulating lining 34 is deposited on the sides of the insulating horizontal grid 32 (as shown). Regardless, the insulating lining 34 is intermittently exposed to a nitrogen-containing plasma during its deposition, as indicated by downward arrows 35, for example. Ideally, and in one embodiment, the amount of insulating lining 34 deposited directly on the sacrificial material 20 with the intermittent exposure is less than the amount of insulating lining 34 deposited under the same deposition conditions excluding the intermittent exposure. Exemplary methods for depositing the insulating lining 34 include chemical vapor deposition and atomic layer deposition, with or without a plasma. Exemplary nitrogen-containing plasmas include N2, NH3, NF3, NO x (e.g., in combination with a non-nitrogen-containing inert gas such as Ar). Exemplary intermittent exposure conditions include a substrate temperature of 0° C. to 1,000° C. and a chamber pressure of 1 mTorr to 1 Torr.

[0014] 9-11, first capacitor electrodes 40 are formed, each in each of the horizontally spaced openings 30, laterally (horizontally) overlying the insulating lining 34 within the opening 30. The insulating lining 34 and hard mask material 28 (not shown) that was directly over the sacrificial material 20 may be removed during processing, as shown.

[0015] 12 and 13, in one embodiment, the entire insulating lining 34 (not shown) is removed (e.g., leaving an empty space 71). Such removal may be performed, for example, by an isotropic etch selective to the first capacitor electrode 40. For example, if the insulating lining 34 is made of undoped silicon dioxide and the sacrificial material 20 is made of silicon dioxide doped with boron and / or phosphorus, an exemplary isotropic etch chemistry may include primarily hydrogen fluoride (HF) and HO, by which the insulating lining 34 may be etched faster than the sacrificial material 20. Then, in one embodiment, an upper insulating grid 42 (e.g., including the insulating material 22) is formed on the sacrificial material 20. This upper insulating grid 42 may have a thickness that is the same as or different from that of the insulating horizontal grid 32 and / or layer 25.

[0016] 14 and 15, sacrificial material 20 (not shown) is removed (e.g., by an isotropic etch selective to insulating material 22 and first capacitor electrode 40). If upper insulating grid 42 is present, exemplary openings 44 may be formed through upper insulating grid 42 (see FIG. 12) to allow an etchant to access sacrificial material 20 underlying upper insulating grid 42. These openings may also be formed through insulating horizontal grid 32 (not shown / not visible in the exemplary drawings). Capacitor insulator 46 is then formed on first capacitor electrode 40 and insulating horizontal grid 32 (e.g., directly above and below them, and also over upper insulating grid 42 and layer 25, if present). A second capacitor electrode material 48 is then formed on capacitor insulator 46, thereby forming second capacitor electrodes 50 and individual capacitors C (some labeled). Each capacitor C includes one (at least one) of a first capacitor electrode 40, a capacitor insulator 46, and a second capacitor electrode 50. The illustrated second capacitor electrode 50 is shown as being common to all capacitors C in the array 10 (memory array region 10). Alternatively, the second capacitor electrode material 48 may be separated (e.g., by a masked anisotropic etch) to separate each second capacitor electrode 50 from each first capacitor electrode 40, or to separate each second capacitor electrode 50 from fewer than all of the first capacitor electrodes 40 in the array 10 (memory array region 10). Regardless, in one embodiment, a memory array 10 (memory array region 10) is formed that includes memory cells MC (some of which are labeled), each of which includes a capacitor C and a transistor T. In one embodiment, as shown, all of the insulating lining 34 is removed (eg, by isotropic etching) before forming the capacitor insulator 46 (eg, as shown in FIGS. 12 and 13).

[0017] In one embodiment, the insulating horizontal grid 32 comprises carbon (e.g., carbon-doped insulating material, silicon carbonitride, etc. [i.e., regardless of stoichiometry / stoichiometric or not]). When such insulating horizontal grid 32 comprises carbon, the insulating horizontal grid 32 immediately laterally (horizontally) adjacent to each of the first capacitor electrodes 40 has less carbon than the insulating horizontal grid 32 laterally separated from each of the first capacitor electrodes 40 (i.e., there is no insulating material 22 of the insulating horizontal grid 32 between the first capacitor electrodes 40 that are immediately laterally adjacent). For example, by way of example only, each insulating horizontal grid 32 is shown to include an individual region 60 immediately laterally adjacent to each of the first capacitor electrodes 40 and an individual region 65 laterally separated from the first capacitor electrode 40 (i.e., compared to the individual region 60). Such a structure may result, by way of example only, from exposure of the region 60 to a nitrogen-containing plasma 35 during deposition of the insulating lining 34. Such a structure may also result for the layer 25 (not shown if it includes carbon). The illustrated regions 60 each have an annular structure, the diameter of which increases depending on the number, intensity, and / or duration of exposures. If the regions 60 are formed in layer 25 or another carbon-containing insulating grid 32 (insulating horizontal grid 32) (not shown), the diameter of which increases will likely decrease with increasing stack depth.

[0018] In one embodiment, the insulating horizontal grid 32 immediately laterally adjacent to each first capacitor electrode 40 is carbon-free (as used herein, "free" means 0 atoms / cm 3 From 1×10 12 atoms / cm 3 In one embodiment, the insulating horizontal grid 32 immediately laterally adjacent to each first capacitor electrode 40 is 1×10 12 atoms / cm 3In one embodiment, the insulating horizontal grid 32 immediately laterally adjacent to each first capacitor electrode 40 has a carbon atomic percentage that is 10.0 atomic percent to 90.0 atomic percent (in one such embodiment, 40.0 atomic percent to 70.0 atomic percent) lower than the carbon atomic percentage of the insulating horizontal grid 32 laterally away from each first capacitor electrode 40.

[0019] Any other attributes or aspects shown and / or described herein for other embodiments may also be used for the embodiments shown and / or described with reference to the above embodiments.

[0020] During deposition of the insulating lining 34, intermittent exposure of the insulating lining 34 to a nitrogen-containing plasma may sufficiently inhibit deposition to reduce the risk or extent of blockage (significant narrowing) of the tops of the individual openings 30. This may result in improved margins and improved critical dimensions of the capacitor.

[0021] Configurations of alternative embodiments may result from the method embodiments described above or otherwise. Nevertheless, embodiments of the present invention encompass memory arrays independent of the manufacturing method, although such memory arrays may have any of the attributes described herein in the method embodiments. Similarly, the method embodiments described above may incorporate, form, or have any of the attributes described with respect to the device embodiments.

[0022] In one embodiment, an array (e.g., 10) of capacitors (e.g., C) includes a plurality of capacitors (e.g., C), each of which includes a first capacitor electrode (e.g., 40), a second capacitor electrode (e.g., 50), and a capacitor insulator (e.g., 46) between the first and second capacitor electrodes. An insulating horizontal grid (e.g., 32) is present within the plurality of capacitors between the top (e.g., 67) and bottom (e.g., 68) of each of the capacitors. Capacitor insulators are present immediately above and below the insulating horizontal grid between immediately horizontally adjacent capacitors. The insulating horizontal grid includes carbon. If the insulating horizontal grid includes carbon, the insulating horizontal grid immediately laterally adjacent each of the first capacitor electrodes has less carbon than the insulating horizontal grid laterally separated from each of the first capacitor electrodes. Any other attributes or aspects shown and / or described herein for other embodiments may also be used.

[0023] In one embodiment, an array (e.g., 10) of memory cells (e.g., MC) includes individual capacitors (e.g., C) above the transistors (e.g., T), including rows (e.g., 85) and columns (e.g., 90) of transistors (e.g., T). Gate lines (e.g., WL) interconnect the multiple transistors along each of the rows. Digit lines (e.g., 131 or 132) interconnect the multiple transistors along each of the columns. The transistors each include a pair of source / drain regions (e.g., 70 and 72). One of the source / drain regions (e.g., 70) of the pair is electrically coupled (e.g., directly) to a respective one of the digit lines. The other of the source / drain region (e.g., 72) of the pair is electrically coupled (e.g., directly) to a first capacitor electrode (e.g., 40) of one of the capacitors (e.g., C) above the transistor. The plurality of capacitors each include a first capacitor electrode, a second capacitor electrode (e.g., 50), and a capacitor insulator (e.g., 46) between the first and second capacitor electrodes. An insulating horizontal grid (e.g., 32) is present within the plurality of capacitors between the top (e.g., 67) and bottom (e.g., 68) of each of the capacitors. Capacitor insulators are present immediately above and below the insulating horizontal grid between immediately horizontally adjacent capacitors. The insulating horizontal grid includes carbon. If the insulating horizontal grid includes carbon, the insulating horizontal grid immediately laterally adjacent each of the first capacitor electrodes has less carbon than the insulating horizontal grid laterally separated from each of the first capacitor electrodes. Any other attributes or aspects shown and / or described herein for other embodiments may also be used.

[0024] The above-described processing or structure may be considered relative to an array of components formed as or in a single stack or deck of such components above, or as part of, an underlying base substrate (although a single stack / deck may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the completed structure and, in some embodiments, may be below the array (e.g., CMOS under-array). Notwithstanding this, one or more additional such stacks / decks may be provided or fabricated above and / or below the stacks / decks shown in the figures or described above. Furthermore, the arrays of components may be the same or different relative to one another in different stacks / decks, and the different stacks / decks may be the same thickness or different thicknesses relative to one another. Intervening structures may be provided between immediately vertically adjacent stacks / decks (e.g., additional circuitry and / or dielectric layers). The different stacks / decks may also be electrically coupled to one another. Multiple stacks / decks may be fabricated separately, sequentially (eg, one on top of the other), or two or more stacks / decks may be fabricated essentially simultaneously.

[0025] The assemblies and structures described above can be used in integrated circuits / circuits and incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communications modems, processor modules, and application-specific modules, and can include multi-layer multi-chip modules. The electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0026] Unless otherwise specified, the terms "height," "higher," "top," "bottom," "top," "above," "bottom," "upper," "lower," "below," "straight below," "upward," and "downward" generally refer to the vertical direction. A "horizontal direction" refers to a direction generally along the plane of the main substrate (i.e., within 10 degrees) and may be the direction along which the substrate is processed during manufacturing, while a vertical direction refers to a direction generally perpendicular to this direction. A "strictly horizontal" refers to a direction along the plane of the main substrate (i.e., no angle from the plane of the main substrate) and may be the direction along which the substrate is processed during manufacturing. Furthermore, as used herein, "vertical" and "horizontal" refer to directions generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. Furthermore, "extending in the height direction" and "extending in the height direction" refer to a direction angled at least 45° from strictly horizontal. Also, with respect to field effect transistors, terms such as "height-extending," "height-extending," "horizontally extending," and "horizontally extending" refer to the orientation of the transistor's channel length, which, in operation, conducts current between the source and drain regions. With respect to bipolar junction transistors, terms such as "height-extending," "height-extending," "horizontally extending," and "horizontally extending" refer to the orientation of the base length, which, in operation, conducts current between the emitter and collector. In some embodiments, any height-extending component, feature, and / or region also extends vertically or within 10° of vertical.

[0027] Additionally, "directly above," "directly below," and "directly below" require at least some lateral (i.e., horizontal) overlap of the two described areas / materials / components with respect to one another. Additionally, the use of "above" without the preceding "direct" requires only that the portion of a described area / material / component that is above another area / material / component be vertically outside of the other (i.e., regardless of whether there is lateral overlap of the two described areas / materials / components). Accordingly, the use of "below" and "below" without the preceding "direct" requires only that the portion of a described area / material / component that is below / below another area / material / component be vertically inside of the other (i.e., regardless of whether there is lateral overlap of the two described areas / materials / components).

[0028] Any of the materials, regions, and structures described herein may be homogeneous or non-homogenous, and regardless, may be continuous or discontinuous across any overlying material. Where one or more exemplary compositions are provided for any material, the material may comprise, consist essentially of, or consist of such one or more compositions. Also, unless otherwise specified, each material may be formed using any suitable technique, existing or later developed, of which atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0029] Furthermore, "thickness" alone (without a preceding directional adjective) is defined as the average linear distance through a given material or region perpendicular to the nearest surface of immediately adjacent materials or regions of different composition. Furthermore, the various materials or regions described herein can be of substantially constant or variable thickness. In the case of variable thickness, thickness refers to the average thickness unless otherwise specified, and such materials or regions will have some minimum and some maximum thickness due to the non-constant thickness. As used herein, "different composition" requires only that two described materials or regions that may directly contact each other be chemically and / or physically different, e.g., when such materials or regions are not homogeneous. When two described materials or regions are not directly contacting each other, "different composition" requires only that the nearest portions of the two described materials or regions be chemically and / or physically different, when such materials or regions are not homogeneous. As used herein, a material, region, or structure is "directly in contact" with another material, region, or structure if there is a contact where at least a portion of the described materials, regions, or structures are in physical contact with each other. In contrast, "above," "on," "adjacent," "along," and "in contact," without the prefix "directly," encompass not only "directly in contact," but also structures where the described materials, regions, or structures are not in physical contact with each other as a result of an intervening material, region, or structure.

[0030] As used herein, regions-materials-components are "electrically coupled" to one another if, under normal operation, electrical current can flow continuously from one to the other, primarily through the transfer of subatomic positive and / or negative charges when sufficient charge is generated. There may be another electronic component between the regions-materials-components and they may be electrically coupled. In contrast, when regions-materials-components are said to be "directly electrically coupled," there is no intervening electronic component (e.g., no diode, transistor, resistor, transformer, switch, fuse, etc.) between the directly electrically coupled regions-materials-components.

[0031] The use of "row" and "column" herein is for convenience to distinguish the orientation of one series or feature from the orientation of another series or feature along which a component is or may be formed. "Row" and "column" are used interchangeably for any series of regions, components, and / or features, regardless of function. Regardless, rows and columns may be straight and / or curved and / or parallel and / or non-parallel to one another. Furthermore, rows and columns may intersect one another at 90° or one or more other angles (i.e., other than a linear angle).

[0032] Any conductive / conductor / conductive material composition herein may be a conductive metallic material and / or a conductively doped semiconductive / semiconductive material. A "metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and one or more metal compounds.

[0033] Any use of "selectively" herein with respect to etching, etching, removing, removing, depositing, forming, and / or forming refers to the act of one described material over another described material in a ratio of at least 2:1 in amount. Also, any use of "selectively depositing," "selectively growing," or "selectively forming" refers to the depositing, growing, or forming of one material over another described material or materials in a ratio of at least 2:1 in amount for at least the first 75 Angstroms of deposition, growth, or formation.

[0034] Unless otherwise stated, the use of "or" herein includes either or both.

[0035] [Conclusion] In some embodiments, a method for forming a capacitor array includes forming horizontally spaced openings through a sacrificial material and an insulating material between the top and bottom of the sacrificial material. The insulating material comprises at least primarily at least one of silicon nitride, silicon boron nitride, and silicon carbonitride. The insulating material having horizontally spaced openings therethrough includes an insulating horizontal grid. An insulating lining is deposited within the horizontally spaced openings and directly over the sacrificial material. The insulating lining comprises at least primarily at least one of silicon oxide and silicon oxynitride. During deposition, the insulating lining is intermittently exposed to a nitrogen-containing plasma. First capacitor electrodes are formed laterally within each of the horizontally spaced openings and on the insulating lining within the horizontally spaced openings. The sacrificial material is removed, and a capacitor insulator is formed on the first capacitor electrodes and the insulating horizontal grid. A second capacitor electrode material is formed on the capacitor insulator.

[0036] In some embodiments, the capacitor array includes a plurality of capacitors, each of which includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. An insulating horizontal grid is present within the plurality of capacitors between the top and bottom of each of the capacitors. The capacitor insulator is present immediately above and below the insulating horizontal grid between horizontally adjacent capacitors. The insulating horizontal grid includes carbon. When the insulating horizontal grid includes carbon, the insulating horizontal grid immediately laterally adjacent to each of the first capacitor electrodes has less carbon than the insulating horizontal grid laterally away from each of the first capacitor electrodes.

[0037] In some embodiments, a memory cell array including individual capacitors above the transistors includes rows and columns of transistors. Gate lines interconnect the transistors along each of the rows. Digit lines interconnect the transistors along each of the columns. Each transistor includes a pair of source / drain regions. One of the source / drain regions is electrically coupled to a respective one of the digit lines. The other of the source / drain region is electrically coupled to a first capacitor electrode of one of a plurality of capacitors above the transistor. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. An insulating horizontal grid is present within the plurality of capacitors between the top and bottom of each of the capacitors. The capacitor insulator is present directly above and below the insulating horizontal grid between immediately horizontally adjacent capacitors. The insulating horizontal grid includes carbon. If the insulating horizontal grids include carbon, the insulating horizontal grids immediately laterally (horizontally) adjacent to each of the first capacitor electrodes have less carbon than the insulating horizontal grids laterally distant from each of the first capacitor electrodes.

Claims

1. 1. A method for use in forming a capacitor array, comprising: forming horizontally spaced apart openings through a sacrificial material and an insulating material between a top and a bottom of said sacrificial material, said insulating material comprising at least predominantly at least one of silicon nitride, silicon boron nitride, and silicon carbonitride, said insulating material having horizontally spaced apart openings therethrough comprising an insulating horizontal grid; depositing an insulating lining within said horizontally spaced openings and directly over said sacrificial material, said insulating lining comprising at least predominantly at least one of silicon oxide and silicon oxynitride; intermittently exposing the insulating lining to a nitrogen-containing plasma during said deposition; forming first capacitor electrodes horizontally over the insulating lining in the horizontally spaced openings and individually within each of the horizontally spaced openings; removing the sacrificial material and forming a capacitor insulator on the first capacitor electrode and the insulating horizontal grid; forming a second capacitor electrode material on the capacitor insulator; A method comprising:

2. 10. The method of claim 1, wherein the amount of the insulating lining deposited directly over the sacrificial material by the intermittent exposure is less than the amount of insulating lining deposited under the same deposition conditions excluding the intermittent exposure.

3. The nitrogen-containing plasma contains at least N ２ , N.H. ３ , N.F. ３ , and NO ｘ 2. The method of claim 1, comprising one of:

4. The method of claim 1 , wherein the insulating material and the insulating horizontal grid comprise at least primarily the silicon nitride.

5. The method of claim 1 , wherein the insulating material and the insulating horizontal grid comprise at least primarily the silicon boron nitride.

6. The method of claim 1 , wherein the insulating material and the insulating horizontal grid comprise at least primarily the silicon carbonitride.

7. 7. The method of claim 6, wherein the silicon carbonitride has a carbon content of 0.1 atomic percent to 30.0 atomic percent.

8. 8. The method of claim 7, wherein the silicon carbonitride has a carbon content of 5.0 atomic percent to 7.0 atomic percent.

9. The method of claim 1 , wherein the insulating material and the insulating horizontal grid are at least predominantly comprised of at least two of the silicon nitride, the silicon boron nitride, and the silicon carbonitride.

10. The method of claim 1 , wherein the insulating lining comprises at least primarily the silicon oxide.

11. The method of claim 1 , wherein the insulating lining comprises at least primarily the silicon oxynitride.

12. The method of claim 1 , wherein the insulating lining is not deposited laterally of the insulating horizontal grid.

13. The method of claim 1 , wherein the insulating lining is deposited laterally on the insulating horizontal grid.

14. 10. The method of claim 1, wherein the entire removal of the insulating lining occurs before the formation of the capacitor insulator.

15. 2. The method of claim 1, wherein the insulating horizontal grid comprises carbon, and when the insulating horizontal grid comprises carbon, the insulating horizontal grid immediately horizontally adjacent each one of the first capacitor electrodes has less carbon than the insulating horizontal grid horizontally separated from each one of the first capacitor electrodes.

16. A capacitor array comprising: a plurality of capacitors, each capacitor including a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode; an insulating horizontal grid present among the plurality of capacitors between the top and bottom of each of the capacitors, and capacitor insulators present immediately above and below the insulating horizontal grid between immediately horizontally adjacent capacitors; a capacitor array, wherein the insulating horizontal grid comprises carbon, and when the insulating horizontal grid comprises carbon, the insulating horizontal grid immediately horizontally adjacent each one of the first capacitor electrodes has less carbon than the insulating horizontal grid horizontally separated from each one of the first capacitor electrodes.

17. 17. The capacitor array of claim 16, wherein the insulating horizontal grid immediately horizontally adjacent each of the first capacitor electrodes is carbon-free.

18. The insulating horizontal grid directly adjacent to each of the first capacitor electrodes is 1×10 １２ atoms / cm ３ 17. The capacitor array of claim 16, comprising more carbon than

19. 20. The capacitor array of claim 18, wherein the insulating horizontal grid immediately horizontally adjacent to each of the first capacitor electrodes has an atomic percentage of carbon that is 10.0 atomic percent to 90.0 atomic percent lower than the atomic percentage of carbon in the insulating horizontal grid horizontally away from each of the first capacitor electrodes.

20. An array of memory cells each including a capacitor above a transistor, rows and columns of transistors, gate lines interconnecting a plurality of the transistors along each of the rows, digit lines interconnecting a plurality of the transistors along each of the columns, the transistors each including a pair of source / drain regions, one of the source / drain regions of the pair electrically coupled to a respective one of the digit lines and the other of the source / drain regions electrically coupled to a first capacitor electrode of one of a plurality of capacitors above the transistor; a plurality of capacitors, each capacitor including the first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode; an insulating horizontal grid present among the plurality of capacitors between the top and bottom of each of the capacitors, and capacitor insulators present immediately above and below the insulating horizontal grid between immediately horizontally adjacent capacitors; the insulating horizontal grid comprises carbon, and when the insulating horizontal grid comprises carbon, the insulating horizontal grid immediately horizontally adjacent each one of the first capacitor electrodes has less carbon than the insulating horizontal grid horizontally separated from each one of the first capacitor electrodes.

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