Pumping controller for multiple charge pump units

Abstract

In one example, a system includes a plurality of charge pump units connected in parallel to receive an input voltage and generate an output voltage greater than the input voltage, and a pump controller that provides a pumping signal to a first charge pump unit of the plurality of charge pump units and provides sequentially delayed versions of the pumping signal to other charge pump units of the plurality of charge pump units.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 442,807, filed February 2, 2023, entitled "Charge Pump Comprising Latch-Based Self-Oscillating Voltage Regulator," and U.S. Patent Application No. 18 / 135,395, filed April 17, 2023, entitled "Pumping Controller For A Plurality Of Charge Pump Units."

[0002] FIELD OF THE INVENTION A pumping controller is disclosed that provides pumping signals to a plurality of charge pump units. [Background technology]

[0003] Charge pumps are commonly used in semiconductor devices to generate voltages greater than the available supply voltage, which is commonly denoted as VDD. For example, charge pumps are used in flash memory systems to generate voltages greater than VDD for program, erase, or read operations.

[0004] Prior art designs include designs with multiple charge pump units operating in parallel. One limitation of these prior art designs is that each charge pump unit begins its charging and discharging operation simultaneously according to a common pumping signal, resulting in a power surge at the beginning of each charging cycle that can harm circuitry sensitive to current or voltage surges. Another drawback of prior art designs is that when the charge pump reaches a desired voltage level, the charging operation may continue for a period of time before stopping, resulting in an output that is higher than desired.

[0005] What is needed is an improved charge pump design and control system. Summary of the Invention

[0006] A pumping controller for multiple charge pumps is disclosed.

[0007]

[0008] [Brief explanation of the drawings]

[0009] [Figure 1] 1 shows a voltage regulator comprising a pumping controller and a plurality of charge pump units. [Figure 2] 2 shows a timing diagram for the voltage regulator of FIG. 1. [Figure 3] 2 illustrates how the voltage regulator of FIG. 1 operates. [Figure 4] 2 illustrates how the voltage regulator of FIG. 1 operates. DETAILED DESCRIPTION OF THE INVENTION

[0010] 1 shows a system including a voltage regulator 100. The voltage regulator 100 includes charge pump units 102-1, 102-2, 102-3, and 102-4. The charge pump units 102-1, 102-2, 102-3, and 102-4 are connected in parallel, each receiving an input voltage VDD and generating an output voltage VD25 that is greater than the input voltage. In this example, four charge pump units are connected in parallel to provide an output voltage VD25 that is capable of powering an attached load without droop.

[0011] The voltage regulator 100 further comprises a pumping controller 101. The pumping controller 101 comprises a voltage divider comprising a first resistor 103 and a second resistor 104, which generates a divided voltage VD25 at a node 113 that is proportional to the output voltage VD25. SGenerate it. The comparator 106 receives the divided voltage V at the first non-inverting input S and the reference voltage VREF at the second inverting input, and compares them. When V S > VREF, the output VDET of the comparator 106 is high, and when V S < VREF, the output of the comparator 106 is low. The capacitor 105 transfers the ripple from VD25 to V S to speed up the comparator 106.

[0012] The latch 107 is a gated D latch with a reset signal and operates according to the following truth table.

Table 1

[0013] The signal RESET is provided to the reset port R of the latch 107 by other logic or controller not shown. The latch enable port LAT of the latch 107 receives the signal VDET from the comparator 106. The data port D of the latch 107 receives a signal from the inverter 112, as will be described in detail below. As shown in the above truth table, when the RESET signal on the reset port R is asserted, the output Q is 0 regardless of the values received by the data port D and the latch enable port LAT. When the RESET signal on the reset port R is not asserted and the signal received by the latch enable port LAT is asserted (this occurs when V S > VREF, indicating that VD25 has reached or exceeded the desired voltage), the output Q holds that level regardless of the value subsequently received by the data port D. When the RESET signal on the R port is not asserted and the signal received by the latch enable port LAT is not asserted (this occurs when V S < VREF, meaning that VD25 is less than the desired voltage and additional pumping is desirable), the output Q becomes what is received by the data port D at that time.

[0014] Output Q is signal PMP CLK, which is provided as a pumping signal to charge pump unit 102-1 and to the input of delay circuit 108. Delay circuit 108 passes its received signal PMP CLK but with an added delay to produce signal PMP CLK' at the output of delay circuit 108.

[0015] PMP CLK' is provided as a pumping signal to charge pump unit 102-2 and to the input of delay circuit 109. Delay circuit 109 passes its received signal PMP CLK' but with an added delay to produce signal PMP CLK'' at the output of delay circuit 109.

[0016] PMP CLK" is provided as a pumping signal to charge pump unit 102-3 and to the input of delay circuit 110. Delay circuit 110 passes its received signal PMP CLK"' but with an added delay to produce signal PMP CLK" at the output of delay circuit 110.

[0017] PMP CLK''' is provided as a pumping signal to the input of charge pump unit 102-4 and to delay circuit 111. Delay circuit 111 passes its received signal PMP CLK''' but with an added delay to produce signal PMP CLK'''' at the output of delay circuit 111. In this example, charge pump unit 102-4 is the last pump unit of the plurality of pump units 102.

[0018] Inverter 112 receives signal PMP CLK'''' and generates an inverse of PMP CLK'''', which is then provided as a data signal at data port D of latch 107.

[0019] The net result is that when RESET is low and VDET is low, the pumping controller generates an oscillating signal (PMP CLK) and sequentially delayed versions of that oscillating signal (PMP CLK', PMP CLK'', PMP CLK''', and PMP CLK'''). When VDET goes high, PMP CLK remains stable at its existing value and oscillation of the oscillating signal (PMP CLK) and sequentially delayed versions of that oscillating signal (PMP CLK', PMP CLK'', PMP CLK''', and PMP CLK''') stops.

[0020] Thus, the voltage regulator 100 can be seen to comprise a plurality of charge pump units 102 for receiving an input voltage (VDD) and generating an output voltage (VD25) greater than the input voltage, and a pumping controller 101 for providing a pumping signal (PMP CLK) to a first pump unit (e.g., pump unit 102-1) of the plurality of pump units and for providing respective sequentially delayed versions of the pumping signal (PMP CLK', PMP CLK'', and PMP CLK''') to other pump units (e.g., pump units 102-2, 102-3, and 102-4) of the plurality of pump units.

[0021] Although the voltage regulator 100 in this example includes four pump units 102, it should be understood that the voltage regulator 100 may alternatively include fewer than four pump units 102 or more than four pump units 102.

[0022] 2 shows a timing diagram 200 of voltage regulator 100, illustrating signals PMP CLK, VD25, and VDET. Unlike certain prior art systems, output voltage VD25 does not experience an additional charge cycle that would cause the output voltage to be higher than the desired voltage (in contrast to the dotted line shown for VD25, which shows how VD25 may experience an additional voltage boost in certain prior art systems), due to VDET being used as the LAT input to latch 107. That is, when VDET goes high, the output PMP CLK of latch 107 remains in its current state and stops oscillating (in contrast to the dotted line shown for PMP CLK, which shows how PMP CLK may behave in certain prior art systems).

[0023] Figure 3 illustrates a method 300 of operation of the voltage regulator 100 of Figures 1 and 2. The method 300 includes receiving (301) an input voltage by a plurality of charge pump units connected in parallel, providing (302) a pumping signal to a first pump unit of the plurality of charge pump units, providing (303) sequentially delayed versions of the pumping signal to other charge pump units in the plurality of charge pump units, and (304) generating, by the plurality of charge pump units, an output voltage greater than the input voltage.

[0024] 4 illustrates a method 400. Method 400 is an example of a method that performs method 300 by providing (302) a pump signal to a first pump unit of the plurality of charge pump units and providing (303) sequentially delayed versions of the pump signal to other charge pump units of the plurality of charge pump units. The method 400 includes comparing a voltage proportional to the output voltage with a reference voltage to generate a comparison output (401); receiving the comparison output as a latch enable signal by a gated D-latch having a reset port (402); receiving a data signal on a data port and a reset signal on a reset port by the gated D-latch (403); generating a pump signal as an output by the gated D-latch (404); generating sequentially delayed versions of the pump signal by respective delay circuits (405); receiving an input including a delayed version of the pump signal to be provided to a last one of the other pump units by an inverter (406); generating an output by the inverter (407); and providing the output of the inverter to the latch as a data signal (408).

[0025] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate materials, elements, or gaps disposed therebetween) and "indirectly" (with intermediate materials, elements, or gaps disposed therebetween). For example, forming an element "over a substrate" can include forming the element directly on the substrate without any intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: a plurality of charge pump units connected in parallel to receive an input voltage and generate an output voltage greater than the input voltage; a pumping controller for providing a pumping signal to a first charge pump unit of the plurality of charge pump units and for providing sequentially delayed versions of the pumping signal to other charge pump units of the plurality of charge pump units.

2. The pumping controller a voltage divider for receiving the output voltage and generating a lower voltage at a node, the voltage divider comprising a first resistor coupled to a second resistor at the node, the first resistor receiving the output voltage; a capacitor coupled between the output voltage and the node.

3. The pumping controller 3. The system of claim 2, comprising a comparator having a first input coupled to the node, a second input coupled to a reference voltage, and an output.

4. The pumping controller 4. The system of claim 3, further comprising: a latch that generates a latch output in response to the output from the comparator received at a latch enable port, a data signal received at a data port, and a reset signal received at a reset port.

5. The system of claim 4 , wherein the latch output is provided as the pumping signal to the first pump unit of the plurality of pump units.

6. The pumping controller The system of claim 5 further comprising a delay circuit for generating the successively delayed versions of the pump signal.

7. The pumping controller an inverter receiving as an input the delayed version of the pumping signal provided to a last pump unit of the other pump units of the plurality of pump units and generating an output; 7. The system of claim 6, wherein the output of the inverter is provided to the latch as the data signal.

8. 1. A method comprising: receiving an input voltage by a plurality of charge pump units connected in parallel; providing a pumping signal to a first pump unit of the plurality of charge pump units; providing sequentially delayed versions of the pump signal to other charge pump units of the plurality of charge pump units; generating an output voltage by the plurality of charge pump units that is greater than the input voltage.

9. 9. The method of claim 8, further comprising the step of comparing a voltage proportional to the output voltage with a reference voltage to generate a comparison output.

10. receiving, by a gated D-latch having a reset port, the comparison output on a latch enable port; receiving, by said latch, a data signal on a data port and a reset signal on a reset port; and generating, by said latch, said pumping signal as an output.

11. 11. The method of claim 10, comprising generating the successively delayed versions of the pump signal with respective delay circuits.

12. receiving an input including the delayed version of the pumping signal provided by an inverter to a last other pump unit of the plurality of pump units; and generating an output with the inverter.

13. 13. The method of claim 12, further comprising providing the output of the inverter as the data signal to the latch.

14. 1. A system comprising:

1. A system comprising: a voltage regulator for generating a pumping signal for a first pump unit of a plurality of pump units connected in parallel and for generating sequentially delayed versions of the pumping signal for other pump units of the plurality of pump units.

15. a voltage divider for receiving output voltages from the plurality of pump units and generating a voltage at a node proportional to the output voltages, the voltage divider comprising a first resistor coupled to a second resistor at the node, the first resistor receiving the output voltages; 15. The system of claim 14, comprising: a capacitor having a first plate receiving the output voltage and a second plate coupled to the node.

16. 16. The system of claim 15, comprising a comparator having a first input coupled to the node, a second input coupled to a reference voltage, and an output.

17. 17. The system of claim 16, comprising a latch that generates a latch output in response to the output from the comparator received at a latch enable port, a data signal received at a data port, and a reset signal received at a reset port.

18. 20. The system of claim 17, wherein the latch output is provided as the pumping signal.

19. 20. The system of claim 18, comprising a delay circuit that generates the successively delayed versions of the pump signal.

20. 20. The system of claim 19, comprising an inverter that receives as an input a last one of the successively delayed versions of the pumping signal and generates an output that is provided to the latch as the data signal.

Images