Systems and methods for baluns optimized for wideband balance characteristics

Abstract

A balun circuit addresses the bandwidth issue by using symmetric amplitude division and phase delay networks to convert single-ended signals to differential signals. Because the balun circuit's balance characteristics are guaranteed over a very wide bandwidth, other performance characteristics that can limit the operating bandwidth, such as impedance matching and insertion loss, can be carefully addressed without concern for amplitude and phase balance. A balun circuit splits a single-ended signal into four differential paths through symmetric networks and applies phase inversion by inverting the polarity of each differential path, thereby reducing the complexity, size, and loss of the balun circuit's overall configuration.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 476,539, filed December 21, 2022, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to signal conversion, and more particularly to a system and associated method for converting a single-ended source signal to a differential signal using a balun optimized for wideband balance. [Background technology]

[0003] Baluns are used to convert signals from single-ended to differential signals. The bandwidth of a balun is limited by various factors, including circuit topology, material properties, package parasitics, and other design constraints such as size, loss, and cost. When designing a system to convert a single-ended signal to a differential signal in an analog-to-digital conversion application, the designer must consider these factors and carefully balance the system. The traditional solution of converting a single-ended source signal directly to a differential signal is an imperfect solution because such a system can be difficult to balance and can result in a suboptimal differential signal.

[0004] It is with respect to these considerations, together with other factors, that the various aspects of the present disclosure have been conceived and developed. [Brief explanation of the drawings]

[0005] [Figure 1A] 1A-1C are a series of schematic diagrams illustrating balun circuits for converting single-ended signals to differential signals. [Figure 1B] 1A-1C are a series of schematic diagrams illustrating balun circuits for converting single-ended signals to differential signals. [Figure 1C] 1A-1C are a series of schematic diagrams illustrating balun circuits for converting single-ended signals to differential signals. [Figure 1D]1A-1C are a series of schematic diagrams illustrating balun circuits for converting single-ended signals to differential signals. [Figure 1E] 1A-1C are a series of schematic diagrams illustrating balun circuits for converting single-ended signals to differential signals. [Figure 2] 1A-D are a series of graphs illustrating amplitude imbalance, phase imbalance, return loss, and insertion loss for a conventional 1:2 Marchand balun and a conventional 1:1 Guanella balun, respectively. [Figure 3] FIG. 2 illustrates a first exemplary balun circuit for implementing the balun circuits of FIGS. 1A-1E. [Figure 4] 4A-4D are a series of graphs illustrating amplitude imbalance, phase imbalance, return loss, and insertion loss, respectively, for the first exemplary balun circuit shown in FIG. 3. [Figure 5] FIG. 2 illustrates a first exemplary balun circuit for implementing the balun circuits of FIGS. 1A-1E. [Figure 6] 6A-6D are a series of graphs illustrating amplitude imbalance, phase imbalance, return loss, and insertion loss, respectively, for the first exemplary balun circuit shown in FIG. 5. [Figure 7] FIG. 2 illustrates a first exemplary balun circuit for implementing the balun circuits of FIGS. 1A-1E. [Figure 8] 8A-8D are a series of graphs illustrating amplitude imbalance, phase imbalance, return loss, and insertion loss, respectively, for the first exemplary balun circuit shown in FIG. 7. [Figure 9] 1A-1E is a process flow diagram illustrating an exemplary method for converting a single-ended signal to a differential signal with the balun circuit of FIGS. 1A-1E. DETAILED DESCRIPTION OF THE INVENTION

[0006] Corresponding reference characters indicate corresponding elements in the various views of the drawings. The headings used in the figures do not limit the scope of the claims.

[0007] Disclosed herein are various embodiments of systems and related methods for converting a single-ended source signal to an output differential signal using a balun optimized for wideband balance. Specifically, the present disclosure provides systems and methods with circuit topologies that symmetrically split a signal to generate a pair of equal-amplitude signals and introduce a phase delay into the pair, thereby addressing the bandwidth limitations of the balun. Because the balance characteristics of such circuit topologies exhibited by the present disclosure enable extremely wide bandwidths, other performance characteristics, such as matching and insertion loss, that can limit the operating bandwidth, can be fully considered without regard for phase and amplitude balance. Furthermore, the circuit topologies described herein allow design tradeoffs related to loss, size, and cost to be made without impacting the balance characteristics that are crucial in analog-to-digital conversion (ADC) applications.

[0008] Baluns are used to convert single-ended signals to differential signals. They split the input signal into two equal-amplitude paths that are 180 degrees out of phase with each other. When baluns are used in the front-end circuit of high-speed ADC devices, the amplitude and phase imbalance of the balun are key parameters affecting the performance of the analog-to-digital converter. Any imbalance caused by the balun in the front-end circuit will degrade the overall data conversion performance. Market and application trends are driving the evolution of ADC technology toward higher bandwidths. Front-end circuits, especially baluns, are becoming a bottleneck in fully realizing the bandwidth and performance potential of modern high-speed ADC integrated circuit chips. In the high-speed ADC market, the industry urgently needs new types of baluns with improved balance characteristics across a wide operating frequency range.

[0009] 1A, a balun circuit 100 for balancing a single-ended source signal to an output differential signal includes a first sub-circuit 120 that receives a single-ended source signal 10 and splits the single-ended source signal 10 into a first stage positive signal 20A and a first stage negative signal 20B. The first sub-circuit 120 includes a front-end balun 122 having a single-ended port 124A that receives the single-ended source signal 10 and a differential port 124B that outputs the first stage positive signal 20A and the first stage negative signal 20B. The first stage positive signal 20A and the first stage negative signal 20B collectively define a common-mode signal introduced into the first sub-circuit 120 by the front-end balun 122.

[0010] The balun circuit 100 further includes a second sub-circuit 140 that receives the first-stage positive signal 20A and the first-stage negative signal 20B. The second sub-circuit 140 splits the first-stage positive signal 20A into a positive second-stage signal pair 40A having a first second-stage positive signal 42A and a second second-stage positive signal 44A, and simultaneously splits the first-stage negative signal 20B into a negative second-stage signal pair 40B having a first second-stage negative signal 42B and a second second-stage negative signal 44B (e.g., to obtain a total of four signals from the original single-ended source signal).

[0011] The balun circuit 100 further includes a third sub-circuit 160 that introduces a phase delay by swapping the first second-stage positive signal 42A of the positive second-stage signal pair 40A and the first second-stage negative signal 42B of the negative second-stage signal pair 40B, thereby generating a first third-stage differential signal pair 60A including a first third-stage positive signal 62A and a first third-stage negative signal 62B, and a second third-stage differential signal pair 60B including a second third-stage negative signal 64A and a second third-stage positive signal 64B. The third sub-circuit 160 introduces the phase delay by symmetrically swapping the positive and negative signals, thereby eliminating the need for a single-ended phase inverter implemented in the prior art, minimizing configuration complexity and facilitating system balancing.

[0012] The balun circuit 100 further includes a fourth sub-circuit 180, which combines the first third-stage positive signal 62A and the first third-stage negative signal 62B of the first third-stage differential signal pair 60A to generate an output stage positive signal 82A of the output differential signal 80. At the same time, the fourth sub-circuit 180 combines the second third-stage negative signal 64A and the second third-stage positive signal 64B of the first third-stage differential signal pair 60A to generate an output stage negative signal 82B of the output differential signal 80. The fourth sub-circuit 180 may include a first back-end balun 182 having a single-ended port 184A associated with the output stage positive signal 82A of the output differential signal 80 and a differential port 184B associated with the first third stage differential signal pair 60A, and a second back-end balun 186 having a single-ended port 188A associated with the output stage negative signal 82B of the output differential signal 80 and a differential port 188B associated with the second third stage differential signal pair 60B. The first back-end balun 182 and the second back-end balun 186 cooperate to reject the common-mode signal introduced into the first sub-circuit 120 by the front-end balun 122.

[0013] The front-end balun 122 of the first sub-circuit 120 introduces imperfect phase and amplitude separation into the single-ended source signal 10, causing common-mode signals to propagate along with the differential signals (e.g., first-stage positive signal 20A and first-stage negative signal 20B). In the fourth sub-circuit 180, the first back-end balun 182 and the second back-end balun 186 both have common-mode rejection characteristics that reject the common-mode signal, reflecting it toward their respective differential ports 184B and 188B. While this common-mode signal reflection may appear as input mismatch or input return loss, the resulting output differential signal 80 maintains the excellent balance characteristics required for ADC applications.

[0014] 1B illustrates an exemplary implementation of first sub-circuit 120. As previously mentioned, first sub-circuit 120 may include a front-end balun 122 that converts single-ended source signal 10 into first stage positive signal 20A and first stage negative signal 20B. The source impedance Z associated with single-ended source signal 10 is s may be present at the single-ended port 124A of the front-end balun 122. Similarly, the load impedance Z associated with each output signal (e.g., first stage positive signal 20A and first stage negative signal 20B) a can be seen at each "line" of the differential port 124B of the front-end balun 122, with a total load impedance of 2×Z a The front-end balun 122 converts the single-ended source signal 10 into a differential signal including a first-stage positive signal 20A and a first-stage negative signal 20B, but does not necessarily exhibit excellent balance characteristics across the entire operating band in the first sub-circuit. In fact, the front-end balun 122 is expected to exhibit imperfect phase and amplitude separation, which introduces a common-mode signal that propagates along with the differential signal, which is ultimately corrected by the fourth sub-circuit 180. The impedance transformation of the first sub-circuit 120 (e.g., transformation from source impedance Zs to load impedance 2×Za) can be achieved by the inherent characteristics of the front-end balun 122. Alternatively, a first-stage impedance matching circuit 126 can be provided at either the single-ended port 124A or the differential port 124B of the front-end balun 122, as shown.

[0015] 1C shows an exemplary implementation of the second sub-circuit 140. The second sub-circuit 140 receives the first-stage positive signal 20A and the first-stage negative signal 20B and outputs two differential signal pairs: a positive second-stage signal pair 40A including a first second-stage positive signal 42A and a second second-stage positive signal 44A, and a negative second-stage signal pair 40B including a first second-stage negative signal 42B and a second second-stage negative signal 44B. The second sub-circuit 140 may be an amplitude division network and may include a first power distribution network 142A and a second power distribution network 142B arranged in parallel as shown. The first power distribution network 142A divides the first-stage positive signal 20A into a second-stage positive signal pair 40A including a first second-stage positive signal 42A and a second second-stage positive signal 44A. Similarly, second power distribution network 142B divides first-stage negative polarity signal 20B into second-stage negative polarity signal pair 40B, including first second-stage negative polarity signal 42B and second second-stage negative polarity signal 44B. The topologies of first power distribution network 142A and second power distribution network 142B are preferably symmetrical so that, at any frequency point, second-stage positive polarity signal pair 40A and second negative polarity signal pair 40B have equal amplitude and phase delay. Thus, first power distribution network 142A and second power distribution network 142B may be identical. Alternatively, first power distribution network 142A and second power distribution network 142B may each be any suitable type of splitter circuit, and may be configured with a signal source impedance Z as shown. a and load impedance Z bFor example, the first power distribution network 142A and the second power distribution network 142B may each be a node splitter. In another example, the first power distribution network 142A and the second power distribution network 142B may each include an RCL (resistor / capacitor / inductor) power distribution network. Alternatively, the first power distribution network 142A and the second power distribution network 142B may include one or more single-stage or multi-stage Wilkinson power dividers. After this stage, the single-ended source signal 10 is evenly split into a positive second-stage signal pair 40A and a negative second-stage signal pair 40B. Here, the positive second-stage signal pair 40A and the negative second-stage signal pair 40B have a differential impedance of 2×Z b The two interleaved differential signal pairs have the following characteristics:

[0016] 1D , the third sub-circuit 160 introduces a wideband 180-degree phase delay by interchanging the first second-stage positive signal 42A of the positive second-stage signal pair 40A with the first second-stage negative signal 42B of the negative second-stage signal pair 40B. In the illustrated example, the third sub-circuit 160 may include four transmission paths 162A-162D with equal phase delays, including crossovers as needed, to interchange or “swap” the polarities of the positive second-stage signal pair 40A and the negative second-stage signal pair 40B as needed to reconfigure them into a first third-stage differential signal pair 60A with positive and negative output polarities and a second third-stage differential signal pair 60B with opposite negative and positive output polarities. The first third-stage differential signal pair 60A includes a first third-stage positive signal 62A and a first third-stage negative signal 62B, and the second third-stage differential signal pair 60B includes a second third-stage negative signal 64A and a second third-stage positive signal 64B. This allows the third sub-circuit 160 to introduce a wideband 180-degree relative phase delay between the first third-stage differential signal pair 60A and the second third-stage differential signal pair 60B. In some embodiments, the four transmission paths 162A-162D of the third sub-circuit 160 simply have characteristic impedances Z bFurthermore, in some embodiments, the third sub-circuit 160 may be configured with four transmission lines having a signal source impedance Z b is the load impedance Z c After this stage, the single-ended source signal 10 is converted into a first third stage differential signal pair 60A and a second third stage differential signal pair 60B, which have equal amplitude and a wideband 180 degree phase delay as shown.

[0017] 1E illustrates an exemplary implementation of the fourth sub-circuit 180, which converts the first third-stage differential signal pair 60A and the second third-stage differential signal pair 60B (four signal paths total) into the output differential signal 80 (two signal paths total). As described above, the fourth sub-circuit 180 may include a first back-end balun 182 and a second back-end balun 186. The first back-end balun 182 may include a differential port 184B that receives the first third-stage differential signal pair 60A and a single-ended port 184A that outputs the output stage positive output signal 82A of the output differential signal 80. Similarly, the second back-end balun 186 may include a differential port 188B that receives the second third-stage differential signal pair 60B and a single-ended port 188A that outputs the output stage negative output signal 82B of the output differential signal 80. As shown, differential ports 184B and 188B of first and second back-end baluns 182 and 186 may each have a port impedance of 2×Zc (e.g., each individual port has an impedance to ground of Zc). Also, single-ended ports 184A and 188A of first and second back-end baluns 182 and 186 may each have a port impedance of Zc. l The impedance transformation in the fourth sub-circuit 180 (e.g., single-ended port impedance Z l to differential port impedance 2×Z c(to ) may be achieved by inherent circuit characteristics of the first back-end balun 182 and the second back-end balun 186. Also, as shown, an optional fourth stage impedance matching network 189 may be included at each single-ended port 184A and 188A or each differential port 184B and 188B of the first back-end balun 182 and the second back-end balun 186. (Note that while FIG. 1E shows an example in which the fourth stage impedance matching network 189 is located at the single-ended ports 184A and 188A, the fourth stage impedance matching network 189 can also be implemented at the differential ports 184B and 188B.) The purpose of the first back-end balun 182 and the second back-end balun 186 is to convert each differential signal (e.g., first third-stage differential signal pair 60A and second third-stage differential signal pair 60B) back into a corresponding single-ended signal of opposite polarity (e.g., output stage positive signal 82A and output stage negative signal 82B, which together define output differential signal 80). As described above, the first back-end balun 182 and the second back-end balun 186 cooperate to remove common-mode signals introduced due to natural non-idealities in the first-stage positive signal 20A and first-stage negative signal 20B generated by the front-end balun 122 of the first sub-circuit 120. After conversion by the fourth sub-circuit 180, the output stage positive signal 82A and the output stage negative signal 82B have equal amplitude and are 180 degrees out of phase with each other, forming a new differential signal, output differential signal 80, based on the single-ended source signal 10. The differential port impedance of this output differential signal 80 is 2×Z l is.

[0018] Impedance Matching By using the balun circuit 100 described herein, the full bandwidth of the entire network as a single balun can be addressed by focusing on impedance matching, without concern for amplitude and phase balance. Various practical implementations at each stage can be used to optimize the impedance matching bandwidth while taking into account complexity and insertion loss.

[0019] The flexibility in selecting the front-end balun 122 in the first subcircuit 120 and the first and second back-end baluns 182 and 186 in the fourth subcircuit 180 allows for bandwidth optimization through impedance matching. For example, while a conventional Marchand balun can provide a flexible impedance transformation ratio, it is typically limited to a relative frequency bandwidth of around 1:3. The Guanella balun has the widest operating bandwidth in terms of return loss, but its available impedance transformation ratios are limited to a few fixed values, such as 1:1, 1:4, and 1:2, and its implementation is somewhat complex. The Guanella balun is often a good choice for both front-end and back-end baluns in wideband applications when the available impedance transformation ratio meets the requirements. Additional impedance matching networks (e.g., first stage impedance matching network 126 and / or fourth stage impedance matching network 189) may be added, such as multi-stage transmission lines or RLC (resistor / inductor / capacitor) lumped parameter networks, to the single-ended port 124A or differential port 124B of the front-end balun 122, the single-ended port 184A or differential port 184B of the first back-end balun 182, and the single-ended port 188A or differential port 188B of the second back-end balun 186.

[0020] Figures 2A-2D show a comparison of the amplitude imbalance (Figure 2A), phase imbalance (Figure 2B), return loss (Figure 2C), and insertion loss (Figure 2D) performance over a wide frequency range for a 1:1 Guanella balun (solid line) and a 1:2 Marchand balun (dashed line). As shown, the bandwidth required to meet the specifications of 10 dB return loss, ±1.5 dB amplitude imbalance, and ±10 degrees phase imbalance is limited to the range of approximately 1600 MHz to 6000 MHz for both baluns. Both amplitude imbalance and phase imbalance deteriorate rapidly outside of the 1600 MHz to 6000 MHz band, resulting in limited bandwidth.

[0021] The dividing network of the second sub-circuit 140 can also be matched using a multi-stage transmission line (e.g., a Wilkinson power divider) or an RLC lumped parameter network, but this increases the complexity of the design and the insertion loss. b and the load impedance Z of the second power distribution network 142B b is the signal source impedance Z a Twice as large as (Z b =2×Z a ), the widest bandwidth and lowest insertion loss are achieved. At this impedance ratio, the first power distribution network 142A has a port impedance Z a The first stage includes a single node connecting a positive polarity signal 20A and outputs two branch paths with a port impedance Z b =2×Z a Similarly, the second power distribution network 142B forms a positive second-stage signal pair 40A including a first second-stage positive signal 42A and a second second-stage positive signal 44A having a port impedance Z a The first stage includes a single node connecting a negative polarity signal 20B and outputs two branch paths with a port impedance Z b =2×Z a The first stage negative polarity signal 20A and the second stage negative polarity signal 20B are formed as a negative polarity second stage signal pair 40B including a first second stage negative polarity signal 42B and a second second stage negative polarity signal 44B having the same polarity. With this configuration, the first stage positive polarity signal 20A and the first stage negative polarity signal 20B are naturally split in half, achieving impedance matching across the entire frequency band.

[0022] Impedance matching can also be implemented in the phase delay network of the third sub-circuit 160, where the third stage impedance matching network 164 may include a multi-stage transmission line or an RLC lumped parameter network, although this may increase the complexity of the design and insertion loss. b =Z c) the widest bandwidth and the smallest insertion loss are obtained. In this case, the characteristic impedance Z b A set of four short transmission lines with

[0023] Example FIG. 3 shows a first exemplary balun circuit 200 including a first sub-circuit 220, a second sub-circuit 240, a third sub-circuit 260, and a fourth sub-circuit 280 that implement a total four-stage cascaded balun that performs 25 Ω single-ended to 100 Ω differential transformation.

[0024] The first sub-circuit 220 uses a 25Ω:25Ω balun (two baluns, part number X4B40L1-5050G, manufactured by TTM RF&S, connected in parallel) as the front-end balun 222, which converts the single-ended signal source signal 10 into a first-stage positive signal 20A and a first-stage negative signal 20B. The second sub-circuit 240 may include a first power distribution network 242A as a first node splitter and a second power distribution network 242B as a second node splitter, which split the first-stage positive signal 20A and the first-stage negative signal 20B, each having an impedance of 12.5Ω, into two parallel 25Ω branch paths to form a second-stage positive signal pair 40A including a first second-stage positive signal 42A and a second second-stage positive signal 44A, and a second second-stage negative signal pair 40B including a first second-stage negative signal 42B and a second second-stage negative signal 44B, respectively. The phase delay network of the third sub-circuit 260 includes four 25Ω transmission lines 262A-262D, which swap the polarities of the positive second-stage signal pair 40A and the negative second-stage signal pair 40B. As a result, the first third stage differential signal pair 60A includes a first third stage positive signal 62A and a first third stage negative signal 62B, and the second third stage differential signal pair 60B includes a second third stage negative signal 64A and a second third stage positive signal 64B. The fourth sub-circuit 280 uses two 50Ω:50Ω baluns (TTM RF&S, part number X4B40L1-5050G) to function as a first back-end balun 282 and a second back-end balun 286. These combine the first third stage differential signal pair 60A into an output stage positive signal 82A of the output differential signal 80, and combine the first third stage differential signal pair 60A into an output stage negative signal 82B of the output differential signal 80.

[0025] 4A-4D show the amplitude imbalance (FIG. 4A), phase imbalance (FIG. 4B), return loss (FIG. 4C), and insertion loss (FIG. 4D) performance of the first exemplary balun circuit 200 over a wide frequency range. If the entire balun of balun circuit 200 were required to meet the same specifications of 10 dB return loss, ±1.5 dB amplitude imbalance, and ±10 degrees phase imbalance, the entire balun of balun circuit 200, from 25 Ω single-ended to 100 Ω differential, would have a bandwidth of 700 MHz to 7500 MHz. In contrast, the conventional balun shown in FIGS. 2A-2D would only have a bandwidth of 1600 MHz to 6000 MHz.

[0026] Furthermore, if an overall single-ended 50 Ω balun is desired, impedance matching can be achieved by adding a multi-section quarter-wave transmission line impedance transformer or a simple resistor (e.g., as first stage impedance matching network 226) at single-ended port 224A of front-end balun 222 of first sub-circuit 220. This can be done without exacerbating the amplitude and phase imbalance.

[0027] FIG. 5 shows a second exemplary balun circuit 300 including a first sub-circuit 320, a second sub-circuit 340, a third sub-circuit 360, and a fourth sub-circuit 380 that implements an overall balun that performs a 50 Ω single-ended to 100 Ω differential transformation.

[0028] The first sub-circuit 320 includes a front-end balun 322, a 50Ω:50Ω balun (part number X4B40L1-5050G manufactured by TTM RF&S), that converts the single-ended source signal 10 into a first-stage positive signal 20A and a first-stage negative signal 20B. The second sub-circuit 340 may include a first resistive divider as a first power distribution network 342A and a second resistive divider as a second power distribution network 342B that split the first-stage positive signal 20A and the first-stage negative signal 20B (each having a 25Ω impedance) into two parallel 25Ω branch paths to form a second-stage positive signal pair 40A including a first second-stage positive signal 42A and a second second-stage positive signal 44A, and a second second-stage negative signal pair 40B including a first second-stage negative signal 42B and a second second-stage negative signal 44B. The phase delay network of the third sub-circuit 360 uses four 25Ω transmission lines 362A-362D to swap the polarities of the positive second-stage signal pair 40A and the negative second-stage signal pair 40B. As a result, the first third-stage differential signal pair 60A includes a first third-stage positive signal 62A and a first third-stage negative signal 62B, and the second third-stage differential signal pair 60B includes a second third-stage negative signal 64A and a second third-stage positive signal 64B. The fourth sub-circuit 380 uses two 50Ω:50Ω baluns (TTM RF&S, part number X4B40L1-5050G) to function as the first back-end balun 382 and the second back-end balun 386. These combine the first third stage differential signal pair 60A into an output stage positive polarity signal 82A of the output differential signal 80, and combine the first third stage differential signal pair 60A into an output stage negative polarity signal 82B.

[0029] 6A-6D show the amplitude imbalance (FIG. 6A), phase imbalance (FIG. 6B), return loss (FIG. 6C), and insertion loss (FIG. 6D) performance of the second exemplary balun circuit 300 over a wide frequency range. If the overall balun using the second exemplary balun circuit 300 must meet specifications of 10 dB return loss, ±1.5 dB amplitude balance, and ±10 degrees phase balance, the bandwidth of the overall balun from 50 Ω single-ended to 100 Ω differential is 900 MHz to 7000 MHz. In contrast, the bandwidth of the conventional balun shown in FIGS. 2A-2D is limited to 1600 MHz to 6000 MHz.

[0030] FIG. 7 shows a third exemplary balun circuit 400 including a first sub-circuit 420, a second sub-circuit 440, a third sub-circuit 460, and a fourth sub-circuit 480 that implements an overall balun that performs a 50 Ω single-ended to 100 Ω differential transformation.

[0031] The first sub-circuit 420 includes a front-end balun 422, a 50Ω:50Ω balun (TTM RF&S, part number X4B40L1-5050G), that converts the single-ended source signal 10 into a first stage positive signal 20A and a first stage negative signal 20B. The second sub-circuit 440 may include a first single-stage Wilkinson power divider as a first power division network 442A and a second single-stage Wilkinson power divider as a second power division network 442B. These divide the first-stage positive signal 20A and the first-stage negative signal 20B, each having an impedance of 25Ω, into two parallel 25Ω branch paths to form a second-stage positive signal pair 40A including a first second-stage positive signal 42A and a second second-stage positive signal 44A, and a second second-stage negative signal pair 40B including a first second-stage negative signal 42B and a second second-stage negative signal 44B. The third sub-circuit 460 uses four 25Ω transmission lines 462A-462D as a phase delay network to invert the polarities of the second-stage positive signal pair 40A and the second-stage negative signal pair 40B. This results in a first third-stage differential signal pair 60A including a first third-stage positive signal 62A and a first third-stage negative signal 62B, and a second third-stage differential signal pair 60B including a second third-stage negative signal 64A and a second third-stage positive signal 64B. Fourth sub-circuit 480 uses two 50Ω:50Ω baluns (TTM RF&S, part number X4B40L1-5050G) to function as a first back-end balun 482 and a second back-end balun 486. These combine the first third-stage differential signal pair 60A into an output stage positive signal 82A of output differential signal 80, and combine the first third-stage differential signal pair 60A into an output stage negative signal 82B.

[0032] 8A-8D show the amplitude imbalance (FIG. 8A), phase imbalance (FIG. 8B), return loss (FIG. 8C), and insertion loss (FIG. 8D) performance of the third exemplary balun circuit 400 over a wide frequency range. If the overall balun using the third exemplary balun circuit 400 must meet specifications of 10 dB return loss, ±1.5 dB amplitude imbalance, and ±10 degrees phase imbalance, the bandwidth of the overall balun from 50 Ω single-ended to 100 Ω differential is 1000 MHz to 7000 MHz. In contrast, the bandwidth of the conventional balun shown in FIGS. 2A-2D is limited to 1600 MHz to 6000 MHz.

[0033] The third exemplary balun circuit 400 configuration exhibited superior flatness in amplitude and phase imbalance response compared to conventional Guanella and Marchand baluns. Furthermore, if desired, performance can be further improved by substituting a first multi-stage Wilkinson power divider for the first power division network 442A instead of the first single-stage Wilkinson power divider and a second multi-stage Wilkinson power divider for the second power division network 442B instead of the second single-stage Wilkinson power divider.

[0034] method 9 illustrates a method 500 for converting a single-ended signal (e.g., single-ended signal 10) to an output differential signal (e.g., output differential signal 80) according to an embodiment of the present disclosure. A first step 510 of method 500 includes splitting a single-ended source signal into a first-stage positive signal and a first-stage negative signal in a first sub-circuit (e.g., first sub-circuit 120, 220, 320, or 420 described above), where the first-stage positive signal and the first-stage negative signal collectively define a common-mode signal introduced into the first sub-circuit. A step 520 of method 500 includes splitting the first-stage positive signal into a positive second-stage signal pair consisting of a first second-stage positive signal and a second second-stage positive signal in a second sub-circuit (e.g., second sub-circuit 140, 240, 340, or 440 described above). Step 530 of method 500 is applicable simultaneously with step 520 and includes splitting the first-stage negative signal into a negative second-stage signal pair consisting of a first second-stage negative signal and a second second-stage negative signal in a second sub-circuit. Step 540 of method 500 includes swapping the first second-stage positive signal of the positive second-stage signal pair with the first second-stage negative signal of the negative second-stage signal pair in a third sub-circuit (e.g., third sub-circuit 160, 260, 360, or 460 described above), thereby obtaining a first third-stage differential signal pair including a first third-stage positive signal and a first third-stage negative signal, and a second third-stage differential signal pair including a second third-stage negative signal and a second third-stage positive signal. Step 550 of method 500 includes combining a first third-stage differential signal pair in a fourth sub-circuit (e.g., fourth sub-circuit 180, 280, 380, or 480 described above) to obtain an output stage positive polarity signal of the output differential signal. A final step 560 of method 500 includes combining a second third-stage differential signal pair in the fourth sub-circuit to obtain an output stage negative polarity signal of the output differential signal.

[0035] As will be understood from the foregoing description, while particular embodiments have been illustrated and described, it will be apparent to those skilled in the art that various modifications can be made therein without departing from the spirit and scope of the invention. All such changes and modifications are intended to be encompassed within the scope and spirit of the invention as defined by the following claims.

Claims

1. 1. A circuit for converting a single-ended source signal into an output differential signal, comprising: a first sub-circuit configured to split a single-ended source signal into a first stage positive signal and a first stage negative signal; a second sub-circuit configured to split the first-stage positive signal into a positive second-stage signal pair including a first second-stage positive signal and a second second-stage positive signal, and to split the first-stage negative signal into a negative second-stage signal pair including a first second-stage negative signal and a second second-stage negative signal; a third sub-circuit configured to generate a first third-stage differential signal pair having a first third-stage positive signal and a first third-stage negative signal, and a second third-stage differential signal pair having a second third-stage positive signal and a second third-stage negative signal, by interchanging the first second-stage positive signal of the positive second-stage signal pair and the first second-stage negative signal of the negative second-stage signal pair; a fourth sub-circuit configured to combine the first third-stage differential signal pairs to obtain an output stage positive polarity signal of an output differential signal and to combine the second third-stage differential signal pairs to obtain an output stage negative polarity signal of the output differential signal.

2. the first sub-circuit comprising:

2. The circuit of claim 1, further comprising: a front-end balun having a single-ended port corresponding to the single-ended source signal and a differential port corresponding to the first stage positive signal and the first stage negative signal.

3. The circuit of claim 2 , wherein the first sub-circuit includes an impedance matching network configured in combination with the front-end balun.

4. the second sub-circuit comprising: a first power distribution network that converts the first-stage positive polarity signal into the second-stage positive polarity signal pair; a second power distribution network that converts said first stage negative polarity signal to said negative polarity second stage signal pair.

5. 5. The circuit of claim 4, wherein the first power distribution network includes a first node splitter and the second power distribution network includes a second node splitter.

6. The circuit of claim 4 , wherein the first power distribution network and the second power distribution network comprise RLC power distribution networks.

7. The circuit of claim 4 , wherein the first power distribution network and the second power distribution network include one or more Wilkinson power dividers.

8. 2. The circuit of claim 1, wherein the positive polarity second stage signal pair and the negative polarity second stage signal pair have equal amplitude and equal phase delay within each signal pair across multiple frequency points.

9. The circuit of claim 1 , wherein the second sub-circuit comprises an impedance matching network.

10. 2. The circuit of claim 1, wherein the second sub-circuit defines a source impedance and a load impedance, and the load impedance of the second sub-circuit is equal to twice the source impedance.

11. 2. The circuit of claim 1, wherein the first third-stage positive signal and the first third-stage negative signal have equal amplitudes and opposite polarities, and the second third-stage negative signal and the second third-stage positive signal have equal amplitudes and opposite polarities.

12. the fourth sub-circuit comprising: a first back-end balun having a differential port corresponding to the first third stage differential signal pair and a single-ended port corresponding to the output stage positive signal of the output differential signal; a second back-end balun having a differential port corresponding to the second third stage differential signal pair and a single-ended port corresponding to the output stage negative polarity signal of the output differential signal.

13. The circuit of claim 1 , wherein the fourth sub-circuit comprises an impedance matching network configured in combination with a first back-end balun and a second back-end balun.

14. 2. The circuit of claim 1, wherein the output stage negative polarity signal and the output stage positive polarity signal of the output differential signal are equal in amplitude and opposite in polarity to each other.

15. 2. The circuit of claim 1, wherein the first stage positive polarity signal and the first stage negative polarity signal collectively define a common mode signal introduced in the first sub-circuit, and the fourth sub-circuit rejects the common mode signal introduced in the first sub-circuit.

16. 1. A method for converting a single-ended source signal to an output differential signal, comprising: splitting a single-ended source signal into a first stage positive signal and a first stage negative signal in a first sub-circuit; splitting the first-stage positive polarity signal into a positive polarity second-stage signal pair having a first second-stage positive polarity signal and a second second-stage positive polarity signal in a second sub-circuit; splitting the first-stage negative polarity signal into a negative second-stage signal pair having a first second-stage negative polarity signal and a second second-stage negative polarity signal in the second sub-circuit; in a third sub-circuit, swapping the first second-stage positive signal of the positive second-stage signal pair with the first negative signal of the negative second-stage signal pair, thereby obtaining a first third-stage differential signal pair including a first third-stage positive signal and a first third-stage negative signal, and a second third-stage differential signal pair including a second third-stage negative signal and a second third-stage positive signal; In a fourth sub-circuit, combining the first third-stage differential signal pair to obtain an output stage positive polarity signal of an output differential signal; in the fourth sub-circuit, combining the second third stage differential signal pair to obtain an output stage negative polarity signal of the output differential signal.

17. the first sub-circuit comprising:

17. The method of claim 16, including a front-end balun having a single-ended port corresponding to the single-ended source signal and differential ports corresponding to the first stage positive polarity signal and the first stage negative polarity signal.

18. the second sub-circuit comprising: a first power distribution network that converts the first-stage positive polarity signal into the second-stage positive polarity signal pair; a second power distribution network that converts the first-stage negative polarity signal to the negative polarity second-stage signal pair.

19. 17. The method of claim 16, wherein the second sub-circuit defines a source impedance and a load impedance, and the load impedance of the second sub-circuit is equal to twice the source impedance.

20. the fourth sub-circuit comprising: a first back-end balun having a differential port corresponding to the first third stage differential signal pair and a single-ended port corresponding to the output stage positive signal of the output differential signal; a second back-end balun having a differential port corresponding to the second third stage differential signal pair and a single-ended port corresponding to the output stage negative polarity signal of the output differential signal.

21. 17. The method of claim 16, wherein the output stage negative polarity signal and the output stage positive polarity signal of the output differential signal are equal in amplitude and opposite in polarity to each other.

22. 17. The method of claim 16, wherein the first stage positive polarity signal and the first stage negative polarity signal collectively define a common mode signal introduced in the first sub-circuit, and the fourth sub-circuit rejects the common mode signal introduced in the first sub-circuit.

23. 10. A circuit for converting a single-ended source signal to an output differential signal according to any configuration, arrangement, or embodiment described herein.

24. A method for converting a single-ended source signal to an output differential signal according to any of the configurations, arrangements, processes, or embodiments described herein.

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