Carrier including a charge trapping layer, related composite substrate including such a carrier, and related manufacturing process

Abstract

A carrier (Sprt) for a composite substrate, the carrier (Sprt) comprising a charge trapping layer (Trap) in contact with a base substrate (BSprt), the trapping layer comprising a low dielectric constant layer made of a material having a dielectric constant lower than that of silicon dioxide.

Description

[Technical Field]

[0001] The present invention relates to a carrier containing a charge trapping layer, which is intended to receive a thin crystalline layer by film transfer techniques to form a composite substrate. Such composite substrates are applicable in the field of integrated electronic components, particularly radio frequency (RF) components that process signals whose frequencies can typically range from 20 kHz to 300 GHz or higher. The thin layer of the composite substrate can be made from a semiconductor, such as silicon, or an insulator, such as a material with piezoelectric and / or ferroelectric properties. In addition to such a carrier, the present invention also relates to a composite substrate containing this carrier and to which the thin layer has been transferred. The present invention also relates to a process for manufacturing the carrier and a process for manufacturing a composite substrate incorporating such a carrier. [Background technology]

[0002] There is a wealth of prior art in this area.

[0003] Thus, as an example of the first approach, U.S. Pat. Nos. 7,585,748 and 9,293,473 propose forming a charge trapping layer (more simply referred to as a "trapping layer" in the remainder of this specification) from a layer of polycrystalline silicon disposed on a silicon-based substrate.

[0004] The boundaries of the silicon grains that make up the polycrystalline layer form traps for charge that can flow. These traps can form at these boundaries due to incomplete or dangling chemical bonds. Electrical conduction is therefore hindered in the trap layer, and the trap layer therefore has a high resistivity, typically higher than 1000 ohm-cm.

[0005] In addition to polycrystalline silicon, trapping layers may more generally be formed from non-single-crystalline layers that contain structural defects such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, pores, etc., which can trap charge.

[0006] Thus, a trapping layer can be formed by implanting relatively heavy species such as argon into the surface thickness of the base substrate in order to create structural defects therein that form electrical traps. As an example of this approach, US Patent No. 10,224,233 proposes a trapping layer formed from nanocavities arranged in the surface region of the base substrate, obtained by implanting helium and nitrogen.

[0007] This layer may also be formed by porosifying the surface thickness of the base substrate. Thus, US Patent No. 10,290,533 proposes a trapping layer consisting of pores formed on the surface of a base substrate, oxidized and filled with a semiconductor, polycrystalline or amorphous material.

[0008] However, for ease of implementation, the trapping layer is generally formed by depositing a polycrystalline silicon layer on a base substrate. In order to maintain the polycrystalline quality of this layer during the heat treatments that the carrier may undergo, it is advantageous to form an amorphous layer, for example made of silicon dioxide, on the base substrate before the trapping layer is deposited, as proposed in US Patent Nos. 8,765,571 and 9,129,800.

[0009] US Patent No. 2015115480 proposes, for its part, the formation of a stack of amorphous or polycrystalline layers of passivated elements as a trapping layer. These basic layers may be composed of silicon, germanium, or silicon-germanium. This stack aims to make the trapping layer more robust, especially against the heat treatments that the carrier undergoes during the manufacturing process of a composite substrate using such a carrier.

[0010] US Pat. No. 1,125,265 proposes, in one implementation, forming the trapping layer from a polycrystalline main layer, interposed with an intermediate layer formed from an alloy of silicon and carbon.

[0011] In WO2021110513, a polycrystalline layer of silicon carbide is formed directly on a base substrate before disposing a polycrystalline trapping layer on the base substrate.

[0012] In EP 3195352 the trapping layer is selected from the group consisting of carbon nitride, silicon carbon nitride and combinations of these materials.

[0013] In EP 3195353, the amorphous or crystalline trapping layer is formed from a wide bandgap material, in particular from a material selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, and aluminum gallium indium boron nitride.

[0014] In EP 3189544, the trapping layer is an amorphous layer of carbon-doped silicon formed on a silicon-based substrate having a silicon oxide surface layer.

[0015] In EP 3266038, prior to deposition of the polycrystalline silicon trapping layer, a nucleation layer made of silicon oxide, silicon nitride, or silicon oxynitride is formed, which is heat treated to form pores therein.

[0016] US Patent No. 10,468,295 provides for the formation of a silicon nitride or silicon oxynitride layer between the polycrystalline silicon trap layer and the silicon oxide dielectric layer, which can be obtained by deposition or by nitridation / oxynitridation of the trap layer, with the aim of maintaining the resistivity of the trap layer and avoiding its recrystallization.

[0017] In general, this prior art identifies a need for a carrier for a composite substrate that includes a trapping layer with high resistivity. The purpose of this trapping layer is to ensure the linearity of electrical signals propagating through an active layer, which includes a thin crystalline layer formed on the surface of the substrate, by reducing coupling between the active layer and the carrier. The linearity must be sufficient to meet the requirements of a wide range of applications, particularly radio frequency applications.

[0018] U.S. Patent Application Publication No. 2021 / 0111019(A1) proposes a solution for limiting RF signal absorption based on the use of a porous semiconductor layer, specifically a porous silicon layer, integrated into an SOI structure (SOI stands for silicon on insulator) that includes a charge trapping layer and a crystalline layer epitaxially grown on the porous semiconductor layer. However, no satisfactory technical solution is known for integrating the formation of a porous silicon layer into an industrial process for manufacturing semiconductor components, such as RF circuits, on an SOI substrate. Furthermore, porous silicon has certain limitations, such as high mechanical fragility due to its porosity (which is difficult to sufficiently reduce), the impact of the initial conductivity of the porosified silicon on high-frequency performance, and the inability to be formed directly on substrates with high electrical resistivity. Summary of the Invention

[0019] It is an object of the present invention to provide an alternative to previously considered solutions. More specifically, prior solutions tend to focus on trapping charge at the interface between the charge trapping layer and the carriers, to the exclusion of other approaches. However, applicant has considered a solution that not only addresses aspects of charge trapping at external interfaces, but also addresses aspects of the electric polarization of the charge trapping layer, and potentially the possibility of trapping charge within the trapping layer itself.

[0020] To this end, a first aspect of the present invention is a carrier for a composite substrate, comprising a charge trapping layer in contact with a base substrate, the trapping layer comprising a low dielectric constant layer made from a material having a dielectric constant lower than that of silicon dioxide.

[0021] A first advantage of the carrier according to the present invention is that it contains a charge trapping layer that effectively fixes charges by means of a disordered structure containing many sites capable of trapping charges.

[0022] A second advantage of the carrier according to the invention is that it reduces the capacitive coupling between the active layer and the substrate, an effect achieved by using so-called "low-k" materials, i.e. materials with a low dielectric constant.

[0023] A third advantage is that charge accumulation at the interface of the charge trapping layer is reduced; such accumulation tends to attract free charges that contribute to the conductivity of the base substrate and thus reduce its effective resistivity, especially near the interface between the trapping layer and the base substrate.

[0024] A fourth advantage of the carrier according to the present invention is that it achieves the aforementioned advantages using fewer layers, facilitating the manufacture of the carrier and reducing the associated manufacturing costs.

[0025] Additional non-limiting features of the first aspect of the present invention may be considered individually or in any technically feasible combination. The low dielectric constant layer may be porous; The low dielectric constant layer may have a porosity of 0% to 50%, preferably 5% to 50%, more preferably 14% to 50%; - the layer has a low dielectric constant and may be in direct contact with the base substrate; An intermediate layer may be interposed between the low-k layer and the base substrate, the intermediate layer being made of SiC or what is called DLK material, where DLK stands for high density low k; The base substrate may have a uniform composition; The material having a lower dielectric constant than silicon dioxide may be SiOC; The material having a dielectric constant lower than that of silicon dioxide may be SiOCH; and -Materials with a dielectric constant lower than silicon dioxide are 10 16 ~1021 at / cm 3 The nitrogen may be present in a concentration of 0.1 to 1.0% by weight.

[0026] Of particular note is the aspect relating to the porosity of the trapping layer, which is advantageous in that the layer itself naturally contains free surfaces and dangling bonds around its pores, creating an equivalent number of sites for trapping charge.

[0027] Furthermore, the use of SiOCH or SiOC to form the charge trapping layer makes it possible to envisage a trapping layer of sufficient thickness to effectively isolate from the carrier any element formed on the charge trapping layer and intended to operate in the radio frequency range.

[0028] A second aspect of the invention relates to a composite substrate comprising a crystalline surface layer disposed on a carrier according to the first aspect of the invention.

[0029] According to additional non-limiting features of the second aspect of the present invention, considered individually or in any technically feasible combination: The surface layer may be made of silicon; The thin layer may be made of a ferroelectric material; A dielectric layer may be interposed between the crystal layer and the trapping layer.

[0030] A third aspect of the present invention relates to a process for manufacturing a carrier for a composite substrate, comprising the steps of providing a base substrate and forming a charge trapping layer on the base substrate, the charge trapping layer comprising a low dielectric constant layer made from a material having a dielectric constant lower than silicon dioxide.

[0031] In the process of the third aspect of the present invention, the low dielectric constant layer may have a porosity of 0% to 50%, preferably 5% to 50%, more preferably 14% to 50%.

[0032] A fourth aspect of the present invention relates to a process for manufacturing a composite substrate, the process comprising the steps of providing a base substrate, forming a charge trapping layer on the base substrate, the charge trapping layer comprising a low dielectric constant layer made from a material having a dielectric constant lower than that of silicon dioxide, forming a dielectric layer on the charge trapping layer, and attaching a surface layer to the dielectric layer.

[0033] In the process of the fourth aspect of the present invention, the surface layer may be a crystalline or monocrystalline layer. [Brief explanation of the drawings]

[0034] Other features and advantages of the present invention will become apparent from the following detailed description of the invention, which description is given with reference to the accompanying drawings. [Figure 1] FIG. 1 shows a composite substrate that forms one subject of this specification. [Figure 2] FIG. 2 shows the specific case of the trap layer of FIG. [Figure 3] FIG. 3 shows a schematic process for manufacturing the composite substrate of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0035] FIG. 1 shows a composite substrate S including a carrier Sprt incorporating a base substrate BSprt and a charge trapping layer Trap on the base substrate BSprt, a surface layer Crist arranged on the carrier Sprt, and a dielectric layer Diel interposed between the surface layer Crist and the carrier Sprt and preferably in direct contact with the surface layer Crist and the charge trapping layer Trap, which will be referred to hereinafter as the trapping layer Trap.

[0036] The surface layer Crist is a layer that makes it possible to provide a function, for example a semiconducting function or a ferroelectric function, to a device fabricated on or in the composite substrate S. It may generally be a layer of crystalline structure, and optionally of monocrystalline structure.

[0037] Conventionally, the composite substrate S may take the form of a circular wafer, the diameter of which may be 100, 200, 300 mm, or even 450 mm, or some other size.

[0038] As described in the prior art documents mentioned above, the composite substrate S can be produced in several ways. Very generally, the composite substrate S can be produced using a manufacturing process that involves bonding a carrier Sprt and a donor substrate, with a dielectric layer Diel interposed between these two elements, followed by a step of removing a portion of the donor substrate to form a surface layer Crist. The step of removing a portion of the donor substrate can be performed by chemical-mechanical thinning of this substrate. However, the composite substrate S is preferably produced by applying the Smart Cut® technology, in which the layer intended to form the surface layer Crist is defined by a weakened plane formed by implanting light species such as hydrogen into the donor substrate. This layer is then separated from the donor substrate, which is bonded to the carrier via the dielectric layer Diel, by splitting within the weakened plane, and the surface layer Crist remains attached to the carrier Sprt with the trap layer Trap interposed therebetween. The function of the layer Diel is essentially to improve the adhesion of the surface layer Crist to the carrier Sprt.

[0039] The carrier Sprt typically has a thickness of several hundred microns. Preferably, the carrier Sprt has a high resistivity of greater than 1000 ohm-cm, and even more preferably greater than 2000 ohm-cm. In this way, the density of charge carriers (holes or electrons) that can move through the carrier is limited. However, the present invention is not limited to carrier Sprts with such resistivity, and has advantages in terms of RF performance when the substrate has a lower resistivity of about several hundred ohm-cm, for example, less than 1000 ohm-cm, or less than 500 ohm-cm, or even less than 10 ohm-cm.

[0040] The base substrate BSprt included in the carrier Sprt is preferably made of single-crystal silicon due to its availability and cost. For example, it may be a CZ silicon substrate with a low interstitial oxygen content of 6 to 10 ppm, or particularly a FZ silicon substrate with a very low interstitial oxygen content. It may also be a CZ silicon substrate with a high interstitial oxygen content (high Oi) of over 26 ppm. Alternatively, the base substrate BSprt may be made of another material, such as sapphire, glass, quartz, or silicon carbide. In certain circumstances, the base substrate BSprt may have a standard resistivity of less than 1 kOhm·cm, especially if the trapping layer is sufficiently thick, e.g., greater than 30 microns.

[0041] The trap layer, as reported in the prior art literature, can be of very different nature. Generally, it is an amorphous layer with structural defects such as dislocations, grain boundaries, amorphous zones, gaps, inclusions, and pores. These structural defects, for example at the sites of incomplete or dangling chemical bonds, form traps for charges that tend to flow through the material. Therefore, electrical conduction within the trap layer is prevented, resulting in a high resistivity.

[0042] Preferably, the trapping layer Trap is integrated so as to be in direct contact with the base substrate BSprt. Therefore, this carrier has a composition that is considered to be uniform and can be in direct contact with the trapping layer Trap, but these characteristics do not exclude the presence of a native oxide on the surface of the base substrate and at its interface with the trapping layer Trap. This may be an oxide layer with a thickness of about 10 nm or less, which is produced by simply exposing the base substrate BSprt to the ambient atmosphere.

[0043] In the context of this specification, the charge trap layer (Trap) comprises a layer of a low-k material, i.e., a material with a dielectric constant lower than that of silicon dioxide. Among low-k materials, mention may be made of porous silica, fluorosilicate glass (FSG), organosilicon compounds, or silicon-based dielectric polymers. In this document, SiOC and SiOCH, more specifically porous SiOCH, are considered. Accordingly, materials with a dielectric constant between 2.25 and 3.1 are considered.

[0044] FIG. 2(a) shows a composite charge trap layer Trap formed from a layer Lk of low-k material and an intermediate layer Inter interposed between the layer Lk and the base substrate. This intermediate layer may be formed from a layer of silicon carbide (SiC), preferably 10-100 nm thick, or indeed from a second layer of low-k material with a higher dielectric constant than the material of the layer Lk (e.g., a layer of what is called DLK material, where DLK stands for high-density low-k, or, for example, a layer of SiOCH that is non-porous or less porous than the layer Lk), preferably 10-500 nm thick. This intermediate layer generates additional electrical traps therein, thus increasing the trap capacitance of the layer Trap. Increasing the thickness of the layer Trap by the intermediate layer also has the effect of reducing its capacitance, thus improving the linearity of the electrical signal propagating through the active layer formed on the surface of the carrier Sprt. Furthermore, the SiC layer strengthens the mechanical strength of the layer Lk and its adhesion to the base substrate BSprt. The SiC layer has further advantages, partly due to its high tensile strength, and the diffusion of carbon atoms in the layer Lk and their relaxation leads to the formation of additional traps in the layer Lk, creating a thin compressive layer at the interface with the base substrate, which reduces the charge carrier mobility and therefore advantageously increases the electrical resistivity.

[0045] Alternatively, as shown in Figure 2(b), the trapping layer Trap may consist solely of a layer Lk of low-k material such as SiOC, SiOCH, or porous SiOCH. SiOC and SiOCH may be non-porous or very slightly porous (less than 5% porosity).

[0046] The dielectric layer Diel may be made of silicon oxide and preferably contains nitrogen, which, where appropriate, is advantageous for the formation of a barrier layer that prevents the diffusion of species, in particular hydrogen, boron and lithium.

[0047] The surface layer Crist may be of any type suitable for the actual application in question. It is highly preferred that it be formed from a monocrystalline material. Thus, if the carrier Sprt is intended to accommodate integrated semiconductor components, the surface layer Crist may consist of monocrystalline silicon or any other semiconductor. If the carrier Sprt is intended to accommodate a surface acoustic wave filter, the surface layer Crist may consist of a ferroelectric material, such as LiTaO3, LiNbO3, LiAlO3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3, or KTaO3. This layer can take the form of a circular wafer of standardized size, for example, 150 mm or 200 mm in diameter. However, the invention is in no way limited to these sizes or this shape. This layer may also be cut from an ingot of ferroelectric material, the cutting being carried out so that the crystal orientation is predetermined. The orientation is selected depending on the intended application. Therefore, when it is desired to utilize the properties of the thin layer to form a SAW filter, it is common to choose an orientation of 42°RY. However, the invention is not limited to one particular crystal orientation. The surface layer Crist may also include finished or semi-finished integrated components formed on a donor substrate and transferred to a carrier Sprt during the process of manufacturing the composite substrate S. In general, the surface layer may have a thickness between 10 nm and 10 μm.

[0048] A process for manufacturing a composite substrate S as shown in FIG. 1 will now be described, purely by way of example, with reference to FIG. 3, in which the surface layer Crist is made from a ferroelectric material.

[0049] In this process, a trapping layer (Trap) made of porous SiOCH is formed on a silicon-based support (BSprt) by deposition using a conventional PECVD process (PECVD, short for Plasma-Enhanced Chemical Vapor Deposition), followed by UV annealing, for example, according to one of the processes described in the paper by V. Jousseaume et al., "SiOCH Thin Films Deposited by Chemical Vapor Deposition: From Low-κ to Chemical and Biochemical Sensors," Microelectronic Engineering 167 (2017) 69-79. The SiOCH layer can have a porosity of 5% to 50% or more immediately after its formation. Thus, a trapping layer (Trap) with a thickness of 80 nm to 4 μm, preferably 200 nm to 1 μm, can be formed to achieve a compromise between the trapping and separation effectiveness that requires a thick deposition and the manufacturing constraints that require a small thickness due to the limited availability of the machine used. It should be noted that shrinkage of the formed layer may be observed after deposition; this shrinkage is associated with the release of porogens during UV annealing and can result in a loss of up to approximately 40% of their thickness. The thicknesses indicated correspond to the thickness after shrinkage. It is also possible to adjust the porosity of the resulting layer to be between 5% and 50%, or between 14% and 50% after shrinkage.

[0050] The SiOCH (or SiOC, if appropriate) layer may be nitrided by the addition of nitrogen, which gives it the property of being impermeable to certain chemical species, such as hydrogen, boron, and lithium, which may be present, for example, in the subsequently formed ferroelectric layer, or more generally as a result of contamination of the surface layer in the device during manufacture; these species tend to reduce the charge trapping ability of the trap layer if they are free to move and occupy charge trap sites. Nitriding an oxide diele placed on the Trap layer may therefore be an option, as the nitriding of the Trap layer allows the benefit of its impermeability to the diffusion of hydrogen, boron, and lithium to be preserved. It is then possible to maintain a pure (substantially non-nitrided) SiO2 layer diele in contact with the surface Crist layer, maintaining a good buried interface between the Crist layer and the diele, especially if the Crist layer is made of silicon. Therefore, the material from which the Trap layer is made may be 10 16 ~10 21 at / cm 3 Another advantage of the addition of nitrogen is that it increases the mechanical strength of the layer, which is potentially very advantageous during the fabrication of devices thereon.

[0051] The trapping layer is then optionally polished in a chemical mechanical polishing (CMP) process.

[0052] A layer of silicon oxide, optionally containing nitrogen and having a thickness of 100 nm to 1500 nm, preferably 150 nm to 500 nm, is deposited on the trap layer Trap, for example using a PECVD technique with a temperature of 300° C. to 500° C., to form a dielectric layer Diel of the composite substrate S. The layer is then optionally polished in a chemical mechanical polishing (CMP) step.

[0053] The dielectric layer Diel may be deposited so that the ratio of nitrogen concentration to hydrogen concentration is favorable for blocking the diffusion of hydrogen, i.e. so that there is an excess of nitrogen relative to the amount of hydrogen, i.e. so that the ratio of nitrogen concentration to hydrogen concentration is strictly greater than 1, preferably greater than 1.5, and even more preferably greater than 3, in terms of concentrations measured using the SIMS method (SIMS stands for Secondary Ion Mass Spectroscopy). Thus, the hydrogen concentration in the dielectric layer is about 10 22 at / cm 3 It is preferable that it is less than 10 ...

[0054] As shown by this embodiment, it is generally preferable to dispose the dielectric layer Diel on the base substrate BSprt (via the trapping layer Trap) rather than on the donor substrate. Specifically, it is generally possible to heat-treat the base substrate BSprt at relatively high temperatures, which may be desirable for certain applications, but is not necessarily the case for the donor substrate. For example, the donor substrate may include a weakened surface, or may be made of or contain components made of a ferroelectric material with a relatively low Curie temperature, which in each of these cases limits the thermal history that can be applied to it to a few hundred degrees for a relatively short period of time (less than one hour). Nevertheless, the present invention does not exclude the possibility that, in certain preferred cases, the dielectric layer Diel may be at least partially formed on the donor substrate 200.

[0055] The structure obtained at this stage is shown in Figure 3(a).

[0056] In parallel with the preparation of the carrier Sprt, hydrogen ions are implanted into the ferroelectric lithium tantalate donor substrate 200 through its lateral first face 210 in order to form a buried weakened surface 220. In this way, the following are defined: a surface layer Crist between this weakened surface 220 and the first face 210 of the donor substrate;

[0057] The donor substrate obtained at this stage is shown in FIG.

[0058] The donor substrate 200 is bonded to a dielectric layer Diel disposed on a carrier Sprt, as shown in FIG. 3(c), and then the donor substrate 200 is split within the weakened surface 220 by a moderate heat treatment at approximately 400°C. The complementary layer 22 is then released from the donor substrate, exposing the free surface 230 of this layer. It can then be prepared to improve its crystalline quality and surface finish. This preparation involves thinning the first layer by chemical-mechanical polishing and a heat treatment at 500°C for 1 hour in a neutral atmosphere. The resulting structure is the structure of FIG. 1, as shown in FIG. 3(d).

[0059] While the above process was applied when the surface layer Crist was a ferroelectric lithium tantalate layer, other types of ferroelectric materials, such as lithium niobate, could also be used. Furthermore, as an alternative to a ferroelectric surface layer, a semiconductor surface layer, such as a silicon layer, or a silicon-containing semiconductor surface layer, such as single-crystal silicon, could be used. It is also possible to transfer layers containing completed or semi-finished components, with the aim of placing these components on a carrier Sprt to utilize their properties in the radio frequency range.

[0060] Test results The radio frequency (RF) performance of a component can be estimated through RF characterization of the composite substrate (more specifically, the carrier of this composite substrate) on which or within which the component is intended to be formed. As described in the January 2015 publication "White Paper - RF SOI Characterization" published by SOITEC, the RF performance of the substrate can be characterized by second harmonic distortion measurements (HD2).

[0061] Therefore, it is generally desired to create carriers that include a trapping layer that allows for the creation of carriers with high RF performance that remains stable with temperature, this performance being characterized by HD2 measurements.

[0062] The applicant has carried out RF performance tests for various shapes and processes on a carrier Sprt formed from a base substrate BSprt made of monocrystalline silicon, which is provided with a silicon oxide dielectric layer Diel and which includes a layer Trap including a layer of porous SiOCH as a material with a low dielectric constant.

[0063] Case 1 In this first case, the SiOCH layer was in direct contact with the carrier Sprt and was not subjected to any heat treatment after its formation. The average HD2 measurements obtained showed an HD2 second harmonic distortion of -60 dBm and an effective resistivity of 1641 ohm-cm, which are satisfactory values ​​for the application of the carrier Sprt in the radio frequency range.

[0064] Case 2 This second case was identical to Case 1, except that the SiOCH layer underwent rapid thermal annealing (RTA) by lamp heating at 1000 °C for 30 seconds under a nitrogen atmosphere. The average HD2 measurements obtained showed an HD2 second harmonic distortion of -78 dBm and an effective resistivity of 2950 ohm-cm. The RTA treatment appeared to have a positive effect on both the HD2 second harmonic distortion and the effective resistivity.

[0065] Case 3 This third case was identical to Cases 1 and 2, except that the SiOCH layer underwent a furnace heat treatment at 1100 °C for 2 hours under nitrogen atmosphere, followed by a rapid thermal anneal (RTA) at 1000 °C for 30 seconds under nitrogen atmosphere. The average HD2 measurements obtained showed an HD2 second harmonic distortion of -73 dBm and an effective resistivity of 1500 Ω·cm, indicating lower RF performance than Case 2 when only the RTA treatment was applied.

[0066] Applicant interprets the measurements in these three cases as indicating that the RTA treatment stabilizes the porous SiOCH layer, limiting the adsorption of gases such as water vapor present in the atmosphere on its surface and within its pores, improving RF performance.

[0067] Case 4 Case 4 differed from Cases 1 through 3 in that the trapping layer, Trap, was a composite layer including an interlayer (Inter) of 100 nm of SiC deposited by PECVD between the porous SiOCH layer and the base substrate, BSprt, following the geometry shown in Figure 3. The average HD2 measurements obtained showed an HD2 second-harmonic distortion of -80 dBm and an effective resistivity of 2895 ohm-cm. This case yielded superior performance, close to that of Case 2, as measured by both HD2 second-harmonic distortion and effective resistivity.

[0068] The invention is naturally not limited to the embodiments described, and variations of the embodiments can be applied without departing from the scope of the invention as defined by the claims.

Claims

1. A carrier (Sprt) for a composite substrate, the carrier (Sprt) comprising a charge trapping layer (Trap) in contact with a base substrate (BSprt), the trapping layer (Trap) comprising a low dielectric constant layer (Lk) made of a material having a dielectric constant lower than that of silicon dioxide, the material having a dielectric constant lower than that of silicon dioxide being SiOC or SiOCH.

2. The carrier (Sprt) according to claim 1, wherein said low dielectric constant layer (Lk) is porous.

3. The carrier (Sprt) according to claim 2, wherein said low dielectric constant layer has a porosity of 0% to 50%, preferably 5% to 50%, more preferably 14% to 50%.

4. The carrier (Sprt) according to any one of claims 1 to 3, wherein the low dielectric constant layer (Lk) is in direct contact with the base substrate (BSprt).

5. The carrier (Sprt) according to any one of claims 1 to 3, wherein an intermediate layer (Inter) is interposed between the low dielectric constant layer (Lk) and the base substrate (BSprt), said intermediate layer being made of SiC or a so-called DLK material, DLK standing for high density low k.

6. The carrier (Sprt) according to any one of claims 1 to 5, wherein the base substrate (BSprt) has a uniform composition.

7. The material is 10 16 ~10 21 at / cm 3 7. The carrier (Sprt) according to claim 1, having a dielectric constant lower than that of silicon dioxide containing nitrogen at a concentration of 0.1 to 1.

0.

8. A composite substrate (S) comprising a crystalline surface layer (Crist) arranged on a carrier (Sprt) according to any one of claims 1 to 7.

9. 9. The composite substrate (S) according to claim 8, wherein said surface layer (Crist) is made of silicon.

10. 9. A composite substrate (S) according to claim 8, wherein said thin layer is made of a ferroelectric material.

11. The composite substrate (S) according to any one of claims 8 to 10, wherein a dielectric layer (Diel) is interposed between the crystal layer (Crist) and the trap layer (Trap).

12. A process for manufacturing a carrier (Sprt) for a composite substrate, comprising: - providing a base substrate (BSprt), - forming on the base substrate (BSprt) a charge trapping layer (Trap) comprising a low dielectric constant layer (Lk) made of a material having a dielectric constant lower than that of silicon dioxide, wherein the material having a dielectric constant lower than that of silicon dioxide is SiOC or SiOCH.

13. The manufacturing process according to claim 12, wherein said low dielectric constant layer (Lk) has a porosity of 0% to 50%, preferably 5% to 50%, more preferably 14% to 50%.

14. A process for producing a carrier (Sprt) for a composite substrate according to claim 12 or 13, further comprising forming a dielectric layer (Diel) on the charge trapping layer (Trap); and - depositing a surface layer (Crist) on said dielectric layer (Diel).

15. 15. Process for manufacturing a composite substrate (S) according to claim 14, wherein said surface layer (Crist) is a crystalline or monocrystalline layer.

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