Die-pair device splitting

Abstract

A method for splitting a die pair can include providing a circuit die having a metal stack and including a majority of the logic transistors of an integrated circuit. The method can also include providing one or more additional circuit dies, the additional circuit dies having one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die, and a majority of the static random access memory and analog devices of the integrated circuit. The method can include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Description

[Background technology]

[0001] Conventional process nodes are delivered as a single planar piece of silicon containing transistors and other devices (e.g., front end of line, or FEOL) and the wires connecting them (e.g., back end of line, or BEOL). This structure has all the capabilities for both high-speed logic, static random access memory (SRAM), and analog devices (e.g., IO interfaces, clock generators, etc.) to allow a fully functional system on chip (SoC). The capabilities of high-speed logic must be balanced with processing / manufacturing requirements to allow other devices (e.g., SRAM, analog) to achieve their requirements. This rebalancing of capabilities results in a compromise between performance and power efficiency improvements for the logic devices.

[0002] The accompanying drawings illustrate several exemplary embodiments and are a part of this specification and, together with the following description, demonstrate and explain various principles of the present disclosure. [Brief explanation of the drawings]

[0003] [Figure 1A] FIG. 1 is a flow diagram illustrating an exemplary method for splitting a die pair device. [Figure 1B] FIG. 1 is a flow diagram illustrating an exemplary method for sensing temperature in a die-pair topology. [Figure 1C] FIG. 1 is a flow diagram illustrating an exemplary method for achieving shared metal connectivity between 3D stacked circuit dies. [Figure 1D] FIG. 1 is a flow diagram illustrating an exemplary method for circuit die stacking. [Figure 1E]FIG. 1 is a flow diagram illustrating an exemplary method for providing backside power. [Figure 1F] FIG. 1 is a flow diagram illustrating an exemplary method for advanced processing in a fuseless process pair. [Figure 2] FIG. 1 is a block diagram illustrating an example integrated circuit including an advanced node and a pair node having face-to-face hybrid bonded metal stacks. [Figure 3] FIG. 1 is a block diagram illustrating an exemplary integrated circuit including an advanced node, a paired node having a surface-to-surface hybrid bonded metal stack, and one or more temperature sensors located within the paired node. [Figure 4] FIG. 1 is a block diagram illustrating an exemplary integrated circuit including an advanced node, a pair node having a surface-to-surface hybrid bonded metal stack, and one or more fuses and / or phase-locked loop circuits located within the pair node. [Figure 5] FIG. 1 is a block diagram illustrating wafer-on-wafer and chip-on-wafer processes. [Figure 6] FIG. 1 is a block diagram illustrating a chip-on-wafer process that avoids placement of fuses in advanced die optimized for logic. [Figure 7] FIG. 1 is a block diagram illustrating an exemplary integrated circuit including an advanced node, a pair node having a hybrid-bonded metal stack, and a connection element provided at the pair node. [Figure 8] FIG. 1 is a block diagram illustrating an exemplary integrated circuit including a first circuit die and a second circuit die having a combined metal stack with a shared metal layer. [Figure 9] FIG. 1 is a block diagram illustrating an exemplary semiconductor device. [Figure 10] 1 is a block diagram illustrating an exemplary semiconductor device and thermal solution. [Figure 11]FIG. 1 is a block diagram illustrating an exemplary semiconductor device demonstrating power supply options. [Figure 12] FIG. 1 is a block diagram illustrating an exemplary semiconductor device demonstrating power supply options. [Figure 13] FIG. 1 is a block diagram illustrating an exemplary semiconductor device demonstrating power supply options. [Figure 14] FIG. 1 is a block diagram illustrating the bottom die showing details of the power curtains with through silicon vias and backside power delivery network. [Figure 15] FIG. 1 is a block diagram illustrating a semiconductor device including a power curtain with through-silicon vias requiring keep-out zones. [Figure 16] FIG. 1 is a block diagram illustrating a semiconductor device including a backside power delivery network that is hybrid coupled either face-to-face or face-to-back. [Figure 17] FIG. 1 is a block diagram illustrating a semiconductor device including a front-to-back hybrid coupled backside power delivery network. [Figure 18] FIG. 1 is a block diagram illustrating an exemplary semiconductor device including a two-die stack with backside power delivery networks for both the top and bottom dies. [Figure 19] FIG. 1 is a block diagram illustrating an exemplary semiconductor device including two-die stacking with a backside power delivery network for the bottom die. [Figure 20] FIG. 1 is a block diagram illustrating an exemplary semiconductor device including two-die stacking with a backside power supply network for the top die and a backside power supply for the bottom die, having an extremely thin body and bonded directly to the package. [Figure 21] FIG. 1 is a block diagram illustrating an exemplary semiconductor device including a three-die stacking with a backside power delivery network for the top die and middle die. [Figure 22]FIG. 1 is a block diagram illustrating an exemplary semiconductor device including a three-die stacking with a backside power delivery network for the middle die. [Figure 23] FIG. 1 is a block diagram illustrating an exemplary semiconductor device including a three-die stacking with a backside power supply for the middle die having an extremely thin body and directly bonded to the bottom die. [Figure 24] FIG. 1 is a block diagram illustrating an exemplary semiconductor device including a three-die stacking with backside power delivery networks for the top die, middle die, and bottom die. [Figure 25] FIG. 1 is a block diagram illustrating an exemplary semiconductor device including a three-die stacking with backside power delivery for both the middle and bottom dies with extremely thin bodies, and a backside power delivery network for the top die. DETAILED DESCRIPTION OF THE INVENTION

[0004] Throughout the drawings, like reference numerals and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] (Introduction - Splitting Die-Pair Devices) The present disclosure is generally directed to integrated circuits and / or semiconductor devices that implement die pair device partitioning. As described in further detail below, embodiments of the present disclosure provide a new approach to delivering a process node. This new approach involves pairing two sets of devices that are fabricated as separate process nodes but are connected by 3D hybrid junctions (e.g., either front-to-front or front-to-back). Either of these paired nodes is included as a pair, rather than the optimized set of devices required for the new process node. This approach allows an “advanced” version of the process pair to include (e.g., primarily or exclusively) logic transistors that are fabricated alone and are optimized solely to improve the performance and power efficiency of the logic, without the compromises necessary to support integrated circuit devices and / or feature sets (e.g., static random access memory (SRAM) and analog devices) that would compromise the performance of the logic transistors. In addition to SRAM and analog devices, less optimized logic devices can be realized (e.g., primarily or exclusively) in a "paired" technology node that is fabricated alone and then 3D bonded to the advanced node. The combination of the advanced node and the paired node in a 3D hybrid bond configuration can provide a much higher performance, more efficient (e.g., with respect to logic, which contributes most to the gain of the technology node), and fully functional (e.g., SRAM and analog) technology node for SoC design.

[0006] Benefits from the above results can include avoiding manufacturing compromises required to balance process optimization windows that deliver a complete suite of analog, SRAM, and logic devices for an advanced technology node. The advanced node can focus (e.g., primarily or exclusively) on optimizing logic devices, which contribute most to performance and performance per watt. Additionally, node pair combinations can provide higher density, higher performance, and more power-efficient technologies than generic technology nodes with all devices in a single FEOL.

[0007] Features from any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from a reading of the following detailed description in conjunction with the accompanying drawings and claims.

[0008] In one example, an integrated circuit includes a circuit die having a metal stack and including most of the logic transistors of the integrated circuit, one or more additional circuit dies having one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die, and most of the static random access memory and analog devices of the integrated circuit.

[0009] Another example may be the exemplary integrated circuit described above, where the circuit die is constructed according to a more advanced technology process compared to one or more paired nodes.

[0010] Another example may be any of the exemplary integrated circuits described above, where the logic transistors included in the circuit die are fabricated separately.

[0011] Another example may be any of the exemplary integrated circuits described above, where one or more additional circuit dies are fabricated separately before connecting them to the circuit die.

[0012] Another example may be any of the exemplary integrated circuits described above, where at least one of the one or more additional metal stacks is connected to the metal stack surface-to-surface.

[0013] Another example may be any of the exemplary integrated circuits described above, where at least one of the one or more additional metal stacks is connected to the metal stack front-to-back.

[0014] Another example may be any of the exemplary integrated circuits described above, where at least one of one or more additional metal stacks is connected to the metal stack by at least one of a hybrid bond, a through silicon via, a fine pitch microbump, or a direct bond.

[0015] In one example, a semiconductor device includes a circuit die having a metal stack and including most of the logic transistors of the integrated circuit, one or more additional circuit dies having one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die, most of the static random access memory and analog devices of the integrated circuit, and an additional die connected to the one or more additional circuit dies.

[0016] Another example may be the exemplary semiconductor device described above, where the circuit die is constructed according to a more advanced technology process compared to one or more additional circuit dies.

[0017] Another example may be any of the exemplary semiconductor devices described above, where the logic transistors included in the circuit die are fabricated separately.

[0018] Another example may be any of the exemplary semiconductor devices described above, where at least one of the one or more additional metal stacks is connected surface-to-surface to the metal stack.

[0019] Another example may be any of the exemplary semiconductor devices described above, where at least one of the one or more additional metal stacks is connected to the metal stack front-to-back.

[0020] Another example may be any of the exemplary semiconductor devices described above, where at least one of one or more additional metal stacks is connected to the metal stack by at least one of a hybrid bond, a through-silicon via, a fine-pitch microbump, or a direct bond.

[0021] In one example, a method includes providing a circuit die having a metal stack and including a majority of logic transistors of an integrated circuit; providing one or more additional circuit dies having one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die; and a majority of static random access memory and analog devices of the integrated circuit; and connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die.

[0022] Another example may be the exemplary method described above, where a circuit die is constructed according to a more advanced technology process compared to one or more additional circuit dies.

[0023] Another example may be any of the exemplary methods described above, further including separately fabricating logic transistors included in the circuit die.

[0024] Another example may be any of the exemplary methods described above, further including fabricating one or more additional circuit dies separately before connecting to the circuit die.

[0025] Another example may be any of the exemplary methods described above, wherein connecting at least one of the one or more additional metal stacks to a metal stack of the circuit die includes connecting at least one of the one or more additional metal stacks to the metal stack surface-to-surface.

[0026] Another example may be any of the exemplary methods described above, wherein connecting at least one of the one or more additional metal stacks to a metal stack of the circuit die includes connecting at least one of the one or more additional metal stacks to the metal stack front-to-back.

[0027] Another example may be any of the exemplary methods described above, wherein connecting at least one of the one or more additional metal stacks to a metal stack of the circuit die includes connecting at least one of the one or more additional metal stacks to the metal stack by at least one of a hybrid bond, a through-silicon via, a fine-pitch microbump, or a direct bond.

[0028] A detailed description of an exemplary method for die pair splitting is provided below with reference to Figure 1A. A detailed description of a corresponding integrated circuit is also provided with reference to Figures 2-4, 7, and 8. Additionally, a detailed description of exemplary wafer-on-wafer and chip-on-wafer processes is provided with reference to Figures 5 and 6. Furthermore, a detailed description of an exemplary semiconductor device is provided with reference to Figures 9-25.

[0029] 1A illustrates an exemplary method 100A for splitting a die pair device. The steps illustrated in FIG. 1A may be performed by any suitable computer-executable code and / or computer system. In one example, each of the steps illustrated in FIG. 1A may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in further detail below.

[0030] 1A, step 102A can include providing a circuit die, for example, step 102A can include providing a circuit die having a metal stack and including most of the logic transistors of the integrated circuit.

[0031] The term "circuit die," as used herein, can generally refer to a small block of semiconductor material on which a given functional circuit is fabricated. For example, without limitation, integrated circuits can be produced in large quantities on a single wafer of electronic-grade silicon (EGS) or other semiconductors (e.g., GaAs) through processes such as photolithography. The wafer is cut (e.g., diced) into many pieces, each containing a copy of one circuit. Each of these pieces can be referred to as a die. Three commonly used plural forms are dice, dies, and die. Most die are packaged in various forms to simplify handling and integration onto printed circuit boards.

[0032] As used herein, the term "metal stack" may generally refer to one or more metal layers provided in or on a circuit die. For example, without limitation, a metal stack may be configured as a back end of line (BEOL), a redistribution layer, a wire, or any other configuration that communicatively couples transistors and / or other devices in a circuit die to each other and / or to transistors and / or other devices in another circuit die.

[0033] As used herein, the term "logic transistor" may generally refer to a circuit element within a circuit die that is configured to perform logical operations. For example, without limitation, a logic transistor may correspond to a logic gate (e.g., an AND gate, a NAND gate, an OR gate, etc.), a junction transistor, or any other type of transistor. In this context, a transistor may correspond to a small semiconductor that regulates or controls the flow of current or voltage, in addition to amplifying and generating these electrical signals and acting as a switch / gate for them. Typically, a transistor consists of three layers or terminals of semiconductor material, each of which is capable of carrying current.

[0034] As used herein, the term "integrated circuit" may generally refer to a set of electronic circuits. For example, without limitation, an integrated circuit may be configured as a chip, microchip, and / or microelectronic circuit of communicatively coupled circuit elements within one or more semiconductor wafers. In this context, exemplary circuit elements may correspond to resistors, capacitors, diodes, transistors, etc. Exemplary circuit elements may also be one or more logic transistors, one or more analog devices, and / or one or more sets of functions (e.g., static random access memory, fuses, temperature sensors, etc.).

[0035] Step 102A can be performed in various manners. For example, the circuit die can correspond to an advanced node built according to an advanced technology process that facilitates improved logic functionality and performance. In other examples, providing a circuit die in step 102A can include independently fabricating logic transistors included in the circuit die. In some of these examples, fabricating logic transistors in step 102A can include independently configuring logic transistors included in the circuit die to improve logic performance and power efficiency while reducing compromises necessary to support at least one of one or more devices or one or more function sets that would compromise the performance of the logic transistors. In some examples, configuring the logic transistors in this manner can include omitting from the first circuit die certain integrated circuit components (e.g., devices, function sets, static random access memories, analog devices, temperature sensors, fuses, phase-locked loops, etc.). In some of these examples, configuring the logic transistors in this manner can include providing one or more distribution paths within the circuit die for one or more such omitted components. Additional details regarding particular wafer-on-wafer and chip-on-wafer process options for providing the circuit die in step 102A are described below with reference to Figures 5 and 6. Additional details regarding particular configuration options for providing the circuit die in step 102A are described below with reference to Figures 3, 4, 7, and 8.

[0036] Step 104A may include providing an additional circuit die. For example, Step 102A may include providing one or more additional circuit dies having one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die, and most of the static random access memory and analog devices of the integrated circuit.

[0037] Step 104A can be performed in various manners. For example, the one or more additional circuit dies provided in step 104A can correspond to one or more pair nodes of the circuit die provided in step 102A. In some of these examples, as described above, the circuit die provided in step 102A can be constructed according to a more advanced technology process compared to the one or more additional circuit dies. The more advanced technology process can enable smaller transistors and other circuit elements implemented within the circuit die, thus facilitating improved logic functionality and performance compared to the less advanced (e.g., older, lower-cost) technology process on which the additional circuit dies are constructed. In another example, the one or more additional circuit dies can include other components (e.g., one or more devices and / or one or more function sets) that, if included in the circuit die, would compromise the performance of the logic transistors. In some examples, step 104A can include fabricating the one or more additional circuit dies separately before connecting them to the circuit die. Additional details regarding specific wafer-on-wafer and chip-on-wafer process options for providing the additional circuit dies in step 104A are described below with reference to FIGS. 5 and 6. Additional details regarding specific configuration options for providing one or more additional circuit dies in step 104A are described below with reference to FIGS.

[0038] As used herein, the term "component" may generally refer to one or more circuit elements. For example, without limitation, a component may correspond to one or more analog devices and / or one or more feature sets. In this context, an analog device may refer to a resistor, a capacitor, a diode, a fuse, etc., and a feature set may refer to a static random access memory, a temperature sensor, etc. In this context, a circuit die may be referred to herein as an "advanced node," and one or more additional dies may be referred to herein as a "paired node," where circuit elements that would compromise the performance of logic transistors are moved to increase the performance of the logic transistors in the advanced node while reducing cost.

[0039] Step 106A can include connecting the metal stacks. For example, step 106A can include connecting at least one of the one or more additional metal stacks to a metal stack of the circuit die.

[0040] As used herein, the term "connect" may generally refer to a physical and / or communicative bond. For example, without limitation, the connection may be performed using bumps, microbumps, vias, through silicon vias (TSVs), nano through silicon vias (nTSVs), direct bonding, hybrid bonding, etc. In this context, direct bonding (e.g., silicon fusion bonding) may include bonding of semiconductor wafers without any intervening layers (e.g., oxide layers). Direct bonding may include pre-treating the wafers (e.g., smoothing and / or polishing the surfaces (e.g., silicon, metal, etc.)), pre-bonding at room temperature (e.g., placing the polished surfaces in contact with each other), and annealing at an elevated temperature to form a chemical bond. Metal layers may be directly bonded to each other, for example, by applying heat and / or pressure.

[0041] Step 106A can be performed in various manners. For example, the additional metal stack can be connected to the metal stack surface-to-surface and / or surface-to-backside. Additionally, step 106A can include connecting at least one of the one or more additional metal stacks to the metal stack by hybrid bonding, through-silicon vias, fine-pitch microbumps, and / or direct bonding. Additional details regarding specific wafer-on-wafer and chip-on-wafer process options for connecting the metal stacks in step 106A are described below with reference to FIGS. 5 and 6. Additional details regarding specific surface-to-surface and / or surface-to-backside options for connecting the metal stacks in step 106A (e.g., using hybrid bonding, vias, through-silicon vias, direct bonding, etc.) are described below with reference to FIGS. 9-25.

[0042] (Introduction - Temperature Sensor in Die Pair Topology) The present disclosure is generally directed to integrated circuits and / or semiconductor devices that implement a die pair topology in which the base die temperature can reasonably track the temperature of a top die that includes a high-power computing engine. Thus, through 3D thermal modeling using commercially available electronic design automation (EDA) tools, the location of a corresponding hot spot on the base die can be identified, and a thermal sensor can be placed within the base die in planar proximity to the hot spot on the top die.

[0043] Benefits derived from the above results include accurately tracking peak temperatures on the top die without placing a sensor on the top die, allowing for little or no design margin with respect to temperature measurements. Thus, by judiciously placing thermal sensors on the base die relative to the top die in a die pair topology, the top die can deliver the highest operating frequency and performance it can offer without the adverse effects seen in monolithic designs.

[0044] Features from any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from a reading of the following detailed description in conjunction with the accompanying drawings and claims.

[0045] In one example, an integrated circuit includes a first circuit die having a first metal stack, a second circuit die having a second metal stack connected to the first metal stack of the first circuit die, and a temperature sensor disposed in a transistor layer of the second circuit die planarly proximate to at least one hot spot located in an additional transistor layer of the first circuit die.

[0046] Another example may be the exemplary integrated circuit described above, where the first circuit die includes logic transistors that are fabricated independently.

[0047] Another example may be any of the exemplary integrated circuits described above, where the second circuit die corresponds to a paired node and the first circuit die corresponds to an advanced node constructed according to a more advanced technology process compared to the paired node.

[0048] Another example may be any of the exemplary integrated circuits described above, where the majority of the static random access memory and analog devices of the integrated circuit are implemented within paired nodes.

[0049] Another example may be any of the exemplary integrated circuits described above, where the majority of all logic transistors of the integrated circuit are implemented in the advanced node.

[0050] Another example may be any of the exemplary integrated circuits described above, where a second circuit die is positioned below the first circuit die within a semiconductor device package that includes the first circuit die and the second circuit die.

[0051] Another example may be any of the exemplary integrated circuits described above, where the second metal stack is connected to the first metal stack at least one of surface-to-surface or surface-to-back.

[0052] Another example may be any of the exemplary integrated circuits described above, where the second metal stack is connected to the first metal stack by at least one of a hybrid bond, a through silicon via, a fine pitch microbump, or a direct bond.

[0053] In one example, a semiconductor device includes an integrated circuit including a first circuit die having a first metal stack and a second circuit die having a second metal stack connected to the first metal stack of the first circuit die, a temperature sensor disposed in a transistor layer of the second circuit die planarly proximate to at least one hot spot located in the additional transistor layer of the first circuit die, and an additional die connected to the second circuit die.

[0054] Another example may be the exemplary semiconductor device described above, where the first circuit die includes logic transistors that are fabricated independently.

[0055] Another example may be any of the exemplary semiconductor devices described above, where the second circuit die corresponds to a paired node and the first circuit die corresponds to an advanced node built according to a more advanced technology process compared to the paired node, and where a majority of all logic transistors of the integrated circuit are realized within the advanced node.

[0056] Another example may be any of the exemplary semiconductor devices described above, where the majority of the integrated circuit static random access memory and analog devices are realized within paired nodes.

[0057] Another example may be any of the exemplary semiconductor devices described above, where a second circuit die is positioned below the first circuit die within a semiconductor device package that includes the first circuit die and the second circuit die.

[0058] In one example, a method includes providing a first circuit die having a first metal stack, positioning a second circuit die having a second metal stack in a manner that positions a temperature sensor in a transistor layer of the second circuit die planarly proximate to at least one hot spot located in an additional transistor layer of the first circuit die, and connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die.

[0059] Another example may be the exemplary method described above, where the first circuit die includes solely fabricating the logic transistors of the first circuit die.

[0060] Another example may be any of the exemplary methods described above, where the second circuit die corresponds to a paired node and the first circuit die corresponds to an advanced node constructed according to a more advanced technology process compared to the paired node.

[0061] Another example may be any of the exemplary methods described above, where the majority of the static random access memory and analog devices of an integrated circuit including an advanced node and a paired node are implemented within the paired node.

[0062] Another example may be any of the exemplary methods described above, where a second circuit die is positioned below a first circuit die within a semiconductor device package that includes the first circuit die and the second circuit die.

[0063] Another example may be any of the exemplary methods described above, where the second metal stack is connected to the first metal stack at least one of surface-to-surface or surface-to-back.

[0064] Another example may be any of the exemplary methods described above, where the second metal stack is connected to the first metal stack by at least one of a hybrid bond, a through silicon via, a fine pitch microbump, or a direct bond.

[0065] A detailed description of an exemplary method for sensing temperature in a die pair topology is provided below with reference to Figure 1B. A detailed description of a corresponding integrated circuit is also provided with reference to Figures 2-4, 7, and 8. Additionally, a detailed description of an exemplary wafer-on-wafer and chip-on-wafer process is provided with reference to Figures 5 and 6. Furthermore, a detailed description of an exemplary semiconductor device is provided with reference to Figures 9-25.

[0066] 1B illustrates an exemplary method 100B for sensing temperature in a die pair topology. The steps illustrated in FIG. 1B may be performed by any suitable computer-executable code and / or computer system. In one example, each of the steps illustrated in FIG. 1B may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in further detail below.

[0067] 1B, step 102B may include providing a circuit die. For example, step 102B may include providing a first circuit die having a first metal stack.

[0068] As used herein, the term "circuit die" may generally refer to a small block of semiconductor material on which a given functional circuit is fabricated. For example, without limitation, integrated circuits may be produced in large quantities on a single wafer of electronic grade silicon (EGS) or other semiconductor (e.g., GaAs) through processes such as photolithography. The wafer is cut (e.g., diced) into many pieces, each containing a copy of one circuit. Each of these pieces may be referred to as a die. Three commonly used plural forms are dice, dies, and die. Most die are packaged in various forms to simplify handling and integration onto printed circuit boards.

[0069] As used herein, the term "metal stack" may generally refer to one or more metal layers provided in or on a circuit die. For example, without limitation, a metal stack may be configured as a back-end-of-line (BEOL), redistribution layer, wire, or any other structure that electrically and / or communicatively couples transistors, wires, and / or other devices in a circuit die to each other and / or to transistors, wires, and / or other devices in another circuit die.

[0070] Step 102B can be performed in various manners, for example, providing a first circuit die in step 104B can include independently fabricating logic transistors in the first circuit die to configure the logic transistors to improve logic performance and power efficiency while reducing compromises necessary to support at least one of one or more devices or one or more sets of functions that would compromise the performance of the logic transistors. In some examples, the first circuit die provided in step 102B can correspond to an advanced node built according to an advanced technology process that facilitates improved logic functionality and performance compared to less advanced technology processes. Additional details regarding substeps that can be performed in step 102B are provided below with reference to FIGS. 2-25.

[0071] Step 104B can include positioning an additional circuit die. For example, step 102B can include positioning a second circuit die having a second metal stack in a manner that positions a temperature sensor in a transistor layer of the second circuit die planarly proximate to at least one hot spot located in the additional transistor layer of the first circuit die.

[0072] As used herein, the term "temperature sensor" may generally refer to an electronic device that measures temperature. For example, without limitation, a temperature sensor may measure the temperature of its environment and convert input signals and / or data into electronic data to record, monitor, or report absolute temperature, relative temperature, and / or temperature changes. In this context, a semiconductor-based temperature sensor may be incorporated into an integrated circuit (IC). Some exemplary semiconductor-based temperature sensors may utilize two identical diodes with temperature-sensitive voltage-to-current characteristics that are used to monitor changes in temperature. Such sensors may be constructed from two metals that generate a voltage or resistance when a temperature change occurs by measuring the voltage across the diode terminals. For example, as the temperature increases, the voltage also increases.

[0073] As used herein, the term "hot spot" may generally refer to a location on a circuit die that exhibits heat. For example, without limitation, a hot spot may be the hottest portion of the circuit die during normal operation of the circuit die. Alternatively or additionally, a hot spot may correspond to a location of one or more circuit elements on the circuit die that are most vulnerable to compromising their normal operation in response to deviations from normal operating temperatures.

[0074] As used herein, the term "planar proximity" can generally refer to a location, such as above or below a hot spot. For example, planar proximity can refer to a location (e.g., of a temperature sensor) in one circuit die that is above or below a location (e.g., of a hot spot) in another circuit die. In this context, the circuit dies can be located in parallel planes and / or adjacent to each other in a 3D stack.

[0075] As used herein, the term "transistor layer" may generally refer to a wafer layer circuit die that includes circuit elements within the circuit die that are configured to perform logical operations. For example, without limitation, such circuit elements may correspond to logic transistors that can function as logic gates (e.g., AND gates, NAND gates, OR gates, etc.) and can be composed of junction transistors or any other type of transistor. In this context, transistors may correspond to small semiconductors that regulate or control the flow of current or voltage in addition to amplifying and generating these electrical signals and acting as switches / gates for them. Typically, a transistor consists of three layers or terminals of semiconductor material, each capable of carrying current.

[0076] Step 104B can be performed in various manners. For example, the second circuit die positioned in step 104B can correspond to a paired node, and the first circuit die provided in step 102B can correspond to an advanced node built according to a more advanced technology process that promotes improved logic functionality and performance compared to the paired node. In some of these embodiments, a significant portion of at least one of one or more devices or one or more sets of functions that would compromise the performance of logic transistors is implemented within the paired node. For example, the one or more devices or at least one of one or more sets of functions can include static random access memory and analog devices of an integrated circuit that includes the advanced node and the paired node. Additional details regarding substeps that can be performed in step 104B are provided below with reference to FIGS. 2-25.

[0077] Step 106B can include connecting the metal stacks. For example, step 106B can include connecting a first metal stack of a first circuit die to a second metal stack of a second circuit die.

[0078] As used herein, the term "connect" may generally refer to a physical and / or communicative bond. For example, without limitation, the connection may be performed using bumps, microbumps, vias, through-silicon vias (TSVs), nano-through-silicon vias (nTSVs), direct bonding, hybrid bonding, etc. In this context, direct bonding (e.g., silicon fusion bonding) may include bonding of semiconductor wafers without any intervening layers (e.g., oxide layers). Direct bonding may include pre-treating the wafers (e.g., smoothing and / or polishing the surfaces (e.g., silicon, metal, etc.)), pre-bonding at room temperature (e.g., placing the polished surfaces in contact with each other), and annealing at an elevated temperature to form a chemical bond. Metal layers may be directly bonded to each other, for example, by applying heat and / or pressure.

[0079] Step 106B can be performed in various manners. For example, the second metal stack can be connected to the first metal stack in step 106B in at least one of a front-to-front or a back-to-back manner. Alternatively or additionally, the second metal stack can be connected to the first metal stack in step 106B by at least one of a hybrid bond, a through-silicon via, a fine-pitch microbump, or a direct bond. Further substeps performed in step 106B can include connecting an additional die (e.g., an active interposer die) to the second circuit die (e.g., using a hybrid bond, a through-silicon via, a fine-pitch microbump, or a direct bond). Additional details regarding connections that can be performed in step 106B are provided below with reference to FIGS. 2-25.

[0080] The term "additional die" may generally refer to any die of semiconductor material having redistribution layers and / or circuitry of an integrated circuit. For example, without limitation, the additional die may be an active interposer die, a circuit die of an additional integrated circuit, another die of another process-pair node, etc.

[0081] As used herein, the term "active interposer die" may generally refer to the bottom circuit die in a stacked circuit die configuration. For example, without limitation, the active interposer die may be used to integrate a flexible distributed interconnect fabric for scalable chiplet traffic, energy-efficient 3D plugs using fine-pitch interconnects, power management functions for power supplies closer to the core, and memory-IO controllers and PHYs for off-chip communications.

[0082] (Introducing a back-end-of-line solution optimized to work with 3D stack configurations) The present disclosure is generally directed to integrated circuits and / or semiconductor devices having a back-end of line optimized to function in a 3D stack configuration. As described in further detail below, embodiments of the present disclosure provide an integrated circuit including a first circuit die having a first metal stack and a second circuit die having a second metal stack connected to the first metal stack of the first circuit die (e.g., by a surface-to-surface hybrid bond). As a result, metal connectivity can be shared between the first and second circuit dies, allowing redundant elements of the combined metal layer stack to be eliminated from the combined stack. This elimination of redundant metal layers reduces the total number of metal layers compared to front-to-backside or Si-metal-Si-metal stacking. An additional result of this configuration is that a final layer (e.g., passivation and bumps) to protect the die is not required, as the top of the metal stack is now embedded within the two dies and therefore not exposed as in a standard single die.

[0083] Benefits resulting from the above can include reduced cost, improved performance, reduced power requirements, and improved reliability. For example, cost can be reduced because fewer metal layers and less final passivation require less processing and therefore less cost. Additionally, fewer metal layers can improve performance because there is less metal resistive-capacitive (RC) delay. Fewer metal layers can also reduce power requirements because there is less metal capacitance. Furthermore, reliability can be improved because the overall physical structure of two connected dies and a shorter metal stack results in a die that is more resistant to cracks and physical stress.

[0084] Features of any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from a reading of the following detailed description in conjunction with the accompanying drawings and claims.

[0085] In one example, an integrated circuit includes an integrated circuit including a first circuit die having a first metal stack and a second circuit die having a second metal stack connected to the first metal stack of the first circuit die, wherein at least one metal layer of the second metal stack is utilized by the first circuit die and the second circuit die.

[0086] Another example may be the exemplary integrated circuit described above, where a first circuit die is constructed according to a more advanced technology process compared to a second circuit die.

[0087] Another example may be any of the exemplary integrated circuits described above, where at least one redundant metal layer is eliminated from the first metal stack.

[0088] Another example may be any of the exemplary integrated circuits described above, where at least one metal layer of the second metal stack is utilized exclusively by the first circuit die.

[0089] Another example may be any of the exemplary integrated circuits described above, where at least one metal layer of the second metal stack is utilized to transmit one or more signals back to the first transistor layer of the first circuit die from the first transistor layer without communicating the one or more signals to the second transistor layer of the second circuit die.

[0090] Another example may be any of the exemplary integrated circuits described above, where the second metal stack is connected surface-to-surface to the first metal stack.

[0091] Another example may be any of the exemplary integrated circuits previously described, where the second metal stack is connected front-to-back to the first metal stack.

[0092] Another example may be any of the exemplary integrated circuits described above, where the second metal stack is connected to the first metal stack by at least one of a hybrid bond, a through silicon via, a fine pitch microbump, or a direct bond.

[0093] In one example, a semiconductor device includes an integrated circuit including a first circuit die having a first metal stack and a second circuit die having a second metal stack connected to the first metal stack of the first circuit die, wherein at least one metal layer of the second metal stack is utilized by the first circuit die and the second circuit die.

[0094] Another example may be the exemplary semiconductor device described above, where a first circuit die is constructed according to a more advanced technology process compared to a second circuit die.

[0095] Another example may be any of the exemplary semiconductor devices described above, where at least one redundant metal layer is eliminated from the first metal stack.

[0096] Another example may be any of the exemplary semiconductor devices described above, where at least one metal layer of the second metal stack is utilized exclusively by the first circuit die.

[0097] Another example may be any of the exemplary semiconductor devices described above, where at least one metal layer of the second metal stack is utilized to transmit one or more signals back to the first transistor layer of the first circuit die from the first transistor layer without communicating the one or more signals to the second transistor layer of the second circuit die.

[0098] Another example may be any of the exemplary semiconductor devices described above, where the second metal stack is connected to the first metal stack at least one of surface-to-surface or surface-to-backside.

[0099] In one example, a method includes providing a first circuit die having a first metal stack, providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by the first circuit die and the second circuit die, and connecting the second metal stack to the first metal stack of the first circuit die.

[0100] Another example may be the exemplary method described above, where a first circuit die is constructed according to a more advanced technology process compared to a second circuit die.

[0101] Another example may be any of the exemplary methods described above, where at least one redundant metal layer is eliminated from the first metal stack.

[0102] Another example may be any of the exemplary methods described above, where at least one metal layer of the second metal stack is utilized exclusively by the first circuit die.

[0103] Another example may be any of the exemplary methods described above, where at least one metal layer of a second metal stack is utilized to transmit one or more signals back to a first transistor layer of a first circuit die from a first transistor layer of a first circuit die without communicating the one or more signals to a second transistor layer of a second circuit die.

[0104] Another example may be any of the exemplary methods described above, where the second metal stack is connected to the first metal stack at least one of surface-to-surface or surface-to-back.

[0105] A detailed description of an exemplary method for achieving shared metal connectivity between 3D stacked circuit dies is provided below with reference to Figure 1C. A detailed description of a corresponding integrated circuit is also provided with reference to Figures 2-4, 7, and 8. Additionally, a detailed description of exemplary wafer-on-wafer and chip-on-wafer processes is provided with reference to Figures 5 and 6. Furthermore, a detailed description of an exemplary semiconductor device is provided with reference to Figures 9-25.

[0106] 1C illustrates an exemplary method 100C for achieving shared metal connectivity between 3D stacked circuit dies. The steps illustrated in FIG. 1C may be performed by any suitable computer-executable code and / or computer system. In one example, each of the steps illustrated in FIG. 1C may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in further detail below.

[0107] 1C, step 102C may include providing a circuit die. For example, step 102C may include providing a first circuit die having a first metal stack.

[0108] The term "circuit die," as used herein, may generally refer to a small block of semiconductor material on which a given functional circuit is fabricated. For example, without limitation, integrated circuits may be produced in large quantities on a single wafer of electronic grade silicon (EGS) or other semiconductor (e.g., GaAs) through processes such as photolithography. The wafer is cut (e.g., diced) into many pieces, each containing a copy of one circuit. Each of these pieces may be referred to as a die. Three commonly used plural forms are dice, die, and die. Most die are packaged in various forms to simplify handling and integration onto printed circuit boards.

[0109] As used herein, the term "metal stack" may generally refer to one or more metal layers provided in or on a circuit die. For example, without limitation, a metal stack may be configured as a back-end-of-line (BEOL), a redistribution layer, a wire, or any other structure that communicatively couples transistors and / or other devices in a circuit die to each other and / or to transistors and / or other devices in another circuit die.

[0110] Step 102C can be performed in various manners. For example, the first circuit die provided in step 102C can correspond to an advanced node built according to an advanced technology process that facilitates improved logic functionality and performance compared to less advanced technology processes. Additional details regarding substeps that can be performed in step 102C are provided below with reference to FIGS. 2-25.

[0111] Step 104C may include providing one or more additional circuit dies. For example, step 104C may include providing a second circuit die having a second metal stack, wherein shared metal connectivity between the first circuit die and the second circuit die is achieved in a manner that eliminates at least one metal layer of at least the first metal stack.

[0112] Step 104C can be performed in various manners. For example, the second circuit die provided in step 104C can correspond to a paired node, and the first circuit die can correspond to an advanced node built according to a more advanced technology process that facilitates improved logic functionality and performance compared to the paired node. Additionally or alternatively, at least one redundant metal layer can be eliminated from the first metal stack. In another example, at least one metal layer of the second metal stack can be utilized exclusively by the advanced node. In this context, at least one metal layer of the second metal stack can be utilized to transmit one or more signals from a first transistor layer of the advanced node back to the first transistor layer without communicating the one or more signals to a second transistor layer of the paired node. Alternatively or additionally, at least one metal layer of the second metal stack is utilized by both the advanced node and the paired node. Additional details regarding substeps that can be performed in step 104C are provided below with reference to FIGS. 2-25.

[0113] Step 106C can include connecting two or more metal stacks, for example, step 106C can include connecting a second metal stack to a first metal stack of a first circuit die.

[0114] As used herein, the term "connect" may generally refer to a physical and / or communicative coupling. For example, without limitation, the connection may be performed using bumps, microbumps, vias, through-silicon vias (TSVs), nano-through-silicon vias (nTSVs), direct bonding, hybrid bonding, etc. In this context, direct bonding (e.g., silicon fusion bonding) may include bonding of semiconductor wafers without any intervening layers (e.g., oxide layers). Direct bonding may include pre-treating the wafers (e.g., smoothing and / or polishing the surfaces (e.g., silicon, metal, etc.)), pre-bonding at room temperature (e.g., placing the polished surfaces in contact with each other), and annealing at an elevated temperature to form a chemical bond. Metal layers may be directly bonded to each other, for example, by applying heat and / or pressure.

[0115] Step 106C can be performed in various manners. For example, the second metal stack can be connected to the first metal stack in step 106C in at least one of a front-to-front or a back-to-back manner. Alternatively or additionally, the second metal stack can be connected to the first metal stack in step 106C by at least one of a hybrid bond, a through-silicon via, a fine-pitch microbump, or a direct bond. Additional details regarding the connections that can be performed in step 106C are provided below with reference to FIGS. 2-25.

[0116] (Introduction - Thermally Aware Stacking Topology) The present disclosure is generally directed to integrated circuits and / or semiconductor devices that implement a thermally-aware stacking topology. The standard approach to improving thermal issues for high-performance computing (HPC) dies in the industry is to manufacture larger dies, which distributes heat over a wider area and therefore reduces heat density. However, benefits in heat dissipation for the computing chip can be achieved by placing the computing chip (e.g., core computing die) farther away from the input / output (IO) die and closer to the package thermal interface material (TIM) and thermal solutions (e.g., heat sink). To achieve this configuration, a die-pair device partitioning approach can be used, which involves pairing two sets of devices fabricated as separate process nodes but connected with 3D hybrid bonding (e.g., surface-to-surface). Neither of these paired nodes is included as a pair, rather than the optimized set of devices required for the new process node. This approach allows an “advanced” version of the process pair to include (e.g., primarily or exclusively) logic transistors that are fabricated alone and optimized solely to improve the performance and power efficiency of the logic without the compromises necessary to support SRAM and analog devices. In addition to SRAM and analog devices, less optimized logic devices can also be realized (e.g., primarily or exclusively) within the “paired” technology node that is fabricated alone and then 3D bonded to the advanced node. Combining the advanced and paired nodes in a 3D hybrid bond configuration can provide a much higher-performing, more efficient (e.g., with respect to the logic that contributes most to the technology node gain), and fully functional (e.g., SRAM and analog) technology node for SoC design. By connecting the paired node to the IO die (e.g., an interposer), the advanced technology process node can be located away from the IO die.

[0117] Benefits derived from the above results can include reduced thermal constraints for HPCs. To stay within cost bounds, thermal platform solutions often fail to remove all heat within the package. In the worst case, this insufficiency can result in thermal runaway, which limits the product's supply voltage and therefore performance. The situation is exacerbated in 3D chiplet stacking approaches, where the bottom die is problematic from a heat dissipation perspective, especially if it is the primary heat source within the package. Locating this chip (i.e., the primary heat source) away from the die and above the IO stack provides a lower thermal resistance path to the hottest chip, thus ensuring cooling and mitigating the associated performance loss. Thus, the disclosed thermally-aware stacking topology can utilize more efficient vertical heat transfer (e.g., versus horizontal), which can keep the overall cost of the product lower compared to increasing the central processing unit (CPU) die area to manage heat density.

[0118] Features from any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from a reading of the following detailed description in conjunction with the accompanying drawings and claims.

[0119] In one example, an integrated circuit includes a first circuit die having a first metal stack, the first circuit die corresponding to a primary heat source of the integrated circuit; a second circuit die having a second metal stack connected to the first metal stack of the first circuit die; and one or more connection elements provided on the second circuit die, the one or more connection elements configured to connect the second circuit die to at least one of a package substrate or an additional die.

[0120] Another example may be the exemplary integrated circuit described above, where a first circuit die contains independently fabricated logic transistors and contains the majority of all logic transistors of the integrated circuit, and a second circuit die contains the majority of static random access memory and analog devices of the integrated circuit.

[0121] Another example may be any of the exemplary integrated circuits described above, where the second circuit die corresponds to a paired node and the first circuit die corresponds to an advanced node constructed according to a more advanced technology process compared to the paired node.

[0122] Another example may be any of the exemplary integrated circuits described above, including one or more routing layers in a second circuit die, where one or more connection elements are configured to connect to the additional die using microbumps.

[0123] Another example may be any of the exemplary integrated circuits described above, including one or more routing layers in a second circuit die, where one or more connection elements are configured to connect to the additional die using through-silicon vias.

[0124] Another example may be any of the exemplary integrated circuits described above, including one or more routing layers in a second circuit die, where one or more connection elements are configured to connect to additional dies using nano-through silicon vias.

[0125] Another example may be any of the exemplary integrated circuits described above, including one or more routing layers in a second circuit die, where one or more connection elements are configured to connect to the additional die using direct bonding.

[0126] Another example may be any of the exemplary integrated circuits described above, where the configuration of the second circuit die for connection is configured to position the first circuit die closer to the cooling solution of the semiconductor device that includes the integrated circuit than the second circuit die.

[0127] In one example, a semiconductor device includes an integrated circuit including a first circuit die connected to a second circuit die, the first circuit die corresponding to a primary heat source of the integrated circuit, an additional die, and one or more connection elements connecting the second circuit die to the additional die.

[0128] Another example may be the exemplary semiconductor device described above, further including a heat spreader positioned over the first circuit die.

[0129] Another example may be any of the exemplary semiconductor devices described above, further including a thermal interface material positioned between the first circuit die and the heat spreader.

[0130] Another example may be any of the exemplary semiconductor devices described above, where a first circuit die includes independently fabricated logic transistors and includes a majority of all logic transistors of the integrated circuit, and a second circuit die includes a majority of the static random access memory and analog devices of the integrated circuit, and the first circuit die is constructed according to a more advanced technology process compared to the second circuit die.

[0131] Another example may be any of the exemplary semiconductor devices described above, including one or more routing layers in a second circuit die, where one or more connection elements are connected to the additional die using microbumps.

[0132] Another example may be any of the exemplary semiconductor devices described above, including one or more routing layers in a second circuit die, where one or more connection elements are connected to the additional die using through-silicon vias.

[0133] Another example may be any of the exemplary semiconductor devices described above, including one or more routing layers in a second circuit die, with one or more connection elements connected to the additional die using nano-through silicon vias.

[0134] Another example may be any of the exemplary semiconductor devices described above, including one or more routing layers in a second circuit die, where one or more connection elements are connected to the additional die using direct bonding.

[0135] In one example, a method includes providing a first circuit die having a first metal stack, the first circuit die corresponding to a primary heat source of an integrated circuit including the first circuit die; providing a second circuit die of the integrated circuit, the second circuit die having a second metal stack and configured to connect to at least one of a package substrate or an additional die; and connecting the first metal stack to the second metal stack.

[0136] Another example may be the exemplary method described above, where a second circuit die has one or more routing layers therein that are configured to connect to additional dies using microbumps.

[0137] Another example may be any of the exemplary methods described above, where the second circuit die has one or more routing layers therein configured to connect to additional dies using through silicon vias.

[0138] Another example may be any of the exemplary methods described above, where the second circuit die has one or more routing layers therein that are configured to connect to additional die using direct bonding.

[0139] A detailed description of an exemplary method for circuit die stacking is provided below with reference to Figure 1D. A detailed description of a corresponding integrated circuit is also provided with reference to Figures 2-4, 7, and 8. Additionally, a detailed description of exemplary wafer-on-wafer and chip-on-wafer processes is provided with reference to Figures 5 and 6. Furthermore, a detailed description of an exemplary semiconductor device is provided with reference to Figures 9-25.

[0140] 1D illustrates an exemplary method 100D for circuit die stacking. The steps illustrated in FIG. 1D may be performed by any suitable computer-executable code and / or computer system. In one example, each of the steps illustrated in FIG. 1D may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in further detail below.

[0141] 1D, step 102D can include providing a circuit die. For example, step 102D can include providing a first circuit die having a first metal stack, the first circuit die corresponding to a primary heat source of an integrated circuit including the first circuit die.

[0142] The term "circuit die," as used herein, may generally refer to a small block of semiconductor material on which a given functional circuit is fabricated. For example, without limitation, integrated circuits may be produced in large quantities on a single wafer of electronic grade silicon (EGS) or other semiconductor (e.g., GaAs) through processes such as photolithography. The wafer is cut (e.g., diced) into many pieces, each containing a copy of one circuit. Each of these pieces may be referred to as a die. Three commonly used plural forms are dice, die, and die. Most die are packaged in various forms to simplify handling and integration onto printed circuit boards.

[0143] As used herein, the term "metal stack" may generally refer to one or more metal layers provided in or on a circuit die. For example, without limitation, a metal stack may be configured as a back-end-of-line (BEOL), a redistribution layer, a wire, or any other structure that communicatively couples transistors and / or other devices in a circuit die to each other and / or to transistors and / or other devices in another circuit die.

[0144] Step 102D can be performed in various manners. For example, the first circuit die provided in step 102D can include logic transistors fabricated independently and configured to improve logic performance and power efficiency while reducing compromises necessary to support at least one of one or more devices or one or more sets of functions that would compromise the performance of the logic transistors. Alternatively or additionally, the first circuit die provided in step 102D can correspond to an advanced node built according to an advanced technology process that facilitates improved logic functionality and performance compared to less advanced technology processes. Additional details regarding substeps that can be performed in step 102D are provided below with reference to FIGS. 2-25.

[0145] Step 104D may include providing one or more additional circuit dies. For example, step 104D may include providing a second circuit die of the integrated circuit, the second circuit die having a second metal stack and configured to connect to at least one of a package substrate or another additional die.

[0146] As used herein, the term "package substrate" may generally refer to a structure that transmits electrical signals between a semiconductor and a main board of a computing device. For example, but not limited to, a package substrate may include a redistribution layer that communicatively couples to connection elements of a semiconductor device. The package substrate may also be implemented to protect the semiconductor from external stresses.

[0147] The term "additional die" may generally refer to any die of semiconductor material having redistribution layers and / or circuitry of an integrated circuit. For example, without limitation, the additional die may be an active interposer die, a circuit die of an additional integrated circuit, another die of another process-pair node, etc.

[0148] As used herein, the term "active interposer die" may generally refer to the bottom circuit die in a stacked circuit die configuration. For example, without limitation, the active interposer die may be used to integrate a flexible distributed interconnect fabric for scalable chiplet traffic, energy-efficient 3D plugs using fine-pitch interconnects, power management functions for power supplies closer to the core, and memory-IO controllers and PHYs for off-chip communications.

[0149] Step 104D can be performed in various manners. For example, the second circuit die provided in step 104D can correspond to a paired node, and the first circuit die provided in step 102D can correspond to an advanced node built according to a more advanced technology process that facilitates improved logic functionality and performance compared to the paired node. In another example, the second circuit die provided in step 104D can have one or more routing layers therein configured to connect to additional die using microbumps. Alternatively or additionally, the second circuit die provided in step 104D can have one or more routing layers therein configured to connect to additional die using through-silicon vias (e.g., hybrid bonds). Alternatively or additionally, the second circuit die provided in step 104D can have one or more routing layers therein configured to connect to additional die using nano-through-silicon vias. Alternatively or additionally, the second circuit die provided in step 104D can have one or more routing layers therein configured to connect to additional die using direct bonding. Additional details regarding the substeps that may be performed in step 104D are provided below with reference to FIGS.

[0150] Step 106D can include connecting two or more metal stacks, for example, step 106D can include connecting a first metal stack to a second metal stack.

[0151] As used herein, the term "connect" may generally refer to a physical and / or communicative bond. For example, without limitation, the connection may be performed using bumps, microbumps, vias, through-silicon vias (TSVs), nano-through-silicon vias (nTSVs), direct bonding, hybrid bonding, etc. In this context, direct bonding (e.g., silicon fusion bonding) may include bonding of semiconductor wafers without any intervening layers (e.g., oxide layers). Direct bonding may include pre-treating the wafers (e.g., smoothing and / or polishing the surfaces (e.g., silicon, metal, etc.)), pre-bonding at room temperature (e.g., placing the polished surfaces in contact with each other), and annealing at an elevated temperature to form a chemical bond. Metal layers may be directly bonded to each other, for example, by applying heat and / or pressure.

[0152] Step 106D can be performed in various manners. For example, step 106D can include connecting the first metal stack to the second metal stack surface-to-surface or surface-to-back. Alternatively or additionally, step 106D can include connecting the first metal stack to the second metal stack using hybrid bonds, bumps, microbumps, vias, through-silicon vias, nano-through-silicon vias, and / or direct bonding. Additional details regarding substeps that can be performed in step 104D are provided below with reference to FIGS. 2-25.

[0153] (Introducing - rear power) The present disclosure is generally directed to integrated circuits and / or semiconductor devices that implement backside power. For example, in a 3D die stacking configuration, a node with backside power technology can be utilized as the bottom die. By utilizing this node as the bottom die, power is delivered directly to both the bottom die circuitry and the top die circuitry through the backside of the bottom die wafer.

[0154] Benefits from the above configuration may result from avoiding the use of TSV arrays to deliver power to stacked products. Thus, the increased area and potential IR drop penalty resulting from the use of through-silicon-via (TSV) arrays (e.g., power curtains) through bottom die circuitry (e.g., transistor layers) may be avoided. Avoiding such TSV arrays that require keep-out zones (KOZ) (e.g., power curtains) may save product cost and / or improve performance of the integrated circuit and / or semiconductor device.

[0155] Features from any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from a reading of the following detailed description in conjunction with the accompanying drawings and claims.

[0156] In one example, an integrated circuit includes a first circuit die having a first metal stack, a second circuit die having a second metal stack connected to the first metal stack of the first circuit die, and a backside power delivery network in a passivation layer of at least one of the first circuit die or the second circuit die.

[0157] Another example may be the exemplary integrated circuit described above, where the backside power delivery network provides power directly to at least one transistor layer of the first circuit die or the second circuit die by at least one of backside vias or nano-through silicon vias.

[0158] Another example may be any of the exemplary integrated circuits described above, where the backside power delivery network is located within the passivation layer of the first circuit die.

[0159] Another example may be any of the exemplary integrated circuits described above, further including an additional backside power delivery network in an additional passivation layer of the second circuit die.

[0160] Another example may be any of the exemplary integrated circuits described above, where an additional backside power delivery network provides power directly to the transistor layer of the second circuit die.

[0161] Another example may be any of the exemplary integrated circuits described above, where an additional backside power delivery network provides power directly to the transistor layer of the second circuit die by at least one of backside vias or nano-through silicon vias.

[0162] Another example may be any of the exemplary integrated circuits described above, where the transistor layer of the second circuit die is configured to receive power directly from the additional die by directly bonding the silicon body of the second circuit die to the additional die.

[0163] In one example, a semiconductor device includes an integrated circuit including: a first circuit die having a first metal stack, the first circuit die corresponding to a primary heat source of the integrated circuit; a second circuit die having a second metal stack connected to the first metal stack of the first circuit die; an additional die connected to the second circuit die; and a backside power delivery network within a passivation layer of at least one of the first circuit die, the second circuit die, or the active interposer die.

[0164] Another example may be the exemplary semiconductor device described above, where the backside power delivery network is located within the passivation layer of the first circuit die.

[0165] Another example may be any of the exemplary semiconductor devices described above, further including an additional backside power delivery network within an additional passivation layer of the second circuit die.

[0166] Another example may be any of the exemplary semiconductor devices described above, further including an additional backside power delivery network in an additional passivation layer of an additional die.

[0167] Another example may be any of the exemplary semiconductor devices described above, where the transistor layer of the second circuit die is configured to receive power directly from the additional die by directly bonding the silicon body of the second circuit die to the additional die.

[0168] Another example may be any of the exemplary semiconductor devices described above, where the transistor layer of the additional die is configured to receive power directly from the package of the semiconductor device by directly bonding the silicon body of the additional die to the package of the semiconductor device.

[0169] In one example, a method includes providing a first circuit die having a first metal stack; and connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located within a passivation layer of at least one of the first circuit die or the second circuit die.

[0170] Another example may be the exemplary method described above, where the backside power delivery network is located within the passivation layer of the first circuit die.

[0171] Another example may be any of the exemplary methods previously described, further including an additional backside power delivery network in an additional passivation layer of the second circuit die.

[0172] Another example may be any of the exemplary methods described above, further including connecting an additional die to the second circuit die.

[0173] Another example may be any of the exemplary methods described above, where an additional backside power delivery network is located in an additional passivation layer of an additional die.

[0174] Another example may be any of the exemplary methods described above, where the transistor layer of the second circuit die is configured to receive power directly from the additional die by directly bonding the silicon body of the second circuit die to the additional die.

[0175] Another example may be any of the exemplary methods described above, where the transistor layer of the additional die is configured to receive power directly from the package of the semiconductor device by directly bonding the silicon body of the additional die to the package of the semiconductor device.

[0176] A detailed description of an exemplary method for providing backside power is provided below with reference to Figure 1E. A detailed description of a corresponding integrated circuit is also provided with reference to Figures 2-4, 7, and 8. Additionally, a detailed description of exemplary wafer-on-wafer and chip-on-wafer processes is provided with reference to Figures 5 and 6. Furthermore, a detailed description of an exemplary semiconductor device is provided with reference to Figures 9-25.

[0177]

[0023] Figure 1E illustrates an exemplary method 100E for providing backside power. The steps illustrated in Figure 1E may be performed by any suitable computer-executable code and / or computer system. In one example, each of the steps illustrated in Figure 1E may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in further detail below.

[0178] 1E, step 102E may include providing a circuit die. For example, step 102E may include providing a first circuit die having a first metal stack.

[0179] As used herein, the term "circuit die" may generally refer to a small block of semiconductor material on which a given functional circuit is fabricated. For example, without limitation, integrated circuits may be produced in large quantities on a single wafer of electronic grade silicon (EGS) or other semiconductor (e.g., GaAs) through processes such as photolithography. The wafer is cut (e.g., diced) into many pieces, each containing a copy of one circuit. Each of these pieces may be referred to as a die. Three commonly used plural forms are dice, dies, and die. Most die are packaged in various forms to simplify handling and integration onto printed circuit boards.

[0180] As used herein, the term "metal stack" may generally refer to one or more metal layers provided in or on a circuit die. For example, without limitation, a metal stack may be configured as a back-end-of-line (BEOL), a redistribution layer, a wire, or any other structure that communicatively couples transistors and / or other devices in a circuit die to each other and / or to transistors and / or other devices in another circuit die.

[0181] Step 102E can be performed in various manners. For example, the backside power delivery network can be located within a passivation layer of the first circuit die. In some of these examples, the backside power delivery network can provide power directly to the transistor layer of the first circuit die through at least one of backside vias or nano-through silicon vias. Additional details of substeps that can be performed in step 102E are described below with reference to FIGS. 11-25.

[0182] As used herein, the term "backside via" may generally refer to a via that directly contacts a device from the backside of a die. For example, without limitation, a backside via may directly contact circuit elements in a transistor layer of a die without connecting to metal layers in and / or on the front side of the die.

[0183] As used herein, the term "nano-through-silicon via" may generally refer to a via formed through the silicon body of a die (e.g., having dimensions less than 1 micrometer) and connecting to a lower-level metal layer on the front side of the die. For example, without limitation, a nano-through-silicon via may connect to a front-side metal layer of the die without requiring a keep-out zone from the devices (e.g., circuit elements) of the die.

[0184] Step 104E can include connecting at least one other circuit die to the circuit die. For example, step 104E can include connecting a second metal stack of a second circuit die to a first metal stack of a first circuit die, wherein a backside power delivery network is located within a passivation layer of at least one of the first circuit die or the second circuit die.

[0185] As used herein, the term "backside power delivery network" may generally refer to power routing elements located on the backside of a circuit die. For example, the backside power delivery network may deliver power to the circuit elements of the die from the backside without the use of a power curtain that requires a keepout zone to deliver power from the circuit elements to the frontside landing metal. Rather, the backside power delivery network may deliver power to the circuit elements of the die and the frontside metal layer of the die through backside vias and / or nano-through-silicon vias without the need for a power curtain or keepout zone.

[0186] As used herein, the term "passivation layer" may generally refer to one or more layers formed to protect the internal semiconductor device after metallization is completed. For example, but not limited to, a passivation layer may be formed by the deposition of an oxide layer and a nitride layer.

[0187] Step 104E can be performed in various manners. For example, the backside power delivery network can be located within a passivation layer of the second circuit die. In some of these examples, the backside power delivery network can provide power directly to the transistor layer of the second circuit die through at least one of backside vias or nano-through silicon vias. In other examples, the backside power delivery network can be located within a passivation layer of the first circuit die, and the additional backside power delivery network can be located within an additional passivation layer of the second circuit die. In some of these examples, the backside power delivery network can provide power directly to the transistor layers of the first and second circuit die through at least one of backside vias or nano-through silicon vias. Alternatively or additionally, step 104E can include connecting an additional die (e.g., an active interposer die) to the second circuit die. In some of these examples, one or more backside power delivery networks can be located in the passivation layer of the first circuit die and / or the second circuit die, and additional backside power delivery networks can be located in additional passivation layers of additional dies. In other examples, the transistor layer of the second circuit die can be configured to receive power directly from the additional die by directly bonding a silicon body (e.g., an ultra-thin silicon body) of the second circuit die to the additional die. Additionally or alternatively, the transistor layer of the additional die can be configured to receive power directly from the semiconductor device package by directly bonding a silicon body (e.g., an ultra-thin silicon body) of the additional die to the semiconductor device package. Additional details of substeps that can be performed in step 104E are described below with reference to FIGS. 11-25.

[0188] The term "additional die" may generally refer to any die of semiconductor material having redistribution layers and / or circuitry of an integrated circuit. For example, without limitation, the additional die may be an active interposer die, a circuit die of an additional integrated circuit, another die of another process-pair node, etc.

[0189] As used herein, the term "active interposer die" may generally refer to the bottom circuit die in a stacked circuit die configuration. For example, without limitation, the active interposer die may be used to integrate a flexible distributed interconnect fabric for scalable chiplet traffic, energy-efficient 3D plugs using fine-pitch interconnects, power management functions for power supplies closer to the core, and memory-IO controllers and PHYs for off-chip communications.

[0190] (Introduction - Advanced Process in Unfused Process Pairs) The present disclosure is generally directed to advanced processing in fuse-less process pairs. For example, by placing one or more fuses in one or more circuit dies (e.g., paired dies) having at least primarily static random access memory and analog devices implemented therein, and using the advanced process die as a base wafer in a chip-on-wafer process, the advanced process die can be optimized to improve logic performance and power efficiency without making the compromises necessary to support other non-logic devices such as static random access memory, analog devices, and one or more fuses. A die-to-die fuse value distribution path can be provided in the advanced process die, allowing die identification information for the advanced process die to be obtained from coordinates within the wafer rather than through programmed fuses. After the addition of an interface metal layer and bumping, the assembly can be flipped and diced so that the advanced process die becomes the top die.

[0191] Advantages resulting from the above results may include the ability to perform die identification for the advanced process die without including fuses within the advanced process die. By placing fuses exclusively within the paired die connected to the advanced process die, the advanced process die may be optimized for data logic by focusing primarily (e.g., exclusively) on logic devices, improving logic device performance.

[0192] Features from any of the embodiments described herein may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood from a reading of the following detailed description in conjunction with the accompanying drawings and claims.

[0193] In one example, an integrated circuit includes a circuit die, one or more additional circuit dies connected to the circuit die, and one or more fuses positioned within the one or more additional circuit dies, wherein the one or more fuses identify the circuit die.

[0194] Another example may be the exemplary integrated circuit described above, where one or more fuses have a fuse value distribution path provided on the circuit die.

[0195] Another example may be any of the exemplary integrated circuits described above, where the circuit die includes logic transistors that are fabricated independently, and the circuit die is constructed according to a more advanced technology process compared to one or more paired nodes.

[0196] Another example may be any of the exemplary integrated circuits described above, where a circuit die contains most of all logic transistors of the integrated circuit and one or more additional circuit dies contain most of all static random access memory and analog devices of the integrated circuit.

[0197] Another example may be any of the exemplary integrated circuits described above, where one or more additional circuit dies include most of all phase-locked loops that generate one or more clock signals useful for high-speed standalone testing of the integrated circuit.

[0198] Another example may be any of the exemplary integrated circuits described above, where the integrated circuit is constructed according to a wafer-on-wafer process using one or more additional circuit dies as a base wafer.

[0199] Another example may be any of the exemplary integrated circuits described above, where the integrated circuit is constructed according to a chip-on-wafer process using a circuit die as a base wafer.

[0200] In one example, a semiconductor device includes an integrated circuit that includes a circuit die, one or more additional circuit dies connected to the circuit die, and one or more fuses positioned within the one or more additional circuit dies, wherein the one or more fuses identify the circuit die and the additional die connected to the one or more additional circuit dies.

[0201] Another example may be the exemplary semiconductor device described above, where one or more fuses have a fuse value distribution path provided on the circuit die.

[0202] Another example may be any of the exemplary semiconductor devices described above, where the circuit die includes logic transistors that are fabricated independently, and the circuit die is constructed according to a more advanced technology process compared to one or more additional circuit dies.

[0203] Another example may be any of the exemplary semiconductor devices described above, where a circuit die contains most of all logic transistors of the integrated circuit and one or more additional circuit dies contain most of all static random access memory and analog devices of the integrated circuit.

[0204] Another example may be any of the exemplary semiconductor devices described above, where one or more additional circuit dies include most of all phase-locked loops that generate one or more clock signals useful for high-speed standalone testing of integrated circuits.

[0205] Another example may be any of the exemplary semiconductor devices described above, where an integrated circuit is constructed according to a wafer-on-wafer process using one or more additional circuit dies as a base wafer.

[0206] Another example may be any of the exemplary semiconductor devices described above, where an integrated circuit is constructed according to a chip-on-wafer process using a circuit die as a base wafer.

[0207] In one example, a method includes providing a circuit die; providing one or more additional circuit dies having one or more fuses positioned therein, the one or more fuses identifying the circuit die; and connecting the one or more additional circuit dies to the circuit die.

[0208] Another example may be the exemplary method described above, where one or more fuses have a fuse value distribution path provided on the circuit die.

[0209] Another example may be any of the exemplary methods described above, where a circuit die includes logic transistors that are fabricated independently, and the circuit die is constructed according to a more advanced technology process compared to one or more additional circuit dies.

[0210] Another example may be any of the exemplary methods described above, where a circuit die contains most of all logic transistors of an integrated circuit, and one or more additional circuit dies contain most of all static random access memory and analog devices of the integrated circuit.

[0211] Another example may be any of the exemplary methods described above, in which a circuit die and one or more additional circuit dies are constructed according to a wafer-on-wafer process using the one or more additional circuit dies as a base wafer.

[0212] Another example may be any of the exemplary methods described above, in which a circuit die and one or more additional circuit dies are constructed according to a chip-on-wafer process using the circuit die as a base wafer.

[0213] A detailed description of an exemplary method for advanced processing of fuse-less process pairs is provided below with reference to Figure 1F. A detailed description of a corresponding integrated circuit is also provided with reference to Figures 2-4, 7, and 8. Additionally, a detailed description of exemplary wafer-on-wafer and chip-on-wafer processes is provided with reference to Figures 5 and 6. Furthermore, a detailed description of an exemplary semiconductor device is provided with reference to Figures 9-25.

[0214]

[0023] Figure 1F illustrates an exemplary method 100F for advanced processing of fuse-less process pairs. The steps illustrated in Figure 1F may be performed by any suitable computer-executable code and / or computer system. In one example, each of the steps illustrated in Figure 1F may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in further detail below.

[0215] 1F, step 102F may include providing a die. For example, step 102F may include providing a circuit die.

[0216] As used herein, the term "circuit die" may generally refer to a small block of semiconductor material on which a given functional circuit is fabricated. For example, without limitation, integrated circuits may be produced in large quantities on a single wafer of electronic grade silicon (EGS) or other semiconductor (e.g., GaAs) through processes such as photolithography. The wafer is cut (e.g., diced) into many pieces, each containing a copy of one circuit. Each of these pieces may be referred to as a die. Three commonly used plural forms are dice, dies, and die. Most die are packaged in various forms to simplify handling and integration onto printed circuit boards.

[0217] Step 102F can be performed in various manners. For example, the circuit die provided in step 102F can include independently fabricated logic transistors. In some of these embodiments, the logic transistors can be configured to improve logic performance and power efficiency while reducing compromises necessary to support at least one of one or more devices or one or more sets of functions that would compromise the performance of the logic transistors. Alternatively or additionally, the first circuit die provided in step 102F can correspond to an advanced node built according to an advanced technology process that facilitates improved logic functionality and performance compared to less advanced technology processes. Additional details regarding substeps that can be performed in step 102F are provided below with reference to FIGS. 2-25.

[0218] Step 104F may include providing additional circuit dies. For example, step 104F may include providing one or more additional circuit dies having one or more fuses positioned therein, the one or more fuses identifying the circuit die.

[0219] The term "fuse," as used herein, may generally refer to a fuse element. For example, without limitation, a fuse may be a wire or strip of low-melting alloy that melts (e.g., blows) to interrupt a circuit when current exceeds a certain amperage. In this context, a circuit die may have a selectively blowable fuse that can be optically readable to perform die identification. The present disclosure relates to placing fuses that identify a circuit die on one or more other circuit dies in the same stack (e.g., 3D stack) as the circuit die.

[0220] Step 104F can be performed in various manners. For example, one or more fuses can have fuse value distribution paths provided on the circuit die. In some embodiments, fuses can include a bottom die that identifies the top die, or vice versa. Alternatively or additionally, fuses can be included on the edges of multiple circuit dies in the 3D stack that identify one or more other circuit dies in the 3D stack. Additionally, the one or more additional circuit dies provided in step 104F can correspond to one or more paired nodes, and the circuit die provided in step 102F can correspond to an advanced node built according to a more advanced technology process that promotes improved logic functionality and performance compared to the one or more paired nodes. Thus, the circuit die can include independently fabricated logic transistors, and the circuit die is built according to a more advanced technology process compared to the one or more additional circuit dies. Also, a significant portion of at least one of one or more devices or one or more sets of functions that would compromise the performance of the logic transistors can be implemented within the one or more paired nodes. In some of these examples, the one or more devices and / or one or more sets of functions may include static random access memory and analog devices of an integrated circuit that includes a circuit die and one or more additional circuit dies. Thus, the circuit die may include a majority of all logic transistors of the integrated circuit, and the one or more additional circuit dies may include a majority of all static random access memory and analog devices of the integrated circuit. Additional details regarding substeps that may be performed in step 104F are provided below with reference to Figures 2-25.

[0221] Step 106F may include connecting the die, for example, step 106F may include connecting one or more additional circuit dies to the circuit die.

[0222] As used herein, the term "connect" may generally refer to a physical and / or communicative coupling. For example, without limitation, the connection may be performed using bumps, microbumps, vias, through-silicon vias (TSVs), nano-through-silicon vias (nTSVs), direct bonding, hybrid bonding, etc. In this context, direct bonding (e.g., silicon fusion bonding) may include bonding of semiconductor wafers without any intervening layers (e.g., oxide layers). Direct bonding may include pre-treating the wafers (e.g., smoothing and / or polishing the surfaces (e.g., silicon, metal, etc.)), pre-bonding at room temperature (e.g., placing the polished surfaces in contact with each other), and annealing at an elevated temperature to form a chemical bond. Metal layers may be directly bonded to each other, for example, by applying heat and / or pressure.

[0223] Step 106F can be performed in various manners. For example, the metal stacks of one or more additional circuit die can be connected to the metal stack of the circuit die. In such examples, the metal stacks can be connected surface-to-surface and / or surface-to-backside. Additionally, the one or more additional metal stacks can be connected to the metal stack by hybrid bonding, through-silicon vias, fine-pitch microbumps, and / or direct bonding. In some embodiments, connecting the one or more additional circuit die to the circuit die can include building an integrated circuit according to a wafer-on-wafer process using the one or more additional circuit die as a base wafer. Alternatively, connecting the one or more additional circuit die to the circuit die can include building an integrated circuit according to a chip-on-wafer process using the circuit die as a base wafer. Additional details regarding substeps that can be performed in step 106F are provided below with reference to FIGS. 2-25.

[0224] Illustrative Embodiments FIG. 2 illustrates an exemplary integrated circuit 200 that may result from the performance of any or a combination of the methods 100A-100F of FIGS. 1A-1F. Future semiconductor products will require the integration of multiple die chiplets to form a final product. Two dies can be connected by their respective metal stacks (e.g., flipping one die over the other, like a sandwich). This connection can be performed using surface-to-surface stacking with hybrid junctions 210 or surface-to-backside stacking with hybrid junctions. This 3D hybrid junction 210 allows for fine-grained connections between two nodes, while each node is specialized to provide optimized logic (e.g., advanced node 212) or SRAM and analog devices (e.g., paired node 214). For example, a first circuit die 202 (e.g., an advanced technology process node 212) having a first metal stack 206 and a second circuit die 204 (e.g., a pair node 214, which may be an older technology process node) having a second metal stack 208 can be connected to the first metal stack 206 of the first circuit die 202 (e.g., by a surface-to-surface or surface-to-backside hybrid bond 210).

[0225] 3, an exemplary integrated circuit 300 can have the features described above with reference to the integrated circuit 200 of FIG. 2. For example, the integrated circuit 300 can include a first circuit die 202 (e.g., an advanced technology process node 212) having a first metal stack 206 and a second circuit die 204 (e.g., a paired node 214, which may be an older technology process node) having a second metal stack 208, connected to the first metal stack 206 of the first circuit die 202 (e.g., by a front-to-front or front-to-back hybrid bond 210). Additionally, optimizing the advanced node for logic devices can include moving some non-logic devices to the paired node 214. For example, electronic design automation (EDA) modeling can be used to predict the locations of hot spots 302 in a transistor layer of the advanced technology process node 212 (e.g., a core compute die (CCD)) and corresponding hot spots in the paired node 214. The temperature sensor 304 may be positioned in the transistor layer of the paired node 214 planarly proximate (e.g., directly below) the hot spot 302 in the transistor layer of the advanced technology process node 212. This placement may avoid spacing out the logic transistors in the advanced technology process node 212 without placing the temperature sensor 304 far from the hot spot. In an alternative embodiment, the advanced technology process node 212 may be located below the paired node 214, in which case the hot spot 302 may be located in the bottom die and the temperature sensor 304 may be located in the top die (e.g., directly above the hot spot 302). However, as will be described in more detail later herein with reference to FIG. 7 , having the advanced technology process node 212 above the paired node 214 may provide heat dissipation benefits for the advanced technology process node 212.

[0226] 4, an exemplary integrated circuit 400 can have the features described above with reference to the integrated circuit 200 of FIG. 2 and / or the integrated circuit 300 of FIG. 3. For example, the integrated circuit 400 can include a first circuit die 202 (e.g., an advanced technology process node 212) having a first metal stack 206 and a second circuit die 204 (e.g., a paired node 214, which may be an older technology process node) having a second metal stack 208, connected to the first metal stack 206 of the first circuit die 202 (e.g., by a front-to-front or front-to-back hybrid bond 210). Additionally, optimizing the advanced node 212 for logic devices can include moving some non-logic devices to the paired node 214. As described herein, fuses 402, typically located in the transistor layer of the die, can be moved from the advanced node 212 to the paired node 214 to identify the die. A die-to-die fuse value distribution path may be provided to the advanced process die of the advanced node 212, allowing die identification for the advanced process die to be obtained from coordinates within the wafer rather than through programmed fuses. Additionally or alternatively, one or more phase-locked loop circuits may be moved from the advanced node 212 to the pair node 214 in a similar manner. Such phase-locked loop circuits may be useful for generating clock signals during high-speed standalone testing.

[0227] Referring to FIG. 5, wafer-on-wafer process 500A and chip-on-wafer process 500B can be used to produce die-paired devices, such as those described herein with respect to FIGS. 2-4 and 7-25. For example, in wafer-on-wafer process 500A, it may be relatively straightforward to place fuse 402 and / or other non-logic components (e.g., phase-locked loop circuitry) exclusively on the paired process die, because die identification is required only after the wafers for paired node 214 and advanced node 212 are bonded. As a result, fuse 402 can be placed on the paired process die while providing a fuse value distribution path for the advanced process die, and similar provision can be made for other non-logic components. However, in chip-on-wafer process 500B, it may be more complicated to place fuse 402 and / or other non-logic components exclusively on the paired process die, because the “chip” portion of the chip-on-wafer pair is required to support die identification, and because the advanced process die is often required to be the top die in a 3D assembly for various reasons (e.g., thermal). However, placing most or all fuses and / or other non-logic components in the paired process die and using the paired process die as the base wafer does not preserve identification and traceability for the advanced process die that has already been diced into chips.

[0228] 6 illustrates chip-on-wafer processes 600A-600C that avoid placing fuses 402 and / or other non-logic components on advanced die optimized for logic. For example, in chip-on-wafer process 600A, paired dies of paired node 214, which may have fuses 402 and / or other non-logic components disposed thereon, can be pre-diced into chips for placement on advanced process dies of advanced node 212, which can be used as a base wafer. Then, in chip-on-wafer process 600B, one or more interface metal layers 502 can be added on the paired dies to form bumps 504. The resulting assembly can then be flipped and diced in chip-on-wafer process 600C, such that the advanced process dies become the top dies.

[0229] 7, an exemplary integrated circuit 700 can have the features described above with reference to the integrated circuit 200 of FIG. 2, the integrated circuit 300 of FIG. 3, and / or the integrated circuit 400 of FIG. 4. For example, the integrated circuit 400 can include a first circuit die 202 (e.g., an advanced technology process node 212) having a first metal stack 206 and a second circuit die 204 (e.g., a paired node 214, which may be an older technology process node) having a second metal stack 208, connected to the first circuit die 202's first metal stack 206 (e.g., by a front-to-front or front-to-back hybrid bond 210). Additionally, with the node specialization described above, the first circuit die 202 can correspond to the advanced technology process node 212 that is a primary heat source for the integrated circuit 700. Also, the second circuit die 204 can correspond to the paired node 214, which may be an older technology process node compared to the advanced technology process node 212 corresponding to the first circuit die 202. The pair node 214 can be connected to the IO die (e.g., the active interposer die) and / or the package substrate by providing the pair node 214 with a connection element 702 (e.g., a backside via, a through-silicon via, a direct bond, a microbump, one or more routing layers in the second circuit die 204 configured to connect to the additional die (e.g., the active interposer die) and / or the package substrate, etc.). In this way, the advanced technology process node 212, which is the main heat source of the integrated circuit 700, can be located farther away from the IO die and / or package substrate and closer to the semiconductor package thermal interface material (TIM) and thermal management (e.g., a heat spreader), thus achieving heat dissipation benefits for the advanced technology process node 212 corresponding to the first circuit die 202.

[0230] The term "additional die" may generally refer to any die of semiconductor material having redistribution layers and / or circuitry of an integrated circuit. For example, without limitation, the additional die may be an active interposer die, a circuit die of an additional integrated circuit, another die of another process-pair node, etc.

[0231] As used herein, the term "active interposer die" may generally refer to the bottom circuit die in a stacked circuit die configuration. For example, without limitation, the active interposer die may be used to integrate a flexible distributed interconnect fabric for scalable chiplet traffic, energy-efficient 3D plugs using fine-pitch interconnects, power management functions for power supplies closer to the core, and memory-IO controllers and PHYs for off-chip communications.

[0232] 8, an exemplary integrated circuit 800 can have the features described above with reference to the integrated circuit 200 of FIG. 2, the integrated circuit 300 of FIG. 3, the integrated circuit 400 of FIG. 4, and / or the integrated circuit 700 of FIG. 7. For example, the integrated circuit 800 can include a first circuit die (e.g., an advanced technology process node 212) having a first metal stack 206 and a second circuit die (e.g., a paired node 214, which may be an older technology process node) having a second metal stack 208 connected to the first metal stack 206 of the first circuit die (e.g., by a surface-to-surface or surface-to-backside hybrid bond). Alternatively, the integrated circuit 800 can include paired dies that are not split in a manner that optimizes one node as the advanced node 212 and the other node as the paired node 214. In any case, the first circuit die and the second circuit die can have the metal stacks 206 and 208 connected by a surface-to-surface hybrid bond to the combined metal layer stack 802.

[0233] The surface-to-surface hybrid bonding of the metal stack 206 of the first circuit die and the metal stack 208 of the second circuit die can enable shared metal connectivity between the first and second circuit dies. Sharing this metal connectivity further enables eliminating redundant elements (e.g., metal layers) of the combined metal layer stack 802 from the combined stack 802. Thus, the total number of metal layers can be reduced compared to front-to-back stacking or Si-metal-Si-metal stacking. For example, a typical die metal stack has N metal layers, and standard stacking of two dies results in 2×N metal layers. The disclosed shared metal layer stack 802 enables metal connectivity to be shared between the two dies in a manner that eliminates one or more (e.g., most or all) redundant metal layers, resulting in fewer than 2N metal layers. Additionally, because the top of the metal stack is now embedded within the two dies rather than exposed as in a standard single die, at least some of the final layers (e.g., passivation and bumps) to protect the dies are not required. Thus, an embodiment may be a two die, less than 2xN metal stack configuration.

[0234] 8 , a combined metal layer stack 802 can extend between a transistor layer 804 of an advanced node 212 and a transistor layer 806 of a paired node 214. The combined metal layer stack 802 includes different categories of metal layers, such as a first portion 808 of metal layers utilized exclusively by the advanced node 212, a second portion 810 of metal layers utilized exclusively by the advanced node 212, a metal layer 812 utilized by both the advanced node 212 and the paired node 214, and a metal layer 814 utilized exclusively by the paired node 214. A circuit die typically includes all of the metal layers it utilizes exclusively, plus one or more metal layers used to communicate with other dies. However, as shown in FIG. 8 , the combined metal layer stack 802 can eliminate one or more redundant metal layers in at least two ways. First, the metal layer 812 utilized by both the advanced node 212 and the paired node 214 can be removed from the advanced node 212 and / or moved from the advanced node 212 to the paired node 214, which can be achieved at a reduced cost. Second, the second portion 810 of the metal layer utilized exclusively by the advanced node 212 can be relocated from the advanced node 212 to the paired node 214, which can be achieved at a reduced cost. Thus, signals can be routed from the transistor layer 804 advanced node 212 to the second portion 810 of the metal layer utilized exclusively by the advanced node 212 and from there back to the advanced node 212 without communicating the signal to the transistor layer 806 of the paired node 214. Thus, costs can be reduced by eliminating one or more redundant metal layers entirely from the combined metal stack, by rearranging one or more metal layers from the first metal stack 206 to the second metal stack 208, and / or by reducing passivation layers. Additional benefits can include improved performance, reduced power, and improved reliability.

[0235] 9 illustrates an exemplary semiconductor device 900. For example, the semiconductor device 900 may include one or more integrated circuits 902 and 904, such as the integrated circuit 200 of FIG. 2, the integrated circuit 300 of FIG. 3, the integrated circuit 400 of FIG. 4, the integrated circuit 700 of FIG. 7, and / or the integrated circuit 800 of FIG. 8. The one or more integrated circuits 902 and 904 may include a first circuit die corresponding to the advanced node 212 and having a first metal stack, and a second circuit die corresponding to the paired node 214 and having a second metal stack connected to the first metal stack of the first circuit die by a hybrid bond (e.g., surface-to-surface or surface-to-backside). The semiconductor device 900 may also include connecting elements (e.g., a passivation layer connected to the second circuit die and a plurality of bumps (e.g., microbumps) connected to the passivation layer).

[0236] As described above, the semiconductor device 900 may include a first circuit die corresponding to advanced technology process nodes 212A and 212B, which may be an older technology process node compared to the advanced technology process node 212, and a second circuit die corresponding to paired nodes 214A and 214B. The semiconductor device 900 may leverage the 3D-optimized process pairing of these nodes, enabling the advanced technology process nodes 212A and 212B to provide superior performance at lower cost and shorter cycle times. The process pairing approach may provide numerous advantages, including streamlining the advanced technology process node device (e.g., the upper circuit die) to optimize for logic only. High-density SRAM, analog, and less performance-critical logic may be realized on the paired nodes 214A and 214B (e.g., the lower circuit die), which may utilize N3p or N2 technology. Another advantage of the process pairing approach may be significantly higher density for higher-performance firmware, enabling more computing power.

[0237] The integrated circuits 902 and 904 can be connected to an additional die (e.g., an active interposer die (AID)) 906 via microbumps provided at the paired node. The additional die 906 can then be connected (e.g., via bumps 908) to a semiconductor device package substrate 910. Additional circuit dies, such as a small outline integrated circuit (SOIC) 912, can also be included in the semiconductor device 900. Also, as discussed above, the process pairing approach allows for the positioning of temperature sensors, fuses, and / or phase-locked loop circuitry within the transistor layers of the paired nodes 214A and 214B rather than the transistor layers of the advanced technology process nodes 212A and 212B, which provides numerous advantages. Furthermore, the combined metal stack of the process pairing can eliminate one or more redundant metal layers, which provides numerous advantages.

[0238] 10 illustrates an exemplary semiconductor device 1000 that may include any or all of the features of the semiconductor device 900 of FIG. 9, such as advanced nodes 212A and 212B, paired nodes 214A and 214B, integrated circuits 902 and 904, additional die 906, bumps 908, package substrate 910, and / or SOIC 912. Additionally, the semiconductor device 1000 may include a heat spreader 1002 located over the advanced technology process node and a thermal interface material (TIM) 1004 positioned between the heat spreader 1002 and the advanced technology process nodes 212A and 212B. Therefore, the advanced technology process nodes 212A and 212B, which are the main heat sources for the integrated circuits 902 and 904, can be located farther away from the additional die 906 and / or IO die such as the package substrate 910 and closer to the semiconductor package thermal interface material (TIM) 1004 and thermal management (e.g., heat spreader 1004), thereby achieving heat dissipation benefits for the advanced technology process nodes 212A and 212B corresponding to the first circuit die.

[0239] 11-13 show exemplary semiconductor devices 1100, 1200, and 1300 demonstrating various power delivery options. Referring to FIG. 11, semiconductor device 1100 can include at least one copper redistribution layer (RDL) 1102 and a power curtain 1104 configured to carry power from connection elements 1106 and passivation layer 1108 through a transistor layer 1110 of a second circuit die (e.g., pair node 214) to a second metal stack 208. Thus, options for power delivery can include the use of redistribution layer 1102 and power curtain 1104, which can correspond to one or more through-silicon vias.

[0240] 12 , a semiconductor device 1200 may include a backside power delivery network 1202 (e.g., a backside power rail) located in a passivation layer 1204 below a transistor layer 1206 of a second circuit die (e.g., a pair node). With this configuration, the backside power delivery network 1202 may receive power through connection elements 1208 and provide power to the transistor layer 1206 of the second circuit die by backside vias and / or nano-through-silicon vias, eliminating the power curtain 1210. Thus, an option for power delivery may be to use the backside power delivery network 1202 located on the bottom layer of the semiconductor device 1200.

[0241] 13 , the semiconductor device 1300 can include a backside power delivery network 1202 (e.g., a backside power rail) located in a passivation layer 1204 below a transistor layer 1206 of a second circuit die (e.g., a paired node) as described above with reference to the conductor device 1200, and can receive power from a half connection element 1208. Additionally, the semiconductor device 1300 can include a top carrier 1302 and an additional passivation layer 1304 located between the first circuit die (e.g., an advanced node) and the top carrier 1302. The semiconductor device 1300 can also include an additional backside power delivery network 1306 located in the additional passivation layer 1304. This configuration allows the backside power delivery networks 1202 and 1306 to supply power to the transistor layer 1204 of the first circuit die and the transistor layer 1308 of the second circuit die by backside vias and / or nano-through silicon vias, eliminating the power curtain 1210. Thus, an option for power delivery may be to use the backside power delivery networks 1202 and 1306 located on the top and bottom layers of the semiconductor device 1300.

[0242] Referring to FIG. 14, bottom dies 1400A and 1400B are shown in more detail. For example, bottom die 1400A illustrates a bottom die that does not have backside power and requires one or more power curtains (e.g., TSVs) 1402A and 1402B through a transistor layer (e.g., circuitry 1404) to landing metal 1406 in a metal stack on the front side of the die. These power curtains 1402A and 1402B require keep-out zones 1406A and 1406B that separate the power curtains 1402A and 1402B from active elements 1408 of the transistor layer, thus increasing the size of bottom die 1400A to prevent device degradation and resulting in increased cost. Also, providing power from landing metal 1406 through power strapping 1410 (e.g., metal stack) on the front side of die 1400A to circuitry 1404 requires additional connections and can result in potential performance impacts with additional IR drop.

[0243] In contrast to the bottom die 1400A, the bottom die 1400B has a backside power delivery network 1450 that receives power directly from the connection elements 1452 and delivers power to the transistor layer 1454 from the active interposer die or package substrate through microbumps and backside vias or nanoTSVs 1456, which do not require keepout zones. As a result, the size of the bottom die 1400B can be reduced and power delivery to the circuitry from landing metal to power strapping (e.g., a metal stack) on the front side of the die 1400B can be avoided. Thus, the backside power delivery network 1450 can provide power directly to the transistor layer 1454 of the bottom die 1400B, avoiding the increased cost, potential performance impact, and additional IR drop that would be introduced by using a power curtain that requires keepout zones and delivers power first to the front side of the bottom die. Power provided directly to the transistor layer 1454 of the bottom die 1400B can also pass through the bottom die 1400B to provide power to the top die through the front side of the bottom die 1400B by way of power and signal connections 1458 to the top die. Alternatively or additionally, the same or similar backside power delivery network 1450 can be provided on the top die, thus avoiding potential IR drop caused by powering the circuitry (e.g., transistor layer) of the top die through power strapping (e.g., metal stack) on the front side of the top die.

[0244] 15, semiconductor devices 1500A and 1500B can include a top die and a bottom die that are hybrid bonded 1502A and 1502B, respectively, and stacked face-to-back and face-to-face. Without backside power, both semiconductor devices 1500A and 1500B utilize power curtains 1504A and 1504B (e.g., arrays of TSVs) that provide power to the top and bottom dies.

[0245] 16, semiconductor devices 1600A, 1600B, and 1600C can include a top die and a bottom die having metal stacks hybrid-bonded to one another. For example, semiconductor devices 1600A and 1600B can be surface-to-surface hybrid-bonded, and semiconductor device 1600C can be surface-to-back hybrid-bonded, with the surface of the top die bonded to the backside of the bottom die. Semiconductor devices 1600A, 1600B, and 1600C can implement the backside power delivery network described above with reference to FIGS. 12-14. For example, semiconductor device 1600A can have a backside power delivery network 1602 located in the passivation layer of bottom die 1604. This backside power delivery network 1602 can be configured to deliver power from an active interposer die and / or a package substrate 1606 to both top die 1608 and bottom die 1604 having metal stacks hybrid-bonded to one another. Additionally, the semiconductor device 1600B may have backside power delivery networks 1630 and 1632 located in the passivation layer of the top die 1634 and the bottom die 1636. The backside power delivery networks 1630 and 1632 may be configured to provide power from the active interposer die and / or the package substrate 1638 to the bottom die 1636 and from the top carrier 1640 to the top die 1634. The semiconductor device 1600C may also have a backside power delivery network 1660 located in the passivation layer of the bottom die 1662. The backside power delivery network 1660 may be configured to provide power from the active interposer die and / or the package substrate 1664 to both the top die 1666 and the bottom die 1662, which have metal stacks hybrid bonded to each other surface-to-surface. Any of these configurations allows semiconductor devices 1600A, 1600B, and 1600C to supply power to their respective top and bottom dies without using an array of through-silicon vias (TSVs) (e.g., power curtains) through the circuitry (e.g., transistor layer) of the bottom die.

[0246] 17, semiconductor devices 1700A, 1700B, and 1700C may include a top die and a bottom die having metal stacks hybridly bonded to each other in a front-to-back direction. For example, semiconductor device 1700A may bond a front surface of top die 1702 to a back surface of bottom die 1704. Additionally, semiconductor device 1700B may bond a front surface of bottom die 1732 to a back surface of top die 1734. Also, semiconductor device 1700C may bond a front surface of bottom die 1762 to a back surface of top die 1764.

[0247] The semiconductor devices 1700A, 1700B, and 1700C can implement the backside power delivery networks described above with reference to Figures 12-14. For example, the semiconductor device 1700A can have backside power delivery networks 1706 and 1708 located in the passivation layers of the top die 1702 and the bottom die 1704. The backside power delivery networks 1706 and 1708 can be configured to deliver power from the active interposer die and / or package substrate 1710 to the bottom die 1704 and from the top carrier 1712 to the top die 1702. Additionally, the semiconductor device 1700B can have a backside power delivery network 1736 located in the passivation layer of the bottom die 1732. The backside power delivery network 1736 can be configured to deliver power from the active interposer die and / or package substrate 1738 to the top die 1734 and the bottom die 1732 using a power curtain 1740. The semiconductor device 1700C can also have backside power delivery networks 1766 and 1768 located in the passivation layers of the top die 1764 and the bottom die 1762. The backside power delivery networks 1766 and 1768 can be configured to provide power from the active interposer die and / or the package substrate 1770 to the bottom die 1762 and to the top die 1764.

[0248] 18 , an exemplary semiconductor device 1800 can include a two-die stacking having backside power delivery networks 1802 and 1804 for both a top die 1806 and a bottom die 1808, respectively. The power delivery network 1804 can receive power from a connection element 1810 and deliver power to the bottom die 1808 using one or more backside vias 1812 and / or one or more nano-through-silicon vias 1814 and a power plane 1816. The front-side metal layer can also direct power to a power curtain 1820 of the top die 1806 through one or more hybrid bonds 1818. A nano-through-silicon via 1822 can deliver this power to the backside power delivery network 1802 and one or more backside vias 1824 to the circuit elements of the top die 1806. The semiconductor device 1800 can also have signal feedthroughs 1826 by way of one or more nano-through-silicon vias 1828.

[0249] 19 , an exemplary semiconductor device 1900 can include a two-die stacking having a backside power delivery network 1902 for a bottom die 1904. The backside power delivery network 1902 can receive power from a connection element 1906 and provide power to the bottom die 1904 using one or more backside vias 1908 and / or one or more nano-through-silicon vias 1910 and a power plane 1912. The frontside metal layer can also route power through one or more hybrid bonds 1914 to a frontside power delivery network 1916 of a top die 1918. The frontside power delivery network 1916 can deliver power to circuit elements of the top die 1918. The semiconductor device 1900 can also have signal feedthroughs 1920 by way of one or more nano-through-silicon vias 1922.

[0250] 20 , an exemplary semiconductor device 2000 can include a two-die stacking having a backside power delivery network 2002 for a top die 2004 and a backside power delivery for a bottom die 2006 having an extremely thin body and directly bonded to the package. The bottom die 2006 can receive power from a connection element 2008 (e.g., direct bond) and provide power to the bottom die 2006 using one or more nano-through silicon vias 2010 and one or more power curtains 2012 and / or power planes 2014. The metal layer can also direct power to the power curtain 2018 of the top die 2004 through one or more hybrid bonds 2016, which can provide power to the backside power delivery network 2002 using one or more nano-through silicon vias 2020. The backside power delivery network 2002 can deliver power to the circuit elements of the top die 2004 using backside vias 2022. The semiconductor device 2000 may also have signal feedthroughs 2024 by way of one or more nano-through silicon vias 2026 .

[0251] 21 , an exemplary semiconductor device 2100 includes a three-die stacking having backside power delivery networks 2102 and 2104 for both a top die 2106 and a middle die 2108, respectively. The bottom die 2110 may correspond to the active interposer die. The connection elements 2112 of the bottom die 2110 can receive power from the package substrate and convey the power via a power curtain 2114 to a metal landing layer 2116 of a frontside power delivery network 2118 of the bottom die 2110. The frontside power delivery network 2118 provides power to the bottom die circuitry and can also provide power to the backside power delivery network 2104 using hybrid bonds 2120. The backside power delivery network 2104 can supply power to the middle die 2108 using one or more backside vias 2122 and / or one or more nano-through-silicon vias 2124 and a power plane 2126. The front-side metal layer can also conduct power to the backside power delivery network 2102 of the top die 2106 through one or more hybrid bonds 2128, power curtains 2130, and nano-through silicon vias 2132. The backside power delivery network 2102 can deliver power to the circuit elements of the top die 2106 by backside vias 2134. The semiconductor device 2100 can also have signal feedthroughs 2136 by one or more nano-through silicon vias 2138 and 2140 and hybrid bonds 2120.

[0252] 22 , an exemplary semiconductor device 2200 can include a three-die stacking having a backside power delivery network 2202 for a middle die 2204 and a frontside power delivery network 2206 for a top die 2208. A bottom die 2210 can correspond to an active interposer die. The connection elements 2212 of the bottom die 2210 can receive power from a package substrate and convey the power via a power curtain 2214 to a metal landing layer 2216 of a frontside power delivery network 2218 of the bottom die 2210. The frontside power delivery network 2218 can provide power to the bottom die circuitry and can also provide power to the backside power delivery network 2202 using hybrid bonds 2220. The backside power delivery network 2202 can deliver power to the middle die 2204 using one or more backside vias 2222 and / or one or more nano-through silicon vias 2224 and a power plane 2226. The front-side metal layer can also conduct power to the front-side power delivery network 2206 of the top die 2208 through one or more hybrid bonds 2228. The front-side power delivery network 2206 can deliver power to the circuit elements of the top die 2108. The semiconductor device 2100 can also have signal feedthroughs 2236 by way of one or more nano-through silicon vias 2238 and 2240 and hybrid bonds 2220.

[0253] 23 , an exemplary semiconductor device 2300 can include a three-die stacking with a backside power supply for a middle die 2302 having an ultra-thin body 2304 and directly and / or hybridly bonded to a bottom die 2308 having a front-side power delivery network 2310. The bottom die 2308 can correspond to an active interposer die. The connection elements 2312 of the bottom die 2308 can receive power from the package substrate and convey the power via a power curtain 2314 to a metal landing layer 2316 of the front-side power delivery network 2310 of the bottom die 2308. The front-side power delivery network 2310 can provide power to the bottom die circuitry and can also provide power to the ultra-thin body 2304 of the middle die 2302 using the direct bond 2306 and / or hybrid bond. The ultra-thin body 2304 can provide power to the middle die 2302 using one or more nano-through-silicon vias 2318 and 2320 and a power plane 2322. The front-side metal layer can also conduct power to a backside power delivery network 2330 of the top die 2332 through one or more hybrid bonds 2324, power curtains 2326, and nano-through silicon vias 2328. The backside power delivery network 2330 can deliver power to the circuit elements of the top die 2332 by backside vias 2334. The semiconductor device 2300 can also have signal feedthroughs 2336 by one or more nano-through silicon vias 2338 and 2340 and direct bonds 2306 and / or hybrid bonds.

[0254] 24 , an exemplary semiconductor device may include a three-die stacking having backside power delivery networks 2402, 2404, and 2406 for a top die 2408, a middle die 2410, and a bottom die 2412. The bottom die 2412 may correspond to an active interposer die. Connection elements 2414 of the bottom die 2412 may receive power from a package substrate and convey the power to the backside power delivery network 2406. The backside power delivery network 2406 may supply power to the bottom die 2412 using one or more backside vias 2415 and / or one or more nano-through-silicon vias 2416 and a power plane 2418. Additionally, a front-side metal layer may conduct power to the backside power delivery network 2404 through one or more hybrid bonds 2420. The backside power delivery network 2404 may supply power to the middle die 2410 using one or more backside vias 2422 and / or one or more nano-through-silicon vias 2424 and a power plane 2426. The front-side metal layer can also conduct power to a backside power delivery network 2402 of the top die 2408 through one or more hybrid bonds 2428, a power curtain 2430, and nano-through silicon vias 2432. The backside power delivery network 2402 can deliver power to the circuit elements of the top die 2408 by backside vias 2434. The semiconductor device 2400 can also have one or more signal feedthroughs 2436 and 2438 by one or more nano-through silicon vias 2440 and 2442 and hybrid bonds 2420.

[0255] 25, an exemplary semiconductor device 2500 can include a three-die stacking with backside power distribution for a middle die 2502 and a bottom die 2504 having ultra-thin bodies 2506 and 2508, and a backside power distribution network 2510 for a top die 2512. The bottom die 2504 can correspond to an active interposer die. Connection elements 2514 of the bottom die 2504 can receive power from a package substrate and convey the power to the ultra-thin body 2506 of the bottom die 2504. The ultra-thin body 2506 can supply power to the bottom die 2504 using one or more nano-through silicon vias 2516 and 2518 and a power plane 2520. Additionally, a front-side metal layer can conduct power to the ultra-thin body 2508 of the middle die 2502 through direct bonding 2521 and / or hybrid bonding. The ultra-thin body 2508 can provide power to the middle die 2502 using one or more nano-through silicon vias 2524 and 2526 and a power plane 2528. The front-side metal layer can also direct power to the backside power delivery network 2510 of the top die 2512 through one or more hybrid bonds 2530, a power curtain 2532, and nano-through silicon vias 2534. The backside power delivery network 2510 can deliver power to the circuit elements of the top die 2512 by backside via 2536. The semiconductor device 2500 can also have signal feedthroughs 2538 and 2540 by one or more nano-through silicon vias 2542 and 2544 and direct bond 2521 and / or hybrid bond.

[0256] (Conclusion - Die pair device division) As detailed above, integrated circuits and semiconductor devices can implement the die-pair device partitioning described herein. The disclosed approach to implementing a process node involves pairing two sets of devices that are fabricated as separate process nodes but connected with 3D hybrid bonding (e.g., surface-to-surface). Either of these paired nodes is included as a pair, rather than the full set of optimized devices required for the new process node. This approach allows an “advanced” version of the process pair to include (e.g., primarily or exclusively) logic transistors that are fabricated separately and optimized solely to improve the performance and power efficiency of the logic without the compromises necessary to support SRAM and analog devices. In addition to SRAM and analog devices, less optimized logic devices can also be implemented (e.g., primarily or exclusively) within the “paired” technology node, which are also fabricated separately and then 3D bonded to the advanced node. The combination of advanced and paired nodes in 3D hybrid junction configurations can provide a much higher performance, more efficient (e.g., for logic, which contributes most to the technology node gain), and fully functional (e.g., SRAM and analog) technology node for SoC design.

[0257] Benefits from the above results can include avoiding manufacturing compromises required to balance process windows that deliver a complete suite of analog, SRAM, and logic devices for an advanced technology node. The advanced node can focus (e.g., exclusively) on optimizing logic devices, which contribute most significantly to performance and performance per watt. Additionally, node pair combinations can provide higher density, higher performance, and more power-efficient technologies than generic technology nodes that include all devices within a single FEOL.

[0258] (Conclusion - Temperature Sensor in Die Pair Topology) As detailed above, integrated circuits and semiconductor devices can implement die pair topologies in which the temperature of the base die can reasonably track the temperature of the top die that includes a high-power computing engine. Thus, through 3D thermal modeling using commercially available electronic design automation (EDA) tools, the location of a corresponding hot spot on the base die can be identified, and a thermal sensor can be placed planarly proximate to the hot spot on the top die.

[0259] Benefits derived from the above results include accurately tracking peak temperatures on the top die without placing a sensor on the top die, allowing for little or no design margin with respect to temperature measurements. Thus, by judiciously placing thermal sensors on the base die relative to the top die in a die pair topology, the top die can deliver the highest operating frequency and performance it can offer without the adverse effects seen in monolithic designs.

[0260] (Conclusion - Backend of line optimized to work with 3D stack configuration) As detailed above, the integrated circuits and semiconductor devices described herein can provide a back-end of line optimized to function in a 3D stack configuration. Metal connectivity can be shared between circuit dies, allowing for the elimination of redundant elements in a combinatorial metal layer stack. This elimination of redundant metal layers reduces the total number of metal layers compared to front-to-backside or Si-metal-Si-metal stacking. An additional result of this configuration is that final layers (e.g., passivation and bumps) are not required to protect the die, since the top of the metal stack is now embedded within the two dies and therefore not exposed as in a standard single die.

[0261] Benefits resulting from the above can include reduced cost, improved performance, reduced power requirements, and improved reliability. For example, cost can be reduced because fewer metal layers and less final passivation require less processing and therefore less cost. Additionally, fewer metal layers can improve performance because metal resistance-capacitance (RC) delays are reduced. Fewer metal layers can also reduce power requirements because metal capacitance is reduced. Furthermore, reliability can be improved because the overall physical structure of two connected dies and a shorter metal stack results in a die that is more resistant to cracks and physical stress.

[0262] (Conclusion - Thermally Considered Stacking Topology) As detailed above, the thermally aware stacking topology places the computing chip (e.g., core computing die) farther away from the IO die and closer to the package thermal interface material (TIM) and thermal solution (e.g., heat sink), thus achieving heat dissipation benefits for the computing chip. By connecting paired nodes to the IO die (e.g., interposer), advanced technology process nodes can be positioned farther away from the IO die.

[0263] Benefits derived from the above results can include reduced thermal constraints for HPC. Placing the computing chip (i.e., the primary heat source) above the IO stack and away from the die provides a lower thermal resistance path to the hottest chip, thus ensuring cooling and mitigating associated performance loss. Thus, the disclosed thermally-aware stacking topology can utilize more efficient vertical heat transfer (e.g., versus horizontal), which can keep the overall cost of the product lower compared to increasing the central processing unit (CPU) die area to manage heat density.

[0264] (Conclusion - rear power) As detailed above, integrated circuits and semiconductor devices can implement the die-pair device partitioning described herein. The disclosed approach to implementing a process node involves pairing two sets of devices that are fabricated as separate process nodes but connected with 3D hybrid bonding (e.g., surface-to-surface). Either of these paired nodes is included as a pair, rather than the full set of optimized devices required for the new process node. This approach allows an “advanced” version of the process pair to include (e.g., primarily or exclusively) logic transistors that are fabricated separately and optimized solely to improve the performance and power efficiency of the logic without the compromises necessary to support SRAM and analog devices. In addition to SRAM and analog devices, less optimized logic devices can also be implemented (e.g., primarily or exclusively) within the “paired” technology node, which are also fabricated separately and then 3D bonded to the advanced node. The combination of advanced and paired nodes in 3D hybrid junction configurations can provide a much higher performance, more efficient (e.g., for logic, which contributes most to the technology node gain), and fully functional (e.g., SRAM and analog) technology node for SoC design.

[0265] Benefits from the above results can include avoiding manufacturing compromises required to balance process windows that deliver a complete suite of analog, SRAM, and logic devices for an advanced technology node. The advanced node can focus (e.g., exclusively) on optimizing logic devices, which contribute most significantly to performance and performance per watt. Additionally, node pair combinations can provide higher density, higher performance, and more power-efficient technologies than generic technology nodes that include all devices within a single FEOL.

[0266] (Conclusion - Advanced process in process pair without fuse) As detailed above, advanced processing of fuseless process pairs can avoid placing fuses in the advanced process die of the die pair. For example, by placing one or more fuses in one or more circuit dies (e.g., paired dies) having at least primarily static random access memory and analog devices implemented therein and using the advanced process die as a base wafer in a chip-on-wafer process, the advanced process die can be optimized to improve logic performance and power efficiency without making the compromises necessary to support other non-logic devices such as static random access memory, analog devices, and one or more fuses. A die-to-die fuse value distribution path can be provided in the advanced process die, allowing die identification information for the advanced process die to be obtained from coordinates within the wafer rather than through programmed fuses. After the addition of an interface metal layer and bumping, the assembly can be flipped and diced so that the advanced process die becomes the top die.

[0267] Advantages resulting from the above results may include the ability to perform die identification for the advanced process die without including fuses within the advanced process die. By placing fuses exclusively within the paired die connected to the advanced process die, the advanced process die may be optimized for data logic by focusing primarily (e.g., exclusively) on logic devices, improving logic device performance.

[0268] The process parameters and order of steps described and / or illustrated herein are given by way of example only and can be changed as desired. For example, although the steps illustrated and / or described herein are shown or described in a particular order, these steps do not necessarily have to be performed in the order illustrated or described. The various exemplary methods described and / or illustrated herein may omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.

[0269] The foregoing description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many changes and modifications are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0270] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and claims should be interpreted as allowing both direct and indirect (i.e., via other elements or components) connections. Additionally, the terms "a" or "an" as used in this specification and claims should be interpreted as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and claims are interchangeable with the term "comprising" and have the same meaning.

Claims

1. 1. An integrated circuit comprising: a circuit die having a metal stack and including a majority of the logic transistors of the integrated circuit; one or more additional circuit dies; the one or more additional circuit dies one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die; a majority of the static random access memory and analog devices of the integrated circuit; Integrated circuit.

2. the circuit die is constructed according to a more advanced technology process than the one or more additional circuit dies; 10. The integrated circuit of claim 1.

3. the logic transistors included in the circuit die are fabricated independently; 10. The integrated circuit of claim 1.

4. the one or more additional circuit dies are fabricated separately before being connected to the circuit die; 10. The integrated circuit of claim 1.

5. the at least one of the one or more additional metal stacks is connected to the metal stack surface-to-surface.

10. The integrated circuit of claim 1.

6. the at least one of the one or more additional metal stacks is connected to the metal stack face-to-face.

10. The integrated circuit of claim 1.

7. the at least one of the one or more additional metal stacks is connected to the metal stack by at least one of a hybrid bond, a through-silicon via, a fine-pitch microbump, or a direct bond.

10. The integrated circuit of claim 1.

8. A semiconductor device comprising: a circuit die having a metal stack and including most of the logic transistors of the integrated circuit; one or more additional circuit dies; an additional die connected to the one or more additional circuit dies; the one or more additional circuit dies one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die; a majority of the static random access memory and analog devices of the integrated circuit; Semiconductor devices.

9. the circuit die is constructed according to a more advanced technology process than the one or more additional circuit dies; The semiconductor device of claim 8.

10. the logic transistors included in the circuit die are fabricated independently; The semiconductor device of claim 8.

11. the at least one of the one or more additional metal stacks is connected to the metal stack surface-to-surface. The semiconductor device of claim 8.

12. the at least one of the one or more additional metal stacks is connected to the metal stack face-to-face. The semiconductor device of claim 8.

13. the at least one of the one or more additional metal stacks is connected to the metal stack by at least one of a hybrid bond, a through-silicon via, a fine-pitch microbump, or a direct bond. The semiconductor device of claim 8.

14. 1. A method comprising: providing a circuit die having a metal stack and including most of the logic transistors of the integrated circuit; providing one or more additional circuit dies, the one or more additional circuit dies having one or more additional metal stacks, at least one of which is connected to the metal stack of the circuit die, and a majority of the static random access memory and analog devices of the integrated circuit; connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. method.

15. the circuit die is constructed according to a more advanced technology process than the one or more additional circuit dies; 15. The method of claim 14.

16. separately fabricating the logic transistors included in the circuit die; 15. The method of claim 14.

17. fabricating the one or more additional circuit dies separately before connecting them to the circuit die.

15. The method of claim 14.

18. connecting the at least one of the one or more additional metal stacks to the metal stack of the circuit die, connecting the at least one of the one or more additional metal stacks to the metal stack surface-to-surface.

15. The method of claim 14.

19. connecting the at least one of the one or more additional metal stacks to the metal stack of the circuit die, connecting the at least one of the one or more additional metal stacks to the metal stack face-to-face.

15. The method of claim 14.

20. connecting the at least one of the one or more additional metal stacks to the metal stack of the circuit die, connecting the at least one of the one or more additional metal stacks to the metal stack by at least one of a hybrid bond, a through silicon via, a fine pitch microbump, or a direct bond.

15. The method of claim 14.

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