Physical interface configuration buffer in flash memory systems

Abstract

This disclosure provides systems, methods, and devices for a memory system that support updating the configuration of a physical layer interface (PHY) using information stored in a buffer of a connected memory system. In a first aspect, a method for accessing data in a flash memory system includes: initializing a PHY for connecting a host device to a memory system at a first speed by a memory controller of a host device; receiving PHY configuration information from a first buffer of the memory system for configuring the PHY to operate at a second speed faster than the first speed; and adjusting the PHY configuration to operate at the second speed according to the PHY configuration information by the memory controller. Other aspects and features are also claimed and described.

Description

Technical Field

[0001] (Cross - reference to Related Applications)

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 187,259, filed on March 21, 2023, entitled "PHYSICAL INTERFACE CONFIGURATION BUFFER IN A FLASH MEMORY SYSTEM", which is hereby incorporated by reference in its entirety.

[0002]

[0002] Aspects of the present disclosure generally relate to apparatuses and methods for controlling memory devices. Some aspects may more specifically relate to apparatuses and methods for controlling operations to update a PHY configuration using information from a physical interface (PHY) configuration buffer.

Background Art

[0003]

[0003] As the value and use of information continue to increase, individuals and businesses are seeking additional ways to process and store information. In addition, the use of information in various locations and the desire for information portability are increasing. For this reason, users are increasingly turning to the use of portable electronic devices such as mobile phones, digital cameras, laptop computers, etc. Portable electronic devices generally employ a memory system that uses a memory device to store data. The memory system can be used as the main memory or auxiliary memory of a portable electronic device.

[0004]

[0004] Memory devices in a memory system may include one type of storage or a combination of multiple types of storage. For example, magnetic-based memory systems such as hard disk drives (HDDs) store data by encoding it as a combination of small magnets. Another example is optical-based memory systems such as digital versatile discs (DVDs) and Blu-ray media, which store data by encoding it as physical bits that cause different reflections when illuminated by a light source. Further examples include electronic memory devices that store data as a collection of electrons that can be detected through voltage and / or current measurements.

[0005]

[0005] Electronic memory devices can be advantageous in certain systems because they allow for quick access to data and consume less power. Examples of electronic memory devices with these advantages include universal serial bus (USB) memory devices (sometimes called "memory sticks"), memory cards (such as those used in some cameras and game systems), and solid state drives (SSDs) (such as those used in laptop computers). NAND flash memory is a type of memory device that can be used in electronic memory devices. NAND flash memory is manufactured as a memory card or flash disk. Examples of memory cards include compact flash (CF) cards, multimedia cards (eMMCs), smart media (SM) cards, and secure digital (SD) cards.

[0006]

[0006] The memory system may be integrated with or otherwise connected to an electronic system. For example, a flash memory system, which may be a universal flash storage (UFS) system, may be integrated with an electronic system such as an access point (AP), station (STA), user equipment (UE), base station, modem, camera, or other system. [Overview of the Initiative]

[0007]

[0007] The following summarizes several aspects of the Disclosure in order to provide a basic understanding of the technology discussed. This summary is not intended to be a comprehensive overview of all conceivable features of the Disclosure, nor to identify any major or significant elements of all aspects of the Disclosure, nor to specify the scope of any or all aspects of the Disclosure. Its sole purpose is to present in summary form some concepts of one or more aspects of the Disclosure as an introduction to the more detailed descriptions to be presented later.

[0008]

[0008] Buffers located on flash memory may be used to store configuration information for patching the PHY to improve its speed. For example, a PHY connecting a memory system, such as a memory system including flash memory, to a host device may be configured to operate at a slower speed during the initialization of the host device, which may include the initialization of the PHY and the memory system. Configuration information stored on the PHY may be accessible during the initialization of the host device, such as before the initialization of the flash memory is complete. The host device may read the PHY configuration information from the flash memory and adjust the PHY configuration according to the PHY configuration information to operate at a faster speed. Thus, the memory controller of the host device may access the configuration information early in the initialization process to patch the PHY in order to operate at an improved speed. Such an improved speed may enable faster initialization of the host device. Furthermore, the buffers may be made available to store other PHY configuration information to facilitate post-silicon patching of PHY bugs or improvements in operational efficiency early in the boot process.

[0009]

[0009] In one aspect of the present disclosure, the memory device includes a memory controller, which is coupled to a memory module through a first channel and configured to access data stored in the memory module through the first channel, and is coupled to a host device through a first physical interface (PHY) and configured to communicate with the host device through the first interface. The memory controller of the memory device may be configured to perform operations including, after the PHY has been initialized to operate at a first speed, receiving a request from the host device for PHY configuration information to configure the PHY to operate at a second speed faster than the first speed from a first buffer of the memory module, and transmitting the PHY configuration information to the host device. In another aspect of the present disclosure, a method for a processor to perform these operations by executing instructions stored in memory coupled to the processor is also disclosed. In an additional aspect of the present disclosure, a non-temporary computer-readable medium stores instructions, and the instructions cause the processor to perform these operations when executed by the processor.

[0010]

[0010] In additional aspects of the present disclosure, the device includes a memory controller for a host device configured to couple the host device to a memory system through a first physical interface (PHY), the memory controller being configured to perform operations including initializing the PHY to operate at a first speed, receiving PHY configuration information from a first buffer of the memory system to configure the PHY to operate at a second speed faster than the first speed, and adjusting the configuration of the PHY to operate at the second speed according to the PHY configuration information. In another aspect of the present disclosure, a method is also disclosed for a processor to perform these operations by executing instructions stored in memory coupled to the processor. In additional aspects of the present disclosure, a non-temporary computer-readable medium stores instructions, which, when executed by the processor, cause that processor to perform these operations.

[0011]

[0011] The above provides a fairly broad overview of the features and technical advantages of the embodiments of this disclosure so that the following “Modes for Carrying Out the Invention” may be better understood. Additional features and advantages are described below. The concepts and specific embodiments disclosed may be readily used as a basis for modifying or designing other structures to accomplish the same objectives of this disclosure. Such equivalent structures shall not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein, both their configuration and method of operation, along with their relevant advantages, will be better understood from the following description by examining them with respect to the appended figures. Each of the figures is provided for illustrative and explanatory purposes and is not provided to define any limitation of the claims.

[0012]

[0012] While this application describes embodiments and implementations by example to several embodiments, those skilled in the art will understand that additional implementations and use cases may occur in many different configurations and scenarios. The innovations described herein can be realized across many different platform types, devices, systems, shapes, sizes, and packaging configurations. For example, embodiments and / or applications may be implemented in integrated chip implementations and other non-modular component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, artificial intelligence (AI)-enabled devices, etc.). Some examples may or may not specifically cover use cases or applications, but a wide range of combinations of the innovations described may be applicable. Implementations may range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more embodiments of the innovations described. In some practical settings, devices incorporating the embodiments and features described may also necessarily include additional components and features for the implementation and practice of the claims and embodiments described. For example, wireless signal transmission and reception necessarily include several components (hardware components, e.g., antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors (one or more), interleavers, adders / analog adders, etc.) for analog and digital purposes. The innovations described herein are intended to be practiced in a wide variety of devices, chip-level components, systems, distributed configurations, end-user devices, etc., of various sizes, shapes, and structures. [Brief explanation of the drawing]

[0013]

[0013] Further understanding of the nature and advantages of this disclosure can be achieved by referring to the following drawings. In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by adding a dash and a second marking that distinguishes similar components after the reference marking. Where only the first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, notwithstanding the second reference label. [Figure 1]

[0014] Figure 1 is a block diagram showing a data processing system including a memory system according to one embodiment of the present invention. [Figure 2]

[0015] Figure 2 is a block diagram showing an exemplary electronic device, including a memory system, according to one or more aspects of the present disclosure. [Figure 3]

[0016] This block diagram shows components for facilitating access from a host device to a flash memory device according to some embodiments of the present disclosure. [Figure 4A]

[0017] This is a timing flow diagram illustrating an initialization process for a host device according to some embodiments of the present disclosure. [Figure 4B]

[0018] This is a timing flow diagram illustrating an initialization process for a host device according to some embodiments of the present disclosure. [Figure 5]

[0019] This flowchart shows a method for initializing a host device according to some embodiments of the present disclosure. [Figure 6]

[0020] This flowchart shows a method for initializing a host device using PHY configuration information stored in a flash buffer, according to some embodiments of the present disclosure. [Figure 7]

[0021] A flowchart showing a method for initializing a host device using PHY configuration information stored in a flash buffer by a host controller according to some embodiments of the present disclosure. [Figure 8]

[0022] A flowchart showing a method for initializing a host device using PHY configuration information stored in a flash buffer by a flash memory device according to some embodiments of the present disclosure. [Figure 9]

[0023] A block diagram showing details of an exemplary wireless communication system according to one or more aspects.

[0014]

[0024] Like reference numerals and names in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0025] With respect to the accompanying drawings, the following "DETAILED DESCRIPTION OF THE INVENTION" is intended as an explanation of various configurations and is not intended to limit the scope of the present disclosure. Rather, the "DETAILED DESCRIPTION OF THE INVENTION" includes specific details for the purpose of providing a complete understanding of the subject matter of the present invention. It will be apparent to those skilled in the art that these specific details are not required in every case, and that in some instances, well-known structures and components are shown in block diagram form for clarity of explanation.

[0016]

[0026] The present disclosure provides a system, apparatus, method, and computer-readable medium that support data processing, including techniques for storing, retrieving, and organizing data in a memory system. Aspects of the present disclosure provide operations for patching a PHY that connects a host device to a memory system to operate more quickly using PHY configuration information stored in a buffer of the memory of the memory subsystem, and data structures used in those operations.

[0017]

[0027] Certain implementations of the subject matter described in this disclosure may be implemented to realize one or more of the following potential advantages or benefits. In some aspects, this disclosure provides techniques for improving the performance of a memory system, such as improving speed and shortening boot time during the boot process of a host device. Improving speed and shortening boot time during boot can be particularly advantageous in the context of automotive computer systems where a boot time of less than 50 mS may be desirable.

[0018]

[0028] The memory can be used in a computing system organized as shown in FIG. 1. FIG. 1 shows a data processing system 100 that may be included in a mobile computing device, according to one or more aspects of this disclosure. The memory system 110 may be coupled to the host device 102 via one or more channels. For example, the host device 102 and the memory system 110 may be coupled via a serial interface including a single channel for data transport, or a parallel interface including two or more channels for data transport. In some aspects, control data may be transferred via the same channel(s) as data, or control data may be transferred via an additional channel. The host device 102 may be, for example, a portable electronic device such as a mobile phone, an MP3 player, a laptop computer, or a non-portable electronic device such as a desktop computer, a game player, a television (TV), a media player, or a projector. As another example, the host device 102 may be an automotive computer system. Additional exemplary host devices are shown and described with reference to FIG. 6.

[0019]

[0029] The memory system 110 can perform operations in response to commands (e.g., requests) from the host device 102. For example, the memory system 110 can store data provided by the host device 102, and the memory system 110 can also provide the stored data to the host device 102. The memory system 110 can be used by the host device 102 as main memory, short-term memory, or long-term memory. As an example of main memory, the host device 102 may use the memory system 110 to supplement or replace system memory by using the memory system 110 to store temporary data such as data related to the operating system and / or threads running within the operating system. As an example of short-term memory, the host device 102 may use the memory system 110 to store a page file for the operating system. As an example of long-term memory, the host device 102 may use the memory system 110 to store user files (e.g., documents, videos, photos) and / or application files (e.g., word processing executables, game applications).

[0020]

[0030] The memory system 110 may implement one of various storage devices according to a host interface protocol for one or more channels connecting the memory system 110 to the host device 102. The memory system 110 may implement one of various storage devices such as a solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), microMMC, secure digital (SD) card, miniSD, microSD, universal serial bus (USB) storage device, universal flash storage (UFS) device, compact flash (CF) card, smartmedia (SM) card, or memory stick.

[0021]

[0031] The memory system 110 may include a memory module 150 and a controller 130 coupled to the memory module 150 via one or more channels. The memory module 150 stores and retrieves data in memory blocks 152, 154, and 156 under the control of the controller 130, and the controller 130 can execute commands received from the host device 102. The controller 130 is configured to control data exchange between the memory module 150 and the host device 102. Storage components such as blocks 152, 154, and 156 within the memory module 150 may be implemented as volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM), or as non-volatile memory devices such as read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (SCRAM), or NAND flash memory.

[0022]

[0032] The controller 130 and the memory module 150 may be formed as an integrated circuit on one or more semiconductor dies (or other substrates). In some embodiments, the controller 130 and the memory module 150 may be integrated on a single chip. In some embodiments, the memory module 150 may include one or more chips coupled in series or parallel to each other and coupled to the controller 130, which is located on a separate chip. In some embodiments, the chips of the memory module 150 and the controller 130 are integrated on a single package, such as a package-on-package (PoP) system. In some embodiments, the memory system 110 is integrated on a single chip together with one or more or all of the components of a host device 102, such as a system-on-chip (SoC), including an application processor, system memory, digital signal processor, modem, graphics processor unit, memory interface, input / output interface, and network adapter. The controller 130 and the memory module 150 can be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, CompactFlash (CF) card, SmartMedia card (SMC), Memory Stick, Multimedia Card (MMC), RS-MMC, MicroMMC, Secure Digital (SD) card, MiniSD, MicroSD, SDHC, and Universal Flash Storage (UFS) device.

[0023]

[0033] The controller 130 of the memory system 110 can control the memory module 150 in response to commands from the host device 102. The controller 130 can execute read commands to provide data from the memory module 150 to the host device 102. The controller 130 can execute write commands to store data provided by the host device 102 in the memory module 150. The controller 130 can manage the data in the memory module 150 by executing other commands such as program commands and erase commands. The controller 130 can also manage control of the memory system 110, such as by executing other commands to set the configuration registers of the memory system 110. By executing commands according to the configuration specified in the configuration registers, the controller 130 can control the operation of the memory module 150, such as read, write, program, and erase operations.

[0024]

[0034] The controller 130 may include several components configured to execute received commands. For example, the controller 130 may include a host interface (I / F) unit 132, a processor 134, an error correction code (ECC) unit 138, a power management unit (PMU) 140, a NAND flash controller (NFC) 142, and / or memory 144. The power management unit (PMU) 140 may provide and manage power for the components in the controller 130 and / or memory module 150.

[0025]

[0035] The host interface unit 132 can process commands and data provided by the host device 102 and can communicate with the host device 102 through at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE). For example, the host interface 132 may be a parallel interface such as the MMC interface, or a serial interface such as an ultra-high speed class 1 (UHS-I) / UHS class 2 (UHS-II) or Universal Flash Storage (UFS) interface.

[0026]

[0036] The ECC unit 138 can detect and correct errors in the data read from the memory module 150 during a read operation. If the number of error bits is greater than the threshold number of error bits that can be corrected, the ECC unit 138 may not correct the error bits, and as a result, the ECC unit 138 may output an error correction failure signal indicating that the correction of the error bits has failed. In some embodiments, the ECC unit 138 may not be provided, or the ECC unit 138 may be configured to be active for some or all of the memory module 150. The ECC unit 138 may perform error correction operations using coded modulation such as low-density parity check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, turbo code, Reed-Solomon (RS) code, convolutional code, recursive systematic code (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM).

[0027]

[0037] The NFC142 provides an interface between the controller 130 and the memory module 150, enabling the controller 130 to control the memory module 150 in response to commands received from the host device 102. The NFC142 can generate control signals for the memory module 150, such as low-line and bit-line signals, and process data under the control of the processor 134. Although the NFC142 is described as a NAND flash controller, other controllers may perform similar functions for other memory types used as the memory module 150.

[0028]

[0038] Memory 144 may function as working memory for the memory system 110 and controller 130. Memory 144 may store data to drive the memory system 110 and controller 130. If controller 130 controls the operation of memory module 150, such as read, write, program, or erase operations, memory 144 may store data used by controller 130 and memory module 150 for operation. Memory 144 may implement volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some embodiments, memory 144 may store address mappings, program memory, data memory, write buffers, read buffers, map buffers, etc.

[0029]

[0039] The processor 134 can control the overall operation of the memory system 110 and can control write or read operations on the memory module 150 in response to write or read requests received from the host device 102. For example, the processor 134 may execute firmware sometimes called a flash translation layer (FTL) to control the overall operation of the memory system 110. The processor 134 may be implemented as, for example, a microprocessor, a central processing unit (CPU), or an application-specific integrated circuit (ASIC).

[0030]

[0040] Figure 2 is a block diagram illustrating an exemplary electronic device including a memory system 100 according to one or more aspects of the present disclosure. The electronic device 200 may include a user interface 210, memory 220, an application processor 230, a network adapter 240, and a storage system 250 (which may be an embodiment of the memory system 100 in Figure 1). The application processor 230 may be coupled to other components via a bus, such as a peripheral component interface (PCI) bus, including a PCI Express (PCIe) bus.

[0031]

[0041] The application processor 230 may execute computer program code, including applications, drivers, and operating systems, to coordinate the execution of tasks by components included in the electronic device 200. For example, the application processor 230 may execute a storage driver for accessing the storage system 250. The application processor 230 may be part of a system-on-a-chip (SoC) that includes one or more other components shown in the electronic device 200.

[0032]

[0042] Memory 220 may function as the main memory, working memory, buffer memory, or cache memory of the electronic device 200. Memory 220 may include volatile random access memories such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM, or non-volatile random access memories such as phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM). In some embodiments, the application processor 230 and memory 220 may be combined using a package-on-package (POP).

[0033]

[0043] The network adapter 240 can communicate with external devices. For example, the network adapter 240 may support wired and / or various wireless communications such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (WiMAX), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, and wireless display (Wi-Di), thereby enabling communication with wired and / or wireless electronic devices, such as mobile electronic devices.

[0034]

[0044] The storage system 250 can store data, for example, data received from the application processor 230, and transmit the stored data to the application processor 230. The storage system 250 may be a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive random-access memory (ReRAM), NAND flash memory, NOR flash memory, or three-dimensional (3-D) NAND flash memory. The storage system 250 may also be a removable storage medium such as a memory card or an external drive. For example, the storage system 250 may correspond to the memory system 110 described above with reference to Figure 1, and may be an SSD, eMMC, UFS, or other flash memory system.

[0035]

[0045] The user interface 210 provides one or more graphical user interfaces (GUIs) for inputting data or commands to the application processor 230 or outputting data to an external device. For example, the user interface 210 may include user input interfaces such as a virtual keyboard, touchscreen, camera, microphone, gyroscope sensor, or vibration sensor, and user output interfaces such as a liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, light-emitting diode (LED), speaker, or tactile motor.

[0036]

[0046] Figure 3 is a block diagram showing components for facilitating access from a host device to a flash memory system according to some embodiments of the present disclosure. The host device 102 accesses the memory system 110 through a first interface 310. The first interface may be, for example, a physical interface (PHY). The host device 102 may include a physical layer access block 312, which is configured to generate signals for output to the first interface 310 and to process signals received through the first interface 310. The memory system 110 includes a similarly configured physical layer access block 322 for communicating over the first interface 310. One exemplary physical layer specification for communicating over the first interface 310 is the MIPI M-PHY® physical layer specification.

[0037]

[0047] The host device 102 also includes a data link layer block 314 configured to format data frames for transmission over the first interface 310. The frames may be provided to the physical layer access block 312 for transmission. The data link layer block 314 can receive frames from the physical layer access block 312 and decode the data frames received over the first interface 310. The memory system 110 includes a similarly configured data link layer block 324 for processing frames transmitted or received over the first interface 310 by the physical layer access block 322. One exemplary data link protocol for communication over a MIPI M-PHY® physical link is the MIPI UNIPRO® specification.

[0038]

[0048] The memory system 110 includes N logical units 350a to n, each containing a logical memory block for storing information including user data (e.g., user documents, application data) and configuration data (e.g., information regarding the operation of the memory system 110). The logical units 350a to n may be mapped to portions of physical memory blocks 152, 154, and 156. Some or parts of the logical units 350a to n may be configured as a specific memory type (e.g., default, system code, non-persistent, extended) with write protection, boot functionality, priority access, or as a replay-protected memory block (RPMB) with replay protection. The physical layer access block 322 and the data link layer block 324 perform the operations of the memory controller of the memory system 110 for storing and retrieving data from the logical units 350a to n. As one specific example, one or more of the logical units 350a to n may be configured as a buffer for storing PHY configuration information, such as one or more patches for configuring interface 310 to operate at different speeds, as described herein. The buffer's logical units may be configured to be accessible before the memory system 110 is fully initialized, such as before the fDeviceInit operation for the memory system is completed, allowing the speed of communication over interface 310 to increase early in the host device 102's boot process. The fDeviceInit operation may be an initialization operation for the memory system. In some embodiments, the fDeviceInit flag may be set at the start of the initialization operation for the UFS memory system and reset when the initialization of the memory system is complete. In some embodiments, the buffer's logical units may be locked or configured as read-only to prevent modification of the PHY configuration information.

[0039]

[0049] The memory system 110 also includes a configuration structure 352. The configuration structure 352 may include information such as configuration descriptors for boot enable (bBootEnable), initial power mode (bInitPowerMode), RPMB active (bRPMBRegionEnable), and / or RPMB region sizes (bRPMBRegion1Size, bRPMBRegion2Size, bRPMBRegion3Size). Such a configuration structure may be specified, for example, by the UFS standard.

[0040]

[0050] The host device 102 may be configured to run one or more applications 334, such as user applications, which are executed by the operating system under the user's control, in order to receive user input and provide the user with information stored in the memory system 110. The host device 102 may include several components for interface the applications 334 to the memory system 110 through a first interface 310. For example, a SCSI driver 332 and a UFS driver 330 may interface the applications 334 to a host memory controller, which includes a data link layer block 314 and a physical layer access block 312. The SCSI driver 332 may run at the application layer to process transactions requested by the applications 334 using the memory system 110. The UFS driver 330 may run at the transport layer and manage the operation of the data link layer block 314, such as to operate the first interface 310 in one of several operating modes. The operating mode may include two or more gear settings, such as one or more PWM-GEAR settings specifying one bitrate from 182MBps, 364MBps, 728MBps, and 1457MBps, and four or more HS-GEAR settings.

[0041]

[0051] The first interface 310 may include one or more lines, including a reset RST line, a reference clock REF_CLK line, a data-in DIN line (for transmitting data from the host device 102 to the memory system 110), and a data-out DOUT line (for transmitting data from the memory system 110 to the host device 102). The DIN line and the DOUT line may be two separate conductors, or the DIN line and the DOUT line may include multiple conductors. In some embodiments, the DIN line and the DOUT line may be asymmetric, with a DIN line containing N conductors and a DOUT line containing M conductors, where N > M or M > N.

[0042]

[0052] The UFS driver 330 can generate and decrypt packets to execute a transaction requested by application 334. The packets are transmitted via the first interface 310. The packets can be formatted as UFS Protocol Information Units (UPIUs). In a transaction with memory system 110, the host device 102 is the initiator and memory system 110 is the target. Based on the type of transaction, the UFS driver 330 can form one of several types of UPIUs to handle SCSI commands, data operations, task management operations, and / or query operations. Each transaction may include one command UPIU, zero or more DATA IN or DATA OUT UPIUs, and a response UPIU. Each UPIU may include a header followed by optional fields, depending on the type of UPIU.

[0043]

[0053] One exemplary transaction is a read operation. A read transaction may involve an initiator (e.g., host device 102) sending a command UPIU to a target (e.g., memory system 110) to perform a read operation requested by application 334. In response to the command UPIU, the target provides one or more DATA IN UPIUs, which contain the requested data. The read transaction is completed when the target sends a response UPIU.

[0044]

[0054] Another exemplary transaction is a write operation. A write operation may involve an initiator (e.g., host device 102) sending a command UPIU to a target (e.g., memory system 110) to perform a write operation requested by application 334. The target provides a Ready to Transfer UPIU signaling the initiator to begin transferring the write data. The initiator then sends one or more DATA OUT UPIUs, followed by Ready to Transfer UPIUs signaling the initiator to continue transferring the write data. The sequence of DATA OUT UPIUs and Ready to Transfer UPIUs continues until all the write data has been delivered to the target, after which the target provides a response UPIU to the initiator.

[0045]

[0055] A further exemplary transaction is a query operation. A query operation may involve an initiator (e.g., host device 102) requesting information about a target (e.g., memory system 110). The initiator may send a query request UPIU to request information such as the target's configuration, enumeration, device descriptors, flags, and / or attributes. Exemplary query operations include reading a descriptor, writing a descriptor, reading an attribute, writing an attribute, reading a flag, setting a flag, clearing a flag, and / or toggling a flag. Exemplary descriptors include device, configuration, unit, interconnect, string, geometry, power, and / or device health. Exemplary flags include fDeviceInit, fPermanenetWPEn, fPowerOnWPEn, fBackgroundOpsEn, fDeviceLifeSpanModeEn, fPurgeEnable, fRefreshEnable, fPhyResourceRemoval, fBusyRTC, and / or fPermanentlyDisableFwUpdate. Examples of attributes include bBootLunEn, bCurrentPowerMode, bActiveICCLevel, bOutOfORderDataEn, bBackgroundOpStatus, bPurgeStatus, bMaxDataInSize, bMaxDataOutSize, dDynCapNeeded, and bRefClkFreq. Such flags may be flags specified, for example, by the UFS standard.

[0046]

[0056] The operations and capabilities described above can be used for a memory system that supports adjusting the PHY configuration according to PHY configuration information stored in the memory of a memory system connected to a host device by the PHY, in order to enable improved communication speed via the PHY. Using a memory buffer in the memory system to store the PHY configuration information allows the PHY configuration to be updated before the host device initialization process is complete, for example, before the initialization of the memory where the buffer is located is complete, and as a result, the PHY configuration information is retrieved from memory before the memory is fully initialized.

[0047]

[0057] As described herein, a host device may be connected to a memory system, such as a UFS flash memory system, via a PHY. In some cases, the host device, memory system, and PHY may be integrated into a single SoC. During host device initialization or booting, the PHY may be configured to operate at different speeds during different parts of the initialization process. In some systems, such as those where the host device is connected to a UFS or NVMe memory system, initialization may require a considerable amount of time, such as 34–150 mS, due to the initialization of the PHY connecting the host device to the memory system, link startup requirements such as link initialization and negotiation between the host device and the memory system, and firmware initialization such as preparing logical-to-physical (L2P) tables and other background activities for the host device and / or memory system. Initialization time may vary based on vendor and device type. In particular, different devices manufactured by different vendors may require different amounts of time for different initialization stages and operations, such as link startup, no-operation messaging (NOP), fDeviceInit, and other operations. Initialization time can be affected by PHY initialization time, link startup time, the slow PHY operating speed when reading from the boot ROM, and multiple UFS initialization processes executed during the initialization process. In some use cases, such as automotive applications, a shorter initialization time, such as less than 50ms, may be desirable.

[0048]

[0058] During the initialization of a host device, the PHY connecting the host device to the memory system may operate at different link speeds at different times. Such initialization may include the initialization of the PHY connecting the host device to the memory system, the initialization of the host device, and the initialization of the memory system. Increasing the speed at which the PHY is configured to operate during one or more initialization processes may reduce the amount of time required for the initialization process. An exemplary initialization process 400 may include the initialization of the PHY, the memory system, and other systems and / or devices. The initialization process 400 may also be called the boot process and may be divided into several stages, as shown in Figure 4A. In a first stage 402, which may be a pre-boot loader (PBL) stage, the PBL may configure the PHY to operate at a lower speed, such as high-speed gear one (HS-G1) speed. For example, the PHY may be configured by the PBL in the first stage 402 to operate at HS-G1 speed in order to minimize post-silicon changes to the PHY that may require PBL patching. At the start of the first stage 402, the PHY may be configured to operate at a pulse width modulation 1 (PWM-1) speed, which may be slower than the HS-G1 speed. In operation 418, the host device, PHY, and memory system may be powered on and initialized to operate at a slow speed, such as PWM-1. For example, such operations may include a power-on reset, a hardware reset, and an endpoint reset. After such resets are performed, there may be no active tasks in the device UFS descriptor, and attributes and flags may be set to their default values. In addition, the UniPro attribute may be reset. The memory system may be minimally initialized to allow the memory system to begin communicating with the host device via the PHY, and a link-start procedure may be performed. Such a link-start procedure may initialize the earliest link between the host device and the memory system via the PHY. Once operation 418 is complete, the PHY speed may be increased to the HS-G1 speed.In operation 420, the host device may read from one or more boot look-up numbers (LUNs). In the second stage 404, a complete reinitialization of the memory system may be performed, and the operating speed of the PHY may be increased to high speed gear 4 (HS-G4) speed. For example, in operation 422, the memory system, which may be a UFS memory system, and the PHY may be reset, and a link start procedure may be performed. After the reset, the PHY speed may be reduced to PWM-1 speed in operation 424 until the UFS is reinitialized, NOP OUT is sent by the host device, NOP IN is received by the host device, and memory system initialization stages such as fDeviceInit are completed. After operation 424 is completed, the PHY may be configured to operate at HS-G4 speed, and the PHY may read from all LUNs of the memory system in operation 426. Speeds such as PWM-1, HS-G1, HS-G2, HS-G3, and HS-G4 may be speeds specified, for example, by the UFS standard.

[0049]

[0059] During the initialization process 400, multiple resets and initializations of the memory system may be performed. For example, a first reset and initialization in the first stage 402, and a second reset and initialization in the second stage 404. Such resets and associated initialization and link-start operations may substantially contribute to the initialization time. For example, a link-start associated with a reset may contribute up to 80 ms and beyond to the initialization time, and each link-start adds 20-30 ms to the initialization time. Furthermore, during a later boot stage, a complete re-initialization may be performed on the PHY and memory system, including configuring the PHY for operation at HS-G4 speed, the link-start procedure, the fDeviceInit procedure, and other startup operations. The link-start performed in operation 422 may invalidate and / or reset any initialization performed by the memory system prior to operation 422.

[0050]

[0060] To reduce initialization times such as boot time, the host device may perform one initialization of the memory system and PHY during the initialization procedure. However, during PBL stage 402, in order to enable the PHY to be initialized for faster operation, PHY configuration information stored in memory such as the memory system's flash memory may be used to patch the PHY for faster operation, such as HS-G4 speed. For example, one or more of the link-start and initialization procedures for the memory system may be eliminated by having the PHY and link-start procedures run only once during the entire initialization procedure. In some cases, two link-start and one device initialization procedure may be eliminated. Eliminating one or more reinitialization procedures for the PHY and / or memory system may reduce the initialization time by up to 70 ms or more. Furthermore, the memory system may be configured to complete initialization in the background during the second stage 404 and subsequent stages, which may allow skipping one or more NOP and fDeviceInit operations performed during the second initialization stage 404. The PHY may also be initialized during the PBL phase to operate at a faster speed, such as HS-G4 instead of HS-G1, further reducing the initialization time. For example, as shown in process 450 in Figure 4B, the PHY speed may be increased from the PWM-1 speed at the start of the first phase 402 of the initialization process to the HS-G4 speed. The host device may then read from the boot LUN at 420 at the HS-G4 speed instead of HS-G1, as shown in Figure 4A. Furthermore, operation 422 may be bypassed, and operation 452 may include a complete initialization of the memory system, including the fDeviceInit operation, while the PHY remains configured to operate at the HS-G4 speed through the second phase 404 and subsequent phases.

[0051]

[0061] Configuring the PHY to operate at high speeds early in the boot process, such as faster than HS-G1, may involve updating the PHY configuration. Such updates may present challenges due to limitations on post-silicon updates for PHY firmware and PBL ROM patching. Configuring the PHY to operate at high speeds early in the boot process, such as during PBL stage 402, may increase the risk of PBL patching requirements due to post-silicon PHY characterization and may also increase the risk of post-silicon PHY changes due to customer board-specific adjustments. Enabling PHY configuration updates to facilitate faster PHY operation than HS-G1 during PBL stage 402 may involve using additional PBL patch space allocation to support such patching and to support UFS PHY updates that may occur following post-silicon characterization. Such additional PBL patch space may increase the cost of the SoC, including the host device, PHY, and memory system. However, such problems may be mitigated through the use of buffers located on memory, such as flash memory in the memory system, to store PHY configuration information, such as one or more PHY patches, in order to update the PHY to operate at higher speeds. For example, the PHY may be patched early in the initialization process, for instance after minimal initialization of the memory system in operation 418, and before the initialization of the memory system is complete, for example before the fDeviceInit operation in 452 is completed, using PHY configuration information stored in a memory buffer of an accessible memory system. Updating the PHY configuration to operate at an improved speed early in the initialization process can reduce the amount of time required for the initialization process to complete. For example, in process 400 in Figure 4A, the PHY may be configured to operate at HS-G1 speed during PBL phase 402, and in process 450 in Figure 4B, the PHY may be configured to operate at HS-G4 or other faster speeds during PBL phase 402. The speed at which the PHY can be reconfigured to operate may be limited by the version of the UFS specification supported by the PHY.For example, if the PHY supports UFS2.x, a maximum speed of 2L with high speed gear three (HS-G3), rate B may be supported; if the PHY supports UFS3.1, a speed of 2L with HS-G4, rate B may be supported; and if the PHY supports UFS4.0, a speed of 2L with high speed gear five (HS-G5), rate B may be supported.

[0052]

[0062] As one specific example, Figure 5 is a flowchart illustrating an exemplary initialization process that may be similar to the initialization process 400 in Figure 4A. In some embodiments, the steps of Method 500 may be performed by a host device connected to a memory system by a PHY. In some embodiments, one or more of the steps may be performed by the PHY and / or the memory system. Method 500 may include, in block 502, configuring the PHY connecting the host device to the memory system to operate at a first speed, such as a high-reliability speed mode. Such a speed mode may be, for example, an HS-G1 speed. Such a configuration may be performed by the PBL of the host device.

[0053]

[0063] In block 504, a first link invocation may be performed. For example, the link between the host device and the memory system may be initialized. During such a stage, the PHY may operate at a PWM-1 speed. Such a link invocation may include sending a NOP OUT message to the memory system controller and receiving a NOP IN message from the memory system controller.

[0054]

[0064] In block 506, a gear change may be performed so that the PHY operates at HS-G1 speed. Such a gear change may be performed, for example, based on the configuration of block 502.

[0055]

[0065] In block 508, a device query may be sent from the host device and received by the memory system, and the host device may receive a response from the memory system. The response may include information about the memory system, such as the class of the memory system, the boot process configuration of the memory system, one or more LUNs of the memory system where the boot information is stored, the boot sequence ID, and other information for the initialization of the host device, PHY, and memory system.

[0056]

[0066] In block 510, the host device may read information from one or more boot LUNs. Such information may include, for example, boot code for initializing the host device, PHY, and / or memory system. In particular, the host device may read boot code from the boot-known logic unit by sending one or more Small Computer System Interface (SCSI) READ requests to the memory system.

[0057]

[0067] In block 512, a UFS reset may be performed on the memory system. For example, a host device may completely reset the memory system to facilitate the configuration of the PHY for faster operation.

[0058]

[0068] In block 514, the PHY may be configured to operate at an increased speed, such as in high-speed mode. For example, the PHY may be configured to operate in the highest speed mode, such as HS-G4 speed. Such a configuration may be performed, for example, by software.

[0059]

[0069] In block 516, a link initiation procedure may be executed. The link initiation procedure in block 516 may be, for example, a second or third link initiation procedure of the initialization process.

[0060]

[0070] In block 518, the fDeviceInit operation may be performed to complete the initialization of the memory system.

[0061]

[0071] In block 520, a gear change may be performed to allow the PHY to operate in a high-speed mode, such as HS-G4 speed mode. In some embodiments, such a configuration may include a configuration for operating in the highest speed mode supported by the memory system. For example, the operating speed of the PHY may be increased from PWM-1 to HS-G4.

[0062]

[0072] In block 522, a device query may be sent from the host device and received by the memory system, and the host device may receive a response from the memory system. Such operation may be similar to the operation described in block 508.

[0063]

[0073] In block 524, the host device may read information from one or more boot LUNs.

[0064]

[0074] However, using PHY configuration information from a memory buffer in the memory system can shorten boot time by enabling the PHY to operate faster earlier in the boot process and by enabling the bypass of one or more reset, initialization, and link-start operations. For example, the operations in blocks 512-516 of method 500 can be bypassed through the use of such configuration information. An exemplary method 600, which includes increasing the speed of the PHY early in the boot process using PHY configuration information stored in a buffer in the memory system connected to the host device by the PHY, is shown in Figure 6. Method 600 may include, in block 602, configuring the PHY connecting the host device to the memory system to operate at a first speed, such as operating in a reliable low-speed mode. The first speed may be, for example, an HS-G1 or PWM-1 speed. Such a configuration may be performed by the host device's PBL to enable the host device to read from a buffer storing the PHY configuration information, such as from the SoC buffer.

[0065]

[0075] In block 604, a link start may be performed. For example, the link between the host device and the memory system may be initialized. During such a stage, the PHY may operate at a PWM-1 speed. The link start in block 604 may be the only link start procedure performed in method 600, for example, or multiple link start procedures may be performed in method 500.

[0066]

[0076] In block 606, the host device may read PHY configuration information from a buffer, such as a buffer in the memory system. As described herein, the PHY configuration information may include one or more patches for patching the PHY. The PHY configuration information may include, for example, instructions for patching the PHY to operate at a faster speed. In some embodiments, the PHY configuration information may include information identifying the timing of patching the PHY, the clock speed of the PHY, and other information for configuring the PHY. The PHY configuration information may be transferred by the PHY from the memory system to the host device while the PHY is operating at a speed of PWM-1 or HS-G1. In some embodiments, the buffer may be an SoC buffer. In some embodiments, the buffer may be located in an OEM-customized data area of ​​the memory. For example, the buffer may be located in a data area of ​​a configuration descriptor field to allow the host device to program and / or lock arbitrary host-specific data. Thus, the buffer may be located in the read-only memory of the host device. The host device may be able to access such data with minimal latency early in the initialization of the memory device, such as early in the PBL initialization phase. For example, in some embodiments, such data may be accessible within 5 ms from the start of the initialization process. For example, such data may be accessible by the host device before it begins reading from one or more boot LUNs in the memory system. However, such data may be protected to prevent modification after the device leaves the factory, and therefore such areas may be marked as read-only. However, storing PHY configuration data in a buffer of read-only memory in the host device may require an increase in the amount of read-only memory, which may increase the device cost.

[0067]

[0077] As another example, the buffer may be located in non-volatile memory, such as the flash memory of the memory system. The buffer may be labeled SoC_BUFFER. Data stored in the buffer may be accessible at any point after the RST_n function has been executed early in the boot process. The buffer may be available for writing PHY configuration information, such as writing one or more PHY patches, during the device provisioning phase using the WRITE BUFFER command. The buffer may then be locked using the bConfigDescrLock command, which may make the buffer read-only. Such a buffer may provide low-latency access to the PHY configuration information. In some embodiments, the latency of such a buffer may be lower than that of a buffer stored in NAND memory. As one particular example, the host may determine that a PHY configuration buffer in the memory system's memory is supported when the MODE variable is set to 02h and the buffer ID is set to F0h. The PHY configuration information may be read from the buffer by the host device using the READ BUFFER command during initialization. In some embodiments, PHY configuration information may be read from the buffer by the host device before the initialization of the memory system is complete, such as the initialization of the flash memory in which the buffer is located. The PHY configuration information stored in the buffer may include information for adjusting the PHY configuration to operate at a faster speed. For example, the PHY configuration information may include information for patching the PHY to operate at the highest speed supported by the UFS version of the memory system. In some embodiments, the buffer may include a library of PHY patches for different maximum PHY speeds, and the PHY patches may be selected based on the UFS version of the memory system. In some embodiments, buffer labels, commands, and functions may be labels, functions, and commands identified by the UFS standard.

[0068]

[0078] In block 608, the PHY may be configured to operate at a second, higher speed based on PHY configuration information. For example, the PHY configuration may be updated based on PHY configuration information stored in a buffer, such as an SoC buffer. For example, the PHY configuration may be updated to adjust the PHY speed from a first, slower speed such as PWM-1 or HS-G1 to a higher speed such as high-speed gear 2 (HS-G2), HS-G3, HS-G4, HS-G5, or another higher speed. Such adjustments may include, for example, patching the PHY.

[0069]

[0079] In block 610, a second link activation procedure may be performed. For example, the link between the host device and the memory system via the PHY may be re-established.

[0070]

[0080] In block 612, gear switching may be performed on the PHY, and the PHY may start operating at a faster speed, supported by adjustments to the PHY configuration. For example, the PHY may start operating at speeds HS-G2, HS-G3, HS-G4, and HS-G5.

[0071]

[0081] In block 614, a device query may be sent from the host device and received by the memory system, and the host device may receive a response from the memory system. Such operation may be similar to the operation described in block 508.

[0072]

[0082] In block 616, the host device can read from one or more boot LUNs of the memory system at a faster speed, supported by a PHY such as HS-G4.

[0073]

[0083] In block 618, the fDeviceInit operation may be performed, and the initialization of the memory system may be completed. Therefore, the PHY configuration information may be read from the memory of the memory system, and the PHY may be configured to operate at a faster speed based on the PHY configuration information before the initialization of the memory system is completed. For example, in the method described with respect to Figure 5, without a buffer containing the PHY configuration information, the PHY cannot operate at maximum speed until after the fDeviceInit operation is completed. However, as described with respect to Figure 6, if a buffer containing the PHY configuration information is used to update the PHY configuration, the PHY may be able to operate at a faster speed, such as HS-G4, even before the initialization of the memory containing the buffer is completed.

[0074]

[0084] In block 620, a device query may be sent from the host device and received by the memory system, and the host device may receive a response from the memory system. Such operation may be similar to the operation described in block 508.

[0075]

[0085] In block 622, the host device can proceed to read from all LUNs. For example, data can be read from all LUNs in the memory system at the highest supported speed. Therefore, using PHY configuration information stored in a buffer to patch the PHY to operate faster earlier in the boot process can reduce the boot process time.

[0076]

[0086] Figure 7 is a flowchart illustrating a method, according to several embodiments of the present disclosure, for updating the configuration of a PHY by a host controller to operate at high speed early in the initialization process. Method 700, in block 702, includes the host controller of a host device initializing a PHY that connects the memory controller of a host device to a memory system to operate at a first speed. For example, the host device, PHY, and memory system may be included in an SoC. The initialization process for the host device may include the initialization of the PHY and the memory system. The memory system may be, for example, a UFS memory system including one or more flash memories. The initialization process may also be called a boot process. The PHY may be initialized, for example, when the memory system is powered on and minimal initialization is completed, to operate at a first speed. The first speed may be a low speed, for example, a PWM-1 speed or an HS-G1 speed. The initialization process may include, for example, a link startup process, also called a link initialization process, for initializing the link between the memory controller of the host device and the memory system via the PHY. Such initialization may be performed, for example, by the PBL of the host device during the PBL phase of the host device initialization.

[0077]

[0087] In block 704, the memory controller of the host device may send a request for PHY configuration information to configure the PHY to operate at a second speed. For example, the memory controller may send a request to the memory system via the PHY to a first buffer of the memory system for PHY configuration information to configure the PHY to operate at a second speed. The PHY configuration information may include, for example, PHY patches associated with a second speed faster than the first speed. For example, the PHY configuration information may include higher gear parameters for PHY reconfiguration. As another example, the PHY configuration information may include one or more post-silicon updates to the PHY configuration, such as updates to increase the PHY speed, updates to patch one or more PHY bugs, updates to optimize the PHY for operation with a particular host device and / or memory system, or updates to adjust PHY operation in a different way. For example, the PHY configuration information may include one or more PHY tuning parameters. The first buffer may be, for example, an SoC buffer stored on the flash memory of the memory system. The buffer may be a portion of memory in the memory system, such as flash memory allocated for use by the host device to store PHY configuration information and, in some embodiments, other information. Other information stored in the buffer may include other information for the configuration of the host device and / or SoC, such as information for use by the host device before the initialization of the memory system is complete. Other information stored in the buffer may include SoC or host configuration information for enabling or disabling hardware or software interfaces and / or for adjusting other hardware or software configuration parameters. The buffer may include PHY configuration information for configuring the PHY to operate at one or more speeds faster than a first speed, such as HS-G2, HS-G3, HS-G4, HS-G5, or another faster speed. In some embodiments, the request may include, for example, a READ BUFFER command.Such commands may be used to access information stored in a buffer before the host device is fully initialized and after the host device is fully initialized. The size of the buffer may be, for example, 4kB. In some embodiments, the buffer may store one or more PHY patches for patching the PHY to operate at one or more higher speeds. In some embodiments, the request may specify a particular PHY patch to be retrieved from the buffer. For example, the request may specify a PHY patch to configure the PHY to operate at the highest speed supported by the UFS version of the memory system. Such a request may be sent, for example, by the host device's PBL during the PBL phase of host device initialization. In some embodiments, the buffer may be configured as read-only to prevent revision of the PHY configuration information. In some embodiments, the request may be sent after receiving a first NOP IN from the memory system and before sending a first device query to the memory system.

[0078]

[0088] In some embodiments, after the host device has been fully initialized, the buffer may be updated using the WRITE BUFFER command. For example, if the bConfigDescrLock variable is set to 00h, the memory system may process a WRITE BUFFER command targeting the buffer. However, in some embodiments, the buffer may be locked and read-only. In such embodiments, the bConfigDescrLock variable may be set to a value of 01h, and the memory system, such as the memory controller of the memory system, may terminate an received WRITE BUFFER command targeting the buffer with a CHECK CONDITION STATUS having a SENSE KEY variable set to DATA PROTECT. In some embodiments, the buffer variables and commands may be variables and commands identified by the UFS standard.

[0079]

[0089] In block 706, the host device's memory controller may receive PHY configuration information from the memory system. For example, the requested PHY configuration information may be received by the memory controller via the PHY that connects the host device's memory controller to the memory system. The requested PHY configuration information may also be received by the host device's PBL during the PBL phase of the host device's initialization.

[0080]

[0090] In block 708, the host device's memory controller may adjust the PHY configuration to operate at a second speed according to PHY configuration information. For example, the memory controller may apply a patch of configuration information to the PHY to adjust the PHY configuration so that the PHY begins to operate at a second, faster speed. The memory controller may then proceed to communicate with the memory system at a second, faster speed via the PHY. The PHY configuration may be adjusted by the host device's PBL during the PBL phase of the host device's initialization, for example. In some embodiments, the host device's memory controller may be configured to complete the initialization of the memory system, such as initializing flash memory containing a buffer for storing PHY configuration information, following the adjustment of the PHY configuration for operation at a second speed. For example, some or all of the fDeviceInit operation may be performed and completed after the PHY configuration has been updated for operation at a second speed. Therefore, the PHY configuration may be updated to increase the PHY speed during the PBL phase of the initialization process, and the PHY may advance to facilitate faster communication between the host device and the memory system during the PBL phase of the initialization process and subsequent phases of the initialization process. Using such a buffer may enable post-silicon updates to facilitate improved PHY speed without requiring additional boot read-only memory for the host device. Thus, such a buffer may enable an optimized boot process, reducing initialization time, enabling the storage of higher gear parameters, and enabling the PHY to be reconfigured to operate faster during the PBL and boot loader phases of initialization. By including a buffer on the memory of the memory system, optimization of the host device's boot read-only memory may be possible. For example, instead of requiring a new die spin if a read-only memory error or inefficiency is found in the host device's read-only memory, the buffer may store patches to the ROM code to resolve the error and / or improve performance.Furthermore, such buffers may be used to store one or more custom actions for one or more stages of host device initialization.

[0081]

[0091] Figure 8 is a flowchart of a method 800 for updating the configuration of a PHY to operate at high speed early in the initialization process by a flash memory system, according to some embodiments of the present disclosure. The memory system may be connected to a memory controller of a host device via the PHY, for example. Method 800 may be performed by the memory controller of the flash memory system. Method 800 includes, in block 802, after the PHY connecting the memory controller to the host device has been initialized to operate at a first speed, the memory controller of the memory system receiving a request from the host device for PHY configuration information to configure the PHY to operate at a second speed faster than the first speed, from a first buffer. The request may be, for example, the request described with respect to block 704 in Figure 7, and the buffer may be a buffer storing PHY configuration information such as one or more PHY patches, as described with respect to Figure 7.

[0082]

[0092] In block 804, the memory controller may send PHY configuration information to the host device. For example, the memory controller of a memory system may send requested PHY configuration information to the memory controller of the host device to update the PHY, as described with respect to block 706 in Figure 7. Thus, the memory controller may receive a request and send PHY configuration information before the memory system is fully initialized, for example, before the fDeviceInit operation of the memory system is completed. The host device may then adjust the configuration of the PHY according to the PHY configuration information so that the PHY is configured to operate at a second speed. The host device may then proceed to communicate with the memory controller of the memory system via the PHY at a second speed.

[0083]

[0093] The operations of Method 500, Method 600, Method 700, or Method 800 may be performed by a UE such as the UE described with reference to Figure 9. For example, exemplary operations of Method 500, Method 600, Method 700, or Method 800 (also called “blocks”) may enable UE 915 to support higher user data confidentiality. Figure 9 is a block diagram detailing exemplary wireless communication systems in one or more embodiments. The wireless communication system may include a wireless network 900. The wireless network 900 may include, for example, a 5G wireless network. As will be understood by those skilled in the art, the components shown in Figure 9 are likely to have related corresponding parts, including other network configurations, such as cellular and non-cellular network configurations (e.g., device-to-device, peer-to-peer, or ad-hoc network configurations).

[0084]

[0094] The wireless network 900 shown in Figure 9 includes several base stations 905 and other network entities. A base station may also be a station communicating with a UE and may be called an evolved node B (eNB), next-generation eNB (gNB), access point, etc. Each base station 905 may provide communication coverage to a specific geographic area. In 3GPP, the term “cell” may refer to this specific geographic coverage area of ​​a base station or base station subsystem serving a coverage area, depending on the context in which the term is used. In the implementations of the wireless network 900 described herein, base stations 905 may be associated with the same operator or different operators (for example, the wireless network 900 may include multiple operator wireless networks). In addition, in the implementations of the wireless network 900 described herein, base stations 905 may provide wireless communication using one or more of the same frequencies as adjacent cells (e.g., one or more frequency bands in the licensed spectrum, unlicensed spectrum, or a combination thereof). In some examples, individual base stations 905 or UE915 may be operated by two or more network operations entities. In some other examples, each base station 905 and UE915 may be operated by a single network operations entity.

[0085]

[0095] Base stations can provide communication coverage to macrocells, or small cells such as picocells or femtocells, or other types of cells. Macrocells generally cover relatively large geographical areas (e.g., a radius of several kilometers) and may enable unrestricted access by UEs (Users) subscribed to a network provider's service. Small cells such as picocells generally cover relatively small geographical areas and may enable unrestricted access by UEs subscribed to a network provider's service. Small cells such as femtocells also generally cover relatively small geographical areas (e.g., a home) and, in addition to unrestricted access, may also provide restricted access by UEs associated with the femtocell (e.g., UEs within a closed subscriber group (CSG), UEs for users in a home, etc.). Base stations for macrocells are sometimes called macro base stations. Base stations for small cells are sometimes called small cell base stations, pico base stations, femto base stations, or home base stations. In the example shown in Figure 9, base stations 905d and 905e are standard macro base stations, while base stations 905a–905c are macro base stations enabled with one of the following: 3D MIMO, full-dimension (FD) MIMO, or massive MIMO. Base stations 905a–905c leverage their higher-dimensional MIMO capabilities to utilize 3D beamforming in both high-level and azimuth beamforming, increasing coverage and capacity. Base station 905f is a small cell base station that can be a home node or a portable access point. A base station may support one or more (e.g., two, three, or four) cells.

[0086]

[0096] The wireless network 900 may support synchronous or asynchronous operation. In synchronous operation, base stations may have similar frame timings, and transmissions from different base stations may be approximately synchronized in time. In asynchronous operation, base stations may have different frame timings, and transmissions from different base stations may not be synchronized in time. In some scenarios, the network may be enabled or configured to handle dynamic switching between synchronous and asynchronous operation.

[0087]

[0097] UE915 is distributed throughout the entire wireless network 900, and each UE may be fixed or mobile. Mobile devices are generally referred to as UEs in the standards and specifications published by 3GPP, but it should be noted that such devices may also be referred to by those skilled in the art in additional or other ways as mobile station (MS), subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal (AT), mobile terminal, wireless terminal, remote terminal, handset, terminal, user agent, mobile client, client, game device, augmented reality device, vehicle component, vehicle device, or vehicle module, or any other appropriate term. For the purposes of this document, a “mobile” device or UE does not necessarily have to be mobile and may be fixed. Some non-exclusive examples of mobile devices that may include one or more implementations of UE915 include mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, laptops, personal computers (PCs), notebooks, netbooks, smartbooks, tablets, and personal digital assistants (PDAs).The mobile device may further include IoT or "Internet of Everything (IoE)" devices such as automobiles or other transport vehicles, satellite radios, global positioning system (GPS) devices, global navigation satellite system (GNSS) devices, logistics controllers, flight devices, smart energy or security devices, solar panels or solar arrays, urban lighting, water, or other infrastructure, industrial automation and enterprise devices, consumer and wearable devices such as eyewear, wearable cameras, smartwatches, health or fitness trackers, mammalian implantable devices, gesture tracking devices, medical devices, digital audio players (e.g., MP3 players), cameras, game consoles, and digital home or smart home devices such as home audio, video, and multimedia devices, home appliances, sensors, vending machines, intelligent lighting, home security systems, and smart meters. In one embodiment, the UE may be a device including a Universal Integrated Circuit Card (UICC). In another embodiment, the UE may be a device not including a UICC. In some embodiments, a UE that does not include UICC may also be called an IoE device. UEs 915a–915d in the implementation shown in Figure 9 are examples of mobile smartphone-type devices accessing the wireless network 900. UEs may also be machines specifically configured for connected communications, including machine-type communication (MTC), enhanced MTC (eMTC), and narrowband IoT (NB-IoT). UEs 915e–915k shown in Figure 9 are examples of various machines configured for communications accessing the wireless network 900.

[0088]

[0098] Mobile devices such as the UE915 may be able to communicate with any type of base station, including macro base stations, pico base stations, femto base stations, and repeaters. In Figure 9, the communication links (represented as lightning bolts) show wireless transmissions between the UE and a serving base station, which is a base station designated to service the UE on the downlink or uplink, or desired transmissions between base stations, and backhaul transmissions between base stations. In some scenarios, the UE may act as a base station or other network node. Backhaul communication between base stations in the wireless network 900 may be performed using wired or wireless communication links.

[0089]

[0099] In operation within the wireless network 900, base stations 905a–905c serve UEs 915a and 915b using coordinated spatial techniques such as 3D beamforming and coordinated multipoint (CoMP) or multi-connectivity. Macro base station 905d performs backhaul communication with base stations 905a–905c and small cell base station 905f. Macro base station 905d also transmits multicast services that UEs 915c and 915d subscribe to and receive. Such multicast services may include mobile television or stream video, or other services to provide community information, such as weather emergencies or alerts such as amber alerts or gray alerts.

[0090]

[0100] The implemented wireless network 900 supports mission-critical communications using ultra-high reliability redundant links for mission-critical devices such as the UE915e, which is an aircraft vehicle. The redundant communication links with the UE915e include those from macro base stations 905d and 905e, as well as from small cell base station 905f. Other mechanical devices such as the UE915f (thermometer), UE915g (smart meter), and UE915h (wearable device) can communicate through the wireless network 900 either directly with base stations such as the small cell base station 905f and macro base station 905e, or with other user devices that relay their information to the network in a multi-hop configuration. For example, the UE915f can communicate temperature measurement information to the smart meter UE915g, and then that information can be reported to the network via the small cell base station 905f. The wireless network 900 can also provide further network efficiency through dynamic low-latency TDD communication or low-latency FDD communication in vehicle-to-vehicle (V2V) mesh networks between UE915i~915k communicating with macro base stations 905e.

[0091]

[0101] In various implementations, techniques and devices may be used for wireless communication networks such as code division multiple access (CDMA) networks, time division multiple access (TDMA) networks, frequency division multiple access (FDMA) networks, orthogonal FDMA (OFDMA) networks, single-carrier FDMA (SC-FDMA) networks, LTE networks, GSM networks, 5th generation (5G) or new radio (NR) networks (sometimes referred to as "5G NR" networks, systems, or devices), and other communication networks. The terms "network" and "system" as used herein may be used interchangeably. For example, a CDMA network may implement wireless technologies such as universal terrestrial radio access (UTRA) and cdma2000. UTRA includes wideband-CDMA (W-CDMA) and low chip rate (LCR). CDMA2000 covers the IS-2000, IS-95, and IS-856 standards. TDMA networks can implement wireless technologies such as Global System for Mobile Communications (GSM). The 3rd Generation Partnership Project (3GPP), also known as GERAN, defines standards for GSM EDGE (GSM Evolutionary High-Speed ​​Data Rate) radio access networks (RAN). OFDMA networks can implement wireless technologies such as evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, and flash OFDM.UTRA, E-UTRA, and GSM are part of the Universal Mobile Telecommunication System (UMTS). In particular, Long-Term Evolution (LTE) is a UMTS release that uses E-UTRA. Various different network types may use different radio access technologies (RATs) and RANs.

[0092]

[0102] While this application describes embodiments and implementations by example to several embodiments, those skilled in the art will understand that additional implementations and use cases may arise in many different configurations and scenarios. The innovations described herein can be realized across many different platform types, devices, systems, forms, sizes, and packaging configurations. For example, implementations or applications may occur via integrated chip implementations or other non-modular component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail or purchasing devices, medical devices, AI-enabled devices, etc.). Some examples may or may not specifically address use cases or applications, but a wide range of applicable combinations of the innovations described may arise. Implementations can range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more of the described embodiments. In some practical settings, devices incorporating the embodiments and features described may also necessarily include additional components and features for the implementation and practice of the claims and embodiments described. The innovations described herein can be practiced in a wide variety of implementations, including both large and small devices of various sizes, shapes, and structures, chip-level components, multi-component systems (e.g., radio frequency (RF) chains, communication interfaces, processors), distributed configurations, and end-user devices.

[0093]

[0103] In one or more embodiments, techniques for supporting data storage and / or data transmission may include additional embodiments, such as any single embodiment or any combination of embodiments, described below or elsewhere in this specification with respect to one or more other processes or devices. In one embodiment, an electronic device such as a UE may be a device such as a host device including a memory controller configured to be coupled to a memory system via a physical interface (PHY), and the memory system may be integrated with the host device or coupled to the host device externally. The memory system may include a memory controller which is coupled to the memory system through a first channel and configured to access data stored in the memory system through the first channel, and is coupled to a host device via a first interface such as a PHY and configured to communicate with the host device via the first interface. The operation may be performed as part of an initialization operation, a read operation, or a write operation.

[0094]

[0104] In a first aspect, the memory controller of the memory system may be configured to perform an operation that includes, after the PHY has been initialized to operate at a first speed, receiving a request from a host device for PHY configuration information to configure the PHY to operate at a second speed faster than the first speed from a first buffer of the memory module, and transmitting the PHY configuration information to the host device.

[0095]

[0105] In the second embodiment, in combination with the first embodiment, the first buffer is located in the flash memory of the memory module.

[0096]

[0106] In the third embodiment, the transmission of PHY configuration information, in combination with one or more of the first or second embodiments, is performed before the initialization of the flash memory is complete.

[0097]

[0107] In the fourth embodiment, in combination with one or more of the first to third embodiments, the PHY is initialized to operate at a first speed during the link initialization phase of the host device initialization.

[0098]

[0108] In the fifth embodiment, in combination with one or more of the first to fourth embodiments, the PHY configuration information includes a PHY patch associated with a second speed.

[0099]

[0109] In the sixth aspect, in combination with one or more of the first to fifth aspects, the buffer stores multiple PHY patches associated with multiple speeds.

[0100]

[0110] In the seventh aspect, the first buffer is configured as read-only in combination with one or more of the first to sixth aspects.

[0101]

[0111] In the eighth aspect, the memory controller of the host device may be configured to perform operations including initializing the PHY to operate at a first speed; receiving PHY configuration information from a first buffer of the memory system for configuring the PHY to operate at a second speed faster than the first speed; and adjusting the configuration of the PHY to operate at the second speed according to the PHY configuration information.

[0102]

[0112] In the ninth aspect, in combination with the eighth aspect, the first buffer is located in the flash memory of the memory system.

[0103]

[0113] In the tenth embodiment, in combination with one or more of the eighth or ninth embodiment, the memory controller is further configured to complete the initialization of the flash memory after adjusting the PHY configuration.

[0104]

[0114] In the eleventh aspect, initializing the PHY to operate at a first speed, in combination with one or more of the eighth to tenth aspects, includes completing the link initialization stage of the host device initialization.

[0105]

[0115] In the twelfth aspect, in combination with one or more of the eighth to eleventh aspects, the memory controller of the memory system may be further configured to perform an operation which includes initializing the PHY to operate at a first speed and then sending a request to the memory system for PHY configuration information.

[0106]

[0116] In the 13th aspect, in combination with one or more of the 8th to 12th aspects, the PHY configuration information includes a PHY patch associated with a second speed, and adjusting the PHY configuration includes applying the PHY patch.

[0107]

[0117] In the 14th aspect, in combination with one or more of the 8th to 13th aspects, the buffer stores multiple PHY patches associated with multiple speeds.

[0108]

[0118] In the 15th aspect, the first buffer is configured as read-only in combination with one or more of the eighth to 14th aspects.

[0109]

[0119] Those skilled in the art will understand that information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips which may be mentioned throughout the above description may be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0110]

[0120] With respect to Figures 1 to 8, the components, functional blocks, and modules described herein include, in particular, processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, or any combination thereof. Software, whether called software, firmware, middleware, microcode, hardware description language, or otherwise, should be broadly interpreted in the examples to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, and / or functions. In addition, the features discussed herein may be executed via dedicated processor circuits, via executable instructions, or in combination thereof.

[0111]

[0121] Those skilled in the art will know that one or more blocks (or actions) described with reference to Figures 4A-4E, 5, 6, 7, or 8 may be combined with one or more blocks (or actions) described with reference to another of the figures. For example, one or more blocks (or actions) in Figure 1 may be combined with one or more blocks (or actions) in Figure 3. As another example, one or more blocks associated with Figure 1 may be combined with one or more blocks (or actions) associated with Figures 4A-4E, 5, 6, 7, or 8. As an addition or alternative, one or more actions described above with reference to Figures 1-3 may be combined with one or more actions described with reference to Figures 4-8.

[0112]

[0122] Those skilled in the art will further understand that various exemplary logic blocks, modules, circuits, and algorithmic steps described herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate this hardware-software compatibility, various exemplary components, blocks, modules, circuits, and steps have been outlined above in relation to their functionality. Whether such functionality is implemented as hardware or as software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may perform the described functionality in various ways for specific applications, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein are merely examples, and that components, methods, or interactions of various aspects of this disclosure may be combined or performed in ways other than those shown and described herein.

[0113]

[0123] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in relation to the implementations disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. Hardware and software compatibility is generally described with respect to functionality and is shown in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0114]

[0124] Hardware and data processing devices used to implement the various exemplary logics, logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or realized using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration. In some implementations, specific processes and methods may be performed by circuit mechanisms specific to a given function.

[0115]

[0125] In one or more embodiments, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, or any combination thereof, including the structures disclosed herein and their structural equivalents. Implementations of the subject matter described herein may also be implemented as one or more computer programs, which are one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device.

[0116]

[0126] Where implemented in software, these functions may be stored on or transmitted via computer-readable media as one or more instructions or code. The processes of the methods or algorithms disclosed herein may be executed in processor-executable software modules that reside on computer-readable media. Computer-readable media include both computer storage media and communication media, including any media that can enable the transfer of computer programs from one location to another. Storage media may be any available media that can be accessed by a computer. Such computer-readable media may include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Any connection may also be appropriately referred to as computer-readable media. The terms "Disk" and "Disc" as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where a disk typically reproduces data magnetically, while a disc reproduces data optically using a laser. Any combination of these should also be included within the scope of computer-readable media. In addition, the operation of a method or algorithm may reside on machine-readable and computer-readable media, which may be incorporated into computer program products as one or any combination or set of code and instructions.

[0117]

[0127] Various modifications of the implementations described herein may be readily apparent to those skilled in the art, and the general principles defined herein may be applied to several other implementations without departing from the spirit or scope of this disclosure. Accordingly, the claims should not be limited to the implementations shown herein, but should be given the broadest scope consistent with this disclosure, the principles disclosed herein, and novel features.

[0118]

[0128] In addition, it will be readily understood by those skilled in the art that antonyms such as "top" and "bottom," or "front" and "back," or "upper" and "lower," or "front" and "rear," are sometimes used to facilitate the description of a figure and indicate a relative position corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device being implemented.

[0119]

[0129] Some features described herein in the context of separate implementations may also be realized in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be realized separately or in any suitable partial combination in multiple implementations. Furthermore, even if features have been described above as functioning in a particular combination and are initially claimed as such, one or more features from the claimed combination may, in some cases, be removed from that combination, and the claimed combination may cover partial combinations or variations of partial combinations.

[0120]

[0130] Similarly, while actions are shown in a specific order in the diagrams, this should not be understood as requiring that such actions be performed in a specific or sequential order shown, or that all shown actions be performed, in order to achieve the desired result. Furthermore, diagrams may schematically represent one or more exemplary processes in the form of flow charts. However, other actions not shown may be incorporated into the schematicly represented exemplary processes. For example, one or more additional actions may be performed before, after, simultaneously with, or between any of the shown actions. In some situations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementation forms described above should not be understood as requiring such separation in all implementation forms, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged in multiple software products. In addition, several other implementation forms fall within the scope of the following claims. In some cases, the actions enumerated in the claims may be performed in a different order and still achieve the desired result.

[0121]

[0131] As used herein, including in the claims, the term “or” means that, when used in a list of two or more items, any one of the listed items may be taken alone, or any combination of two or more of the listed items may be taken. For example, if a composition is described as containing component A, B, or C, the composition may include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C. Also, as used herein, including in the claims, “or” means a disjunctive list, such as when the list “at least one of A, B, or C” means any of these in A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C), or any combination thereof. As those skilled in the art will understand, the term “substantially” means the majority of what is specified (for example, substantially 90 degrees includes 90 degrees, substantially parallel includes parallel), but not necessarily the whole. In any disclosed implementation, the term “substantially” may be replaced with “within [percentage] of” the specified percentage, including 0.1 percent, 1 percent, 5 percent, or 10 percent.

[0122]

[0132] The above description in this disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. It is a device, The host device comprises a memory controller configured to couple the host device to a memory system via a physical layer interface (PHY), wherein the memory controller Initializing the aforementioned PHY to operate at a first speed, The PHY configuration information for configuring the PHY to operate at a second speed faster than the first speed is received from a first buffer of the memory system. A device configured to perform an operation which includes adjusting the configuration of the PHY to operate at the second speed according to the PHY configuration information.

2. The apparatus according to claim 1, wherein the first buffer is located in the flash memory of the memory system.

3. The apparatus according to claim 2, wherein the memory controller is further configured to complete the initialization of the flash memory after adjusting the configuration of the PHY.

4. The apparatus according to claim 3, wherein initializing the PHY to operate at the first speed completes the link initialization step of the host device initialization.

5. The aforementioned memory controller The apparatus according to claim 1, further configured to perform an operation including initializing the PHY to operate at a first speed, and then sending a request to the memory system for PHY configuration information.

6. The apparatus according to claim 1, wherein the PHY configuration information includes a PHY patch associated with the second speed, and adjusting the configuration of the PHY includes applying the PHY patch.

7. The apparatus according to claim 6, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds.

8. The apparatus according to claim 1, wherein the first buffer is configured to be read-only.

9. It is a method, The host device's memory controller initializes the physical interface (PHY) for connecting the host device to the memory system to operate at a first speed, The PHY configuration information for configuring the PHY to operate at a second speed faster than the first speed is received from a first buffer of the memory system. A method comprising: adjusting the configuration of the PHY to operate at the second speed according to the PHY configuration information using the memory controller.

10. The method according to claim 9, wherein the first buffer is located in the flash memory of the memory system.

11. The method according to claim 10, further comprising completing the initialization of the flash memory after adjusting the configuration of the PHY.

12. The method according to claim 11, wherein initializing the PHY to operate at the first speed completes the link initialization step of the host device initialization.

13. The method according to claim 9, further comprising initializing the PHY to operate at the first speed, and then sending a request to the memory system for PHY configuration information.

14. The method according to claim 9, wherein the PHY configuration information includes a PHY patch associated with the second speed, and adjusting the configuration of the PHY includes applying the PHY patch.

15. The method according to claim 14, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds.

16. The method according to claim 9, wherein the first buffer is configured to be read-only.

17. It is a device, It is a memory controller, It is coupled to a memory module through a first channel and is configured to access data stored in the memory module through the first channel, and A memory controller is coupled to a host device through a first physical interface (PHY) and configured to communicate with the host device via the first PHY. The aforementioned memory controller After the PHY has been initialized to operate at a first speed, the host device receives a request for PHY configuration information from the first buffer of the memory module to configure the PHY to operate at a second speed faster than the first speed. A device configured to perform an operation which includes transmitting the PHY configuration information to the host device.

18. The apparatus according to claim 17, wherein the first buffer is located in the flash memory of the memory module.

19. The apparatus according to claim 18, wherein the transmission of the PHY configuration information is performed before the initialization of the flash memory is completed.

20. The apparatus according to claim 19, wherein the PHY is initialized to operate at the first speed during the link initialization phase of the host device initialization.

21. The apparatus according to claim 17, wherein the PHY configuration information includes a PHY patch associated with the second speed.

22. The apparatus according to claim 21, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds.

23. The apparatus according to claim 17, wherein the first buffer is configured for read-only use.

24. It is a method, After the physical interface (PHY) connecting the memory controller to the host device has been initialized to operate at a first speed, the memory controller receives a request from the host device for PHY configuration information to configure the PHY to operate at a second speed faster than the first speed, from a first buffer of a memory module coupled to the memory controller. A method comprising transmitting the PHY configuration information to the host device by the memory controller.

25. The method according to claim 24, wherein the first buffer is located in the flash memory of the memory module.

26. The method according to claim 25, wherein the transmission of the PHY configuration information is performed before the initialization of the flash memory is completed.

27. The method according to claim 26, wherein the PHY is initialized to operate at the first speed during the link initialization phase of the host device initialization.

28. The method according to claim 24, wherein the PHY configuration information includes a PHY patch associated with the second speed.

29. The method according to claim 28, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds.

30. The method according to claim 24, wherein the first buffer is configured to be read-only.

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