2x2 logic chiplet

Abstract

Embodiments of this specification describe various 2x2 configurations of integrated circuits (ICs) in which the ICs can communicate with multiple adjacent ICs using an inter-chip interface. Thus, the 2x2 configuration is an improvement over other horizontal chip integration formats (such as 1x2, 1x3, and 1x4) in which some of the ICs can only communicate directly with one of the other ICs.

Description

Technical Field

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[0001] Examples of the present disclosure generally relate to arranging integrated circuits in a 2×2 configuration.

Background Art

[0002] Many devices include a plurality of integrated circuits (or dies or chips) interconnected on a substrate or an interposer. That is, chip interconnects can be used to form devices such as 1×2, 1×3, 1×4, etc. However, in a 1×2 configuration, two integrated circuits (ICs) communicate using only one side, which limits the number of inter-chip signals. In a 1×3 configuration, only the central chip uses multiple sides to communicate with other chips. Similarly, in a 1×4 configuration, only two of the four ICs can use multiple sides to communicate with other chips.

Summary of the Invention

[0003] One embodiment described herein includes an interposer having horizontal and vertical stitches formed from overlapping exposure regions, and four integrated circuits (ICs) disposed on the interposer in a 2×2 configuration, each of the four ICs being connected to adjacent ICs on two sides via the interposer.

[0004] One embodiment described herein includes forming an interposer having horizontal and vertical stitches using overlapping exposure regions, and disposing four ICs on the interposer in a 2×2 configuration, each of the four ICs being connected to adjacent ICs on two sides via the interposer.

[0005] One embodiment described herein includes four integrated circuits (ICs) arranged in a 2×2 configuration, each of the four ICs being connected to adjacent ICs on at least two sides, and the four ICs having the same design.

Brief Description of the Drawings

[0006] The features listed above can be understood in detail, and more specific explanations, which are briefly summarized above, can be provided by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting in scope. [Figure 1] An example of a 2x2 configuration of ICs on an interposer is shown. [Figure 2] This is a flowchart illustrating how to form an interposer with horizontal and vertical stitching to support a 2x2 configuration of an IC, as an example. [Figure 3] An example of an interposer with horizontal and vertical stitching is shown. [Figure 4] An example of a 2x2 configuration of ICs using mirrored ICs is shown. [Figure 5] An example of a 2x2 configuration of ICs using a rotated IC is shown. [Figure 6] This example demonstrates the use of rotated ICs to improve yield. [Figure 7] This example demonstrates the use of a rotated IC to improve yield.

[0007] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements of one embodiment are intended to be usefully incorporated into other embodiments. [Modes for carrying out the invention]

[0008] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of features. They are not intended as an exhaustive description of the embodiments herein or as a limitation on the scope of the claims. In addition, illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment even if not illustrated or explicitly described in that way.

[0009] Embodiments of this specification describe various 2x2 configurations of ICs, in which the ICs can communicate with multiple adjacent ICs using an inter-chip interface. Thus, the 2x2 configuration is an improvement over other horizontal chip integration formats (such as 1x2, 1x3, and 1x4) in which some of the ICs can only communicate directly with one of the other ICs.

[0010] In one embodiment, ICs forming a 2x2 configuration are arranged on an interposer using horizontal and vertical stitching. The use of stitching allows the interposer to be larger than the reticle size, thereby enabling the arrangement of multiple dies (also constrained by the reticle size) on the same interposer. To form the horizontal and vertical stitching, the interposer can be manufactured using four exposure areas (smaller than or equal to the reticle size and slightly overlapping). The ICs are then arranged at the four corners of the interposer and can subsequently be interconnected using traces within the interposer.

[0011] While the ICs in a 2x2 configuration can vary, in one embodiment, two of the ICs are of the same design (e.g., exactly the same), and the other two ICs are mirror images of that design. This aligns the interfaces of the ICs, allowing for a straight connection in the interconnects when the ICs are arranged in a 2x2 configuration.

[0012] In another embodiment, the same IC can be used to form a 2x2 configuration, but the IC is rotatable so that it can form straight connections within the interconnect when connecting adjacent chips. By using straight connections, routing in the interconnect is simplified, allowing for more inter-chip connections to the interposer that supports connections crossing within the interposer.

[0013] In yet another embodiment, yield can be improved by using rotatable ICs. The IC manufacturing process often introduces defects into ICs. Instead of simply discarding defective ICs, defective ICs can be used to form devices that are sold with less capability or performance than devices containing only fully functional ICs. Using rotatable ICs means that defective ICs can be rotated when placed in the device, resulting in the defective areas of the IC being placed in unused parts of the device, thereby increasing yield.

[0014] Figure 1 shows an example of a 2x2 configuration of IC105 on an interposer 100. In this top view, the IC105s are positioned at each corner of the interposer 100. The interposer 100 provides connections between adjacent IC105s. For example, the interposer 100 may be a silicon interposer including one or more layers containing traces for forming connection sections 110. In one embodiment, the IC105s may be mounted on the interposer using, for example, copper pillars, which then electrically couple the IC105s to connection sections 110s that route electrical signals from one IC105 to an adjacent IC105.

[0015] Unlike 1x2, 1x3, or 1x4 configurations, where at least some ICs use only one side to communicate with adjacent ICs, in the 2x2 configuration shown in Figure 1, each IC 105 uses two sides to communicate with two adjacent ICs. For example, IC 105C communicates with IC 105D using the horizontal connection 110B and with IC 105A using the vertical connection 110A. Thus, the 2x2 configuration effectively doubles the amount of inter-chip connectivity each IC can have compared to some of the ICs in a 1x2, 1x3, or 1x4 configuration that communicate using only one side.

[0016] In this embodiment, the interposer 100 has a surface area exceeding the reticle limit of the manufacturing technique used to produce the interposer. The size of IC105 is limited by the reticle limit, which defines the amount of area that can be exposed and processed using the mask. Currently, for monolithic dies, the maximum size is limited to the reticle limit of 33-26 mm. Therefore, the width and height of IC105 are limited by this reticle limit.

[0017] For the interposer 100 to support multiple ICs 105 that are at or just below the reticle limit, the interposer 100 must have a surface area exceeding the reticle limit. This means that the interposer 100 cannot be manufactured using a single exposure process. Instead, the interposer 100 includes vertical stitches 120 and horizontal stitches 130 in which multiple exposure areas slightly overlap. This allows the interposer to still have traces for forming connections 110 and to have sufficient surface area to support a 2x2 configuration of ICs 105. The manufacturing of the interposer 100 is described in more detail in Figures 2 and 3.

[0018] In one embodiment, the interposer 100 has a total surface area that is three times the size of the reticle limit (e.g., maximum reticle field). Further, unlike interposers that may have only horizontal stitches and support 1×2, 1×3, and 1×4 configurations, the interposer 100 has both horizontal stitches 130 and vertical stitches 120.

[0019] FIG. 2 is a flowchart of a method 200 for manufacturing an interposer having horizontal and vertical stitches to support a 2×2 configuration of an IC, according to an example. In block 205, the method 200 forms an interposer having horizontal and vertical stitches. In one embodiment, in block 210, these stitches are formed by performing four overlapping exposures.

[0020] FIG. 3 shows an interposer 100 having horizontal stitches 130 and vertical stitches 120 formed using four exposure regions 305A - 305D. In this example, each exposure region 305 has a size that is less than or equal to the reticle limit (e.g., maximum reticle field). Thus, each of the exposure regions 305 can be fabricated using a separate set of masks.

[0021] As shown, exposure region 305A overlaps exposure region 305B on the right side and exposure region 305C at the bottom. Exposure region 305A also slightly overlaps exposure region 305D at the center of the interposer 100 (all four exposure regions 305 slightly overlap). In addition to overlapping exposure region 305A, exposure region 305B overlaps exposure region 305D at the bottom. Further, exposure region 305D overlaps exposure region 305C on the left side.

[0022] By ensuring that the exposure areas 305 slightly overlap, the ability to form vertical stitches 120 and horizontal stitches 130 in these overlapping portions is provided. If the exposure areas 305 are not overlapped (for example, when the exposure areas touch but are not overlapped), it is very difficult to pattern traces on the interposer 100 to form the chip-to-chip connections shown in FIG. 1. This is due to the misalignment between two exposures. In one embodiment, the overlap of the exposures and the minimum width and spacing of the features (metal lines) on the interposer 100 near the stitch zone are larger than the maximum misalignment. If the exposure areas 305 are not overlapped, it becomes difficult to pattern the traces extending between the exposure areas 305 to form the chip-to-chip connections 110 shown in FIG. 1.

[0023] Mask sets are expensive, but the masks for the interposer 100 currently formed using a 65 nm manufacturing process are much less expensive than the mask sets for ICs currently formed using a 7 nm or 3 nm manufacturing process. Therefore, it is relatively inexpensive to form an interposer that exceeds the reticle limit. In contrast, it may be impossible to use overlapping exposure areas to form an IC that exceeds the reticle limit using 7 nm or 3 nm technology.

[0024] Returning to method 200, in block 215, an interposer is used to connect four ICs in a 2×2 configuration. For example, the interposer may include bond pads to which the ICs are soldered. By doing so, the ICs are electrically connected to the chip-to-chip connections extending between adjacent ICs, as shown in FIG. 1.

[0025] Figure 4 shows an example of a 2x2 configuration of ICs using mirrored ICs. Although not labeled, the interposer 100 in Figure 4 may include the vertical and horizontal stitching described in the embodiments above. That is, the interposer 100 may exceed the maximum reticle field. However, this is not a requirement. For example, the interposer 100 may have dimensions within the maximum reticle field, but the ICs on the interposer 100 may be much smaller than the maximum reticle field and therefore can fit on the interposer 100.

[0026] Figure 4 shows two pairs of ICs arranged on an interposer in a 2x2 configuration. Each pair of ICs can be exactly the same (for example, they can be formed using the same mask set). In this embodiment, ICs 405A and 405B are the same IC, and ICs 410A and 410B are the same IC. The letter "F" indicates the rotation of the ICs relative to each other. In this example, IC 405A is the same as IC 405B but is rotated 180 degrees when placed on the interposer 100. Doing so allows the I / O and transceivers on IC 405 to be aligned with each other. As a result, the inter-chip connection between ICs 405A and 405B can be straight, which can greatly increase the number of inter-chip connections that can extend through the interposer 100, as described above. The same applies to IC 410 if IC 410A is the same as IC 410B but is rotated 180 degrees when placed on the interposer 100.

[0027] Furthermore, IC410A and 410B are mirror designs of IC405A and 405B. For example, after designing IC405A and 405B, the chip designer can instruct the software design application to mirror the design. This is indicated by the fact that the letter "F" on IC405A and 405B is a mirror image of the letter "F" on IC410A and 410B. By mirroring the ICs, the I / O and transceivers between IC405A and IC410A, and between IC405B and IC410B, are aligned so that horizontal chip-to-chip connections can extend straight through the interposer 100 (i.e., without crossing), just like vertical chip-to-chip connections. Thus, the devices in Figure 4 show two pairs of ICs that have essentially the same performance and functionality, with one pair being a mirrored version of the other pair.

[0028] Using two pairs of mirrored ICs allows for a straightforward inter-chip connection via the interposer 100, but it also means that two mask sets are used. That is, ICs 405A and 405B are manufactured using a different mask set than ICs 410A and 410B, which increases costs. However, Figure 5 avoids the cost of the additional mask set.

[0029] Figure 5 shows an example of a 2x2 configuration of ICs using rotated ICs. Similar to Figure 4, Figure 5 shows the implementation of four ICs 505A-505D on the interposer 100 (this may or may not exceed the maximum reticle field). However, unlike Figure 4, the four ICs 505 are of the same design (e.g., formed using the same mask set). Therefore, the ICs 505 have the same performance and functionality as one another.

[0030] Here again, the letter "F" is used to indicate the relative rotation of IC505. In this example, IC505B is rotated 90 degrees relative to IC505A, IC505C is rotated 90 degrees relative to IC505B (and 180 degrees relative to IC505A), and IC505D is rotated 90 degrees relative to IC505C (and 270 degrees relative to IC505A).

[0031] The 2x2 configuration in Figure 5 shows the use of the same IC design (and therefore only one mask set is required), but it is also far more difficult to design IC505 so that the I / O and transceivers on both sides align when rotated as shown. In other words, it is far more difficult to have straight, non-crossing inter-chip connections through the interposer 100 for IC505. For example, the circuits within a rotated IC505 may not be perfectly aligned horizontally and vertically between adjacent IC505s, complicating the interposer routing for connecting the IC505s. Furthermore, while IC505 may need to be a perfect square to align when rotated as shown, in Figure 4, the die could be a rectangle with two of its sides longer than the other perpendicular sides, and it is still necessary to align those I / O circuits.

[0032] Figure 6 illustrates, as an example, the use of rotated ICs to improve yield. Figure 6 illustrates a scenario in which the 2x2 configuration of rotated ICs from Figure 5 can be used to improve yield. Despite significant improvements in IC manufacturing, defects can still occur in ICs. This can result in having to discard an IC for having just one defect.

[0033] However, to improve yield, manufacturers may sell devices that are advertised as having lower performance than fully functional devices. For example, if the device shown in Figure 5 has four fully functional IC505s (e.g., none of the IC505s are defective), the device will be sold as a fully functional device. In contrast, Figure 6 shows a device 600 defined as having only 75% of the resources (or 75% of the performance) of a fully functional device. That is, the product definition of device 600 may indicate that 25% of device 600 consists of unused circuitry 605, and the remaining 75% of device 600 consists of used circuitry 610. Specifically, the unused circuitry 605 contains at least one defect, while the used circuitry 610 is defect-free.

[0034] Figure 6 also shows four IC650s with the same design, but two of the ICs have defects. For example, after manufacturing the IC650s, a testing process can be used to confirm that IC650A has defect 655, IC650B has defect 660, and IC650C and 650D are defect-free. However, instead of discarding IC650A and 650B, they can still be used in device 670, which meets the product definition of device 600 (i.e., 75% of the circuit is usable).

[0035] As illustrated, half of IC650A and IC650B have defects (or multiple defects). In practice, the defects may affect only a very small portion of IC650A and 650B, but to satisfy the product definition of device 600, only half of the circuitry within IC650A and 650B must be usable. Hashing indicates the half of IC650A and 650B that is not used due to having defects.

[0036] Since IC650 is rotatable, IC650A and 650B can be used to form device 670. That is, according to the product definition of device 600, the top 25% of the circuit should not be used. Therefore, since defect 655 is in the upper half of IC650A, this half of IC650A is deactivated and can then be placed in the upper right corner of device 670. In contrast, defect 660 is in the lower left of IC650B, and therefore the left half of this IC is deactivated. Therefore, when IC650B is rotated when placed in device 670, the deactivated half is in the upper half of device 670. Since IC650 is rotatable, it can be connected to adjacent ICs even when rotated. Therefore, IC650A and 650B satisfy the product definition that the top 25% of the circuit is not used and the remaining 75% of the circuit is used (including the usable halves of IC650A and 650B and all of the circuit in IC650C and 650D).

[0037] Advantageously, having a rotatable IC650 means that defects can be located in various positions on the IC and it can still be used in lower-performance products such as device 600. In this example, if the defect is in the upper half or lower left corner of IC650, the IC can still be used in device 670. Thus, IC650 may have defects in 75% of its area and can still be used in device 670. However, if the defect is in the lower right corner, it cannot be rotated to meet the product definition of device 600 and therefore cannot be used. These ICs can be discarded or may be usable in devices with different product definitions. In either case, using a rotatable die can improve yield by providing more opportunities to use defective ICs in lower-performance devices compared to devices where the rotatable die is not used in a 2x2 configuration.

[0038] Figure 7 illustrates, as an example, the use of a rotatable IC to improve yield. Similar to Figure 6, Figure 7 shows a scenario in which a 2x2 configuration of the rotated ICs from Figure 5 can be used to improve yield when the ICs are defective. For ease of explanation, the embodiment in Figure 7 is discussed in the context of device 600 in Figure 6, which is defined as having only 75% of the resources (or 75% of the performance) of a fully functional device. That is, the product definition of device 600 may indicate that 25% of device 600 is unused circuit 605 and the remaining 75% of device 600 is used circuit 610.

[0039] In Figure 6, each IC650 can be rotated and used in a 2x2 configuration. In Figure 7, each IC705 is the same, but each IC705 has complete logical rotational symmetry, and there are four possible orientations for each IC: 0, 90, 180, or 270 degrees. That is, while device 670 in Figure 6 had a product-level rotational symmetry axis, device 750 in Figure 7 has both a product-level rotational symmetry axis and a die-level rotational symmetry axis.

[0040] Device 750 may include an interposer on which dummy ICs 710A-710D, IO ICs 715A-715H, and ICs 705A-705D are arranged. Dummy IC 710 is optional and may be used for reasons of mechanical integrity. IO IC 715 may include an I / O circuit and transceiver coupled to the circuit in IC 705. The interposer can provide a direct inter-chip connection between IO IC 715 and IC 705.

[0041] In one embodiment, IC705 includes programmable logic (e.g., a programmable fabric) and has a direct connection that couples the programmable logic (or programmable fabric) to an inter-chip connection extending through an interposer and to IO IC715. Although not shown, IO IC715 may also be connected via the interposer to an external connection that allows an external device to communicate with IC705 through IO IC715.

[0042] The letter "F" in IC705A-705D indicates that their rotation is not a concern. That is, IC705A-705D are designed to be placed in any position and orientation on device 750. This is different from device 670 in Figure 6, where each position on device 670 corresponds to a specific orientation of IC650.

[0043] To satisfy the product definition of device 600, the top 25% of the circuit of device 750 may not be used, which gives manufacturers the opportunity to sell devices containing defective IC705. Figure 7 shows four IC705E-705H, where two of the ICs (i.e., IC705E and 705F) have their respective defects, and the other two ICs (i.e., 705G and 705H) do not have defects.

[0044] Figure 7 shows how ICs 705E to 705H form device 770. In this example, IC 705E is located in the upper left corner of device 770. IC 705F is located in the upper right corner of device 770 and is rotated 180 degrees relative to the orientation of IC 705F shown above in Figure 7. However, since ICs have rotational symmetry, the orientation of ICs 705 does not affect their function. Nevertheless, since ICs 705E and 705F are defective, the defective regions of these ICs are rotated into the portion of device 770 that includes the unused circuit 775. This can be achieved by rotating IC 705F 180 degrees as shown, or by rotating IC 705F 90 degrees (counterclockwise). In either case, the defective portion of IC 705F is part of the unused circuit 775 of the device.

[0045] Therefore, as in Figure 6, half of IC705E and 705F are not used in device 770. Due to rotational symmetry, IC705 can have defects in 100% of its region and still be usable in device 770. That is, IC650 in Figure 6 can recover from a defect in 75% of its region, while IC705 can recover from a defect in any region (e.g., the upper left and upper right corners, and the lower left and lower right corners). Therefore, if IC705 has a defect somewhere, IC705 can still be used to satisfy the product definition corresponding to device 770. That is, these defective ICs can be used in two upper positions of device 770.

[0046] If IC705 has multiple defects, it may still be usable in device 770. For example, if there are two defects in the same quarter of the die (e.g., multiple defects in the upper left area), IC705 can be used as shown in Figure 7. Furthermore, if there are multiple defects in two consecutive areas (e.g., defects in both the upper left and upper right corners, or the upper left and lower left corners), the IC can still be rotated so that the defective areas are within the unused circuit 775. However, if IC705 has defects in three areas (e.g., three corners), or if defects are in discontinuous areas of IC705 (e.g., defects in both the upper left and lower right corners), those ICs cannot be used in device 770. In any case, by using IC705 with rotational symmetry, the yield of those IC705s can be further improved compared to the device in Figure 6.

[0047] Furthermore, the redundancy and yield improvement techniques described in Figures 6 and 7 are not limited to using interposers with vertical and horizontal stitching, as described in Figures 1 to 5. For example, the devices in Figures 6 and 7 may include interposers without stitching. Alternatively, ICs within the device may be connected without using an interposer, for example, using the IC substrate to enable inter-chip connections.

[0048] The embodiments presented in this disclosure are referenced above. However, the scope of this disclosure is not limited to the specific embodiments described. Rather, any combination of the features and elements described is intended to implement and practice the intended embodiments, whether or not they relate to different embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Accordingly, the aforementioned aspects, features, embodiments, and advantages are merely illustrative and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims.

[0049] As will be understood by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Accordingly, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments that combine software and hardware embodiments, which may all be collectively referred to herein as “circuits,” “modules,” or “systems.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media in which computer-readable program code is embodied.

[0050] Any combination of one or more computer-readable media may be used. A computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any preferred combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections with one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any preferred combination thereof. In the context of this specification, a computer-readable storage medium is any tangible medium that can contain or store programs for use by, or in connection with, an instruction execution system, apparatus, or device.

[0051] A computer-readable signal medium may include, for example, a propagating data signal in which computer-readable program code is embodied, either in the baseband or as part of a carrier wave. Such a propagating signal may take any of various forms, including but not limited to electromagnetic, optical, or any preferred combination thereof. A computer-readable signal medium may be any computer-readable medium, rather than a computer-readable storage medium, that can communicate, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device.

[0052] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, or any preferred combination thereof.

[0053] Computer program code for performing the operations of the embodiments of this disclosure may be written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The program code may run entirely on the user's computer, partially as a standalone software package on the user's computer, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider).

[0054] Aspects of the present disclosure are described below with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments presented herein. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a general-purpose computer, a dedicated computer, or a processor of another programmable data processing device such that instructions executed via the processor of the computer or other programmable data processing device result in a machine that creates means for implementing the functions / actions specified in the blocks of the flowcharts and / or block diagrams.

[0055] These computer program instructions may also be stored in computer-readable storage media, and the instructions may also instruct computers, programmable data processing devices, and / or other devices to function in a particular manner, such as to produce products containing instructions that implement functions / actions specified in blocks of flowcharts and / or block diagrams.

[0056] Computer program instructions can also be loaded into a computer, other programmable data processing device, or other device to perform a series of operational steps on the computer, other programmable device, or other device, thereby generating a computer implementation process. Thus, instructions executed on a computer or other programmable device provide a process for implementing the functions / actions specified in the blocks of a flowchart and / or block diagram.

[0057] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur in a different order than shown in the figure. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs a specified function or action or a combination of dedicated hardware and computer instructions.

[0058] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, and the scope will be determined by the following "Claims".

Claims

1. It is a device, An interposer having horizontal and vertical stitches formed from overlapping exposure regions, A device comprising four integrated circuits (ICs) arranged in a 2x2 configuration on the interposer, wherein each of the four ICs is connected to an adjacent IC on two sides via the interposer.

2. The device according to claim 1, wherein the total surface area of ​​the interposer is greater than the maximum reticle field corresponding to the exposure region.

3. The device according to claim 2, wherein the total surface area of ​​the interposer is at least three times the size of the maximum reticle field.

4. The device according to claim 2, wherein the horizontal stitch and the vertical stitch are formed by slightly overlapping four exposure regions, and each of the four exposure regions is less than or equal to the maximum reticle field.

5. The device according to claim 1, wherein a first pair of the four ICs has the same design, a second pair of the four ICs has the same design, the design of the first pair differs from the design of the second pair, the first IC of the first pair is oriented 180 degrees relative to the second IC of the first pair, and the third IC of the second pair is oriented 180 degrees relative to the fourth IC of the second pair.

6. The device according to claim 1, wherein the four ICs have the same design, the first IC of the four ICs is oriented 90 degrees relative to the second IC of the four ICs, the third IC of the four ICs is oriented 180 degrees relative to the second IC of the four ICs, and the fourth IC of the four ICs is oriented 270 degrees relative to the second IC of the four ICs.

7. It is a method, Using overlapping exposure areas, an interposer having horizontal and vertical stitching is formed, A method comprising arranging four ICs on the interposer in a 2x2 configuration, wherein each of the four ICs is connected to an adjacent IC on two sides via the interposer.

8. The method according to claim 7, wherein the total surface area of ​​the interposer is greater than the maximum reticle field used to form the interposer using the overlapping exposure areas, the total surface area of ​​the interposer is at least three times the size of the maximum reticle field, the horizontal stitch and the vertical stitch are formed by slightly overlapping four exposure areas, each of the four exposure areas is less than or equal to the maximum reticle field.

9. The method according to claim 7, wherein a first pair of the four ICs has the same design, a second pair of the four ICs has the same design, the design of the first pair is a mirror of the design of the second pair, the first IC of the first pair is oriented 180 degrees relative to the second IC of the first pair when placed on the interposer, and the third IC of the second pair is oriented 180 degrees relative to the fourth IC of the second pair when placed on the interposer.

10. The method according to claim 7, wherein the four ICs have the same design, the first IC among the four ICs is oriented 90 degrees relative to the second IC among the four ICs, the third IC among the four ICs is oriented 180 degrees relative to the second IC among the four ICs, and the fourth IC among the four ICs is oriented 270 degrees relative to the second IC among the four ICs.

11. The method according to claim 7, wherein the four ICs have the same design and are rotationally symmetrical so that they can be arranged on the interposer in any orientation without changing the function or performance of the four ICs.

12. It is a device, It comprises four integrated circuits (ICs) arranged in a 2x2 configuration, and each of the four ICs is connected to an adjacent IC on at least two sides. The four ICs mentioned above are devices with the same design.

13. The device according to claim 12, wherein the first IC among the four ICs is oriented at a 90-degree angle to the second IC among the four ICs, the third IC among the four ICs is oriented at a 180-degree angle to the second IC among the four ICs, and the fourth IC among the four ICs is oriented at a 270-degree angle to the second IC among the four ICs.

14. The device according to claim 6 or 12, wherein both the first IC and the second IC are defective, and the defective portions of the first IC and the second IC are disposed in an unused portion of the device.

15. The device according to claim 1 or 12, wherein the four ICs have rotational symmetry so that they can be arranged in any orientation without changing the function or performance of the four ICs.

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