System and method for wet cleaning of nanoholes

Abstract

An exemplary semiconductor processing method may include providing a substrate to the processing area of ​​a semiconductor processing chamber. The substrate may include alternating stacked materials. Feature portions may extend through the alternating stacked materials. One of the alternating stacked materials may include a silicon-containing material. A native oxide film material may be placed on at least a portion of the exposed surface of the silicon-containing material. These methods may include performing a pre-cleaning treatment on the substrate. These methods may include providing a fluorine-containing precursor to the processing area. These methods may include contacting the substrate with the fluorine-containing precursor, which removes the native oxide film from the silicon-containing material. [Representative diagram] Figure 4

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit and priority of U.S. Patent Application No. 18 / 442,681, filed on Mar. 15, 2024, which claims the benefit of U.S. Provisional Patent Application No. 63 / 456,256, filed on Mar. 31, 2023, both of which are hereby incorporated by reference in their entirety for all purposes.

[0002] This technology relates to semiconductor processes and products. More specifically, this technology relates to selectively etching material layers on a substrate.

Background Art

[0003] Integrated circuits are enabled by a process of fabricating complexly patterned material layers on a substrate surface. To fabricate patterned materials on a substrate, a controlled method for depositing and removing the exposed materials is required. Chemical etching is used for various purposes, including transferring a pattern in a photoresist to a layer below, thinning a layer, or removing a native oxide film present on the surface. In many cases, an etching process that etches one material faster than another is desired, for example, to facilitate a pattern transfer process or individual material removal. Such an etching process is considered to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etching processes with selectivity to various materials have been developed.

[0004] Etching processes can be called wet or dry, depending on the materials used in the process. For example, wet etching can preferentially remove certain oxide dielectrics over other dielectrics and materials. However, wet processes can have difficulty penetrating some restricted trenches and may deform the remaining material. Dry etching, which is brought about by a localized plasma formed within the substrate processing area, can penetrate more restricted trenches while causing less deformation to the delicate remaining structure. However, localized plasma can damage the substrate by generating an electric arc during discharge.

[0005] Therefore, there is a need for improved systems and methods that can be used to fabricate high-quality devices and structures. This technology addresses the other needs mentioned above. [Overview of the project]

[0006] An exemplary semiconductor processing method may include providing a substrate to the processing area of ​​a semiconductor processing chamber. The substrate may include alternating stacked materials. Feature portions may extend through the alternating stacked materials. One of the alternating stacked materials may include a silicon-containing material. A native oxide film material may be placed on at least a portion of the exposed surface of the silicon-containing material. These methods may include performing a pre-cleaning treatment on the substrate. These methods may include providing a fluorine-containing precursor to the processing area. These methods may include contacting the substrate with the fluorine-containing precursor, which removes the native oxide film from the silicon-containing material.

[0007] In embodiments, the alternatingly stacked materials may include a first nitrogen-containing material. A silicon-containing material may be stacked on top of the first nitrogen-containing material. A second nitrogen-containing material may be stacked on top of the silicon-containing material. An oxygen-containing material may be stacked on top of the second nitrogen-containing material. The feature portion may have an aspect ratio greater than or about 10:1. The pre-cleaning treatment may include introducing water or steam into the substrate and filling the feature portion extending through the alternatingly stacked materials. The pre-cleaning treatment may include shaking the substrate to remove bubbles from the feature portion. The pre-cleaning treatment may condense steam at the bottom of the feature portion extending through the alternatingly stacked materials. The feature portion may be filled from the bottom to the top of the feature portion. The feature portion may be filled without the formation of bubbles. These methods may include providing a surfactant to the treatment area, either together or together with a fluorine-containing precursor, during the pre-cleaning treatment. The surfactant may be or may include hydrophilic hydrocarbons. The fluorine-containing precursor may be diluted hydrofluoric acid, or may contain diluted hydrofluoric acid.

[0008] Some embodiments of this technology encompass semiconductor processing methods. These methods may include providing a substrate to a processing area in a semiconductor processing chamber. The substrate may include alternating stacked materials. Featured portions may extend through the alternating stacked materials. One of the alternating stacked materials may include a silicon-containing material. A native oxide film material may be placed on at least a portion of the exposed surface of the silicon-containing material. These methods may include providing a fluorine-containing precursor to the processing area. These methods may include bringing the substrate into contact with the fluorine-containing precursor. Contact can remove the native oxide film from the silicon-containing material. Contact does not form bubbles beneath the featured portions.

[0009] In embodiments, the alternately stacked materials may include a first nitrogen-containing material. A silicon-containing material may be stacked on top of the first nitrogen-containing material. A second nitrogen-containing material may be stacked on top of the silicon-containing material. An oxygen-containing material may be stacked on top of the second nitrogen-containing material. The height of the feature area may be greater than 2 μm or about 2 μm. The pressure in the processing area may be less than 1,000 Torr or about 1,000 Torr. These methods may include providing a surfactant to the processing area together with a fluorine-containing precursor. The surfactant may be or may include a hydrophilic hydrocarbon. These methods may include performing a pre-cleaning treatment on the substrate. The pre-cleaning treatment may include filling the feature area with water from the bottom to the top of the feature area. Before performing the pre-cleaning treatment on the substrate or before contacting the substrate with the fluorine-containing precursor, these methods may include cooling the substrate. The relative humidity in the processing area may be greater than 70% or maintained at about 70%.

[0010] Some embodiments of this technology encompass semiconductor processing systems. These systems may include a semiconductor processing chamber defining a processing area. These systems may include a moisture vaporizer fluid-coupled to the processing area. The moisture vaporizer may be operable to adjust the relative humidity within the processing area. These systems may include a cooling unit fluid-coupled to the processing area. The cooling unit may be operable to deliver a cooling fluid to the processing area. These systems may include an acid container fluid-coupled to the processing area. The acid container may be operable to deliver an etchant species to the processing area.

[0011] Such technologies can offer numerous advantages over conventional semiconductor processing methods and structures. For example, embodiments of the processing method can reduce or eliminate the presence of bubbles in high-aspect-ratio feature areas during the native oxide film cleaning operation. By reducing or eliminating the presence of bubbles in high-aspect-ratio feature areas during the cleaning operation, uniform removal of the native oxide film can be achieved while minimizing the removal of other materials. In addition, since bubbles have already been removed from the feature areas, the removal time for the native oxide film can be reduced. The other embodiments described above, along with many of their advantages and features, will be described in more detail below in relation to the accompanying figures.

[0012] Further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is a top view of one embodiment of an exemplary processing system according to several embodiments of this technology. [Figure 2] This is a schematic diagram illustrating an exemplary semiconductor processing system according to several embodiments of this technology. [Figure 3] This block diagram shows an exemplary computer system in which embodiments of the present invention can be carried out according to several embodiments of this technology. [Figure 4] This figure shows an exemplary operation in a method according to several embodiments of this technology. [Figure 5A] This is a cross-sectional view of a substrate being processed according to an embodiment of this technology. [Figure 5B] This is a cross-sectional view of a substrate being processed according to an embodiment of this technology. [Figure 5C] This is a cross-sectional view of a substrate being processed according to an embodiment of this technology. [Modes for carrying out the invention]

[0014] Some of these diagrams are included as schematics. Please understand that these diagrams are for illustrative purposes only and are not considered to be to actual size unless specifically stated to be to actual size. In addition, as schematics, these diagrams are provided to aid understanding and may not include all aspects or information compared to realistic representations, and may include material that is emphasized for illustrative purposes.

[0015] In the attached diagram, similar components and / or feature parts may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a letter after the reference label that distinguishes similar components. If only the first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016] In many different semiconductor processes, diluted acids are sometimes used to clean substrates and remove materials from them. For example, diluted hydrofluoric acid can be an effective etchant for silicon dioxide, titanium dioxide, and other materials and can be used to remove these materials from the substrate surface. After the etching or cleaning operation is complete, the acid can be dried from the wafer or substrate surface. Using diluted hydrofluoric acid ("DHF") can be called "wet" etching, and the diluent is often water. Additional etching processes that utilize precursors delivered to the substrate can also be used. For example, plasma-enhanced processes can also selectively etch materials by enhancing the precursor with plasma and performing dry etching, including reactive ion etching.

[0017] Wet etchants using aqueous solutions or aqueous processes can function effectively for certain substrate structures, but the reduction in feature size and increase in aspect ratio may hinder wet etching operations, such as the removal of native oxide films from silicon-containing materials. For example, bubbles may become trapped beneath features such as patterned holes or trenches in stacked materials. If trapped bubbles are not pushed out, uniform cleaning or etching may not be possible. Removing trapped bubbles may require shaking to push them out of the features, which may increase the overall contact time between the substrate and the acid. Increased contact time may lead to over-etching on the top of the features, potentially damaging the structure.

[0018] Embodiments of this technology address these problems associated with conventional wet etching processes by performing a pre-cleaning treatment or by utilizing a surfactant. The pre-cleaning treatment may include immersing the substrate in water while optionally agitating it to completely fill the feature areas with water. Alternatively, the pre-cleaning treatment may include condensing the water within the feature areas by capillary condensation to fill the feature areas from bottom to top. During the pre-cleaning treatment, or together with the acid, a surfactant having a higher vapor pressure than the water or acid used during cleaning or etching may also be provided. The high vapor pressure of the surfactant can push out bubbles from the feature areas. By performing a pre-cleaning treatment or utilizing a surfactant, the uniformity of the removal of the native oxide film within the feature areas can be increased while reducing the contact time between the substrate and the acid.

[0019] The remaining disclosures, as is customary, identify specific etching processes that utilize the disclosed technology. However, it will be readily apparent that these systems and methods are equally applicable to other etching techniques, including deposition and cleaning processes that can be performed within the described chambers, as well as intermediate and wiring processes and other etchings that can be carried out on various exposed materials that can be maintained or substantially maintained. Therefore, this technology should not be considered limited to use in exemplary etching processes or chambers only. Furthermore, while the exemplary chambers are described as providing the basis for this technology, it should be understood that this technology can be applied to substantially any semiconductor processing chamber capable of enabling the described operations.

[0020] Figure 1 shows a top view of one embodiment of a deposition, etching, firing, and curing chamber processing system 100 according to an embodiment. In this figure, a pair of forward-opening unified pods (FOUPs) 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a-f positioned in tandem sections 109a-c. A second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f can be equipped to perform multiple substrate processing operations, including periodic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, degassing, orientation, and other substrate processes, as well as the etching process described herein.

[0021] The substrate processing chambers 108a - f can include one or more system components for the deposition, annealing, curing, and / or etching of dielectric films on a substrate wafer. In one configuration, two pairs of processing chambers, such as 108c - d and 108e - f, can be used to deposit a dielectric material on a substrate, and a third pair of processing chambers, such as 108a - b, can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, such as 108a - f, can be configured to etch the dielectric film on the substrate. Any one or more of the processes described can be performed in a chamber separated from the manufacturing system shown in different embodiments. It will be understood that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are also contemplated by the system 100.

[0022] FIG. 2 shows a schematic view of a semiconductor processing system 200. The system 200 can be included as part of the processing system 100. The system 200 can include a semiconductor processing chamber 205. The semiconductor processing chamber 205 can be, for example, one of the substrate processing chambers 108a - f of the processing system 100. The semiconductor processing chamber 205 can define a processing region capable of accommodating a substrate during processing.

[0023] A moisture vaporizer 210 can be fluidly connected to the processing region of the semiconductor processing chamber 205. The moisture vaporizer 210 can be fluidly connected to the processing region of the semiconductor processing chamber 205 via a supply line 212. The moisture vaporizer 210 can adjust the relative humidity within the processing region of the semiconductor processing chamber 205. For example, during processing, the relative humidity within the processing region can be adjusted. The moisture vaporizer 210 can increase the relative humidity to be greater than, for example, 10% or about 10% or more, as further discussed below.

[0024] The cooling unit 215 can be fluidly connected to the processing region of the semiconductor processing chamber 205. The cooling unit 215 can deliver a cooling fluid to the processing region of the semiconductor processing chamber 205. The cooling unit 215 can be, for example, a water tank, a water vaporizer, or a cooling air blower. For example, the water vaporizer can be an ultrasonic water vaporizer. The cooling unit 215 can be fluidly connected to the processing region of the semiconductor processing chamber 205 via a supply line 216. A return line 218 can fluidly couple the processing region of the semiconductor processing chamber 205 and the cooling unit 215 to return the cooling fluid to the cooling unit 215.

[0025] The acid container 220 can be fluidly connected to the processing region of the semiconductor processing chamber 205. The acid container 220 can deliver an etchant species to the processing region of the semiconductor processing chamber 205. The acid container 220 can be fluidly connected to the processing region of the semiconductor processing chamber 205 via a supply line 222. A return line 224 can fluidly couple the processing region of the semiconductor processing chamber 205 and the acid container 220 to return the etchant species to the acid container 220. Although not shown, a filtration device may be present along the return line 224 to remove by-products from the etchant species.

[0026] FIG. 3 is a block diagram showing an exemplary computer system in which embodiments of the present invention can be implemented. This example shows a computer system 300 that can be used in whole, in part, or with various modifications to provide the functions of the system 10 and other components and functions of the present invention described herein.

[0027] A computer system 300 is shown, comprising hardware elements that can be electrically coupled via a bus 390. The hardware elements may include one or more central processing units 310, one or more input devices 320 (e.g., a mouse, a keyboard, etc.), and one or more output devices 330 (e.g., a display device, a printer, etc.). The computer system 300 may also include one or more storage devices 340 representing remote, local, fixed, and / or removable storage devices and storage media for temporary and / or more permanent storage of computer-readable information, and one or more storage media readers 350 for accessing the storage devices 340. For example, the storage devices 340 may be disk drivers, optical storage devices, solid-state storage devices, such as random access memory ("RAM") and / or read-only memory ("ROM"), which may be programmable, flash-updatable, etc.

[0028] The computer system 300 may also include a communication system 360 (for example, a modem, a wireless or wired network card, an infrared communication device, a Bluetooth® device, a near-field communication (NFC) device, a cellular communication device, etc.). The communication system 360 can enable the exchange of data with the aforementioned network, system, computer, mobile device, and / or other components. The system 300 also includes a working memory 380, which may include the RAM and ROM devices described above. In some embodiments, the computer system 300 may also include a processing acceleration unit 370, which may include a digital signal processor, a special-purpose processor, etc.

[0029] The computer system 300 may also include software elements, which are shown as being located in working memory 380, and include an operating system 384 and / or other code 388. The software code 388 can be used to perform the functions of various elements of the architecture described herein. For example, when performing the processes described herein, software stored and / or executed on a computer system such as system 300 may be used.

[0030] It should be understood that alternative embodiments of the computer system 300 can have numerous modifications from the above. For example, customized hardware may be used, and / or certain elements may be implemented in hardware, software (including portable software such as applets), or both. Furthermore, connections to other computing devices, such as network input / output and data acquisition devices (not shown), may be present.

[0031] Semiconductor structures according to some embodiments of the present art can be fabricated using System 100, or more specifically, a chamber incorporated into System 100 including Chamber 200, or other processing systems. Figure 4 shows a method 400 for forming a semiconductor structure, many of which can be carried out, for example, in Chamber 200. Method 400 may include one or more operations that can be carried out before the start of this method, including front-end processing, polishing, cleaning, deposition, etching, or any other operations that can be carried out before the operations described. This method may include several optional operations shown in the figure, whether or not they are specifically associated with the method according to the present art. For example, many of the operations described are provided to offer a broader range of structure formation, but are not essential to the art or can be carried out by alternative methods, which will be discussed further below.

[0032] Method 400 describes the operation schematically shown in Figures 5A to 5C, and an example thereof will be described in relation to the operation of Method 400. Figures 5A to 5C show only partial schematic diagrams, and it should be understood that the structure 500 or substrate 505 can accommodate any number of transistor sections having the embodiments shown in these figures. The operation of Method 400 can be implemented to increase uniformity in the removal of native oxide film in feature portions extending through the alternating stacked material on the substrate 505. The operation of Method 300 can also be implemented to prevent over-etching of one or more materials in the alternating stacked material on the substrate 505. The operation of Method 400 can also be implemented to reduce the waiting time during the removal of native oxide film in feature portions extending through the alternating stacked material on the substrate 505.

[0033] Method 400 can begin in operation 405 by providing a substrate 505 to a processing area in a semiconductor processing chamber, such as a processing area in a chamber 205. The substrate 505 can be made of silicon or some other semiconductor substrate material, or may contain such material. As already discussed, as shown in Figure 5A, the substrate 505 may include alternatingly stacked materials. For example, the materials may include one or more silicon-containing materials, one or more silicon and nitrogen-containing materials, and one or more silicon and oxygen-containing materials. In the exemplary embodiment shown in Figure 5A, the alternatingly stacked materials may include a first nitrogen-containing material 510, such as a silicon and nitrogen-containing material. A silicon-containing material 515, such as polycrystalline silicon, may be stacked on top of the first nitrogen-containing material 510. A second nitrogen-containing material 520, such as a silicon and nitrogen-containing material, may be stacked on top of the silicon-containing material. In embodiments, the first nitrogen-containing material 510 and the second nitrogen-containing material 520 may be the same material. A second nitrogen-containing material can be topped with an oxygen-containing material 525, such as silicon and an oxygen-containing material. The next alternating stack of materials may include another layer of the first nitrogen-containing material 510 on top of the oxygen-containing material 525.

[0034] Although the structure 500 shown in Figures 5A to 5C only shows three parts of alternately stacked material, it is intended that any number of materials can be deposited on the substrate 505. For example, the substrate 505 may include parts of more than five alternately stacked materials, such as more than seven, more than ten, more than fifteen, more than twenty, more than twenty-five, more than thirty, more than thirty-five, more than forty, more than forty, more than forty-five, more than fifty, more than fifty-five, more than sixty, more than sixty-five, more than seventy, more than seventy-five, or more.

[0035] Features 530, such as trenches or holes, can extend through alternatingly stacked materials. The aspect ratio or height-to-width ratio of the features 530 can be greater than or approximately 10:1, greater than or approximately 15:1, greater than or approximately 20:1, greater than or approximately 25:1, greater than or approximately 30:1, greater than or approximately 35:1, greater than or approximately 40:1, or approximately 40:1. The height or depth of the feature portion 530 can be greater than or approximately 1 μm, for example, greater than or approximately 1.2 μm, greater than or approximately 1.4 μm, greater than or approximately 1.6 μm, greater than or approximately 1.8 μm, greater than or approximately 1.8 μm, greater than or approximately 2 μm, for example, greater than or approximately 2.2 μm, greater than or approximately 2.4 μm, greater than or approximately 2.6 μm, greater than or approximately 2.8 μm, greater than or approximately 3 μm, or greater than or approximately 3 μm. In addition, each layer may feature a reduced width or thickness of less than 100 nm or about 100 nm, for example less than 80 nm or about 80 nm, less than 60 nm or about 60 nm, less than 50 nm or about 50 nm, less than 40 nm or about 40 nm, less than 30 nm or about 30 nm, less than 20 nm or about 20 nm, less than 10 nm or about 10 nm, less than 5 nm or about 5 nm, less than 1 nm or about 1 nm, or less, which includes fractions of any of the numbers listed, for example 20.5 nm, 1.5 nm, etc. As will be discussed further below, this combination of high aspect ratio and minimum thickness may interfere with many conventional etching operations or may require substantially longer etching times to remove the layer along a vertical or horizontal distance through a limited width. Furthermore, as with conventional techniques, damage to or removal of other exposed layers may also occur.

[0036] Native oxide material 535 may be present along at least a portion of the exposed surface of the feature area, for example, along the silicon-containing material. The native oxide material 535 may be formed by etching the feature area 530 through the alternately stacked materials and then exposure to ambient conditions. As shown in the left feature area of ​​Figure 5A, the native oxide material 535 may be formed only on the exposed surface of the silicon-containing material 515. However, as shown in the right feature area 530 of Figure 5A, the native oxide material 535 may also be formed on all exposed surfaces of the alternately stacked materials. Any amount of native oxide material 535 coverage on the exposed surfaces within the feature area 530 is considered.

[0037] It should be understood that the described structure 500 is not intended to be limiting and similarly encompasses a variety of other semiconductor structures. Since this technique can selectively remove native oxide films from any number of other materials, including each of the materials described above, other exemplary structures can include two-dimensional and three-dimensional structures common in semiconductor manufacturing, in which native oxide films are removed from one or more other materials within or on the structure. In addition, while high aspect ratio structures can benefit from this technique, it can be equally applied to lower aspect ratios and any other structures.

[0038] In the optional operation 410, method 400 may include performing a pre-cleaning procedure on the substrate 505. Conventional processes for removing native oxide material from feature areas extending through alternating stacked materials on a substrate may provide etchant species to the substrate without performing a pre-cleaning procedure. However, as the aspect ratio of the feature areas extending through the alternating stacked materials on the substrate continues to increase, the etchant species may not be able to immediately reach the bottom of the feature area. Instead, one or more bubbles may form and become trapped at the bottom of the feature area. The presence of bubbles may prevent the etchant species from immediately reaching the bottom of the feature area. Therefore, it becomes impossible to remove the native oxide material from the bottom of the feature area. Complete removal of the native oxide may require the etchant species to remain in the feature area for a longer period of time. However, as the contact time of the etchant species in the feature area increases, the etchant species may begin to etch one or more of the materials in the alternating stacked materials. Etching one or more of the materials in the alternating stacked materials may damage the structure.

[0039] Therefore, by performing a pre-cleaning treatment, the formation and / or trapping of bubbles at the bottom of the feature portion 530 can be reduced or prevented. In one embodiment, the pre-cleaning treatment may include introducing water or steam into the processing area and / or the substrate 505. To reduce or prevent the formation and / or trapping of bubbles, the pre-cleaning treatment may include filling the feature portion 530 extending through the alternately stacked material. In an embodiment, the pre-cleaning treatment may be continued for a period of time sufficient to allow water or steam to fill the feature portion 530. However, the pre-cleaning treatment may also be intended to be continued for a period of time to fill at least 25 volume%, at least 30 volume%, at least 35 volume%, at least 40 volume%, at least 45 volume%, at least 50 volume%, at least 65 volume%, at least 60 volume%, at least 65 volume%, at least 70 volume%, at least 75 volume%, at least 80 volume%, at least 85 volume%, at least 90 volume%, at least 95 volume%, at least 97 volume%, at least 99 volume%, or more of the feature portions 530 that extend through the alternately stacked materials on the substrate 505. Partially filling the feature portions 530 can substantially reduce the aspect ratio of the unfilled feature portions 530, thereby preventing the formation and / or trapping of bubbles.

[0040] In some embodiments, the pre-cleaning procedure may include agitating the substrate 505. By agitating the substrate 505, the feature portions 530 extending through the alternately stacked materials can be filled in a shorter period of time. In addition, agitation ensures that all feature portions 530 on the substrate are filled. To agitate the substrate 505, the substrate 505 can be vibrated or ultrasonic waves can be induced on the substrate 505. Alternatively, the substrate 505 can be agitated by water jetting or vacuum immersion. It is intended that the filling of the feature portions 530 can be accelerated by using any agitating means to reduce or eliminate the formation and / or trapping of air bubbles at the bottom of the feature portions 530. The pre-cleaning procedure may include immersing the substrate 505 in water, for example, ion-depleted water. By immersing the substrate 505 in water, for example for a long period of time, with optional agitation, the feature portions 530 can be completely filled and no air bubbles will be present.

[0041] In the embodiment, reducing the substrate temperature can facilitate filling the feature portion 530. Therefore, method 400 may include reducing the substrate temperature before or during the pre-cleaning treatment. In the embodiment, the substrate temperature can be reduced before or during the pre-cleaning treatment to less than 300°C or about 300°C, for example, less than 280°C or about 280°C, less than 260°C or about 260°C, less than 240°C or about 240°C, less than 220°C or about 220°C, less than 200°C or about 200°C, less than 180°C or about 180°C, less than 160°C or about 160°C, less than 140°C or about 140°C, less than 120°C or about 120°C, less than 100°C or about 100°C, or below. By reducing the substrate temperature, vapor can preferentially condense at the bottom of the feature portion 530 by capillary condensation. Capillary condensation allows the feature portion 530 to be gradually filled from the bottom to the top, starting at the bottom of the feature portion 530, thereby reducing or eliminating the formation and / or trapping of air bubbles.

[0042] Similarly, the efficient filling of the feature section 530 extending through the alternately stacked materials during the pre-washing treatment can be increased under high humidity. For example, high humidity can cause the lower part of the feature section 530 to saturate, condensing the vapor and allowing the feature section 530 to fill first from the bottom. In embodiments, the relative humidity can be greater than or about 60%, greater than or about 65%, greater than or about 70%, greater than or about 75%, greater than or about 80%, greater than or about 85%, greater than or about 90%, greater than or about 95%, greater than or about 99%, or higher. Increasing humidity, as with reducing temperature, allows the vapor to preferentially condense at the bottom of the feature section 530 without the formation and / or trapping of bubbles, allowing the feature section 530 to fill gradually from the bottom to the top.

[0043] Method 400 may include providing a fluorine-containing precursor to the processing area in operation 415. Exemplary fluorine-containing precursors used in Method 400 may include hydrofluoric acid or ammonium fluoride. However, various other fluorine-containing precursors used or useful in semiconductor processing are also intended. Other fluorine sources can be used with or instead of hydrofluoric acid. In embodiments, the fluorine-containing precursor may be diluted by making it an aqueous solution.

[0044] In the embodiment, an optional operation 420 can provide a surfactant to the fluorine-containing precursor. If bubbles are formed or trapped within the feature portion 530, the surfactant can destabilize the bubbles and push them out of the feature portion 530. The surfactant can feature a high vapor pressure, thereby pushing the bubbles to the top of the feature portion 530 and ultimately pushing them out of the feature portion 530. In the embodiment, the surfactant can feature a vapor pressure at room temperature greater than or about 5 kPa, greater than or about 6 kPa, greater than or about 7 kPa, greater than or about 8 kPa, greater than or about 9 kPa, greater than or about 10 kPa, or higher. Exemplary surfactants can be hydrophilic hydrocarbons, such as ethanol, acetone, or isopropyl alcohol.

[0045] The surfactant can be provided with or without performing an optional pre-cleaning treatment. It is also intended that the surfactant may be provided during the pre-cleaning treatment. Even in embodiments where the pre-cleaning treatment is not performed, the surfactant can still reduce or prevent the formation and / or trapping of bubbles within the feature portion 530. In embodiments where the pre-cleaning treatment is performed, the surfactant can reduce waiting time by increasing the rate at which any bubbles formed are removed.

[0046] After providing a fluorine-containing precursor and optionally a surfactant, method 400 may include, in operation 425, contacting the substrate 505 with the fluorine-containing precursor and, if present, with the surfactant. The fluorine-containing precursor can remove the native oxide film material 535 from within the feature portion 530. The native oxide film material 530 may react with the fluorine-containing precursor to form by-products such as hexafluorosilicic acid and water.

[0047] The pressure within the processing area can also affect the operation performed. In some embodiments, the pressure can be maintained at less than or about 1,000 Torr, less than or about 950 Torr, less than or about 900 Torr, less than or about 850 Torr, less than or about 800 Torr, less than or about 790 Torr, less than or about 780 Torr, less than or about 770 Torr, less than or about 760 Torr, less than or about 750 Torr, or less than or equal to these. The pressure can also be maintained at any pressure within these ranges, within a smaller range encompassed by these ranges, or between any of these ranges. In some embodiments, the processing pressure can be maintained between about 750 Torr and about 1,000 Torr, thereby facilitating the initiation of etching and facilitating the etching of the native oxide film material 535.

[0048] In the embodiments, performing a pre-cleaning treatment and / or providing a surfactant can reduce the overall time required to remove the native oxide film material 535 compared to the conventional technique. In the conventional technique, where no pre-cleaning treatment is performed and / or a surfactant is not provided, a residence time of more than 5 minutes may be required to remove the native oxide film material from a similar structure. Even then, the presence of bubbles may prevent the native oxide film from being removed from the bottom of the feature, potentially leading to over-etching of the material at the top of the feature. Conversely, the technique can uniformly remove the native oxide film material 535 throughout the entire feature 530 in less than or about 5 minutes, less than or about 4 minutes, less than or about 3 minutes, less than or about 2 minutes, less than or about 1 minute, or less.

[0049] As shown in Figure 5C, after removing the native oxide film material 535 from the silicon-containing material 515, the metallic silicon compound 540 can be selectively formed on the exposed silicon-containing material 515. For example, molybdenum and silicon-containing materials can be selectively formed on the exposed silicon-containing material 515. By performing the operation of this technique and removing the native oxide film material 535 from the silicon-containing material 515, the metallic silicon compound 540 can be formed on all exposed layers of the silicon-containing material 515 extending through the feature portion 530.

[0050] In the preceding description, numerous details have been provided for illustrative purposes to provide an understanding of various embodiments of the Technology. However, it will be apparent to those skilled in the art that certain embodiments can be carried out without some of these details, or with additional details.

[0051] While several embodiments have been disclosed, it will be understood by those skilled in the art that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. In addition, several well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be construed as limiting the scope of the Art. Furthermore, while methods or processes may be described sequentially or stepwise, it should be understood that these operations may be performed simultaneously or in an order different from that described.

[0052] Where a range of values ​​is provided, unless otherwise explicitly indicated in the context, it will be understood that each intermediate value between the upper and lower limits of that range is also specifically disclosed, down to the smallest decimal unit of the lower limit. Narrower ranges between any stated values ​​or unstated intermediate values ​​within the stated range, and values ​​or intermediate values ​​in any other statement within that range, are included. The upper and lower limits of those smaller ranges may independently include or exclude within that range, and each range that contains either, zero, or both limits within a smaller range by any specifically excluded limit within the stated range is also included within the scope of this art. Where a stated range includes one or both limits, ranges that exclude either or both of those included limits are also included. "About" and / or "approximately" in this Specified and the attached claims, when referring to measurable values ​​such as quantity, duration, etc., include variations of ±20%, ±10%, ±5%, or +0.1% from a specified value, where such variations are appropriate in the context of the systems, devices, circuits, methods, and other embodiments described herein. "Substantially" also in this Specified and the attached claims, when referring to measurable values ​​such as quantity, duration, physical attributes (such as frequency), etc., include variations of ±20%, ±10%, ±5%, or ±0.1% from a specified value, where such variations are appropriate in the context of the systems, devices, circuits, methods, and other embodiments described herein.

[0053] In this specification and the appended claims, unless otherwise clearly indicated by the context, the singular forms “a,” “an,” and “the” include plural references. Thus, for example, a reference to “feature” includes multiple such feature sections, a reference to “material” includes one or more materials and their equivalents known to those skilled in the art, and so on.

[0054] Furthermore, when the words “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including” are used herein and in the following claims, they are intended to specify the presence of a described feature, integer, component, or action, but not to exclude the presence or addition of one or more other feature, integer, component, action, behavior, or group.

Claims

1. To provide a substrate for a semiconductor processing chamber processing area, wherein the substrate comprises alternately stacked materials, a feature portion extends through the alternately stacked materials, one of the alternately stacked materials comprises a silicon-containing material, and a native oxide film material is disposed on at least a portion of the exposed surface of the silicon-containing material. The aforementioned substrate is subjected to a pre-cleaning procedure, To provide a fluorine-containing precursor in the aforementioned processing region, The method involves contacting the substrate with the fluorine-containing precursor, thereby removing the native oxide film from the silicon-containing material and making contact. A semiconductor processing method including [specific components].

2. The semiconductor processing method according to claim 1, wherein the alternately stacked materials include a first nitrogen-containing material, the silicon-containing material is stacked on top of the first nitrogen-containing material, the second nitrogen-containing material is stacked on top of the silicon-containing material, and the oxygen-containing material is stacked on top of the second nitrogen-containing material.

3. The semiconductor processing method according to claim 1, wherein the feature portion is characterized by an aspect ratio greater than 10:1 or about 10:

1.

4. The aforementioned pre-cleaning treatment Introducing water or steam into the substrate, A semiconductor processing method according to claim 1, comprising filling the characteristic portion extending through the alternately stacked materials.

5. The substrate is shaken to remove air bubbles from the characteristic portion. The semiconductor processing method according to claim 4, further comprising:

6. The method further includes condensing the vapor at the lower part of the feature portion extending through the alternately stacked materials, wherein the feature portion is filled from the bottom to the top of the feature portion. The semiconductor processing method according to claim 4.

7. The semiconductor processing method according to claim 6, wherein the aforementioned feature portion is filled without the formation of air bubbles.

8. During the pre-washing treatment, provide the surfactant to the treatment area together with or in combination with the fluorine-containing precursor. The semiconductor processing method according to claim 1, further comprising:

9. The semiconductor processing method according to claim 8, wherein the surfactant includes a hydrophilic hydrocarbon.

10. The semiconductor processing method according to claim 1, wherein the fluorine-containing precursor comprises diluted hydrofluoric acid.

11. To provide a substrate for a semiconductor processing chamber processing area, wherein the substrate comprises alternately stacked materials, a feature portion extends through the alternately stacked materials, one of the alternately stacked materials comprises a silicon-containing material, and a native oxide film material is disposed on at least a portion of the exposed surface of the silicon-containing material. To provide a fluorine-containing precursor in the aforementioned processing region, The method involves bringing the substrate into contact with the fluorine-containing precursor, removing the native oxide film from the silicon-containing material, bringing it into contact, and ensuring that no air bubbles are formed below the characteristic portion. A semiconductor processing method including [specific components].

12. The semiconductor processing method according to claim 11, wherein the alternately stacked materials include a first nitrogen-containing material, the silicon-containing material is stacked on top of the first nitrogen-containing material, the second nitrogen-containing material is stacked on top of the silicon-containing material, and the oxygen-containing material is stacked on top of the second nitrogen-containing material.

13. The semiconductor processing method according to claim 11, wherein the height of the characteristic portion is greater than 2 μm or approximately 2 μm.

14. The semiconductor processing method according to claim 11, wherein the pressure within the processing area is less than 1,000 Torr or about 1,000 Torr.

15. The method further includes providing a surfactant to the processing region together with the fluorine-containing precursor, wherein the surfactant includes a hydrophilic hydrocarbon. The semiconductor processing method according to claim 11.

16. Perform a pre-cleaning procedure on the aforementioned substrate. The semiconductor processing method according to claim 11, further comprising:

17. The semiconductor processing method according to claim 16, wherein the pre-cleaning treatment includes filling the feature portion with water from the bottom of the feature portion to the top of the feature portion.

18. Before performing the pre-cleaning treatment on the substrate, or before bringing the substrate into contact with the fluorine-containing precursor, the substrate is cooled. The semiconductor processing method according to claim 16, further comprising:

19. The semiconductor processing method according to claim 16, wherein the relative humidity within the processing area is maintained at a level greater than or approximately 70%.

20. A semiconductor processing chamber that defines the processing area, A moisture vaporizer fluidly connected to the processing area, which is capable of adjusting the relative humidity within the processing area, A cooling unit fluidly connected to the processing area, the cooling unit being capable of delivering cooling fluid to the processing area, An acid container fluidly connected to the processing region, the acid container being capable of delivering etchant species to the processing region. A semiconductor processing system equipped with the following features.

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