Stepped grid structure for incoupling

Abstract

A waveguide combiner is provided. The waveguide combiner includes a waveguide combiner substrate. The waveguide combiner provides a plurality of staircase structures arranged on the substrate. Each staircase structure includes a plurality of steps. Each step has the same step width. The plurality of steps has a trim width from the first step to the last step. The plurality of steps includes an upper step having an upper width.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to waveguide combiners for augmented reality, virtual reality, and mixed reality. More specifically, the embodiments described herein provide a waveguide combiner having a stepped grating structure.

Background Art

[0002]

[0002] Virtual reality is generally considered to be a computer-generated simulated environment in which a user has an apparent physical presence. Virtual reality experiences are generated in 3D and can be viewed through a head-mounted display (HMD) (e.g., glasses or other wearable display devices having a near-eye display panel as a lens for displaying a virtual reality environment that replaces the actual environment).

[0003]

[0003] However, augmented reality enables an experience in which a user can view the surrounding environment through the display lens of glasses or other HMD devices, but can also view images of virtual objects that are generated for display and appear as part of the environment. Augmented reality may include any type of input (e.g., voice input and haptic input), as well as virtual images, graphics, and videos that enhance or augment the environment experienced by the user. However, it should be noted that conventional augmented reality devices utilize waveguides that include binary gratings that can reduce optical efficiency.

[0004]

[0004] Therefore, what is needed in the art is an improved waveguide combiner.

Summary of the Invention

[0005]

[0005] In one embodiment, a waveguide combiner is provided. The waveguide combiner includes a waveguide combiner substrate. The waveguide combiner provides a plurality of etched staircase structures arranged on the substrate. Each staircase structure includes a plurality of steps. Each step has the same staircase width. The plurality of steps has a trim width from the first step to the last step. The plurality of steps includes an upper step having an upper width.

[0006]

[0006] In another embodiment, a waveguide combiner is provided. The waveguide combiner includes a waveguide combiner substrate. The waveguide combiner provides a plurality of etched staircase structures disposed on the substrate. Each staircase structure includes a plurality of steps. Each step has the same staircase width. The plurality of steps has a trim width from the first step to the last step. The plurality of steps includes intermediate steps having an intermediate width less than the trim width. The plurality of steps includes upper steps having an upper width.

[0007]

[0007] In another embodiment, a method for forming a waveguide combiner is provided. This method includes depositing a photoresist layer on a patterned hard mask placed on a device layer. The photoresist layer is exposed to generate a plurality of photoresist segments. The device layer is etched to generate a first step of a blazed grid having a step width. The plurality of photoresist segments are trimmed horizontally. The etching of the device layer and trimming of the plurality of photoresist segments are repeated horizontally to generate intermediate steps. The intermediate steps have an intermediate width greater than the step width. The plurality of photoresist segments and the patterned hard mask are removed.

[0008]

[0008] To enable a more detailed understanding of the above-described features of the Disclosure, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments of the Disclosure and should not be considered to limit the scope of the Disclosure, as other equally valid embodiments may be permitted. [Brief explanation of the drawing]

[0009] [Figure 1A] This is a perspective front view of a waveguide combiner according to an embodiment described herein. [Figure 1B-1C] This is a schematic cross-sectional view of a waveguide combiner according to an embodiment described herein. [Figure 2] This is a flowchart of a method for forming a waveguide combiner according to certain embodiments. [Figure 3A-3J] This is a schematic cross-sectional view of a portion of the device material in a method for forming a waveguide combiner according to certain embodiments. [Modes for carrying out the invention]

[0010]

[0013] For ease of understanding, the same reference numerals were used to indicate identical elements common to the figures where possible. It is assumed that elements and features of one embodiment may be usefully incorporated into other embodiments without further description.

[0011]

[0014] Embodiments of this disclosure generally relate to waveguide combiners for augmented reality, virtual reality, and mixed reality. The waveguide combiner includes an asymmetrical stepped structure that preferentially directs light to a desired position in the waveguide. The stepped structure includes a plurality of steps having a trim width from the first step to the last step, and an upper step having an upper width. In some embodiments that can be combined with other embodiments, the upper width is greater than the trim width to allow precise control over the amount of light direction. In some embodiments that can be combined with other embodiments, the upper width is less than the trim width.

[0012]

[0015] Figure 1A shows a perspective front view of the waveguide combiner 100. The waveguide combiner 100 described later should be understood as an exemplary waveguide combiner. Waveguide combiner 100 is an augmented reality waveguide combiner. Waveguide combiner 100 includes a plurality of device structures 102 disposed on a substrate 101, as shown in Figures 1B and 1C. The device structures 102 can be nanostructures having nano-size dimensions, such as submicron dimensions, e.g., critical dimensions of less than 1 μm. Regions of the device structures 102 may correspond to one or more grids 104, such as a first grid 104a, a second grid 104b, and a third grid 104c. Waveguide combiner 100 includes at least a first grid 104a corresponding to an input coupling grid and a third grid 104c corresponding to an output coupling grid. The waveguide combiner 100 may include a second grid 104b corresponding to an intermediate grid. The first grid 104a has a stepped structure 106. The second grid 104b and the third grid 104c have a device structure 107.

[0013]

[0016] Figures 1B and 1C are schematic cross-sectional views of the waveguide combiner 100. The staircase structure 106 includes a staircase surface 108, side walls 112, depth h, and line width d. The depth h corresponds to the height of the side walls 112 of the staircase structure 106, and the line width d corresponds to the distance between the side walls 112 of adjacent staircase structures. For example, the depth h may include the distance from the top surface of the substrate 101 to the upper step 130 of the staircase structure. As a further example, the line width d may include the distance between the side wall of the first staircase structure and the side wall of the second staircase structure.

[0014]

[0017] The stair surface 108 has multiple staircases 110. Each staircase in the multiple staircases 110 has the same staircase width 122. For example, the multiple staircases 110 may include 16, 32, 64, or 128 steps, each having the same step width. Each staircase in the multiple staircases 110 has the same staircase height. For example, the multiple staircases 110 may include 16, 32, 64, or 128 steps, each having the same step height. The staircase width 122 and staircase height are independent and can be the same size or different sizes, as shown in Figure 1B.

[0015]

[0018] Alternatively, the stair width 122 and stair height may be of different sizes. Each stair in the multiple staircases 110 has a different stair width 122. For example, the multiple staircases 110 may include 16, 32, 64, or 128 steps, each with a different step width. Each stair in the multiple staircases 110 has a different stair height. For example, the multiple staircases 110 may include 16, 32, 64, or 128 steps, each with a different step height. Each staircase structure in the multiple staircase structure has a refractive index from about 1.5 to about 4.0. For example, each staircase structure in the multiple staircase structure has a refractive index from about 2.65 to about 4.0.

[0016]

[0019] Multiple steps 110 have a trim width 118 defined by the steps from the first step to the last step. The first step is the first step perpendicular to the substrate 101. The last step is the last step perpendicular to the upper step 130 from the waveguide combiner 100, or there is an intermediate step 132, in which case the upper step 130 is a parallel plane p from the substrate 101, and the intermediate step 132 is a step located between the last step and the upper step 130. The trim width 118 may be less than half of the total width 134 of the step structure 106, for example less than 50%. The trim width 118 may be greater than half of the total width 134 of the step structure 106, for example greater than 50%. The trim width 118 may be less than the upper width 116 of the step structure and greater than the intermediate width 120. The trim width 118 may be greater than the upper width 116 of the step structure and greater than the intermediate width 120. The top width 116 is defined by the total width of the top step 130. The middle width 120 is defined by the total width of the middle step 132. The top width 116 may be greater than 50% of the width of the stair structure 106. The top width 116 may be less than 50% of the width of the stair structure 106. The top width 116 may be greater than the trim width 118 and the middle width 120. The top width 116 may be less than the trim width 118 and the middle width 120.

[0017]

[0020] The stair surface 108 has a stair angle γ. The stair angle γ is the angle between the stair surface 108 and a surface p parallel to the substrate 101, for example, a horizontal portion of one of the steps of a stair structure. In addition, each individual stair angle γ' is the angle between the surface normal s of the substrate 101 and the facet normal f of the stair surface 108. In some embodiments, the stair angle γ and each individual stair angle γ' may be the same or different.

[0018]

[0021] The stair angles γ' of two or more stair structures 106 may be different. The stair angles γ' of two or more stair structures 106 may be the same. The depths h of two or more stair structures 106 may be different, for example, different depths. The depths h of two or more stair structures 106 may be the same. The line widths d of two or more stair structures 106 may be different. The line widths d of one or more stair structures 106 may be the same.

[0019]

[0022] The substrate 101 can be any substrate used in the art and, depending on its use as a waveguide substrate, can be either opaque or transparent to light of a selected wavelength. The choice of substrate may include, but is not limited to, amorphous dielectrics, non-amorphous dielectrics, crystalline dielectrics, polymers, or combinations thereof, any suitable material substrate. In some embodiments, the substrate 101 includes, but is not limited to, silicon-containing materials, silicon- and oxygen-containing compounds, germanium-containing materials, indium- and phosphide-containing compounds, gallium- and arsenic-containing compounds, gallium- and nitrogen-containing compounds, carbon-containing materials, silicon- and carbon-containing compounds, silicon- and carbon-and-oxygen-containing compounds, silicon- and nitrogen-containing compounds, silicon- and oxygen-containing compounds, niobium- and oxygen-containing compounds, as well as lithium-, niobium- and oxygen-containing compounds, aluminum- and oxygen-containing compounds, indium-, tin- and oxygen-containing compounds, titanium- and oxygen-containing compounds, lanthanum- and oxygen-containing compounds, gadolinium- and oxygen-containing compounds, zinc- and oxygen-containing compounds, yttrium- and oxygen-containing compounds, tungsten- and oxygen-containing compounds, potassium- and oxygen-containing compounds, phosphorus- and oxygen-containing compounds, barium- and oxygen-containing compounds, sodium- and oxygen-containing compounds, or combinations thereof. In other embodiments that can be combined with other embodiments described herein, the substrate 101 comprises an oxide containing one or more of the following materials: gadolinium, silicon, sodium, barium, potassium, tungsten, phosphorus, zinc, calcium, titanium, tantalum, niobium, lanthanum, zirconium, lithium, or yttrium.Exemplary materials for substrate 101 include silicon (Si), silicon monoxide (cell layout for standard cells), silicon dioxide (SiO2), silicon carbide (SiC), fused silica, diamond, quartz germanium (Ge), silicon germanium (SiGe), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), sapphire (Al2O3), lithium niobate (LiNbO3), and indium tin oxide. The substrate includes at least one of the following: (ITO), lanthanum oxide (La2O3), gadolinium oxide (Gd2O5), zinc oxide (ZnZnO), yttrium oxide (Y2O3), tungsten oxide (WO3), titanium oxide (TiO2), zirconium oxide (ZrO3), sodium oxide (Na2O), niobium oxide (Nb2O5), barium oxide (BaO)(K2O), phosphorus pentoxide (P2O5), calcium oxide (CaO), or a combination thereof. In some embodiments that can be combined with other embodiments, the substrate may be configured to transmit wavelengths from 100 to 3000 nanometers.

[0020]

[0023] The structural material 114 includes materials different from those of the substrate 101. The structural material 114 includes, but is not limited to, oxides, carbides, or nitrides of one or more of silicon, aluminum, zirconium, tin, tantalum, barium, titanium, hafnium, lithium, lanthanum, cadmium, niobium, or combinations thereof. Exemplary materials of structural material 114 include silicon carbide, silicon oxycarbide, titanium oxide, silicon oxide, vanadium oxide, aluminum oxide, aluminum-doped zinc oxide (AZO), indium tin oxide, tin oxide, zinc oxide, tantalum oxide, silicon nitride, zirconium oxide, niobium oxide, cadmium tin oxide, silicon oxynitride, barium titanate, diamond-like carbon, hafnium oxide, lithium niobate, silicon carbonitride, silver, cadmium selenide, mercury telluride, zinc selenide, silver-indium-gallium-sulfur, silver-indium-sulfur, indium phosphide, gallium phosphide, lead sulfide, lead selenide, zinc sulfide, molybdenum sulfide, tungsten sulfide, or combinations thereof.

[0021]

[0024] The encapsulation layer 124 is disposed on the stepped structure of the first grating 104a. The encapsulation layer 124 includes, but is not limited to, aluminum, silver, gold, chromium, silicon nitride, silicon oxide, or combinations thereof. Examples of the encapsulation layer 124 include silicon dioxide, aluminum oxide, magnesium oxide, or combinations thereof. The encapsulation layer 124 can be formed using one or more vapor deposition processes that utilize plasma, such as physical vapor deposition (PVD) or sputtering processes, furnace chemical vapor deposition (FCVD) processes, plasma-enhanced chemical vapor deposition (PE-CVD) processes, plasma-enhanced atomic layer deposition (PE-ALD) processes, or other plasma processes.

[0022]

[0025] In one or more embodiments, the encapsulation layer 124 can be deposited by a PVD process that includes generating ozone or oxygen plasma during deposition of the encapsulation layer 124. For example, silver can be deposited in a magnetron sputtering PVD chamber using a silicon target and reactively deposited with a plasma containing argon and oxygen (Ar / O2). The encapsulation layer 124 can have a thickness of from about 10 nm to about 1000 nm or more, such as from about 10 nm to about 200 nm.

[0023]

[0026] FIG. 2 is a flow diagram of a method 200 for forming the waveguide combiner 100. FIGS. 3A-3I illustrate a portion 300 of the structural material 114. In one embodiment, the portion 30 is corresponding to the first grating 104a of the waveguide combiner 100 to be formed.

[0024]

[0027] As shown in FIG. 3A, before step 202, a hard mask segment 306 is disposed and patterned on the structural material 114. The patterned hard mask includes a plurality of hard mask segments, such as a first hard mask segment 306a, a second hard mask segment 306b, and a third hard mask segment 306c, separated from each other. The separation (e.g., distance) between the segments of the patterned hard mask determines the width of each staircase structure to be generated. FIG. 3B is a schematic cross-sectional view of the device layer 302 in step 202. In step 202, as shown in FIG. 3B, a photoresist layer 308 is deposited or disposed on the hard mask segment 306.

[0025]

[0028] In step 204, as shown in FIG. 3C, the photoresist layer 308 is exposed by lithography to generate a plurality of photoresist segments 310, such as a first photoresist segment, a second photoresist segment, and a third photoresist segment. The plurality of photoresist segments 310 are offset from the hard mask segment 306 such that the photoresist segments 310 directly contact and cover a portion of the structural material 114 and expose a portion of each hard mask segment 306. Further, the photoresist segments 310 do not extend to subsequent hard mask segments (e.g., from the first hard mask segment 306a to the second hard mask segment 306b). Rather, each photoresist segment 310 terminates at a distance from a subsequent hard mask segment.

[0026]

[0029] In step 206, the plasma etchant 304 comes into contact with the structural material 114, as shown in Figure 3D. The structural material 114 is exposed to and comes into contact with the plasma etchant 304, such as radicals and ion beams. Exposure of the structural material 114 to the plasma etchant 304 may include etching processes such as ion etching and reactive ion etching (RIE). The plasma etchant 304 etches a first depth 320 of a plurality of depths 324 to create a step 330 within the structural material 114. After step 206, in addition to the first depth 320, the step 330 includes an initial leading sidewall portion 342 of the leading sidewall 344 (shown in Figure 3D), a succeeding sidewall 352, and a first line width 362 from the initial leading sidewall portion 342 to the succeeding sidewall 352. The first line width 362 is controlled by the distance 332 between the leading edge surface 334 defined by the first side 312 of each photoresist segment 310 and the trailing edge surface 336 defined by the exposed side of each hard mask segment 306 that contacts the structural material 114. The distance 332 corresponds to the first line width 362 because the plasma etchant 304 does not contact the structural material 114 outside of the distance 332.

[0027]

[0030] In step 208, the photoresist segments 310a, 310b, and 310c are trimmed by an isotropic ion etching process that indents the photoresist segments vertically and horizontally. This operation increases the distance from the first line width 362 (defined by the first front sidewall portion 342) to the distance 332 between the front sidewall 344 and the rear end face 334.

[0028]

[0031] To etch the second depth 322 of the multiple depths 324 of the step 330 into the structural material 114, steps 206 and 208 may be optionally repeated. As shown in Figure 3E, each photoresist segment 310 is trimmed so that the width of each photoresist segment 310 is reduced such that the first side 312 of each photoresist segment 310 is shifted along the device layer 302 and the distance 332 increases.

[0029]

[0032] In addition to the second depth 322, the step 330 includes a second front sidewall 346 and a second line width 364 extending from the second front sidewall 346 to the rear sidewall. The second line width 364 is controlled by the distance 332 between the front edge surface 334 and the rear edge surface 336 during iterations of processes 206 and 208. As the distance 332 increases in each iteration of processes 206 and 208, the second line width 364 becomes longer than the first line width 362. The distance 332 corresponds to the second line width 364 because the plasma etchant 304 does not come into contact with the structural material 114 outside of the distance 332. As shown in Figure 3E, in various embodiments, the increase in distance 332 between each photoresist segment 310 after trimming is uniform and equal to twice the first line width 362, for example, the second line width 364 is twice the length of the first line width 362 so that each step 330 is symmetrical. Alternatively, the second line width 364 may increase non-uniformly above the first line width 362, for example, becoming non-uniformly larger than the first line width 362. For example, the second line width 364 may increase by 1.5 times the first line width 362, producing an asymmetrical stepped or blazed grid. Similarly, subsequent line widths may increase symmetrically or asymmetrically.

[0030]

[0033] Steps 206 and 208 are repeated until a waveguide combiner is formed in which the step 330 has multiple depths 324, including a first depth 320 and a second depth 322 corresponding to the step depth, as shown in Figures 3G and 3H. Reducing the first depth 320 and each second depth 322 results in a smoother front sidewall of the step 330. For example, the photoresist segment 310 is trimmed, further increasing the distance 332. A third depth 326 of the multiple depths 324 is formed, along with a third front sidewall and a third linewidth 366 from the third front sidewall to the rear sidewall 352. The third linewidth 366 is controlled by the distance between the front edge surface 334 and the rear edge surface 336. The distance 332 corresponds to the third linewidth 366, so that the plasma etchant 304 does not come into contact with the structural material 114 outside the distance 332.

[0031]

[0034] Steps 206 and 208 are repeated to generate a trim width 118. The trim width 118 may be smaller than the top width 116 of the staircase structure. Optionally, the trim width 118 may be larger than the top width 116 of the staircase case structure. Steps 208 and 208 are repeated to generate an intermediate step 132, which includes an intermediate width 120 smaller than the trim width 118.

[0032]

[0035] In step 210, as shown in Figure 3I, the patterned hard mask and photoresist layer 308 contain an opaque material and are removed after the waveguide combiner is formed. For example, the patterned hard mask and photoresist layer 308 contain a reflective material such as Cr or silver (Ag). In another embodiment, the patterned hard mask and photoresist layer 308 contain a transparent material such that the patterned hard mask and photoresist layer 308 remain after the waveguide combiner is formed.

[0033]

[0036] After step 210, step 330 remains, forming a staircase structure 106. Although only 10 steps and one intermediate step are shown in Figure 3I, steps 206 and 208 may be repeated to produce a desired number of steps with an intermediate step, e.g., 5, e.g., 10, e.g., 25. It should be noted that as the number of steps increases, the line width of each step (e.g., 362, 364) decreases, resulting in smoother leading sidewall portions (e.g., 342, 344) for each staircase structure 106. For example, method 200 may allow for the formation of multiple staircase structures 106, each approximating a continuous blaze profile.

[0034]

[0037] In step 212, as shown in Figure 3J, the encapsulation layer 124 is placed on the structural material 114. The encapsulation layer 124 may be formed using one or more plasma-based vapor deposition processes, such as PVD or sputtering, furnace CVD (FCVD), PE-CVD, PE-ALD, or other plasma processes.

[0035]

[0038] The waveguide combiner 100 described herein includes a staircase structure 106. Each staircase structure 106 includes a plurality of steps 110. The combination of the plurality of steps 110 forms a staircase surface 108. The staircase surface 108 formed by the plurality of steps 110 provides a staircase structure 106 having optical functions equivalent to a blazed structure. By repeating lithography and etching processes, it is possible to form the plurality of steps 110 to controlled dimensions and obtain the staircase surface.

[0036]

[0039] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. Waveguide combiner, circuit board and Multiple staircase structures arranged on the aforementioned substrate, Each staircase structure is equipped with, Multiple staircases, each having the same staircase width and a trim width from the first staircase to the last staircase, It comprises an upper step having an upper width, Waveguide combiner.

2. The waveguide combiner according to claim 1, wherein each of the plurality of stair structures includes a stair surface.

3. The waveguide combiner according to claim 2, wherein the stepped surface has facet normals of each step parallel to the stepped surface of the substrate.

4. The waveguide combiner according to claim 3, wherein the stepped surface has a stepped angle defined by the stepped surface and the facet normal.

5. Waveguide combiner according to claim 4, wherein the stair angles of two of the aforementioned plurality of stair structures are different.

6. Waveguide combiner according to claim 4, wherein the stair angles of two of the aforementioned plurality of stair structures are the same.

7. Waveguide combiner according to claim 6, wherein two of the aforementioned stair structures have different depths.

8. The waveguide combiner according to claim 1, wherein each staircase has the same stair height.

9. The waveguide combiner according to claim 1, wherein the plurality of step structures include oxides, carbides, or nitrides of silicon, aluminum, zirconium, tin, tantalum, zirconium, barium, titanium, hafnium, lithium, lanthanum, cadmium, niobium, or combinations thereof.

10. The waveguide combiner according to claim 1, wherein the substrate comprises an amorphous dielectric, a non-amorphous dielectric, a crystalline dielectric, a polymer, or a combination thereof.

11. The substrate is made of silicon (Si), silicon dioxide (SiO ２ A waveguide combiner according to claim 1, comprising germanium (Ge), silicon germanium (SiGe), sapphire, or a combination thereof.

12. The waveguide combiner according to claim 1, wherein the substrate is configured to transmit wavelengths from 100 to 3000 nanometers.

13. The waveguide combiner according to claim 1, wherein each of the multiple stair structures has a refractive index of about 1.5 to about 4.

0.

14. The waveguide combiner according to claim 1, wherein each of the multiple stair structures has a refractive index of about 2.65 to about 4.

0.

15. Waveguide combiner, circuit board and Multiple staircase structures arranged on the aforementioned substrate, Each staircase structure is equipped with, Multiple staircases, each having the same staircase width and a trim width from the first staircase to the last staircase, An intermediate step having an intermediate width, It comprises an upper step having an upper width, Waveguide combiner.

16. The waveguide combiner according to claim 15, wherein the intermediate step is positioned between the last step and the upper step.

17. The waveguide combiner according to claim 15, wherein the substrate is configured to transmit wavelengths from 100 to 3000 nanometers.

18. The waveguide combiner according to claim 15, wherein each of the multiple stair structures has a refractive index of about 1.5 to about 4.

0.

19. A method for forming a waveguide combiner, Depositing a photoresist layer on a patterned hard mask placed on a device layer, The photoresist layer is exposed to generate multiple photoresist segments, Etching the device layer to generate the first step of a blazed grid having a step width, The process involves horizontally trimming the aforementioned plurality of photoresist segments, In order to generate an intermediate step having an intermediate width greater than the aforementioned step width, the process involves repeatedly etching the device layer and horizontally trimming the plurality of photoresist segments, Removing the plurality of photoresist segments and the patterned hard mask, Methods that include...

20. The method according to claim 19, further comprising placing an encapsulation layer on the device layer.

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