Method for curvature correction using tensile nitrides

Abstract

Embodiments of this technology may include a semiconductor processing method. The method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon-containing precursor and a nitrogen-containing precursor. A substrate containing one or more materials may be placed in the processing area. The substrate may be characterized by a first curvature of the substrate. The method may include generating plasma emissions of the deposition precursor. The method may include forming layers of silicon and nitrogen-containing material on the substrate. The layers of silicon and nitrogen-containing material may be characterized by tensile stress. After the formation of the layers of silicon and nitrogen-containing material, the substrate may be characterized by a second curvature of the substrate that is smaller than the first curvature of the substrate.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit and priority of U.S. Patent Application No. 18 / 631,384, filed on April 10, 2024, which claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 462,315, filed on April 27, 2023, and these applications are hereby incorporated by reference in their entirety for all purposes.

[0002] This technology relates to semiconductor systems and processes. More particularly, this technology relates to deposition systems and methods in which a tensile silicon nitride layer can be formed.

Background Art

[0003] Integrated circuits are enabled by a process that creates complexly patterned layers of material on a substrate surface. To create patterned material on a substrate, controlled methods of forming and removing exposed material are required. Material properties can affect how a device operates and can further affect how films are removed relative to each other. During formation and removal, different stresses can be applied to the substrate. If the overall stress applied to the substrate becomes too tensile or too compressive, the methods of forming and removing the exposed material can become difficult to control.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high - quality devices and structures. These and other requirements are addressed by this technology.

Summary of the Invention

[0005] Embodiments of this technology may include a semiconductor processing method. The method may include supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber. The deposition precursor may include a silicon-containing precursor and a nitrogen-containing precursor. A substrate containing one or more materials may be placed in the processing area. The substrate may be characterized by a first curvature of the substrate. The method may include generating plasma emissions of the deposition precursor. The method may include forming layers of silicon and nitrogen-containing material on the substrate. The deposited layers of silicon and nitrogen-containing material may be characterized by tensile stress. After the formation of the layers of silicon and nitrogen-containing material, the substrate may be characterized by a second curvature of the substrate with a compressive stress smaller than the first curvature of the substrate.

[0006] In embodiments, one or more materials may include alternating pairs of silicon-containing material and silicon- and germanium-containing material. Layers of silicon- and nitrogen-containing material may be formed on alternating pairs of silicon-containing material and silicon- and germanium-containing material. One or more materials may include more than 36 alternating pairs of silicon-containing material and silicon- and germanium-containing material. The thickness of the silicon- and germanium-containing material may be greater than 5 nm or about 5 nm. The first curvature of the substrate may be greater than 200 μm or about 200 μm. The method may include treating the silicon- and nitrogen-containing material layer with a treatment plasma to increase the tensile stress of the silicon- and nitrogen-containing material layer. The thickness of the silicon- and nitrogen-containing material layer may be greater than 50 nm or about 50 nm. The method may include depositing one or more additional layers of material on the silicon- and nitrogen-containing material layer. One or more additional layers of material may define a patterning stack. The patterning stack may include a second layer of silicon- and nitrogen-containing material. A second layer of silicon and nitrogen-containing material may be characterized by a thickness greater than that of the silicon and nitrogen-containing layer. The method may include etching one or more feature areas through one or more materials on a substrate. Etching may consume the silicon and nitrogen-containing layer. Etching may reduce the compressive stress of the substrate and one or more materials.

[0007] Some embodiments of this technology can encompass a semiconductor processing method. The method may include supplying a substrate to a processing area of ​​a semiconductor processing chamber. The substrate may include alternating pairs of silicon-containing material and silicon- and germanium-containing material. The substrate may be characterized by a first curvature of the substrate. The method may include forming a patterning stack comprising one or more layers of material on the alternating pairs of silicon-containing material and silicon- and germanium-containing material. One or more layers of material may include at least one layer of silicon- and nitrogen-containing material characterized by tensile stress. After the formation of the patterning stack, the substrate may be characterized by a second curvature of the substrate, which may be smaller than the first curvature of the substrate. The method may etch one or more feature areas through the alternating pairs of silicon-containing material and silicon- and germanium-containing material. Etching may remove at least a portion of the patterning stack. After etching, the substrate may be characterized by a third curvature of the substrate, which may be smaller than the first curvature of the substrate.

[0008] In the embodiment, the substrate may include more than 50 alternating pairs of silicon-containing material and silicon- and germanium-containing material. The thickness of the silicon- and germanium-containing material may be less than 30 nm or about 30 nm. The first curvature of the substrate may be greater than 275 μm or about 275 μm. The patterning stack may include a first layer of silicon- and nitrogen-containing material arranged on the alternating pairs. The patterning stack may include a layer of silicon-containing material arranged on the first layer of silicon- and nitrogen-containing material. The patterning stack may include a second layer of silicon- and nitrogen-containing material arranged on the layer of silicon-containing material. The patterning stack may include a layer of carbon-containing material arranged on the second layer of silicon- and nitrogen-containing material. The patterning stack may include a third layer of silicon- and nitrogen-containing material arranged on the layer of carbon-containing material. The second curvature of the substrate may be less than 175 μm or about 175 μm. The compressive stress provided by alternating pairs of silicon-containing material and silicon- and germanium-containing material can be reduced while etching one or more feature areas. The tensile stress provided by at least one layer of silicon- and nitrogen-containing material can be reduced while etching removes at least a portion of the patterning stack.

[0009] Some embodiments of this technology may encompass semiconductor structures. The structure may include a substrate. The structure may include alternating pairs of silicon-containing material and silicon- and germanium-containing material arranged on the substrate. The structure may include a patterning stack comprising at least one layer of silicon- and nitrogen-containing material characterized by compressive stress, arranged on the alternating pairs. The semiconductor structure may be characterized by a curvature of the substrate of less than -200 nm or about -200 nm.

[0010] In the embodiment, the patterning stack may include a first layer of silicon and nitrogen-containing material arranged in alternating pairs. The patterning stack may include a layer of silicon-containing material arranged on top of the first layer of silicon and nitrogen-containing material. The patterning stack may include a second layer of silicon and nitrogen-containing material arranged on top of the layer of silicon-containing material. The patterning stack may include a layer of carbon-containing material arranged on top of the second layer of silicon and nitrogen-containing material. The patterning stack may include a third layer of silicon and nitrogen-containing material arranged on top of the layer of carbon-containing material.

[0011] Such techniques can offer numerous advantages compared to conventional systems and methods for addressing substrate curvature. For example, by using silicon and nitrogen-containing materials characterized by tensile stress, it is possible to form materials within the patterning stack that are removed during the subsequent etching process. Thus, as the compressive stress from the material on the substrate decreases, the tensile stress from the silicon and nitrogen-containing materials also decreases, allowing for the maintenance of the desired amount of curvature compensation. In addition, this technique avoids the need to deposit and then remove a front or back compensation layer. Fewer deposit and removal steps improve throughput and reduce waiting times. Embodiments of this technique, along with many of its advantages and features, will be described in more detail below in conjunction with the accompanying diagrams.

[0012] A further understanding of the nature and advantages of the disclosed technology can be obtained by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1A] This is a top view of an exemplary processing system according to several embodiments of this technology. [Figure 1B] This is a schematic cross-sectional view illustrating an exemplary processing system according to several embodiments of this technology. [Figure 2]This figure shows the steps of an exemplary method for semiconductor processing according to several embodiments of this technology. [Figure 3A-3B] This is a cross-sectional view of an exemplary semiconductor structure according to several embodiments of this technology. [Modes for carrying out the invention]

[0014] Some of the figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. In addition, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to actual representations, and may contain exaggerated material for illustrative purposes.

[0015] In the attached diagrams, similar components and / or features may have the same reference label. Furthermore, various components of the same type may be distinguished by a letter following the reference label that distinguishes them from similar components. Where only the first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016] In dynamic random access memory (DRAM) structures such as 3D DRAM, alternating layers of materials can be formed on a substrate. These alternating layers may include alternating pairs of silicon-containing materials and silicon- and germanium-containing materials. As the number of layers increases, so does the challenge of maintaining defect-free epitaxial growth and minimizing substrate curvature. For example, as the number of silicon- and germanium-containing material layers increases, or as the material thickness increases, increased compressive stress can cause the substrate to curve. Excessive curvature of the substrate can lead to breakage and / or disrupt downstream processes. Many downstream processes, including deposition, lithography, and etching, have curvature limitations. Therefore, processes to counteract substrate curvature are necessary for these downstream processes to proceed.

[0017] In conventional processes, one or more layers of material may be deposited on the front or back side of the substrate to compensate for curvature. The compensating material may exhibit stress hysteresis on either the front or back side. In addition, the compensating material may result in material defects and a large thickness in order to compensate for substrate curvature. Furthermore, the compensating material eventually needs to be removed, which introduces additional processing for material removal. This technique can instead form a patterning stack on the substrate that introduces tensile stress to the substrate in order to counteract the compressive stress of the material formed on the substrate. More specifically, this technique includes silicon and nitrogen-containing material in the patterning stack characterized by tensile stress. The amount of silicon and nitrogen-containing material is selected to reduce the curvature of the substrate. When the material on the substrate is etched in a downstream process, the compressive stress imparted by this material can be reduced. Similarly, as etching progresses, a portion of the patterning stack containing silicon and nitrogen-containing material may be removed, and the tensile stress can be reduced. Thus, when the compressive stress is reduced, the tensile stress is also reduced, which maintains the curvature of the substrate at the desired amount. Since the patterning stack containing silicon and nitrogen-containing materials is removed during etching, the complexity of curvature compensation is reduced, the risk of wafer curvature inversion is minimized, and the additional processing required to remove curvature compensation materials is reduced and / or eliminated.

[0018] After describing a general configuration of a chamber configured to perform a process according to an embodiment of this technology capable of performing plasma processing, the configuration of specific methods and components can be discussed. It should be understood that this technology is not intended to be limited to the specific films and processes discussed, as the described techniques may be used to improve several thin-film deposition processes and may be applicable to a variety of semiconductor processing chambers and processes.

[0019] Figure 1A shows a top view of one embodiment of a processing system 10 comprising deposition, treatment, etching, baking, and curing chambers according to the embodiment. In the figure, a pair of forward-opening unified pods 12 supply substrates of various sizes, which are received by a robotic arm 14 and placed in a low-pressure holding area 16, and then placed in one of the semiconductor processing chambers 18a-18f located in tandem sections 19a-19c. A second robotic arm 11 can be used to transport the substrate wafers from the holding area 16 to the semiconductor processing chambers 18a-18f and back. Each semiconductor processing chamber 18a-18f may be equipped to perform several substrate processing steps, including the formation of semiconductor stacks as described herein, in addition to other substrate processes including plasma chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and plasma treatment, annealing, ashing, etc.

[0020] The semiconductor processing chambers 18a-18f may include one or more system components for depositing, plasma treating, curing, and / or etching dielectric films or other films on a substrate. In one configuration, two pairs of semiconductor processing chambers, e.g., 18c-18d and 18e-18f, may be used to deposit dielectric material onto a substrate, and a third pair of semiconductor processing chambers, e.g., 18a-18b, may be used to treat the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 18a-18f, may be configured to deposit and treat stacks of alternating dielectric films on a substrate. Any one or more of the processes described may be performed in a chamber separated from the manufacturing system shown in different embodiments. It will be recognized that additional configurations of deposition, treatment, etching, annealing, and curing chambers for dielectric films are intended by system 10.

[0021] Figure 1B shows a cross-sectional view of an exemplary semiconductor processing chamber 100 according to several embodiments of the present technology. This figure can illustrate an overview of a system that can be specifically configured to incorporate one or more aspects of the present technology and / or to perform one or more steps according to embodiments of the present technology. Additional details of the chamber 100 or the method performed can be further described below. While the chamber 100 can be used to form tensile nitride films according to several embodiments of the present technology, it should be understood that the method can be similarly performed in any chamber capable of film formation. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and surrounding the substrate support 104 within a processing volume 120. A substrate 103 can be supplied to the processing volume 120 through an opening 126, which can be conventionally sealed using a slit valve or door for processing. The substrate 103 can be placed on the surface 105 of the substrate support during processing. The substrate support 104 can be made rotatable along an axis 147 on which the shaft 144 of the substrate support 104 can be mounted, as indicated by the arrow 145. Alternatively, the substrate support 104 may be lifted to rotate as needed during the deposition process.

[0022] A plasma profile modulator 111 can be disposed in a semiconductor processing chamber 100 to control the plasma distribution across a substrate 103 disposed on a substrate support 104. The plasma profile modulator 111 can include a first electrode 108, which can be disposed adjacent to the chamber body 102 and can separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 can be part of the lid assembly 106 or can be a separate sidewall electrode. The first electrode 108 can be an annular or ring-shaped member and can be a ring electrode. The first electrode 108 can be a continuous loop surrounding the periphery of the semiconductor processing chamber 100 surrounding the processing volume 120 or can be discontinuous at selected locations as needed. The first electrode 108 can also be a perforated electrode such as a perforated ring or mesh electrode or can be a plate electrode such as, for example, a secondary gas distributor.

[0023] One or more isolators 110a, 110b, which can be made of a dielectric material such as ceramic or metal oxide, e.g., aluminum oxide and / or aluminum nitride, contact the first electrode 108 and can electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 can define apertures 118 for distributing process precursors into the processing volume 120. The gas distributor 112 can be coupled to a first power source 142 such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or other power source that can be coupled to the semiconductor processing chamber. In some embodiments, the first power source 142 can be an RF power supply.

[0024] The gas distributor 112 can be a conductive or non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered by a first power source 142, as shown in Figure 1B, or, in some embodiments, the gas distributor 112 may be connected to earth.

[0025] The first electrode 108 may be coupled to a first tuning circuit 128 that can control the ground path of the semiconductor processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit element. The first tuning circuit 128 may be one or more inductors 132. The first tuning circuit 128 may be any circuit that enables a variable or controllable impedance under the plasma state present in the processing volume 120 during processing. In some embodiments as shown in the figures, the first tuning circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B can be positioned between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage sensor or a current sensor and can be coupled to the first electronic controller 134, which can provide some degree of closed-loop control of the plasma state inside the processing volume 120.

[0026] The second electrode 122 can be coupled to the substrate support 104. The second electrode 122 can be embedded within the substrate support 104 or coupled to the surface of the substrate support 104. The second electrode 122 can be a plate, perforated plate, mesh, wire screen, or other distributed arrangement of conductive elements. The second electrode 122 can be a tuning electrode and can be coupled to the second tuning circuit 136, for example, by a conductor 146 disposed within the shaft 144 of the substrate support 104, such as a cable having a selected resistance, such as 50 ohms. The second tuning circuit 136 can include a second electronic sensor 138 and a second electronic controller 140 that can be a second variable capacitor. The second electronic sensor 138 can be a voltage sensor or a current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma state within the processing volume 120.

[0027] A third electrode 124, which can be a bias electrode and / or an electrostatic chuck electrode, can be coupled to the substrate support 104. The third electrode can be coupled to a second power source 150 through a filter 148 that can be an impedance matching circuit. The second power source 150 can be DC power, pulsed DC power, RF bias power, a pulsed RF source, or a bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 can be RF bias power.

[0028] The lid assembly 106 and substrate support 104 in Figure 1B can be used in any semiconductor processing chamber for plasma or heat treatment. During the process, the semiconductor processing chamber 100 can provide real-time control of the plasma state within the processing volume 120. The substrate 103 can be placed on the substrate support 104, and a process gas can be flowed through the lid assembly 106 using the inlet 114 according to a desired flow plan. The gas can exit the semiconductor processing chamber 100 through the outlet 152. Power can be coupled to the gas distributor 112 to establish the plasma within the processing volume 120. In some embodiments, the substrate can be electrically biased using a third electrode 124.

[0029] When energy is supplied to the plasma in the processing volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. The flow characteristics of the ground path, represented by two tuning circuits 128 and 136, can then be adjusted using the electronic controllers 134 and 140. Set values ​​can be sent to the first tuning circuit 128 and the second tuning circuit 136 to independently control the deposition rate and plasma density uniformity from the center to the edge. In embodiments where both electronic controllers are variable capacitors, the electronic sensor can independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0030] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor and the inductances of the first inductor 132A and the second inductor 132B can be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which can have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at its minimum or maximum value, the impedance of the first tuning circuit 128 can be high, resulting in a plasma shape with minimal air coverage or lateral coverage over the substrate support. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma can grow to its maximum, effectively covering the entire working area of ​​the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, and the air coverage of the substrate support may decrease. The second electronic controller 140 has a similar effect, and since the capacitance of the second electronic controller 140 can be changed, the air coverage of the plasma over the substrate support can be increased or decreased.

[0031] The respective circuits 128 and 136 can be tuned in a closed loop using electronic sensors 130 and 138. A current or voltage setpoint can be incorporated into each sensor, depending on the type of sensor used, and the sensor may have control software that determines adjustments to each respective electronic controller 134 and 140 to minimize deviation from the setpoint. Thus, the plasma shape can be selected and dynamically controlled during processing. While the above discussion is based on electronic controllers 134 and 140, which can be variable capacitors, it should be understood that tuning circuits 128 and 136 with adjustable impedance can be provided using any electronic component having adjustable characteristics.

[0032] Figure 2 shows exemplary steps in processing method 200 according to several embodiments of the present technology. The method can be performed in various semiconductor processing chambers, including the semiconductor processing chamber 100 described above. Method 200 may include several optional steps, which may or may not be specifically related to some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader range of structure formation, but may be performed by alternative methods that are not definitive to the present technology or that are easily understood.

[0033] Method 200 may include additional steps before commencing the enumerated steps. For example, the additional processing steps may include forming a structure on the substrate, which may include both forming and removing material. The pre-processing steps may be performed in a chamber on which Method 200 can be performed, or the processing may be performed in one or more other semiconductor processing chambers before the substrate is brought into the semiconductor processing chamber on which Method 200 can be performed. In any case, Method 200 may optionally include bringing the substrate into a processing area of ​​a semiconductor processing chamber, such as the semiconductor processing chamber 100 described above, or another chamber that may include the components described above. The substrate may be deposited on a substrate support, the substrate support may be a pedestal such as the substrate support 104, and may reside in a processing area of ​​a chamber such as the processing volume section 120 described above.

[0034] In embodiments, pretreatment can involve forming one or more materials on the substrate. For example, the substrate may be pre-treated with alternating layers of silicon-containing material and silicon- and germanium-containing material, which may be applicable to the formation of a 3D DRAM structure. However, as the number of alternating layers of silicon-containing material and silicon- and germanium-containing material increases, the substrate may be characterized by increased curvature. Increased substrate curvature can hinder many downstream processes, and some tools may be unable to process the substrate. Conventional techniques have generally addressed substrate curvature by depositing materials on the front or back side of the substrate that can be removed later. However, these conventional techniques require additional forming and removal steps that reduce throughput and can result in structural defects. Therefore, Method 200 can form tensile silicon and nitrogen-containing materials to counteract and reduce substrate curvature, allowing further processing to continue. In addition, this technology allows for the formation of tensile silicon and nitrogen-containing materials within the patterning stack, which are consumed during etching of feature areas through alternating layers of silicon-containing material and silicon- and germanium-containing material. The consumption of tensile silicon and nitrogen-containing materials reduces the overall tensile stress applied to the substrate because the compressive stress provided by the alternating layers of silicon-containing material and silicon- and germanium-containing material decreases during etching.

[0035] Depending on the materials formed on the substrate, such as the number and thickness of the materials, the substrate may be characterized by a first curvature of the substrate. In the embodiment, the first curvature of the substrate may be greater than or about 150 μm, greater than or about 175 μm, greater than or about 200 μm, greater than or about 225 μm, greater than or about 250 μm, greater than or about 275 μm, greater than or about 300 μm, greater than or about 350 μm, greater than or about 350 μm, greater than or about 400 μm, greater than or about 450 μm, greater than or about 500 μm, greater than or about 550 μm, greater than or about 600 μm, greater than or about 650 μm, greater than or about 675 μm, greater than or about 700 μm, or more. In the embodiment, silicon and germanium-containing materials may impart compressive stress that causes the substrate to bend. Therefore, the first bending may correlate with the number of layers of silicon and germanium-containing material and their thickness.

[0036] In forming a patterning stack comprising layers of silicon and nitrogen-containing material characterized by tensile stress, Method 200 may include, in step 205, injecting a deposition precursor into a processing area of ​​a semiconductor processing chamber. The deposition precursor may include at least one silicon-containing precursor and at least one nitrogen-containing precursor. The silicon-containing precursor may be, or may include, silanes and disilanes, in particular, among several silicon-containing precursors useful for semiconductor processing. The nitrogen-containing precursor may be, or may include, ammonia (NH3) and a mixture of molecular nitrogen and hydrogen (N2+H2), in particular, among several nitrogen-containing precursors useful for semiconductor processing. The deposition precursor may further include at least one carrier gas. Embodiments of the carrier gas may include molecular nitrogen (N2), helium, xenon, or argon, in particular, among several carrier gases useful for semiconductor processing.

[0037] Embodiments of Method 200 may further include, in step 210, generating plasma emissions of the deposition precursor within the processing area of ​​a semiconductor processing chamber. The deposition plasma can be generated by supplying plasma power to the deposition precursor flowing into the processing area. In some embodiments, the plasma power may be supplied by a radio frequency (RF) power source electrically coupled to at least one electrode in the semiconductor processing chamber. In embodiments, the RF power supply can supply power to at least one electrode, which creates an electric field within the processing area of ​​the semiconductor processing chamber that energizes the deposition precursor and forms the deposition plasma. The plasma power supplied to the deposition precursor can be less than or about 60 watts, less than or about 55 watts, less than or about 50 watts, less than or about 45 watts, less than or about 40 watts, less than or about 35 watts, less than or about 30 watts, or less. The frequency of the RF power supplied to the deposition precursor can be 13.56 MHz in one non-limiting example. In some embodiments, the plasma power supplied to the deposition precursor may be supplied continuously, while in additional embodiments, the plasma power may be pulsed. In pulsed embodiments, the supplied RF plasma power may be less than or about 10 kHz and may have pulse frequencies of less than or about 9 kHz, less than or about 8 kHz, less than or about 7 kHz, less than or about 6 kHz, less than or about 5 kHz, less than or about 4 kHz, less than or about 3 kHz, less than or about 2 kHz, less than or about 1 kHz, or less. In some pulsed embodiments, the off portion of the duty cycle of the plasma power can allow for greater diffusion of plasma emitters in the as-deposited silicon and nitrogen-containing material. The longer the diffusion time of the plasma emitters, the more uniform the as-deposited material can be formed.

[0038] Embodiments of processing method 200 may further include, in step 215, depositing a layer of silicon and nitrogen-containing material from a deposition plasma onto a substrate in a semiconductor processing chamber. In embodiments, the as-deposited layer of silicon and nitrogen-containing material may be silicon nitride. The layer of silicon and nitrogen-containing material may be formed on alternating pairs of silicon-containing material and silicon and germanium-containing material. In addition, the layer of silicon and nitrogen-containing material may be one layer of a patterning stack formed on one or more materials on the substrate, such as alternating pairs of silicon-containing material and germanium-containing material. In embodiments, depending on the curvature imparted to the substrate by the material, the patterning stack may include one or more layers of silicon and nitrogen-containing material to counteract the curvature. For example, the patterning stack may include additional patterning materials, such as silicon-containing material or carbon-containing material, in addition to one or more layers of tensile silicon and nitrogen-containing material.

[0039] In the embodiment, the deposition of silicon and nitrogen-containing materials onto the substrate can be carried out at a deposition temperature that affects the deposition rate of the materials. For example, the processing area of ​​the semiconductor processing chamber may be characterized by deposition temperatures of less than or about 550°C, less than or about 500°C, less than or about 475°C, less than or about 450°C, less than or about 425°C, less than or about 400°C, less than or about 400°C, less than or about 375°C, less than or about 350°C, or less than or about 300°C, or lower. By depositing at a temperature of less than or about 500°C, the technology can protect the thermal history of the device. Silicon and nitrogen-containing materials can be deposited at deposition rates of less than 2 nm / second or approximately 2 nm / second, less than 1.5 nm / second or approximately 1.5 nm / second, less than 1.2 nm / second or approximately 1.2 nm / second, less than 1 nm / second or approximately 1 nm / second, less than 0.8 nm / second or approximately 0.8 nm / second, less than 0.5 nm / second or approximately 0.5 nm / second, less than 0.2 nm / second or approximately 0.2 nm / second, or less.

[0040] As will be further discussed below, the thickness of the as-deposited layers of silicon and nitrogen-containing material on the substrate may depend on the stress required to compensate for the curvature of the substrate caused by one or more materials deposited on the substrate. In embodiments, the thickness of the as-deposited layers of silicon and nitrogen-containing material may be greater than or about 10 nm, greater than or about 15 nm, greater than or about 20 nm, greater than or about 25 nm, greater than or about 30 nm, greater than or about 35 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, greater than or about 125 nm, greater than or about 150 nm, greater than or about 175 nm, greater than or about 200 nm, or greater than or greater than that. However, Method 200 may include a number of cycles to deposit the layers of silicon and nitrogen-containing material. For example, as will be discussed further below, a treatment may be performed after depositing a portion of the silicon and nitrogen material layer. Method 200 may include multiple cycles of deposition and treatment to form the entire silicon and nitrogen-containing material layer. In embodiments, the thickness of the as-deposited layer of silicon and nitrogen-containing material after one cycle may be greater than or about 1 nm, greater than or about 1.5 nm, greater than or about 2 nm, greater than or about 2.5 nm, greater than or about 3 nm, greater than or about 3.5 nm, greater than or about 5 nm, greater than or about 7.5 nm, greater than or about 10 nm, greater than or about 12.5 nm, greater than or about 15 nm, greater than or about 17.5 nm, greater than or about 20 nm, or greater than0 nm, greater than or about 12.5 nm, greater than or about 15 nm, greater than or about 17.5 nm, greater than or about 20 nm, or greater than or greater than 10 nm. Therefore, in the embodiment, each cycle of the deposition process may take less than 100 seconds or about 100 seconds, less than 75 seconds or about 75 seconds, less than 60 seconds or about 60 seconds, less than 30 seconds or about 30 seconds, less than 15 seconds or about 15 seconds, less than 10 seconds or about 10 seconds, less than 5 seconds or about 5 seconds, less than 2 seconds or about 2 seconds, less than 1 second or about 1 second, or less.

[0041] The deposited layers of silicon and nitrogen-containing materials may be characterized by tensile stress, but additional treatment can further increase the tensile stress of the silicon and nitrogen-containing material layers. Therefore, Method 200 may include treatments to increase the tensile stress of the silicon and nitrogen-containing material layers. The treatment step may include, in an optional step 220, flowing one or more treatment precursors into the treatment area of ​​a semiconductor processing chamber. In embodiments, Method 200 may include performing a purging step after deposition and before treatment, the purging step can limit particle deposition on the substrate. The treatment precursor may include a nitrogen-containing precursor such as N2, along with an inert gas precursor such as helium, argon, xenon, or neon. In embodiments, the treatment precursor may include some or all of the carrier gases also used as the deposition precursor. For example, embodiments may include reducing or stopping the flow of the silicon-containing precursor and nitrogen-containing deposition precursor used during the deposition process while continuing to flow at least one of the carrier gases in the deposition precursor. In embodiments, the flow rate of the carrier gas may be increased during the transition from the deposition process to the treatment process.

[0042] Embodiments of the processing method 200 may further include generating plasma emissions of the treatment precursor within the processing area of ​​a semiconductor processing chamber. Plasma emissions of the treatment precursor can be generated by supplying plasma power to the treatment precursor flowing into the processing area. In some embodiments, the treatment plasma power may be supplied by the same radio frequency (RF) power source used to supply the deposition plasma power and through the same system electrodes. In embodiments, the treatment plasma power may be greater than the deposition plasma power that energizes the deposition plasma. In embodiments, the treatment plasma power may be greater than 60W, greater than 70W or about 70W, greater than 80W or about 80W, greater than 90W or about 90W, greater than 100W or about 100W, greater than 110W or about 110W, greater than 120W or about 120W, greater than 130W or about 130W, greater than 140W or about 140W, greater than 150W or about 150W, or more. Increasing the plasma power can increase the dissociation and available radicals for impact and distribution within the film. The frequency of the RF power supplied to the treatment precursor can be 13.56 MHz in one non-limiting example. In some embodiments, the plasma power supplied to the treatment precursor may be supplied continuously, while in additional embodiments, the plasma power may be pulsed.

[0043] Plasma power may be delivered as a continuous wave during the transition from deposition to treatment plasma. This allows for a reduction in the time required for each deposition and treatment cycle to form silicon and nitrogen-containing layers with tensile stress. If several deposition and treatment cycles are performed to complete layer formation, the cumulative reduction in treatment time can be substantial. In embodiments, increasing the plasma power during the treatment process can further increase the tensile stress level of the fully formed silicon and nitrogen-containing layers.

[0044] The processing method 200 may further include, in an optional step 220, treating the as-deposited silicon and nitrogen-containing material on the substrate in a semiconductor processing chamber using a treatment plasma. The treatment plasma exposure time may be more than 1 second or about 1 second, more than 2 seconds or about 2 seconds, more than 5 seconds or about 5 seconds, more than 10 seconds or about 10 seconds, more than 15 seconds or about 15 seconds, more than 30 seconds or about 30 seconds, more than 45 seconds or about 45 seconds, more than 60 seconds or about 60 seconds, or longer. In embodiments, the exposure time of the as-deposited silicon and nitrogen-containing material to the treatment plasma may depend on the thickness of the as-deposited material. In embodiments, the exposure time may be more than 0.1 seconds (0.1 sec / Å) or about 0.1 sec / Å per angstrom of the deposited material. For example, exposure times could be greater than or approximately 0.2 seconds / Å, greater than or approximately 0.3 seconds / Å, greater than or approximately 0.4 seconds / Å, greater than or approximately 0.5 seconds / Å, greater than or approximately 0.6 seconds / Å, greater than or approximately 0.7 seconds / Å, greater than or approximately 0.8 seconds / Å, greater than or approximately 0.9 seconds / Å, greater than or approximately 1 second / Å, greater than or approximately 2 seconds / Å, or even longer.

[0045] Treatment of silicon and nitrogen-containing materials on a substrate can be carried out at a treatment temperature that affects the treatment rate of the material. In embodiments, the treatment area of ​​a semiconductor treatment chamber may be characterized by treatment temperatures of less than or about 550°C, less than or about 500°C, less than or about 475°C, less than or about 450°C, less than or about 425°C, less than or about 400°C, less than or about 400°C, less than or about 375°C, less than or about 350°C, or less than or about 300°C, or lower.

[0046] Once a portion of the silicon and nitrogen-containing material layer has formed, it can be determined whether the layer formation is complete. If the portion of the silicon and nitrogen-containing material layer has completed its formation, another cycle of deposition and treatment of the silicon and nitrogen-containing material may not be performed. If the portion of the silicon and nitrogen-containing material layer has not completed its formation, another cycle of deposition and treatment of the silicon and nitrogen-containing material may be initiated. As previously discussed, a complete tensile silicon and nitrogen-containing layer can be formed when the thickness of the layer reaches over 10 nm or about 10 nm, over 15 nm or about 15 nm, over 20 nm or about 20 nm, over 25 nm or about 25 nm, over 30 nm or about 30 nm, over 35 nm or about 35 nm, over 50 nm or about 50 nm, over 75 nm or about 75 nm, over 100 nm or about 100 nm, over 125 nm or about 125 nm, over 150 nm or about 150 nm, over 175 nm or about 175 nm, over 200 nm or about 200 nm, or greater.

[0047] In embodiments, steps 205-220 may be performed in one or more cycles to form a silicon and nitrogen-containing material on a substrate. Embodiments may include a number of cycles to form the material using optional treatment steps performed intermittently as needed or desired. For example, steps 205-220 may be repeated at least two, at least three, at least four, at least five, at least seven, at least ten, or more times. In addition, each cycle may or may not include optional treatment in optional step 220.

[0048] Method 200 may include, in an optional step 225, depositing one or more additional layers of material on top of the silicon and nitrogen-containing material layers. Together with the silicon and nitrogen-containing material layers, one or more additional layers of material can define a patterning stack. For example, a patterning stack may include one or more layers of silicon-containing material, one or more layers of carbon-containing material, and one or more additional layers of silicon and nitrogen-containing material. The patterning stack may be formed to pattern the material beneath the first layer of silicon and nitrogen-containing material, such as alternating pairs of silicon-containing material and silicon and germanium-containing material placed on the substrate. Therefore, Method 200 may include a step to pattern the top layer of material on the patterning stack before etching the underlying material.

[0049] After depositing one or more layers of silicon and nitrogen-containing material, the substrate may be characterized by a second curvature of the substrate that is smaller than a first curvature of the substrate. The tensile stress of one or more layers of silicon and nitrogen-containing material can counteract the compressive stress of other materials deposited on the substrate. In embodiments, the second curvature of the substrate may be less than or about 350 μm, less than or about 300 μm, less than or about 275 μm, less than or about 250 μm, less than or about 225 μm, less than or about 225 μm, less than or about 200 μm, less than or about 175 μm, less than or about 150 μm, less than or about 125 μm, less than or about 100 μm, less than or about 75 μm, less than or about 50 μm, or less.

[0050] After forming the patterning stack, Method 200 may, in an optional step 230, etch one or more feature areas through the material beneath the silicon and nitrogen-containing material layers, such as alternating pairs of silicon-containing material and silicon and germanium-containing material arranged on the substrate. The feature areas can be of any shape or size, such as holes or trenches, and may extend through part or all of the underlying material to the substrate. In embodiments, etching can remove at least a portion of the patterning stack. For example, as etching proceeds into the underlying material, portions of the patterning stack, such as entire layers of material, may also be etched. When the curvature imparted by the underlying material is reduced by etching the feature areas, portions of the patterning stack that impart tensile stress to counteract the curvature may also be removed. More specifically, etching reduces the curvature of the substrate while simultaneously reducing the tensile stress imparted by the patterning stack.

[0051] Figures 3A and 3B show cross-sectional views of exemplary semiconductor structures 300 according to several embodiments of the present technology. The exemplary embodiments shown in structure 300 include a patterning stack comprising a number of layers 320, 330, and 340 of silicon and nitrogen-containing materials that can be formed by the processing method according to embodiments of the present technology. In the embodiment shown in Figure 3A, structure 300 may further include alternating pairs of silicon-containing material 310 and silicon and germanium-containing material 315. The first layer 320 of silicon and nitrogen-containing material may be formed on the alternating pairs of silicon-containing material 310 and silicon and germanium-containing material 315. The patterning stack may include a layer 325 of silicon-containing material, for example, a layer of silicon and oxygen-containing material, placed on the first layer 320 of silicon and nitrogen-containing material. The layer 325 of silicon-containing material may be, for example, silicon oxide. The patterning stack may include a second layer 330 of silicon and nitrogen-containing material, placed on the layer 325 of silicon-containing material. The patterning stack may include a layer 335 of carbon-containing material, such as amorphous carbon material, which may be placed on a second layer 330 of silicon and nitrogen-containing material. The patterning stack may also include a third layer 340 of silicon and nitrogen-containing material placed on the carbon-containing material layer 335.

[0052] In the embodiment of the structure 300 shown in Figure 3A, alternating pairs of silicon-containing material 310 and silicon and germanium-containing material 315 formed on the substrate may cause the substrate 305 to bend due to the compressibility of the materials. In the embodiment, the substrate 305 may include more than 36 alternating pairs of silicon-containing material 310 and silicon and germanium-containing material 315, for example, more than 40 alternating pairs, more than 44 alternating pairs, more than 48 alternating pairs, more than 50 alternating pairs, more than 52 alternating pairs, more than 56 alternating pairs, more than 60 alternating pairs, more than 64 alternating pairs, more than 68 alternating pairs, more than 72 alternating pairs, or more. The thickness of each alternating layer of silicon and germanium-containing material 315 may be less than 30 nm or about 30 nm, less than 28 nm or about 28 nm, less than 26 nm or about 26 nm, less than 24 nm or about 24 nm, less than 22 nm or about 22 nm, less than 20 nm or about 20 nm, less than 18 nm or about 18 nm, less than 16 nm or about 16 nm, less than 14 nm or about 14 nm, less than 12 nm or about 12 nm, less than 10 nm or about 10 nm, or less. In embodiments, the thickness of each alternating layer of silicon and germanium-containing material 315 may be greater than 5 nm or about 5 nm, greater than 10 nm or about 10 nm, greater than 12 nm or about 12 nm, greater than 14 nm or about 14 nm, greater than 16 nm or about 16 nm, greater than 18 nm or about 18 nm, greater than 20 nm or about 20 nm, or more.

[0053] As previously discussed, depending on the number of alternating pairs of silicon-containing material 310 and silicon and germanium-containing material 315 and / or the thickness of the alternating pairs, the substrate 305 is greater than or about 150 μm, greater than or about 175 μm, greater than or about 200 μm, greater than or about 225 μm, greater than or about 250 μm, greater than or about 275 μm, greater than or about 275 μm, greater than or about 300 μm The curvature can be characterized by a first curvature of 300 μm, greater than or about 350 μm, greater than or about 400 μm, greater than or about 450 μm, greater than or about 500 μm, greater than or about 550 μm, greater than or about 600 μm, greater than or about 650 μm, greater than or about 675 μm, greater than or about 675 μm, greater than or about 700 μm, or greater than or about 700 μm. As previously discussed, downstream processes may be hindered, and some tools may not be able to process the substrate in the increased curvature state. Therefore, to counteract the curvature given by the alternating pairs, tensile silicon and nitrogen-containing materials may be formed within the patterning stack.

[0054] In one exemplary embodiment, the structure 300 may include 72 alternating pairs of silicon-containing material 310 and silicon- and germanium-containing material 315. To counteract the curvature of the substrate 305, a first layer 320 of silicon- and nitrogen-containing material may be formed on the alternating pairs. In embodiments, the thickness of the first layer 320 of silicon- and nitrogen-containing material may be greater than or about 10 nm, greater than or about 15 nm, greater than or about 20 nm, greater than or about 25 nm, greater than or about 30 nm, or more. A layer 325 of silicon-containing material placed on the first layer 320 of silicon- and nitrogen-containing material may have a thickness of greater than or about 200 nm, greater than or about 300 nm, greater than or about 400 nm, greater than or about 500 nm, or more. A second layer 330 of silicon and nitrogen-containing material, placed on top of the silicon-containing material 325, can further resist the curvature of the substrate 305. In embodiments, the second layer 330 of silicon and nitrogen-containing material may be thicker than the first layer 320 of silicon and nitrogen-containing material. The second layer 330 of silicon and nitrogen-containing material may have a thickness of more than 50 nm or about 50 nm, more than 75 nm or about 75 nm, more than 100 nm or about 100 nm, more than 150 nm or about 150 nm, more than 200 nm or about 200 nm, or greater. The carbon-containing material layer 335 may have a thickness of more than 200 nm or about 200 nm, more than 300 nm or about 300 nm, more than 400 nm or about 400 nm, more than 500 nm or about 500 nm, or greater. Finally, in the exemplary embodiment shown in Figure 3A, the third layer 340 of silicon and nitrogen-containing material, placed on the carbon-containing material layer 335, can have a thickness of more than 25 nm or about 25 nm, more than 50 nm or about 50 nm, more than 75 nm or about 75 nm, more than 100 nm or about 100 nm, or greater. Similar to the second layer 330 of silicon and nitrogen-containing material, the third layer 340 of silicon and nitrogen-containing material can further reduce the curvature of the substrate 305.

[0055] Figure 3B shows the structure 300 after etching the feature area 345 within alternating pairs of silicon-containing material 310 and silicon- and germanium-containing material 315. As shown in Figure 3B, the feature area 345 may extend through all alternating pairs to the substrate 305. However, it is also expected that the feature area 345 may not extend completely to the substrate 305. When the silicon-containing material 310 and silicon- and germanium-containing material 315 of the alternating pairs are etched, the stress applied to the substrate that would cause initial bending can be reduced. Similarly, etching can remove material from the patterning stack. In the embodiment shown in Figure 3B, the third layer 340 of the silicon- and nitrogen-containing material and the layer 335 of the carbon-containing material may be removed during etching. Depending on the thickness of the material deposited on the substrate 305, and the etching used to pattern the alternating pairs, additional or less material from the patterning stack can be removed. When the patterning stack, specifically the silicon and nitrogen-containing material, is removed, the tensile stress counteracting the alternating compressive stresses can be reduced. Thus, the tensile stress can be reduced, but at the same time, the compressive stress is also reduced.

[0056] In the preceding description, a great deal of detail was provided for explanatory purposes to provide an understanding of the various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be implemented without some of these details, or with additional details.

[0057] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the foregoing description should not be construed as limiting the scope of the Art. Furthermore, while methods or processes may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in an order different from that listed.

[0058] Where a range of values ​​is provided, it is understood that each intervening value between the upper and lower limits of that range is also explicitly disclosed, to the first decimal place of the lower limit, unless the context explicitly indicates otherwise. Narrower ranges between an explicitly stated value or an unexpressed intervening value within an explicitly stated range and other explicitly stated values ​​or intervening values ​​within that explicitly stated range are included. The upper and lower limits of those smaller ranges may, independently, be included in or excluded from the range, and each range in which either limit is included in a smaller range, or neither limit is included in a smaller range, or both limits are included in a smaller range, is further included in this technique, subject to the explicitly excluded limits in the explicitly stated range. Where an explicitly stated range includes one or both limits, ranges excluding one or both of those included limits are also included. When referring to measurable values ​​such as quantity, temporal duration, etc., “about” or “approximately” as used herein and in the appended claims includes variations of ±20%, ±10%, ±5%, or +0.1% from the specified value, for such variations are appropriate in the context of the systems, devices, circuits, methods, and other embodiments described herein. When referring to measurable values ​​such as quantity, temporal duration, physical attributes (such as frequency), etc., “substantially” as used herein and in the appended claims also includes variations of ±20%, ±10%, ±5%, or ±0.1% from the specified value, for such variations are appropriate in the context of the systems, devices, circuits, methods, and other embodiments described herein.

[0059] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context explicitly indicates otherwise. Thus, for example, a reference to “precursor” includes multiple such precursors, and a reference to “layer” includes a reference to one or more layers and their equivalents known to those skilled in the art, and so on.

[0060] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” when used herein and in the following claims, are intended to specify the presence of an expressly stated feature, integer, component, or process, but do not preclude the presence or addition of one or more other features, integers, components, processes, actions, or groups.

Claims

1. A semiconductor processing method, The method involves supplying a deposition precursor to a processing area of ​​a semiconductor processing chamber, wherein the deposition precursor comprises a silicon-containing precursor and a nitrogen-containing precursor, and a substrate comprising one or more materials is placed within the processing area, and the substrate is characterized by a first curvature of the substrate. To generate plasma emissions from the aforementioned deposition precursor, The process involves forming a layer of silicon and nitrogen-containing material on the substrate, wherein the layer of silicon and nitrogen-containing material is characterized by tensile stress, and after the formation of the layer of silicon and nitrogen-containing material, the substrate is formed such that it is characterized by a second curvature of the substrate that is smaller than the first curvature of the substrate. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the one or more materials include alternating pairs of a silicon-containing material and a silicon and germanium-containing material.

3. The semiconductor processing method according to claim 2, wherein the silicon and nitrogen-containing material layer is formed on the alternating pairs of the silicon-containing material and the silicon and germanium-containing material.

4. The semiconductor processing method according to claim 2, wherein the one or more materials include more than 36 alternating pairs of the silicon-containing material and the silicon and germanium-containing material.

5. The semiconductor processing method according to claim 2, wherein the thickness of the silicon and germanium-containing material is greater than 5 nm or about 5 nm.

6. The semiconductor processing method according to claim 1, wherein the first curvature of the substrate is greater than 200 μm or about 200 μm.

7. The semiconductor processing method according to claim 1, further comprising treating the silicon and nitrogen-containing material layer with a treatment plasma to increase the tensile stress of the silicon and nitrogen-containing material layer.

8. The semiconductor processing method according to claim 1, wherein the thickness of the silicon and nitrogen-containing material layer is greater than 50 nm or about 50 nm.

9. The semiconductor processing method according to claim 1, further comprising depositing one or more additional layers of material on the silicon and nitrogen-containing material layer, wherein the one or more additional layers of material define a patterning stack, and the patterning stack includes a second layer of silicon and nitrogen-containing material.

10. The semiconductor processing method according to claim 9, wherein the second layer of the silicon and nitrogen-containing material is characterized by having a thickness greater than the thickness of the layer of the silicon and nitrogen-containing material.

11. The semiconductor processing method according to claim 1, further comprising etching one or more feature portions through one or more materials on the substrate, wherein the etching consumes layers of silicon and nitrogen-containing material, and the etching reduces the compressive stress of the substrate and the one or more materials.

12. A semiconductor processing method, The supply of a substrate to the processing area of ​​a semiconductor processing chamber, wherein the substrate comprises alternating pairs of silicon-containing material and silicon and germanium-containing material, and the substrate is characterized by a first curvature of the substrate. The method involves forming a patterning stack comprising one or more layers of material on the alternating pairs of silicon-containing material and silicon and germanium-containing material, wherein one or more layers of material comprise at least one layer of silicon and nitrogen-containing material characterized by tensile stress, and after the formation of the patterning stack, the substrate is formed to be characterized by a second curvature of the substrate that is smaller than the first curvature of the substrate. The etching involves etching one or more feature portions through the alternating pairs of the silicon-containing material and the silicon and germanium-containing material, wherein the etching removes at least a portion of the patterning stack, and after etching, the substrate is characterized by a third curvature of the substrate that is smaller than the first curvature of the substrate. A semiconductor processing method, including the following.

13. The semiconductor processing method according to claim 12, wherein the substrate includes more than 50 alternating pairs of the silicon-containing material and the silicon and germanium-containing material.

14. The semiconductor processing method according to claim 12, wherein the thickness of the silicon and germanium-containing material is less than 30 nm or about 30 nm.

15. The semiconductor processing method according to claim 12, wherein the first curvature of the substrate is greater than 275 μm or about 275 μm.

16. The aforementioned patterning stack, A first layer of silicon and nitrogen-containing material arranged on the alternating pairs, A layer of silicon-containing material disposed on the first layer of the silicon and nitrogen-containing material, A second layer of silicon and nitrogen-containing material is disposed on the layer of silicon-containing material, A layer of carbon-containing material disposed on the second layer of silicon and nitrogen-containing material, A third layer of silicon and nitrogen-containing material is disposed on the carbon-containing material layer, The semiconductor processing method according to claim 12, including the method described in claim 12.

17. The semiconductor processing method according to claim 12, wherein the second curvature of the substrate is less than 175 μm or about 175 μm.

18. The compressive stress provided by the alternating pairs of the silicon-containing material and the silicon and germanium-containing material decreases during etching of one or more feature portions. The tensile stress given by at least one layer of the silicon and nitrogen-containing material is reduced while etching removes at least the portion of the patterning stack. The semiconductor processing method according to claim 12.

19. It is a semiconductor structure, circuit board and Alternating pairs of silicon-containing material and silicon and germanium-containing material arranged on the substrate, A patterning stack comprising at least one layer of silicon and nitrogen-containing material characterized by compressive stress arranged on the alternating pairs, wherein the semiconductor structure is characterized by curvature of the substrate of less than -200 nm or about -200 nm, A semiconductor structure that includes this.

20. The aforementioned patterning stack, A first layer of silicon and nitrogen-containing material arranged on the alternating pairs, A layer of silicon-containing material disposed on the first layer of the silicon and nitrogen-containing material, A second layer of silicon and nitrogen-containing material is disposed on the layer of silicon-containing material, A layer of carbon-containing material disposed on the second layer of silicon and nitrogen-containing material, A third layer of silicon and nitrogen-containing material disposed on the carbon-containing material layer and The semiconductor structure according to claim 19, including the above.

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