Method and apparatus for forming wideband PRN signal

Abstract

The apparatus for forming a wideband pseudorandom noise signal includes a channel set having an NCO with controlled frequency and phase and a PRN code generator, the NCO generating a strobe that is output to the PRN code generator. The PRN code generator forms a new sequence element of +1 or -1 in response to the strobe. The apparatus also includes a first modulator having a plurality of weighting coefficients, a plurality of multipliers each multiplying one of the weighting coefficients, a summer outputting a sum of the output signals of the plurality of multipliers, and a mixer having a quadrature output signal that multiplies the output of the summer by a sine and cosine of a low intermediate frequency. The apparatus also includes a processor for controlling the channel set, a transceiver module for receiving and / or transmitting the quadrature signals, and an interface connecting the output of the mixer to the transceiver module.

Description

[Technical field]

[0001] The present disclosure relates generally to methods and apparatus for generating signals, and more particularly to forming wideband pseudorandom noise signals for various applications. [Background technology]

[0002] Navigation equipment for industrial applications often includes a satellite navigation receiver for receiving satellite signals. The satellite signals can be utilized to determine the position of the receiver with some level of accuracy. These navigation equipment are often extended with additional hardware modules for generating additional navigation signals. These additional navigation signals can be similar to the received navigation signals and are used to perform calibration, correction, etc. of the received navigation signals. The additional navigation signals can also be used as extended navigation signals to improve the accuracy of the position determination based on the received navigation signals. Thus, the generated signals can be used for calibrating the receiver RF front end, for subtraction of jamming signals (from its own or nearby transmitters) from the received signals, for local positioning of other receivers, for mm-wave radar, etc. Although the above mentioned applications are usually implemented in the same equipment, the applications are usually not used and / or operated simultaneously. Typically, the generated additional navigation signals are wideband pseudorandom noise ("PRN") signals.

[0003] If the generated additional navigation signal is used as a subtraction signal to be subtracted from the received signal to cancel unwanted echo signals or to solve the near-far problem in case of code division multiple access ("CDMA"), the subtraction signal should be precisely adjusted in amplitude, carrier phase and code phase. This precise adjustment of the subtraction signal is done so that the generated additional navigation signal is synthesized as close as possible to the received unwanted signal so that it is mitigated by the subtraction operation. In the case of direct sequence CDMA ("DS-CDMA") signals, which are PRN based on a known code sequence, a precise representation of the signal shape means reproducing the end-to-end characteristics of the RF front-end through which the received signal passes. Typically, this is a low pass filter (LPF).

[0004] In other cases, when the CDMA signal is an additional navigation signal generated for global or local positioning, the generated signal can be presented as the sum of several signals based on different PRN codes with different amplitudes, chip rates and subcarriers.

[0005] Navigation signals are known that are generated as the sum of different codes. For example, the Galileo Composite Binary Offset Carrier ("CBOC") is a satellite signal that is generated as the sum of different codes. Some components of the CBOC signal are transmitted with a larger amplitude than others. A feature of the device that generates such a CBOC signal is the availability of a single numerically controlled oscillator ("NCO") that causes all transition aspects of the signal level. In other words, the added signal components all have the same code phase. The device does not adjust the phase using any value. Such a device cannot be used to generate a signal to subtract from the received signal and, as a result, cannot be used to weaken a jamming signal.

[0006] Known methods and devices for obtaining code phases with accurately generated leading parts with the help of an interpolator at the output of the PRN generator are similar to the above-mentioned methods. The interpolator is a bank of transversal filters. In order to interpolate the multilevel signal at the output of the generator, all multiplication operations in the interpolator are multi-digit. The advantage of this implementation when subtracting undesired signals is the quality representation of the signal. The main disadvantage is the relatively high cost of the interpolator, which generally uses a lot of area in the microchip. Moreover, the added interpolator cannot be used for generating a composite signal for a local positioning system. To generate a multilevel composite signal, it is necessary to combine devices such as those described above, which may require additional hardware costs.

[0007] Another method to solve the near-far problem is to subtract a copy of the unwanted signal from the received signal. Such subtraction is performed at the output of the correlator. The subtracted value is taken from a table containing the cross-correlation functions of the interfering unwanted signal and the desired signal for all possible code phases and Doppler offsets. This method allows to correct the desired signal by eliminating the effect of the interference on the level of the correlation result. The disadvantage of this method is that it requires the storage and application of large tables for all possible pairs of unwanted and desired signals. Certain signals (e.g. signals that are not currently tracked because they have not yet been discovered) cannot be corrected in this way.

[0008] The above methods and devices can solve the problem of generating a wideband PRN signal to some extent, but solving multiple functions with the same device requires additional hardware, which can be cost prohibitive. Summary of the Invention

[0009] In one embodiment, an apparatus for forming a pseudorandom wideband signal includes a set of channels each having a numerically controlled oscillator ("NCO") with a controlled frequency and phase and a pseudorandom number ("PRN") code generator, where the NCO generates a strobe that is output to the PRN code generator. The PRN code generator forms a new sequence element of +1 or -1 in response to the strobe. The apparatus also includes a first modulator having a plurality of weighting coefficients, a plurality of multipliers each multiplying by one of the weighting coefficients, a summer outputting a sum of output signals of the plurality of multipliers, and a mixer having a quadrature output signal that multiplies the output of the summer by a sine and cosine of a low intermediate frequency. The apparatus also includes a processor for controlling the set of channels, a transceiver module for receiving and / or transmitting the quadrature signals, and an interface for connecting the output of the mixer to the transceiver module.

[0010] In one embodiment, the interface comprises a quadrature DAC, the input of which is connected to the quadrature mixer output and the output of which is connected to an RF path (RF-tract). The interface may alternatively comprise a quadrature ADC, the input of which is connected to the RF front-end and the output of which is applied to the output of the quadrature mixer.

[0011] In one embodiment, a quadrature ADC and a quadrature DAC are additionally included in the interface, the inputs of the quadrature ADCs and the outputs of the quadrature DACs are connected to the RF front end, the signal from the output of the quadrature DAC is converted to an intermediate frequency or radio frequency in the transmit section of the RF front end and converted back to a zero or near-zero frequency in the receive section of the RF front end, and the signal is added to or replaces a signal received from a radio broadcast antenna at the radio frequency.

[0012] In one embodiment, the device may be part of a transmitter or receiver of a local positioning signal or part of a GNSS receiver.

[0013] A method for forming a pseudorandom wideband signal is also disclosed herein. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a schematic diagram of a wideband pseudorandom noise ("WPRN") former according to one embodiment. [Figure 2A] 2 is a detail of one embodiment of an interface for local positioning for subtracting a third-party interference signal from a received signal shown in FIG. 1; [Figure 2B] 2 is a detail of one embodiment of an interface for calibration of a Global Navigation Satellite System ("GNSS") receiver shown in FIG. 1; [Figure 2C] 2 is a detail of one embodiment of an interface for local positioning at a transmitter shown in FIG. 1; [Figure 2D] FIG. 2 is a detail of one embodiment of an interface shown in FIG. 1 that transmits a signal to an antenna and subtracts the transmitter near-end echo from the signal received by a millimeter-range radar from this antenna or another antenna. [Diagram 3] 1 is a specific example of the use of a channel with a code generator according to one embodiment. [Figure 4] 1 is a WPRN former including additional components according to an embodiment. [Diagram 5] FIG. 2 is a block diagram of an embodiment including a digital combiner. [Figure 6] FIG. 1 is a schematic diagram of a WPRN former for use in a navigation receiver. [Figure 7] FIG. 2 is a schematic diagram of a time code multiplexer and a navigation channel according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Wideband pseudorandom noise shapers (WPRN shapers) are used to accomplish several tasks, including calibrating Global Navigation Satellite System (GNSS) radio frequency (RF) front-ends with pseudolite signals, generating synthetic signals for local positioning, transmitting signals from nearby transmitters which are further subtracted from the received signal to partially solve the near-far problem, generating signals for truck-platooning, millimeter-range radars, and prism direction finding for total stations.

[0016] In one embodiment, the basic WPRN former comprises: (a) a set of channels having a code generator, each channel having a PRN code generator and an NCO having a controlled frequency and phase, the output of the NCO generating a strobe that is sent to the PRN code generator, the PRN code generator generating new elements of a sequence of +1 and -1 in response to the received strobe; (b) (1) Multiple weighting factors, (2) a plurality of multipliers that multiply an output of one of the plurality of PRN code generators by a weighting coefficient; (3) an adder that outputs the sum of the outputs of the multipliers; and (4) A mixer that multiplies the output of the summer by a sine and cosine of an intermediate frequency (low IF) close to zero to produce a quadrature output; a modulator having (c) a processor controlling a channel set having a code generator; (d) a transceiver device including an RF front end and an antenna for receiving / transmitting quadrature signals; (e) an interface for connecting an output of the quadrature mixer to a transceiver for receiving / transmitting the quadrature signal; Equipped with. In one embodiment, the output of the mixer of the WPRN former transmits the broadcast orthogonal signal converted to a radio frequency and / or adds the orthogonal signal from the mixer output to a received broadcast signal converted to a frequency of zero or near zero by the orthogonal signal or replaces the received orthogonal signal converted to a frequency of zero or near zero. In one embodiment, the number of channels in the channel set is an integer multiple greater than the number of weighting coefficients in the plurality of weighting coefficients, and the clock rate of the NCO is the same integer multiple less than the bandwidth of the signals transmitted and / or received by the antenna of the transceiver module.

[0017] 1 shows a schematic diagram of a wideband pseudorandom noise ("WPRN") former 10 according to one embodiment. FIG. 1 shows a CPU 100, a channel with code generators 101(1)...101(N), a code rate numerically controlled oscillator (CRNCO) 102, a code generator 103, a data buffer 104, an XOR 105, a PRN code S106, a data synchronization signal S107, data S108, a 1-bit pseudorandom sequence with data S109, a modulator 110, and weight multiplexers 112(1)...112(N). 1 illustrates WPRN former 10 comprising: multiplier units 113(1)···113(N), 115, 116, weighting coefficients 114(1)···114(N), intermediate frequency NCO ("IFNCO") 117, cosine unit 118, sine unit 119, cosine modulated signal S120, sine modulated signal S121, interface 122, RF path 123, antenna 124, and summer unit 125. In one embodiment, a digital quadrature mixer (i.e., a mixer with quadrature outputs) includes unit 115, unit 116, IFNCO 117, cosine unit 118, and sine unit 119.

[0018] In one embodiment, before operation, the CPU 100 initializes the CRNCO 102, the code generator 103, the data buffer 104, the weighting coefficients 114(1)...114(N), the intermediate frequency of the IFNCO 117, and the coding rate and initial phase of the interface 122.

[0019] CRNCO 102 generates a strobe at the code rate. The strobe is input to code generator 103. Code generator 103 generates a PRN code S106 that is input to XOR 105. Code generator 103 generates a data synchronization signal S107 that is input to data buffer 104. Data buffer 104 outputs signal S108 that is input to XOR 105. The data of signal S108 output from data buffer 104 is modified according to signal S107. If necessary, CPU 100 writes new data to data buffer 104. XOR 105 outputs a 1-bit pseudorandom sequence with data S109.

[0020] Signals S109(1)...S109(N) are output from the channel with code generators 101(1)...101(N) and input to modulator 110. In modulator 110, signals S109(1)...109(N) are input to the control inputs of weight multiplexers 112(1)...112(N). If S109 is active, a value -1 is input to output unit 112, otherwise a value +1 is input to output unit 112. The outputs of output units 112(1)...112(N) are input to multipliers 113(1)...113(N). The outputs of weight coefficients 114(1)...114(N) are input to multipliers 113(1)...113(N). The output of output unit 112 and the output of output unit 114 are multiplied by multiplier 113 and input to adder 125 where multiplication results 113(1) to 113(N) are added. The output of adder 125 is input to multiplier unit 115 and multiplier unit .

[0021] The IFNCO 117 generates an intermediate frequency phase which is input to a cosine unit 118 and a sine unit 119. The output of the cosine unit 118 is input to a multiplier unit 115. The output of the sine unit 119 is input to a multiplier unit 116.

[0022] In multiplier unit 115, the output of adder unit 125 is multiplied by the output of cosine unit 118. That is, the output of adder unit 125 is modulated by the output of cosine unit 118.

[0023] In multiplier unit 116, the output of adder unit 125 is multiplied by the output of sine unit 119. That is, the output of adder unit 125 is modulated by the output of sine unit 119. In one embodiment, multiplier unit 115 and multiplier unit 116 function as quadrature mixers disposed in modulator 110. The output of multiplier unit 115 is signal S120. The output of multiplier unit 116 is signal S121. Signals S120 and S121 from the output of modulator 110 are input to interface 122. The output of interface 122 is input to RF unit 123, which outputs a signal to antenna 124.

[0024] During operation, CPU 100 controls CRNCO 102, data buffer 104, the code frequency and phase of weighting coefficients 114(1)...114(N), and the frequency and phase of IFNCO 117. A channel having code generators 101(1)...101(N) generates signals S109(1)...S109(N) by superimposing data S108 on code signal S106, and the S109s can be shifted in time (phase) from one another.

[0025] In modulator 110, signals S109(1)...S109(N) are given a positive or negative sign, scaled by weighting factors 114(1)...114(N), and summed and modulated in cosine unit 118 and sine unit 119.

[0026] This arrangement makes it possible to generate complex multi-level composite signals or to interpolate and smooth the front without using conventional complementers, which involve sophisticated control circuits and the multiplication of many multi-bit data. Both of these functions are implemented using several NCOs, where different code phases and weighting factors are preset and the results are summed. Since the weighting factors are multiplied by +1 or -1, this multiplication operation can be implemented with a compact multiplier that occupies less space than a multi-bit multiplier.

[0027] The signal at the output of adder unit 125 is brought to an intermediate frequency by sine and cosine multiplication, which in one embodiment is necessary for most of the tasks to be solved.

[0028] Depending on the problem to be solved, the device may use different embodiments of the interface 122. Such embodiments may be changed by reconfiguring the interface, allowing the same device to be used for different applications. Figures 2A, 2B, 2C, and 2D show different embodiments of the interface 122.

[0029] 2A shows an interface 122 comprising an analog-to-digital converter ("ADC") 205 and an adder unit 130 and an adder unit 131. From the RF front end 123, the signal is fed to the ADC 205 for digitization, and the digitized quadrature signal is input to the adder unit 130 and the adder unit 131, and added to the signal of the multiplier unit 115 (also called a quadrature mixer) and the multiplier unit 116 (also called a quadrature mixer). The output of the adder unit 130 and the adder unit 131 is input to the signal processing section 126 (signal processor) for further processing. This interface implementation can be used for local positioning to subtract third party interference signals from the received signal.

[0030] FIG. 2B shows the interface 122 including a digital-to-analog converter ("DAC") 202 and an ADC 205. The output of the quadrature mixer 115 and the quadrature mixer 116 are input to the DAC 202 and converted to an intermediate radio frequency in the transmit section of the RF front end 123. The output is then shifted to a zero or near-zero frequency in the receive section of the RF 123 and the signal is added to or replaces the received broadcast radio signal from the antenna 124. Such an embodiment can be applied to the calibration of a GNSS receiver. In some embodiments, the RF front end is calibrated before the GNSS receiver starts searching and tracking satellite signals. In such an embodiment, during the calibration phase, the signal from the antenna is replaced by a signal generated by the RF switch. After the calibration phase, the RF switch is reconfigured to provide a path for the satellite signal from the antenna. In another embodiment, the RF front end is calibrated simultaneously with the reception of the satellite signal. In this embodiment, a signal generated with a relatively low power is added to the signal from the antenna. A combiner, a differential op amp, or other RF components can be used to sum the signals.

[0031] In some embodiments, the signal output by the transmitter of the RF front end 123 is a calibration signal. The calibration signal is, in some embodiments, similar to a GNSS navigation signal. In some embodiments, the calibration signal is a specific signal having characteristics that are not similar to the characteristics of a GNSS navigation signal. In some embodiments, the characteristics of the specific signal are periodically changed during the calibration process.

[0032] 2C shows the interface 122 including the DAC 202. The output signals of the quadrature mixer 115 and the quadrature mixer 116 pass through the DAC 202 and are converted to an intermediate radio frequency in the transmit section of the RF 123. Such an implementation can be used for local positioning in the transmitter. In some embodiments, the code phase and / or carrier phase of the generated signal are adjusted according to the corresponding code phase and / or carrier phase of the master transmitter or according to a GNSS reference signal. In other embodiments, the parameters are adjusted according to a reference signal locally connected to the transmitter.

[0033] 2D shows interface 122 with subtractor 206, DAC 202 and ADC 205. The output signal from modulator 110(1) passes through DAC 202 and is converted to an intermediate frequency in the transmit section of RF 123. Another mode of operation is also possible, in which a broadcast signal is input to the receive section of RF 123, where it is converted to a zero or near-zero frequency, digitized and added or subtracted in subtractor 206 to the signal from modulator 110(2). This implementation can transmit a signal to an antenna and subtract the near-end echo of its own transmitter from the signal received from this or another antenna in a millimeter-range radar.

[0034] FIG. 3 shows a particular case where a channel with code generators 101(1), 101(2), 101(3), 101(4), 101(5) generates signals S109(1), S109(2), S109(3), S109(4), S109(5). At the same time, the PRN codes S106 (shown in FIG. 1) are phase shifted relative to each other by Tdelta. Tdelta is used to specify the phase offset of the code frequency of the CRNCO 102 during initialization. The weighting factors 114(1), 114(2), 114(3), 114(4), 114(5) are set equal to a value of +1, and the weighting factors (6)...(N) are equal to a value of 0. At the output of the adder 125, a multilevel PRN code with sloping edges is generated.

[0035] 4 illustrates an embodiment of a WPRN former including additional features. In one embodiment, the WPRN former 40 can be implemented with two antennas (transmit 124(1), receive 124(2)) or with a single transmit / receive antenna 124 (not shown).

[0036] 4, to fabricate a more complex embodiment of WPRN former 40, the following components are added to the embodiment shown in FIG 1: digital combiners 201(1)...201(2), DACs 202(1)...202(2), analog summing unit 203, subtractor multiplexer 204, ADC 205, subtractor unit 206, navigation receiver 207, and decimator 208.

[0037] 4, the number of the following units is increased: modulators 110(1)...110(8), RF paths 123(1)...123(2), antennas 124(1)...124(2), and a channel with code generators 101(1)...101(N*2).

[0038] The WPRN former 40 operates at synchronous clock speeds CLKsend and CLKch. In one embodiment, CLKsend and CLKch can be the same speed. CLKch can also be, for example, twice (or 2^M times) slower than CLKsend.

[0039] The following components of WPRN former 40 operate at clock speed CLKsend: channel code generators 101(1)...101(N*2), modulators 110(1)...110(8), digital combiners 201(1)...201(2), DACs 202(1)...202(2), subtractor multiplexer 204, and part of decimator 208. The following components of WPRN former 40 operate at clock speed CLKch: part of decimator 208, subtractor 206, navigation receiver 207, and ADC 205.

[0040] Before operation, the CPU 100 adjusts the channel code generators 101(1)...101(N*2), the modulators 110(1)...110(8), the digital combiners 201(1)...201(2), the subtractor multiplexer 204, the decimator 208, the subtractor 206, the navigation receiver 207, and the ratios of the clocks CLKsend and CLKch.

[0041] The channel with code generator 101 generates a signal S109. From the output of the channel with code generators 101(1)...101(N), signals S109(1)...S109(N) are input to modulators 110(1)...110(4) where they are scaled and downconverted to an intermediate frequency. Signals S120 and S121 from the output of modulators 110(1)...110(4) are input to digital combiner 201(1) for further conversion. From the output of digital combiner 201(1) they are provided to the inputs of DAC 202(1) and subtractor multiplexer 204.

[0042] Returning to FIG. 1, in various embodiments, the interface 122 may include: (1) a quadrature DAC 202(1) and a quadrature DAC 202(2) in which DAC 202(2) is clocked with a half-cycle delay relative to DAC 202(1); (2) a splitter circuit having two quadrature inputs and two quadrature outputs, which converts the quadrature outputs of the mixers of the modulators 110(1)...110(8) and connects the quadrature outputs to the inputs of the DACs 202(1) and 202(2); (3) an analog component-by-component summing module for two orthogonal signals to obtain one orthogonal signal, in which a splitter generates an orthogonal output of the mixer such that after summing in the analog component-by-component summing module, there is a signal shaped as a DAC double clock rate signal (a signal with a clock rate twice that of the DAC), in which even samples are the output signal of the mixer of one modulator and odd samples are the output signal of the mixer of the other modulator, the output of the analog component-by-component summing module is connected to an RF front end, and the output of the RF front end is connected to a transmitting antenna; Equipped with. The device is part of a local positioning transmitter of the signal. In one embodiment, the splitter is part of the digital combiner 201.

[0043] Returning to Figure 4, signals S109(N+1)...S109(N*2) from the output of the channel with code generators 101(N+1)...101(N*2) are input to modulators 110(5)...110(8) where they are modulated. From the output of modulators 110(5)...110(8), signals S120, S121 are input to digital combiner 201(2) where they are converted. From the output of digital combiner 201(2), the signals are input to DAC 202(2) and subtractor multiplexer 204.

[0044] The signals from the outputs of DAC 202(1)...DAC(2) are summed in analog summer 203 and then input to RF path 123(1). An operational amplifier can function as analog summer 203. After passing through RF path 123(1), the signal is transmitted to antenna 124(1).

[0045] The output of the subtractor multiplexer 204 is input to a decimator 208. In the decimator 208, the signal is decimated according to a preset ratio of the clock rates CLKsend and CLKch. The output signal from the decimator 208 is input to a subtractor 206.

[0046] The signal from antenna 124(2) is input to RF path 123(2). After passing through RF path 123(2), the signal is input to ADC 205. The digitized signal from the output of ADC 205 is input to subtractor 206.

[0047] In subtractor 206, if necessary (e.g., as assigned by CPU 100), the signal from the output of decimator 208 is subtracted from the sampled signal from the output of ADC 205 and input to navigation receiver 207. In navigation receiver 207, the signal is processed.

[0048] In one embodiment, during operation, CPU 100 controls a channel having code generators 101(1)...101(N*2), modulators 110(1)...110(8), digital combiners 201(1)...201(2), subtractor multiplexer 204, decimator 208, subtractor 206, and navigation receiver 207.

[0049] 5 is a block diagram of an embodiment including a digital combiner circuit. In one embodiment, the digital combiner includes multiplexers 310(1...4), 311(1...4), 306, adders 320 and 321, subtractors 330 and 331, and splitter signals S350, S351, S360, and S361 and DAC input signals S340 and S341 in digital combiner 201.

[0050] In one embodiment, CPU 100 initiates and controls modulators 110(1)...110(8) and subtractor multiplexer 204. Prior to operation, CPU 100 adjusts multiplexers 310(1)...310(4), multiplexers 311(1)...311(4), and multiplexer 306. Digital combiner 201(1) and digital combiner 201(2) are paired.

[0051] The signals S120 and S121 from the outputs of the modulators 110(1) through 110(4) are input to a digital combiner 201(1). The signals S120 and S121 from the outputs of the modulators 110(5) through 110(8) are input to a digital combiner 201(2).

[0052] Signal S120 is input to multiplexers 310(1)...310(4). If the signals at the control inputs of multiplexers 310(1)...310(4) are active, then the output has signal S120, otherwise the output has the value 0. The output signals of multiplexers 310(1)...310(4) are input to adder 320 and added. The output signal of adder 320 is input to subtractor 330 and multiplexer 306.

[0053] Signal S121 is input to multiplexers 311(1)...311(4). If the signals at the control inputs of multiplexers 311(1)...311(4) are active, then the output has signal S121, otherwise the output has the value 0. The output signals of multiplexers 311(1)...311(4) are input to adder 321 and added. The output signal of adder 321 is input to subtractor 331 and multiplexer 306.

[0054] Signal S350 is signal S360 from the paired digital combiner 201. Signal S350 is input to subtraction unit 330 and summation unit 320. In subtraction unit 330, signal S350 is subtracted from the output signal of summation unit 320. The output signal of subtraction unit 330 is signal S360. S360 is provided to an input of multiplexer 306 and provided to the paired digital combiner 201. In some embodiments, digital combiner 201(1) has a delay of signal S360.

[0055] Signal S351 is signal S361 from paired digital combiner 201. Signal S351 is input to subtractor 331 and adder 321. In subtraction unit 331, signal S351 is subtracted from the output signal of adder unit 321. The output signal of subtraction unit 331 is signal S361. Signal S361 is input to multiplexer 306 and input to paired digital combiner 201. In some embodiments, digital combiner 201(1) has a delay of signal S361.

[0056] When the signal at the control input of multiplexer 306 is inactive, signal S360 is provided to the output and signal S340 is equal to S360.

[0057] When the signal at the control input of multiplexer 306 is inactive, signal S361 is provided to the output and signal S341 is equal to S361.

[0058] When the signal at the control input of multiplexer 306 is active, the output signal of unit 320 is provided to the output and signal S340 is equal to the output signal of unit 320.

[0059] When the signal at the control input of multiplexer 306 is active, the output signal of adder 321 is provided to the output and signal S341 takes on the value of the output signal of adder 321.

[0060] The signals S340 and S341 from the output of the digital combiner 201(2) are input to the DAC 202(2) and the subtractor multiplexer 204.

[0061] From the outputs of modulators 110(1)...110(4), signals S120 and S121 are input to digital combiner 201(1). Digital combiner 201(1) operates in a similar mode as digital combiner 201(2). From the outputs of digital combiner 201(1), signals S340 and S341 are input to DAC 202(1) and subtractor multiplexer 204.

[0062] 6 shows an embodiment using a more complex embodiment of the WPRN former with navigation receiver 60. In this embodiment, instead of a channel with a code generator 101, there is a navigation channel 400. This embodiment also includes time code multiplexers 401(1)...401(2). Also in this embodiment, the clock CLKch is twice as slow as CLKsend.

[0063] In this embodiment, navigation channels 400(1)...400(N*4) are used to generate signal S109, and the remaining navigation channels 400 (numbered from greater than N*4 to N*4+K, where K is the limit amount of navigation signals that need to be received, the number of channels being sufficient to receive the required signals) process the signals arriving from subtractor 206. Time code multiplexers 401(1)...401(2) operate at a clock speed CLKsend.

[0064] In one embodiment, prior to operation, CPU 100 adjusts navigation channels 400(1)...400(N*4), modulators 110(1)...110(8), digital combiners 201(1)...201(2), subtractor multiplexer 204, decimator 208, subtractor 206, navigation receiver 207 (for channel numbers greater than N*4 to N*4+K), and the ratio of clock speeds of CLKsend and CLKch.

[0065] In this embodiment, the navigation channels 400(1)...400(N*4) generate signals S109(1)...S109(N*4). The signals S109(1)...S109(N*2) from the outputs of the navigation channels 400(1)...400(N*2) are input to a time code multiplexer 401(1) where the signal S109 is selected in time. The output of the time code multiplexer 401(1) is input to the modulators 110(1)...110(4) where it is scaled and down-converted to an intermediate frequency. From the outputs of the modulators 110(1)...110(4), the signals S120, S121 are input to the digital combiner 201(1) for further conversion. From the outputs of digital combiner 201(1), they are input to DAC 202(1) and subtractor multiplexer 204.

[0066] The signals S109(N*2+1)...S109(N*4) from the outputs of the navigation channels 400(N*2+1)...400(N*4) are input to a time code multiplexer 401(2), where the signal S109 is selected in time. The output of the time code multiplexer 401(2) is input to the modulators 110(5)...110(8), where it is scaled and down-converted to an intermediate frequency. The signals S120, S121 from the outputs of the modulators 110(5)...110(8) are input to a digital combiner 201(2) for further conversion. From the output of the digital combiner 201(2), they are input to a DAC 202(2) and a subtractor multiplexer 204.

[0067] The DAC202(2) operates on a clock delayed by a half cycle from the clock of the DAC202(1).

[0068] The signals output from DAC 202(1)...DAC(2) are summed in analog summer 203, and the resulting signal is provided to RF path 123(1) at a value close to twice the DAC clock rate. In one embodiment, an operational amplifier can function as analog summer 203. RF path 123(1) outputs a signal that is input to antenna 124(1).

[0069] The signal from the selected digital combiner 201(1)...201(2) passes through subtractor multiplexer 204. The output signal of subtractor multiplexer 204 is input to decimator 208. Decimator 208 decimates the signal according to a preset clock ratio of CLKsend and CLKch. The output signal of decimator 208 is input to subtractor 206.

[0070] Antenna signal 124(2) is input to RF path 123(2). After RF path 123(2), the signal is input to ADC 205. The sampled (digitized) signal from the output of ADC 205 is then input to subtractor 206. In subtractor 206, if assigned by CPU 100, the output signal of decimator 208 is subtracted from the sampled signal from the output of ADC 205 and provided to the input of navigation receiver 207 for processing.

[0071] In one embodiment, during operation, CPU 100 controls navigation channels 400(1)...400(N*4), modulators 110(1)...110(8), digital combiners 201(1)...201(2), subtractor multiplexer 204, decimator 208, subtractor 206, and navigation receiver 207 (the number of channels 400 can range from greater than N*4 to N*4+K).

[0072] FIG. 7 is a schematic diagram of a time code multiplexer and a navigation channel according to an embodiment. In this embodiment, a navigation channel 400 is used instead of the channel with the code generator 101. The clock CLKch is twice as slow as CLKsend. This embodiment includes a multiplexer 500, a time control multiplexer 501, a CRNCO 502, a code generator 503, a secondary code buffer 504, an XOR 505, a PRN code signal S506, a data synchronization signal S507, a secondary code signal S508, a 1-bit pseudorandom sequence with data S509, an integration period counter 510, a navigation channel intermediate frequency NCO 511, and a correlator 512. The secondary code buffer 504 is used to generate the secondary code signal S508 through the transfer of data. In one embodiment, the secondary code buffer 504 is used as the data buffer 104.

[0073] In one embodiment, CPU 100 activates and controls modulators 110(1) to 100(4) and subtractor 206. Before operation, CPU 100 initializes the following units of navigation channels 400(1) to 400(N*2): code frequency and initial phase of CRNCO 502, code generator 503, and secondary code buffer 504. In one embodiment, during operation, the following units are not used in navigation channels 400(1) to 400(N*4): integration period counter 510, navigation channel intermediate frequency NCO 511, and correlator 512. In one embodiment, before operation, CPU 100 initializes navigation channels (greater than N*4 to N*4+K), and during operation, CPU 100 controls navigation channels 400.

[0074] CRNCO 502 generates a code frequency that is input to code generator 503. Code generator 503 forms PRN code S506, which is input to XOR 505. Code generator 503 generates data synchronization signal S507, which is input to secondary code buffer 504. Secondary code signal S508 is output from secondary code buffer 504 and input to XOR 505. Secondary code signal S508 at the output of secondary code buffer 504 is modified according to signal S507. CPU 100 may additionally write new data to secondary code buffer 504. A 1-bit pseudorandom sequence with data S509 is output from XOR 505.

[0075] In one embodiment, the signal S509 is the same as the signal S109. The signal S109 from the navigation channels 400(1...N*4) is fed to the inputs of the time code multiplexer 401(1) and the multiplexer 500. The signal S109 (S509) is generated with the clock CLKch. The time code multiplexer 401(1) operates with a clock CLKsend that is twice the CLKch. The time control multiplexer 501 generates at its output a meandering signal that changes with each clock pulse of the clock CLKsend. The output signal of the time control multiplexer 501 is fed to the control input of the multiplexer 500. If the state of the control input of the multiplexer 500 is inactive, the signals S109(1)...S109(N) are output, otherwise the signals S109(N+1)...S109(N*2) are output. The signal from the output of unit 401(1) is input to modulators 110(1) through 110(4). Navigation channel 400 (greater than N*4 through N*4+K) processes the signal from the output of subtractor 206. In one embodiment, a method of forming a pseudorandom wideband signal comprises the steps of controlling the frequency and phase of a plurality of NCOs, each associated with a respective one of a set of channels; generating a strobe by one of the plurality of NCOs to a PRN code generator; forming a new sequence element of +1 or -1 in response to the strobe by the PRN code generator; multiplying one of a plurality of weighting coefficients by an output of the PRN code generator by one of a plurality of multipliers; outputting a sum of the output signals of the plurality of multipliers from a summer; multiplying the output of the summer with a low intermediate frequency sine and cosine by a mixer having a quadrature output signal; receiving the quadrature signal by a transceiver module; and transmitting the quadrature signal by the transceiver module, wherein the transceiver module transmits the quadrature signal output from the mixer and converted to a radio frequency, and adds the quadrature signal to or replaces the quadrature signal received from the antenna and converted to a frequency of zero or near zero. In one embodiment of the method, the method steps include mitigating unwanted signals received together with the navigation signals from the antenna from one of the transceiver modules or transmitters located within a transmission range of the transceiver module, In one embodiment of the method, the method steps include forming a combined signal including the signal received from the antenna and the locally generated signal, which is processed by the GNSS receiver to obtain a position of the GNSS receiver and which is processed as a calibration signal for calibrating the receiver RF front end upon receipt of the satellite signals.

[0076] It should be understood that the above detailed description is in all respects non-limiting, illustrative and exemplary. The scope of the invention disclosed herein should be determined not from the detailed description, but from the claims, which should be interpreted in accordance with the broadest scope permitted by patent law. It should be understood that the embodiments described and shown herein are merely illustrative of the principles of the invention, and that various modifications may be made by those skilled in the art without departing from the scope and spirit of the invention. Those skilled in the art could implement various other feature combinations without departing from the scope and spirit of the invention.

Claims

1. 1. An apparatus for forming a pseudorandom wideband signal, comprising: (a) a set of channels each having a numerically controlled oscillator (NCO) having a controlled frequency and phase, and a PRN code generator, the NCO configured to generate a strobe that is output to the PRN code generator, the PRN code generator configured to form a new sequence element of +1 or -1 in response to the strobe; (b) (1) a plurality of weighting factors; (2) a plurality of multipliers configured to multiply the output of the PRN code generator by one of a plurality of weighting coefficients; (3) an adder configured to output a sum of the output signals of a plurality of the multipliers; and (4) a mixer having quadrature output signals configured to multiply the output of the summer with a low-intermediate frequency (Low-IF) sine and cosine; a first modulator having (c) a processor configured to control the channel set; and (d) a transceiver module configured to receive and / or transmit quadrature signals, the transceiver including an RF front end and an antenna; (e) an interface configured to connect an output of the mixer and the transceiver module; Equipped with the transceiver module is configured to transmit the quadrature signals output from the mixer and converted to a radio frequency, or to add the quadrature signals to or replace the quadrature signals received from the antenna and converted to a zero or near-zero frequency signal; Device.

2. 2. The apparatus of claim 1, wherein the interface comprises a quadrature DAC, an input of the quadrature DAC connected to an output of the mixer and an output of the quadrature DAC connected to the RF front end.

3. 2. The apparatus of claim 1, wherein the interface comprises a quadrature ADC, an input of the quadrature ADC being connected to the RF front end and an output of the quadrature ADC being applied to an output of the quadrature mixer.

4. The interface further comprises a quadrature ADC and a quadrature DAC, the inputs of the quadrature ADC and the output of the quadrature DAC being connected to the RF front end, a signal from the output of the quadrature DAC being converted to an intermediate frequency or radio frequency in a transmit section of the RF front end and converted back to a zero or near-zero frequency in a receive section of the RF front end, the signal being added to or replacing a signal received from a radio broadcast antenna at the radio frequency.

2. The apparatus of claim 1.

5. The apparatus of claim 2 , wherein an output of the RF front end is sent to the antenna.

6. The apparatus of claim 3 , wherein the input of the RF front end is connected to the antenna.

7. 5. The apparatus of claim 4, which is part of a GNSS receiver, wherein an input of the receive portion of the RF front end is connected to the antenna.

8. The apparatus of claim 1, further comprising a second modulator similar to the first modulator.

9. the interface further comprises a quadrature ADC and a quadrature DAC, an output of the mixer of one of the modulators is subtracted from an ADC output signal, an output of the mixer of another of the modulators is connected through the quadrature DAC to a transmitter portion of the RF front end, an output of the transmitter portion of the RF front end is connected to a transmit / receive antenna, the transmit / receive antenna is also connected to a receiver portion of the RF front end, and an output of the receiver portion of the RF front end is connected to the quadrature ADC; 9. The device of claim 8, which is part of a radar.

10. 2. The apparatus of claim 1, wherein the number of channels in the channel set is an integer multiple greater than the number of weighting coefficients in the plurality of weighting coefficients, and the clock rate of the NCO is the same integer multiple less than a bandwidth of signals transmitted and / or received by the antennas in the transceiver module.

11. The interface includes: (1) a first DAC and a second DAC configured such that the second DAC operates at a clock speed delayed by a half cycle relative to the first DAC; (2) a splitter having two quadrature inputs and two quadrature outputs configured to convert quadrature outputs of the mixer of the first modulator and the second modulator, the quadrature outputs being connected to inputs of the first DAC and the second DAC; (3) a module for analog-adding two quadrature signals from the two DACs to obtain one quadrature signal; Further equipped with the splitter converts the quadrature outputs of the mixers such that after summing the outputs of the mixers a signal is generated which is shaped as a signal at twice the DAC clock rate, where even samples are samples from the output of the mixer of one modulator and odd samples are the output of the mixer of the other modulator; The output of the analog summing module is connected to the RF front end, the output of the RF front end is connected to a transmitting antenna, and the whole device is a part of a transmitter of a local positioning signal.

9. The apparatus of claim 8.

12. The apparatus of claim 11 , wherein the analog summing module in the interface is implemented with a differential op-amp.

13. The apparatus of claim 11 , wherein the analog summing module in the interface is implemented with a combiner.

14. 2. The apparatus of claim 1, further comprising a modulator similar to the first modulator, the output of the mixer of the modulator being input to a quadrature adder, and the output of the quadrature adder being input to the interface.

15. 2. The apparatus of claim 1, wherein a navigation channel is available as one of said set of channels.

16. 1. A method for forming a pseudorandom wideband signal, comprising the steps of: Controlling the frequency and phase of a plurality of NCOs associated with each of the channel sets; generating a strobe by one of the plurality of NCOs that is output to a PRN code generator; forming a new sequence element of +1 or -1 in response to the strobe by a PRN code generator; multiplying the output of the PRN code generator by one of a plurality of weighting factors by one of a plurality of multipliers; outputting a sum of the output signals of the plurality of multipliers from an adder; multiplying the output of said summer with a low intermediate frequency sine and cosine by a mixer having a quadrature output signal; receiving the orthogonal signals by a transceiver module; transmitting orthogonal signals by the transceiver module; Including, The transceiver module transmits the quadrature signals output from the mixer that have been converted to a radio frequency, and adds the quadrature signals to quadrature signals received from an antenna and converted to a frequency of zero or close to zero, or replaces the quadrature signals with quadrature signals received from the antenna and converted to a frequency of zero or close to zero. method.

17. 17. The method of claim 16, wherein each step of the method mitigates unwanted signals from either the transceiver module or a transmitter located within transmission range of the transceiver module, the unwanted signals being received along with the navigation signal from the antenna.

18. 17. The method of claim 16, wherein each step of the method comprises forming a combined signal including a signal received from the antenna and a locally generated signal, the combined signal being processed by a GNSS receiver to obtain a position of the GNSS receiver, and the combined signal being processed as a calibration signal for calibrating an RF front end of the receiver upon receiving satellite signals.

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