Semiconductor Device

Abstract

To provide: a semiconductor device with favorable electrical characteristics; a semiconductor device with high reliability; and a semiconductor device with stable electrical characteristics.SOLUTION: A semiconductor device includes a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order over the first insulating layer. The first insulating layer has a stacked-layer structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The second insulating layer includes an oxide. The third insulating film includes a part in contact with the semiconductor layer. The first insulating film includes silicon and nitrogen. The second insulating film includes silicon, nitrogen, and oxygen. The third insulating film includes silicon and oxygen. The semiconductor layer includes indium and oxygen.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have been attracting attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel among the plurality of oxide semiconductor layers contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Metal oxides that can be used for the semiconductor layer can be formed by sputtering or the like, and therefore can be used for the semiconductor layer of transistors that constitute large display devices. In addition, since it is possible to use a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon by improving it, capital investment can be reduced. In addition, transistors using metal oxides have higher field-effect mobility than those using amorphous silicon, and therefore a high-performance display device provided with a driver circuit can be realized. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2014-7399 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable display device.

[0007] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device having a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. A semiconductor layer, a second insulating layer, and a first conductive layer are stacked in this order over the first insulating layer. The first insulating layer has a stacked structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The second insulating layer contains an oxide. The semiconductor layer contains indium and oxygen. The third insulating film has a portion in contact with the semiconductor layer. The first insulating film contains silicon and nitrogen. The third insulating film contains silicon and oxygen. The second insulating film contains silicon, nitrogen, and oxygen. The second insulating film contains more oxygen than the first insulating film and less nitrogen than the third insulating film. The second insulating film contains less nitrogen than the first insulating film and more nitrogen than the third insulating film.

[0009] In the above, the semiconductor layer preferably contains M (M is one or more selected from aluminum, gallium, yttrium, and tin) and zinc. In this case, the semiconductor layer preferably has a region in which the content of indium is higher than the content of M.

[0010] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. A semiconductor layer, a second insulating layer, and a first conductive layer are stacked over the first insulating layer in this order. The first insulating layer has a stacked structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The semiconductor layer has a stacked structure in which a first metal oxide film and a second metal oxide film are stacked in this order. The second insulating layer contains an oxide. The first metal oxide film and the second metal oxide film each contain indium and oxygen. The second insulating layer has a portion in contact with the second metal oxide film. The third insulating film has a portion in contact with the first metal oxide film. The first insulating film contains silicon and nitrogen. The third insulating film contains silicon and oxygen. The second insulating film contains silicon, nitrogen, and oxygen. The second insulating film contains more oxygen than the first insulating film and less nitrogen than the third insulating film. The second insulating film contains less nitrogen than the first insulating film and more nitrogen than the third insulating film.

[0011] In the above, it is preferable to have a second conductive layer. In this case, the first insulating layer is located between the second conductive layer and the semiconductor layer. The second conductive layer has a region overlapping the semiconductor layer and the first conductive layer. The first insulating film has a portion in contact with the second conductive layer.

[0012] In the above, the second insulating film is preferably thicker than the first insulating film, and the second insulating film is preferably thicker than the third insulating film.

[0013] In the above, the thickness of the second insulating film is preferably 2 to 20 times the thickness of the first insulating film. The thickness of the second insulating film is preferably 2 to 20 times the thickness of the third insulating film. The thickness of the second insulating film is preferably 50% to 95% of the total thickness of the first insulating layer.

[0014] In the above, the second insulating layer preferably has a laminated structure in which a fourth insulating film, a fifth insulating film, and a sixth insulating film are laminated in this order. In this case, the fourth insulating film has a region in contact with the semiconductor layer. In addition, each of the fourth insulating film, the fifth insulating film, and the sixth insulating film preferably contains an oxide.

[0015] In the above, the first metal oxide film preferably contains gallium and zinc, and the second metal oxide film preferably contains gallium and zinc. In this case, the second metal oxide film preferably has a region having a higher indium content and a lower gallium content than the first metal oxide film.

[0016] Alternatively, in the above, it is preferable that the first metal oxide film contains gallium and zinc, and the second metal oxide film does not contain gallium.

[0017] In the above, it is preferable that a metal oxide layer is provided between the second insulating layer and the first conductive layer. In this case, it is preferable that the metal oxide layer contains one or more elements selected from aluminum, hafnium, tin, indium, gallium, and zinc. Effect of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, a highly reliable semiconductor device, a semiconductor device with stable electrical characteristics, or a highly reliable display device can be provided.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0020] [Figure 1]1A and 1B are diagrams illustrating configuration examples of transistors. [Diagram 2] 2A and 2B are diagrams illustrating configuration examples of transistors. [Diagram 3] 3A and 3B are diagrams illustrating configuration examples of transistors. [Figure 4] 4A to 4C are diagrams illustrating configuration examples of transistors. [Diagram 5] 5A to 5C are diagrams illustrating configuration examples of transistors. [Figure 6] 6A to 6C are diagrams illustrating configuration examples of transistors. [Figure 7] 7A to 7C are diagrams illustrating configuration examples of transistors. [Figure 8] 8A to 8D are diagrams illustrating configuration examples of transistors. [Figure 9] 9A to 9D are diagrams illustrating configuration examples of transistors. [Figure 10] 10A to 10D are diagrams illustrating configuration examples of transistors. [Figure 11] 11A to 11E illustrate a method for manufacturing a transistor. [Figure 12] 12A to 12D illustrate a method for manufacturing a transistor. [Figure 13] 13A and 13B illustrate a method for manufacturing a transistor. [Figure 14] 14A to 14D illustrate a method for manufacturing a transistor. [Figure 15] 15(A) to 15(C) are top views of the display device. [Figure 16] FIG. 16 is a cross-sectional view of the display device. [Figure 17] FIG. 17 is a cross-sectional view of the display device. [Figure 18] FIG. 18 is a cross-sectional view of the display device. [Figure 19] FIG. 19 is a cross-sectional view of the display device. [Figure 20] Fig. 20(A) is a block diagram of a display device, and Fig. 20(B) and Fig. 20(C) are circuit diagrams of the display device. [Figure 21] 21A, 21C, and 21D are circuit diagrams of a display device, and FIG 21B is a timing chart. [Figure 22] 22(A) and 22(B) are diagrams showing configuration examples of a display module. [Figure 23] 23(A) and 23(B) are diagrams showing configuration examples of electronic devices. [Figure 24] 24A to 24E are diagrams showing configuration examples of electronic devices. [Diagram 25] 25A to 25G are diagrams showing configuration examples of electronic devices. [Figure 26] 26A to 26D are diagrams illustrating configuration examples of electronic devices. [Figure 27] 27(A) to 27(F) show the results of TDS analysis. [Figure 28] 28A to 28D are diagrams showing the Id-Vg characteristics of transistors. [Figure 29] FIG. 29 shows the reliability test results of the transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0022] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component may be exaggerated for clarity.

[0023] In addition, the ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and do not limit the numbers.

[0024] In addition, in this specification, the terms "above" and "below" indicating the position are used for convenience in order to explain the positional relationship between components with reference to the drawings. The positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] In this specification and the like, the functions of a source and a drain of a transistor may be interchanged when transistors of different polarities are used, when the direction of current flow is changed during circuit operation, etc. For this reason, the terms source and drain can be used interchangeably.

[0026] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of a current flowing through a semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be determined to be one.

[0027] In addition, in this specification, "electrical connection" includes a case where a connection is made via "something having some electrical action." Here, "something having some electrical action" is not particularly limited as long as it enables transmission and reception of an electrical signal between the connection objects. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0028] In addition, in this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the terms "conductive layer" and "insulating layer" can sometimes be interchangeable with the terms "conductive film" and "insulating film".

[0029] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when the transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to the voltage V between the gate and the source of an n-channel transistor. gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0030] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0031] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or a substrate having an IC (Integrated Circuit) mounted thereon using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0032] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0033] The touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. The touch panel can also have a display panel and a touch sensor panel. Alternatively, the touch panel can have a function as a touch sensor inside or on the surface of the display panel.

[0034] In addition, in this specification and the like, a touch panel substrate on which a connector and / or an IC are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0035] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. In particular, in this embodiment, as an example of a semiconductor device, a transistor including an oxide semiconductor for a semiconductor layer in which a channel is formed will be described.

[0036] [Configuration example 1] [Configuration Example 1-1] FIG. 1A is a schematic cross-sectional view of a transistor 10 taken in the channel length direction.

[0037] The transistor 10 includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode.

[0038] A conductive film containing a metal or an alloy is preferably used for the conductive layer 112 because electrical resistance can be reduced. Note that a conductive film containing an oxide may be used for the conductive layer 112.

[0039] The metal oxide layer 114 has a function of supplying oxygen to the insulating layer 110. When a conductive film containing a metal or alloy that is easily oxidized is used as the conductive layer 112, the metal oxide layer 114 can also function as a barrier layer that prevents the conductive layer 112 from being oxidized by oxygen in the insulating layer 110. Note that the metal oxide layer 114 may be removed before the conductive layer 112 is formed, so that the conductive layer 112 and the insulating layer 110 are in contact with each other. Note that the metal oxide layer 114 may not be provided if it is not necessary.

[0040] The insulating layer 110 in contact with the semiconductor layer 108 preferably includes an oxide insulating film. The insulating layer 110 more preferably includes a region that contains oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 preferably includes an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the insulating layer 110 after the film formation in an oxygen atmosphere, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0041] The insulating layer 110 can be formed by, for example, a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method, a thermal CVD method, etc.

[0042] In particular, it is preferable that the insulating layer 110 be formed by the PECVD method.

[0043] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. The semiconductor layer 108 preferably contains at least indium and oxygen. When the semiconductor layer 108 contains an oxide of indium, carrier mobility can be increased. For example, a transistor that can pass a larger current than a transistor using amorphous silicon can be realized.

[0044] A region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region. The semiconductor layer 108 preferably has a pair of low-resistance regions 108n sandwiching the channel formation region. The low-resistance regions 108n have a higher carrier concentration than the channel formation region and function as a source region and a drain region.

[0045] The low-resistance region 108n can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier concentration, a region having a large amount of oxygen vacancies, a region having a high hydrogen concentration, or a region having a high impurity concentration.

[0046] The insulating layer 103 has a stacked structure of an insulating film 103a, an insulating film 103b, and an insulating film 103c. The insulating film 103c is in contact with the semiconductor layer .

[0047] The insulating layer 103 preferably functions as a barrier layer that suppresses diffusion of impurities from the formation surface into the semiconductor layer 108 and the like. The insulating layer 103 preferably satisfies one or more of the following, and more preferably all of them: low film stress, low release of hydrogen and water, and low diffusion of hydrogen and water.

[0048] Of the three insulating films included in the insulating layer 103, an insulating film containing nitrogen is preferably used for the insulating film 103a located closest to the surface to be formed. On the other hand, an insulating film containing oxygen is preferably used for the insulating film 103c in contact with the semiconductor layer 108. In addition, the three insulating films included in the insulating layer 103 are preferably formed successively without exposure to air using a plasma CVD apparatus.

[0049] The insulating film 103a is preferably a dense film that can prevent diffusion of impurities from below. The insulating film 103a is preferably a film that can block metal elements, hydrogen, water, and the like contained in a member (such as a substrate) on the surface on which the insulating film 103a is to be formed. For this reason, an insulating film formed under conditions with a lower film formation rate than the insulating film 103b can be used for the insulating film 103a.

[0050] The insulating film 103a may be, for example, an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film. In particular, it is preferable to use a dense silicon nitride film formed by using a plasma CVD apparatus as the insulating film 103a. By using such an insulating film containing nitrogen, even if the insulating film is thin, it is possible to suitably suppress the diffusion of impurities from the surface to be formed.

[0051] In this specification, an oxynitride refers to a material having a higher oxygen content than nitrogen, and a nitride oxide refers to a material having a higher nitrogen content than oxygen. For example, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0052] In addition, in the present specification, when an oxynitride and a nitride oxide each containing the same element are described, the oxynitride includes a material that satisfies either one or both of the following: the oxygen content is higher than that of the nitride oxide and the nitrogen content is lower. Similarly, the nitride oxide includes a material that satisfies either one or both of the following: the oxygen content is lower than that of the oxynitride and the nitrogen content is higher. For example, when silicon oxynitride and silicon nitride oxide are described, the silicon oxynitride includes a material that has a higher oxygen content and a lower nitrogen content than that of silicon nitride oxide. Similarly, the silicon nitride oxide includes a material that has a lower oxygen content and a higher nitrogen content than that of silicon oxynitride.

[0053] The insulating film 103c in contact with the semiconductor layer 108 is preferably formed using an insulating film containing an oxide. In particular, it is preferable to use an oxide film for the insulating film 103c. In addition, it is preferable to use a dense insulating film whose surface does not easily adsorb impurities such as water as the insulating film 103c. In addition, it is preferable to use an insulating film with as few defects as possible and in which impurities such as water and hydrogen are reduced.

[0054] The insulating film 103c preferably has a region that contains oxygen in excess of the stoichiometric composition. In other words, the insulating film 103c is preferably an insulating film that can release oxygen by heating. For example, oxygen can be supplied to the insulating film 103c by forming the insulating film 103c in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the formed insulating film 103c in an oxygen atmosphere, or forming an oxide film on the insulating film 103c in an oxygen atmosphere. Alternatively, oxygen can be supplied to the insulating film 103c from an insulating film that can release oxygen by heating that is formed on the insulating film 103c and then performing heat treatment.

[0055] Furthermore, oxygen can be supplied to the insulating film 103c when the metal oxide film to be the semiconductor layer 108 is formed by a sputtering method in an atmosphere containing oxygen. By performing heat treatment after the metal oxide film to be the semiconductor layer is formed, oxygen in the insulating film 103c can be supplied to the metal oxide film, and oxygen vacancies in the metal oxide film can be reduced.

[0056] The insulating film 103c can be, for example, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. In particular, it is preferable to use a silicon oxide film or a silicon oxynitride film as the insulating film 103c.

[0057] The insulating film 103b located between the insulating films 103a and 103c is preferably an insulating film that has low stress and is deposited at a high deposition rate. For example, the insulating film 103b is preferably a film that has lower stress than the insulating films 103a and 103c. Furthermore, the insulating film 103b is preferably a film that is deposited at a high deposition rate than the insulating films 103a and 103c.

[0058] The insulating film 103b is preferably an insulating film that releases as little hydrogen or water as possible. By using such an insulating film, hydrogen or water can be prevented from diffusing from the insulating film 103b through the insulating film 103c to the semiconductor layer 108 due to heat applied during a heat treatment or other process, and the carrier concentration in the channel formation region of the semiconductor layer 108 can be reduced.

[0059] Furthermore, the insulating film 103b is preferably an insulating film that does not easily absorb oxygen. In other words, it is preferable to use an insulating film through which oxygen does not easily diffuse. This can prevent a decrease in the amount of oxygen supplied to the semiconductor layer 108 due to diffusion of oxygen from the insulating film 103c to the insulating film 103b when heat treatment is performed to supply oxygen from the insulating film 103c to the semiconductor layer 108 (or a metal oxide film to be the semiconductor layer 108).

[0060] The insulating film 103b can be, for example, an insulating layer containing one or more of a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an aluminum nitride film, and a hafnium nitride film. In particular, it is preferable to use a silicon nitride oxide film or a silicon nitride film as the insulating film 103b.

[0061] Of the insulating films 103a, 103b, and 103c constituting the insulating layer 103, it is preferable that the insulating film 103b is made the thickest. The thickness (total thickness) of the insulating layer 103 can be determined based on the value of the relative dielectric constant of each insulating film and the thickness of each insulating film, taking into consideration the value of the relative dielectric constant required for the insulating layer 103 and the dielectric strength performance required for the insulating layer 103. That is, the thicknesses of the insulating films can be adjusted relative to one another within a range that satisfies the above requirements.

[0062] In particular, the insulating film 103b is preferably thicker than the insulating film 103a. By making the insulating film 103b thicker than the insulating film 103a, even when a film that easily releases hydrogen by heating is used as the insulating film 103a, the amount of hydrogen that can reach the insulating film 103c can be reduced. Furthermore, by making the insulating film 103a thinner than the insulating film 103b, the volume of the insulating film 103a can be relatively small, and therefore the amount of hydrogen that the insulating film 103a can release can be reduced.

[0063] In addition, the insulating film 103b is preferably thicker than the insulating film 103c. If the insulating film 103c is too thick, when a process for supplying oxygen into the insulating film 103c is performed, the amount of oxygen remaining in the insulating film 103c without being released by heating increases, which may result in a decrease in the amount of oxygen that can be supplied to the semiconductor layer 108 (or the metal oxide film that becomes the semiconductor layer 108). Therefore, by making the insulating film 103c thinner (reducing the volume) than the insulating film 103b, the amount of oxygen remaining in the insulating film 103c after heating can be reduced. As a result, the ratio of oxygen supplied to the semiconductor layer 108 to the oxygen supplied to the insulating film 103c can be increased, and the amount of oxygen supplied to the semiconductor layer 108 can be effectively increased.

[0064] Furthermore, by forming the thickest insulating film 103b under conditions of a high film formation rate and forming the thinner insulating films 103a and 103c to be dense films under conditions of a low film formation rate, the film formation time of the insulating layer 103 can be shortened and productivity can be increased without impairing reliability.

[0065] Here, the insulating film 103a is preferably an insulating film containing at least silicon and nitrogen, typically a silicon nitride film or a silicon nitride oxide film. The insulating film 103b is preferably an insulating film containing at least silicon, nitrogen, and oxygen, typically a silicon nitride oxide film or a silicon oxynitride film. The insulating film 103c is preferably an insulating film containing at least silicon and oxygen, typically a silicon oxide film or a silicon oxynitride film. At this time, the amount of oxygen contained in the insulating film 103b is preferably greater than that of the insulating film 103a and less than that of the insulating film 103c. The amount of nitrogen contained in the insulating film 103b is preferably less than that of the insulating film 103a and more than that of the insulating film 103c.

[0066] The oxygen and nitrogen contents of the insulating films 103a, 103b, and 103c can be analyzed by secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or other analytical methods. 3 or more than 1 atoms / cm 3 On the other hand, when the content of the target element in the film is low (e.g., 0.5 atoms / cm or more), XPS is suitable. 3 or less than 1atoms / cm 3 In the following cases, SIMS is suitable. When comparing the contents of elements in a film, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0067] The thickness of insulating film 103b is preferably at least 2 times, more preferably at least 3 times, and more preferably at least 5 times, and is preferably at most 20 times, and is preferably at most 15 times, the thickness of insulating film 103a. The thickness of insulating film 103b is preferably at least 2 times, more preferably at least 3 times, and more preferably at least 5 times, and is preferably at most 20 times, and is preferably at most 15 times, the thickness of insulating film 103c. The above upper and lower limit values ​​can be combined arbitrarily.

[0068] The thickness of the insulating film 103b can be set to 34% or more, preferably 40% or more, more preferably 50% or more, even more preferably 60% or more, even more preferably 70% or more, and even more preferably 80% or more, and 95% or less, or 90% or less, when the thickness of the entire insulating layer 103 (also referred to as the total thickness) is 100%. The higher the ratio of the thickness of the insulating film 103b to the total thickness of the insulating layer 103, the higher the productivity can be.

[0069] The insulating film 103a is preferably as thin as possible, for example, 5 nm or more, preferably 8 nm or more, more preferably 10 nm or more, and even more preferably 15 nm or more, and can be 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. The above upper and lower limits can be combined arbitrarily. Typically, the film thickness is preferably 15 nm or more and 50 nm or less, or 15 nm or more and 20 nm or less.

[0070] It is also preferable that the insulating film 103c is as thin as possible, for example, 5 nm or more, preferably 8 nm or more, more preferably 10 nm or more, and even more preferably 15 nm or more, and can be 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. The above upper and lower limit values ​​can be arbitrarily combined. Typically, the film thickness is preferably 15 nm or more and 50 nm or less, or 15 nm or more and 20 nm or less.

[0071] It is preferable that both the insulating film 103a and the insulating film 103c are as thin as possible, but it is extremely important that they can be formed under conditions with small variations in accordance with the performance of a film formation apparatus. Therefore, it is preferable to select the minimum thickness for each of the insulating film 103a and the insulating film 103c so that the variations are sufficiently small.

[0072] The thickness of insulating film 103b may be determined by subtracting the thicknesses of insulating films 103a and 103c from the total thickness of insulating layer 103, which is determined so as to satisfy the required physical properties such as dielectric constant and withstand voltage. For example, insulating film 103b is preferably 20 nm or more, 50 nm or more, 100 nm or more, 150 nm or more, or 200 nm or more, and 500 nm or less, 400 nm or less, or 350 nm or less. The above upper and lower limits can be combined in any combination.

[0073] Among the insulating films 103a, 103b, and 103c, the insulating film 103b may have a smaller film density than the other two insulating films. Therefore, in a transmission electron microscope (TEM) image of the cross section of the insulating layer 103, the insulating films 103a, 103b, and 103c may be observed as different contrasts due to the difference in film density, and may be distinguished from each other. In particular, even if a silicon nitride film or a silicon nitride oxide film formed by a plasma CVD method is used for each of the insulating films 103a and 103b, the boundary between them may be confirmed. When the compositions and densities are similar, the boundary between them may be unclear.

[0074] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 108, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0075] The semiconductor layer of the transistor preferably contains a metal oxide (also referred to as an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single crystal silicon).

[0076] When a metal oxide is used as the semiconductor layer 108, it is preferable that the metal oxide contains, for example, indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0077] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) as the semiconductor layer.

[0078] The semiconductor layer may be made of an oxide containing one or more of aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium in addition to indium, gallium, and zinc. In particular, it is preferable to use an oxide containing tin, aluminum, or silicon in addition to indium, gallium, and zinc in the semiconductor layer, because this can provide a transistor with high field-effect mobility.

[0079] When the semiconductor layer is an In-M-Zn oxide, the sputtering target used for depositing the In-M-Zn oxide preferably has an atomic ratio of In to M of 1 or more. Examples of atomic ratios of metal elements in such a sputtering target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=10:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5. In the above, when two or more kinds of elements are contained as the element M, the proportion of M in the above atomic ratio corresponds to the sum of the numbers of atoms of the two or more metal elements.

[0080] As the sputtering target, it is preferable to use a target containing a polycrystalline oxide, since it is easy to form a semiconductor layer having crystallinity. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer is In:M:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer to be formed may be close to In:M:Zn=4:2:3 [atomic ratio].

[0081] When describing the atomic ratio as In:M:Zn=4:2:3 or thereabout, it includes the case where, when In is 4, M is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When describing the atomic ratio as In:M:Zn=5:1:6 or thereabout, it includes the case where, when In is 5, M is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. When describing the atomic ratio as In:M:Zn=1:1:1 or thereabout, it includes the case where, when In is 1, M is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0082] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 preferably contains a metal oxide containing at least indium and oxygen. The semiconductor layer 108 may also contain zinc in addition to these. The semiconductor layer 108 may also contain gallium.

[0083] Here, the composition of the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 10. For example, by increasing the indium content in the semiconductor layer 108, carrier mobility is improved, and a transistor with high field-effect mobility can be realized.

[0084] One of the indicators for evaluating the reliability of transistors is the Gate Bias Stress Test (GBT), which applies an electric field to the gate and holds it there. Among them, a test in which a positive potential is applied to the gate with respect to the source potential and drain potential and it is held at high temperature is called the Positive Bias Temperature Stress (PBTS) test, and a test in which a negative potential is applied to the gate and it is held at high temperature is called the Negative Bias Temperature Stress (NBTS) test. In addition, the PBTS test and the NBTS test, which are performed under irradiation with light such as white LED light, are called the Positive Bias Temperature Illumination Stress (PBTIS) test and the Negative Bias Temperature Illumination Stress (NBTIS) test, respectively.

[0085] In particular, in an n-type transistor using an oxide semiconductor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows), so the amount of change in the threshold voltage in a PBTS test is one of the important items to focus on as an index of the reliability of the transistor.

[0086] Here, by using a metal oxide film that does not contain gallium or has a low gallium content as the composition of the semiconductor layer 108, the amount of variation in threshold voltage in the PBTS test can be reduced. When gallium is contained, the composition of the semiconductor layer 108 preferably has a lower gallium content than an indium content. This makes it possible to realize a highly reliable transistor.

[0087] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the more significant the degradation in the PBTS test. The generation of the defect levels can be suppressed by reducing the gallium content in the part of the semiconductor layer that contacts the gate insulating layer.

[0088] The reason why PBTS degradation can be suppressed by not including gallium or by reducing the gallium content is, for example, as follows. Gallium contained in the semiconductor layer 108 has a property of attracting oxygen more easily than other metal elements (for example, indium and zinc). Therefore, it is presumed that at the interface between the metal oxide film containing a large amount of gallium and the insulating layer 110 containing oxide, gallium bonds with excess oxygen in the insulating layer 110, which makes it easier to generate carrier (here, electron) trap sites. Therefore, it is considered that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing the threshold voltage to fluctuate.

[0089] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, a metal oxide film in which the atomic ratio of In is greater than that of Ga can be applied to the semiconductor layer 108. It is more preferable to use a metal oxide film in which the atomic ratio of Zn is greater than that of Ga. In other words, it is preferable to apply a metal oxide film in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga to the semiconductor layer 108.

[0090] For example, as the semiconductor layer 108, a metal oxide film in which the atomic ratio of metal elements is In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=10:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, or a ratio close to these can be used.

[0091] When a metal oxide film containing indium and gallium is used as the semiconductor layer 108, the ratio of the number of gallium atoms to the number of atoms of metal elements contained in the metal oxide (atomic ratio) can be set to be greater than 0 and less than 50%, preferably 0.05% to 30%, more preferably 0.1% to 15%, and more preferably 0.1% to 5%. Note that the inclusion of gallium in the semiconductor layer 108 has the effect of making oxygen vacancies less likely to occur.

[0092] A metal oxide film that does not contain gallium may be applied to the semiconductor layer 108. For example, In-Zn oxide may be applied to the semiconductor layer 108. In this case, the field effect mobility of the transistor can be increased by increasing the atomic ratio of In to the atomic number of metal elements contained in the metal oxide film. On the other hand, a metal oxide film with high crystallinity can be obtained by increasing the atomic ratio of Zn to the atomic number of metal elements contained in the metal oxide, so that the fluctuation of the electrical characteristics of the transistor can be suppressed and the reliability can be improved. A metal oxide film that does not contain gallium or zinc, such as indium oxide, may be applied to the semiconductor layer 108. By using a metal oxide film that does not contain gallium at all, the fluctuation of the threshold voltage, particularly in the PBTS test, can be made extremely small.

[0093] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide film having an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these can be used.

[0094] In the transistor 10 of one embodiment of the present invention, a metal oxide film containing a small amount of gallium or a metal oxide film containing no gallium is used for the semiconductor layer 108, and a film formed by a deposition method that reduces damage to the semiconductor layer 108 is used for the insulating layer 110 in contact with the top surface of the semiconductor layer 108. Therefore, the density of defect states at the interface between the semiconductor layer 108 and the insulating layer 110 is reduced, and the transistor 10 can have high reliability.

[0095] Although gallium has been described as a representative example here, the present invention can also be applied to a case where an element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) is used instead of gallium. In particular, it is preferable that M is one or more elements selected from gallium, aluminum, yttrium, or tin.

[0096] In particular, it is preferable to use a metal oxide film in which the atomic ratio of In is higher than the atomic ratio of the element M for the semiconductor layer 108. It is also preferable to use a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of the element M.

[0097] It is preferable to use a metal oxide film having crystallinity for the semiconductor layer 108. For example, a metal oxide film having a c-axis aligned crystal (CAAC) structure, a nano crystal (nc) structure, a polycrystalline structure, a microcrystalline structure, or the like, which will be described later, can be used. By using a metal oxide film having crystallinity for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0098] The higher the crystallinity of the semiconductor layer 108, the more the density of defect states in the film can be reduced. On the other hand, by using a metal oxide film with low crystallinity, a transistor capable of passing a large current can be realized.

[0099] When a metal oxide film is formed by a sputtering method, the higher the substrate temperature (stage temperature) during film formation, the higher the crystallinity of the formed metal oxide film. Also, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during film formation (also called the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide film. In this way, the crystallinity of the formed metal oxide film can be controlled by the substrate temperature and the oxygen flow rate ratio in the film formation gas.

[0100] [Configuration Example 1-2] 1B is a schematic cross-sectional view of a transistor 10A. The transistor 10A is different from the transistor 10 described above mainly in that the transistor 10A has a conductive layer 106.

[0101] The conductive layer 106 has a region overlapping with the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 with the insulating layer 103 interposed therebetween. The conductive layer 106 functions as a first gate electrode (also referred to as a back gate electrode). The insulating layer 103 functions as a first gate insulating layer. In this case, the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode), and the insulating layer 110 functions as a second gate insulating layer.

[0102] For example, the transistor 10A can increase the current that can flow in an on state by applying the same potential to the conductive layer 112 and the conductive layer 106. The transistor 10A can also apply a potential to one of the conductive layer 112 and the conductive layer 106 for controlling a threshold voltage and apply a potential to the other for controlling the on state and off state of the transistor 10A. The electrical characteristics of the transistor 10A can also be stabilized by electrically connecting one of the conductive layer 112 and the conductive layer 106 to the source.

[0103] The insulating layer 103 has a layered structure in which an insulating film 103a, an insulating film 103b, and an insulating film 103c are stacked from the conductive layer 106 side. The insulating film 103a is in contact with the conductive layer 106. The insulating film 103c is in contact with the semiconductor layer 108.

[0104] The insulating layer 103 functioning as the first gate insulating layer preferably satisfies one or more of the following requirements: high withstand voltage, low film stress, little release of hydrogen or water, few defects in the film, and suppression of diffusion of a metal element contained in the conductive layer 106, and most preferably satisfies all of these requirements.

[0105] The insulating film 103a is preferably a dense film that can prevent diffusion of impurities from below the insulating film 103a. The insulating film 103a is preferably a film that can block metal elements contained in the conductive layer 106. For this reason, the insulating film 103a can be an insulating film formed at a lower deposition rate than either or both of the insulating film 103b and the insulating film 103c.

[0106] [Configuration Example 1-3] 2A is a schematic cross-sectional view of a transistor 10B. The transistor 10B is different from the transistor 10 described above mainly in that the configuration of the semiconductor layer 108 is different.

[0107] The semiconductor layer 108 included in the transistor 10B has a stacked structure in which a semiconductor layer 108a and a semiconductor layer 108b are stacked from the insulating layer 103 side. Each of the semiconductor layer 108a and the semiconductor layer 108b is preferably formed using a metal oxide film.

[0108] For simplicity, the low-resistance region of the semiconductor layer 108a and the low-resistance region of the semiconductor layer 108b are collectively referred to as the low-resistance region 108n and are shown with the same hatching pattern. In reality, the compositions of the semiconductor layer 108a and the semiconductor layer 108b are different, so that the electrical resistivity, carrier concentration, amount of oxygen vacancy, hydrogen concentration, impurity concentration, and the like of the low-resistance region 108n may differ.

[0109] The semiconductor layer 108b is in contact with the upper surface of the semiconductor layer 108a and the lower surface of the insulating layer 110. The metal oxide film that can be used for the semiconductor layer 108, as exemplified in the above-described Structure Example 1-1, can be used for the semiconductor layer 108.

[0110] On the other hand, the semiconductor layer 108a can be a metal oxide film having a higher atomic ratio of M than the semiconductor layer 108b. In particular, it is preferable to use a metal oxide film containing indium, gallium, and zinc and having a higher atomic ratio of gallium than the semiconductor layer 108b for the semiconductor layer 108a.

[0111] Gallium has a stronger bond with oxygen than indium, so oxygen vacancies are less likely to be formed by using a metal oxide film with a high atomic ratio of gallium for the semiconductor layer 108a. The presence of many oxygen vacancies in the semiconductor layer 108a leads to deterioration in the electrical characteristics and reliability of the transistor. Therefore, by using a metal oxide film with a higher atomic ratio of gallium than the semiconductor layer 108b for the semiconductor layer 108a, the transistor 10B can be realized with good electrical characteristics and high reliability.

[0112] More specifically, the semiconductor layer 108a can be preferably a metal oxide film containing indium, gallium, and zinc, which has a region in which the atomic ratio of gallium is higher than that of the semiconductor layer 108b and the atomic ratio of indium is lower than that of the semiconductor layer 108b. In other words, the semiconductor layer 108b can be a metal oxide film having a region in which the atomic ratio of indium is higher and the atomic ratio of gallium is lower than that of the semiconductor layer 108a.

[0113] In addition, the semiconductor layer 108a is preferably a metal oxide film having a region in which the atomic ratio of zinc is equal to that of the semiconductor layer 108b or a region in which the atomic ratio of zinc is lower than that of the semiconductor layer 108b.

[0114] As the semiconductor layer 108a, for example, a metal oxide film in which the atomic ratio of metal elements is In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=2:2:1, or a ratio close to these can be used.

[0115] Typically, it is preferable to use a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 or a similar ratio for the semiconductor layer 108a, and to use a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=4:2:3, In:Ga:Zn=5:1:6, or a similar ratio for the semiconductor layer 108b.

[0116] Alternatively, it is preferable to use a metal oxide film that does not contain gallium for the semiconductor layer 108b. For example, it is preferable to use an oxide that contains indium and zinc for the semiconductor layer 108b. In this case, a metal oxide film having an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these can be used.

[0117] Furthermore, by using a metal oxide film in which oxygen vacancies are unlikely to occur as the semiconductor layer 108a, deterioration in the above-mentioned NBTIS test can be reduced.

[0118] 2A, a metal oxide film having a relatively high gallium content is used for the semiconductor layer 108a located on the insulating layer 103 side, thereby reducing oxygen vacancies in the semiconductor layer 108. Furthermore, a metal oxide film having a low gallium content or no gallium content is used for the semiconductor layer 108b located on the insulating layer 110 side, thereby reducing the interface defect density between the semiconductor layer 108 and the insulating layer 110. Thus, the transistor 10B has both extremely high electrical characteristics and extremely high reliability.

[0119] Here, it is preferable to form the semiconductor layer 108b thinner than the semiconductor layer 108a. Even if the semiconductor layer 108b is an extremely thin film, for example, 0.5 nm to 10 nm, the density of defects at the interface with the insulating layer 110 can be reduced. On the other hand, by making the semiconductor layer 108a, which is less likely to have oxygen vacancies, relatively thick, a transistor with higher reliability can be realized.

[0120] For example, the thickness of the semiconductor layer 108a can be set to 1.5 to 20 times, preferably 2 to 15 times, more preferably 3 to 10 times, relative to the thickness of the semiconductor layer 108b. The thickness of the semiconductor layer 108b is preferably set to 0.5 to 30 nm, more preferably 1 to 20 nm, more preferably 2 to 10 nm.

[0121] The semiconductor layer 108a and the semiconductor layer 108b are preferably formed using a metal oxide film having the above-mentioned crystallinity. Both the semiconductor layer 108a and the semiconductor layer 108b may be formed using a metal oxide film having high crystallinity or a metal oxide film having low crystallinity. Alternatively, the semiconductor layer 108a and the semiconductor layer 108b may have different crystallinity. For example, the semiconductor layer 108a may be formed using a film having higher crystallinity than the semiconductor layer 108b, and the semiconductor layer 108b may be formed using a film having higher crystallinity than the semiconductor layer 108a. The crystallinity of the metal oxide film used for the semiconductor layer 108a and the semiconductor layer 108b can be determined based on the required electrical characteristics and reliability of the transistor and the specifications of a film formation apparatus and the like.

[0122] [Configuration Example 1-4] 2B is a schematic cross-sectional view of a transistor 10C. The transistor 10C is an example in which the conductive layer 106 included in the transistor 10A illustrated in the above-described Structure Example 1-2 (FIG. 1B) is applied to the transistor 10B illustrated in the above-described Structure Example 1-3 (FIG. 2A).

[0123] With such a structure, a transistor with favorable electrical characteristics and extremely high reliability can be realized.

[0124] [Configuration Example 1-5] 3A is a schematic cross-sectional view of a transistor 10D. The transistor 10D is different from the transistor 10 described above mainly in that the configuration of the insulating layer 110 is different.

[0125] The insulating layer 110 has a layered structure in which an insulating film 110a, an insulating film 110b, and an insulating film 110c are stacked in this order from the insulating layer 103 side. The insulating film 110a has a region in contact with a channel formation region of the semiconductor layer 108. The insulating film 110c has a region in contact with the metal oxide layer 114. The insulating film 110b is located between the insulating films 110a and 110c.

[0126] Each of the insulating films 110a, 110b, and 110c is preferably an insulating film containing an oxide. In this case, the insulating films 110a, 110b, and 110c are preferably formed successively in the same film formation apparatus.

[0127] As the insulating film 110a, the insulating film 110b, and the insulating film 110c, for example, an insulating layer including one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used.

[0128] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a stacked structure of oxide insulating films. The insulating layer 110 more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film capable of releasing oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment in an oxygen atmosphere after the insulating layer 110 is formed, performing plasma treatment or the like in an oxygen atmosphere after the insulating layer 110 is formed, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (e.g., nitrous oxide or ozone) may be used instead of or in addition to oxygen.

[0129] The insulating films 110a, 110b, and 110c can be formed by, for example, a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, etc. Examples of the CVD method include a plasma CVD method and a thermal CVD method.

[0130] In particular, it is preferable that the insulating films 110a, 110b, and 110c are formed by the plasma CVD method.

[0131] Since the insulating film 110a is formed over the semiconductor layer 108, it is preferable that the insulating film 110a be formed under conditions that minimize damage to the semiconductor layer 108. For example, the insulating film 110a can be formed under conditions where the film formation rate (also referred to as the film formation rate) is sufficiently low.

[0132] For example, when a silicon oxynitride film is formed as the insulating film 110a by a plasma CVD method, damage to the semiconductor layer 108 can be made extremely small by forming the film under low power conditions.

[0133] The deposition gas used for forming the silicon oxynitride film may be a source gas containing a deposition gas containing silicon, such as silane or disilane, and an oxidizing gas, such as oxygen, ozone, nitrous oxide, or nitrogen dioxide, etc. In addition to the source gas, a dilution gas, such as argon, helium, or nitrogen, may be included.

[0134] For example, by reducing the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter simply referred to as the flow rate ratio), the film-forming rate can be reduced, and a dense film with few defects can be formed.

[0135] The insulating film 110b is preferably formed under conditions that provide a faster film formation rate than the insulating film 110a, which can improve productivity.

[0136] For example, the insulating film 110b can be formed under conditions in which the flow rate ratio of the deposition gas is made higher than that of the insulating film 110a, thereby enabling the insulating film 110b to be formed under conditions in which the film formation rate is increased.

[0137] The insulating film 110c is preferably an extremely dense film with reduced surface defects and low adsorption of impurities such as water contained in the air. For example, like the insulating film 110a, the insulating film 110c can be formed under conditions where the film formation rate is sufficiently low.

[0138] Furthermore, since the insulating film 110c is formed over the insulating film 110b, the insulating film 110c has a smaller effect on the semiconductor layer 108 during formation than the insulating film 110a. Therefore, the insulating film 110c can be formed under higher power conditions than the insulating film 110a. By reducing the flow rate ratio of the deposition gas and forming the insulating film at relatively high power, a dense film with reduced surface defects can be obtained.

[0139] That is, a stacked film formed under conditions in which the film formation rate is highest for the insulating film 110b, followed by the insulating film 110a and the insulating film 110c, in that order, can be used for the insulating layer 110. Moreover, for the insulating layer 110, the etching rate under the same wet etching or dry etching conditions is highest for the insulating film 110b, followed by the insulating film 110a and the insulating film 110c, in that order.

[0140] The insulating film 110b is preferably formed thicker than the insulating films 110a and 110c. By forming the insulating film 110b, which has the fastest film formation speed, thick, the time required for the film formation process of the insulating layer 110 can be shortened.

[0141] Here, since the boundary between the insulating films 110a and 110b and the boundary between the insulating films 110b and 110c may be unclear, these boundaries are indicated by dashed lines in Fig. 3(A) etc. Note that since the insulating films 110a and 110b have different film densities, these boundaries may be observed as differences in contrast in a transmission electron microscope image of the cross section of the insulating layer 110. Similarly, the boundary between the insulating films 110b and 110c may also be observed as differences in contrast.

[0142] In the transistor 10D of one embodiment of the present invention, a metal oxide film containing a small amount of gallium or a metal oxide film containing no gallium is preferably used for the semiconductor layer 108. Furthermore, the insulating film 110a in contact with the top surface of the semiconductor layer 108 is preferably formed by a film formation method that reduces damage to the semiconductor layer 108. This reduces the density of defect states at the interface between the semiconductor layer 108 and the insulating layer 110, thereby enabling the transistor 10D to have high reliability.

[0143] [Configuration Example 1-6] 3B is a schematic cross-sectional view of a transistor 10E, which is an example in which the conductive layer 106 included in the transistor 10A illustrated in the above-described Structure example 1-2 (FIG. 1B) is applied to the transistor 10D illustrated in the above-described Structure example 1-5 (FIG. 3A).

[0144] With such a structure, a transistor with favorable electrical characteristics and extremely high reliability can be realized.

[0145] Note that the semiconductor layer 108 having a stacked structure applied to the transistor 10B illustrated in Configuration Example 1-3 can also be applied to the transistor 10D illustrated in Configuration Example 1-5 and the transistor 10E illustrated in Configuration Example 1-6. This makes it possible to realize a transistor with better electrical characteristics and higher reliability.

[0146] [Configuration example 2] A more specific example of the configuration of a transistor will be described below.

[0147] [Configuration Example 2-1] 4A is a top view of the transistor 100, FIG. 4B corresponds to a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 4A, and FIG. 4C corresponds to a cross-sectional view of the cut surface taken along dashed line B1-B2 in FIG. 4A. Note that in FIG. 4A, some of the components of the transistor 100 (such as a gate insulating layer) are omitted. The dashed line A1-A2 direction corresponds to the channel length direction, and the dashed line B1-B2 direction corresponds to the channel width direction. Note that in the following drawings, the top views of the transistor are also illustrated with some of the components omitted, as in FIG. 4A.

[0148] The transistor 100 is provided over a substrate 102 and includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, and the like. The island-shaped semiconductor layer 108 is provided over the insulating layer 103. The insulating layer 110 is provided in contact with an upper surface of the insulating layer 103 and an upper surface and side surfaces of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are stacked in this order over the insulating layer 110 and have a portion overlapping with the semiconductor layer 108. The insulating layer 118 is provided to cover an upper surface of the insulating layer 110, a side surface of the metal oxide layer 114, and an upper surface of the conductive layer 112.

[0149] The insulating layer 103 has a multilayer structure in which an insulating film 103a, an insulating film 103b, and an insulating film 103c are stacked from the substrate 102 side. The insulating layer 110 has a multilayer structure in which an insulating film 110a, an insulating film 110b, and an insulating film 110c are stacked from the semiconductor layer 108 side.

[0150] 4A and 4B, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode and a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108n through an opening 141a and an opening 141b provided in the insulating layer 118 and the insulating layer 110, respectively.

[0151] Part of the conductive layer 112 functions as a gate electrode. Part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer .

[0152] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes roughly match each other.

[0153] In this specification, the phrase "top surface shapes roughly match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, and in this case, it is also called "top surface shapes roughly match."

[0154] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112. The metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing toward the insulating layer 110. The metal oxide layer 114 is preferably made of a material that is less permeable to oxygen and hydrogen than the insulating layer 110, for example.

[0155] The metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Even when the conductive layer 112 contains hydrogen, the metal oxide layer 114 can prevent hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0156] An insulating material or a conductive material can be used as the metal oxide layer 114. When the metal oxide layer 114 has insulating properties, the metal oxide layer 114 functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, the metal oxide layer 114 functions as a part of the gate electrode.

[0157] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 114. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like, because the driving voltage can be reduced.

[0158] A conductive oxide such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can also be used as the metal oxide layer 114. In particular, a conductive oxide containing indium is preferable because of its high conductivity.

[0159] In addition, it is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108 for the metal oxide layer 114. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 for the metal oxide layer 114, because this allows the use of a common device.

[0160] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0161] Note that a metal oxide film that can be used for the metal oxide layer 114 may be formed, and then the metal oxide film may be removed after oxygen is supplied to the insulating layer 110 and the semiconductor layer 108. If unnecessary, the metal oxide layer 114 or a metal oxide film that can be used for the metal oxide layer 114 is not necessarily provided.

[0162] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108n sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 100. On the other hand, the pair of low-resistance regions 108n function as a source region and a drain region of the transistor 100.

[0163] The low-resistance region 108n can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier concentration, a region having a high oxygen defect density, a region having a high impurity concentration, or an n-type region.

[0164] The low-resistance region 108n of the semiconductor layer 108 may be a region containing an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable that the low-resistance region 108n contains boron or phosphorus. The low-resistance region 108n may contain two or more of these elements.

[0165] As described later, the process of adding impurities to the low-resistance region 108n can be performed through the insulating layer 110 by using the conductive layer 112 as a mask.

[0166] The low resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0167] The concentration of impurities contained in the low-resistance region 108n can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or rear side with XPS analysis.

[0168] In addition, in the low-resistance region 108n, the impurity element is preferably present in an oxidized state. For example, it is preferable to use an element that is easily oxidized, such as boron, phosphorus, magnesium, aluminum, or silicon, as the impurity element. Since such an element that is easily oxidized can be stably present in an oxidized state by bonding with oxygen in the semiconductor layer 108, even if a high temperature (for example, 400° C. or higher, 600° C. or higher, or 800° C. or higher) is applied in a later process, the element is prevented from being desorbed. Furthermore, the impurity element removes oxygen from the semiconductor layer 108, so that many oxygen vacancies are generated in the low-resistance region 108n. The oxygen vacancies are bonded with hydrogen in the film to become a carrier supply source, so that the low-resistance region 108n has an extremely low resistance state.

[0169] For example, when boron is used as an impurity element, the boron contained in the low-resistance region 108n may exist in a state of being bonded to oxygen. This can be confirmed by observing a spectrum peak due to the B2O3 bond in an XPS analysis. In addition, in an XPS analysis, a spectrum peak due to the state in which the boron element exists alone is not observed, or the peak intensity is so small that it is buried in background noise observed near the lower limit of measurement.

[0170] The insulating layer 110 has a region in contact with a channel formation region of the semiconductor layer 108, that is, a region overlapping with the conductive layer 112. The insulating layer 110 also has a region in contact with a low-resistance region 108n of the semiconductor layer 108 and not overlapping with the conductive layer 112.

[0171] The region of the insulating layer 110 overlapping with the low-resistance region 108n may contain the above-mentioned impurity element. In this case, like the low-resistance region 108n, the impurity element in the insulating layer 110 is preferably present in a state bonded to oxygen. Since such an element that is easily oxidized can be stably present in an oxidized state by bonding with oxygen in the insulating layer 110, desorption is suppressed even when a high temperature is applied in a later process. In particular, when the insulating layer 110 contains oxygen (also referred to as excess oxygen) that can be desorbed by heating, the excess oxygen and the impurity element are bonded to be stabilized, so that it is possible to suppress the supply of oxygen from the insulating layer 110 to the low-resistance region 108n. Furthermore, a part of the insulating layer 110 containing the oxidized impurity element is in a state where oxygen is difficult to diffuse, so that it is suppressed that oxygen is supplied to the low-resistance region 108n from above the insulating layer 110 through the insulating layer 110, and it is also possible to prevent the low-resistance region 108n from becoming high-resistance.

[0172] The insulating layer 118 functions as a protective layer that protects the transistor 100. For example, an inorganic insulating material such as an oxide or a nitride can be used as the insulating layer 110. More specific examples of the insulating layer 110 that can be used include inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate.

[0173] [Configuration Example 2-2] 5A is a top view of the transistor 100A, FIG. 5B is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 5C is a cross-sectional view of the transistor 100A in the channel width direction.

[0174] The transistor 100A differs from the transistor in structural example 2-1 mainly in that a conductive layer 106 is provided between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112.

[0175] In the transistor 100A, the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode), and the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode). Part of the insulating layer 110 functions as a second gate insulating layer, and part of the insulating layer 103 functions as a first gate insulating layer.

[0176] A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of explanation, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 may be referred to as a channel formation region hereinafter; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 and overlaps with the conductive layer 106 (a portion including the low-resistance region 108n).

[0177] 5C, the conductive layer 106 may be electrically connected to the conductive layer 112 through an opening 142 provided in the metal oxide layer 114, the insulating layer 110, and the insulating layer 103. In this way, the conductive layer 106 and the conductive layer 112 can be applied with the same potential.

[0178] The conductive layer 106 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because wiring resistance can be reduced.

[0179] 5(A) and 5(C), it is preferable that the conductive layer 112 and the conductive layer 106 protrude outward in the channel width direction beyond the end portion of the semiconductor layer 108. In this case, as shown in FIG. 5(C), the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 via the insulating layer 110 and the insulating layer 103.

[0180] With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In particular, it is preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. This makes it possible to effectively apply an electric field for inducing a channel in the semiconductor layer 108, thereby increasing the on-state current of the transistor 100A. This also enables miniaturization of the transistor 100A.

[0181] Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 100A may be applied to the other of the pair of gate electrodes. In this case, the threshold voltage when the transistor 100A is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0182] The conductive layer 106 may be electrically connected to the conductive layer 120a or the conductive layer 120b. In this case, the conductive layer 120a or the conductive layer 120b may be electrically connected to the conductive layer 106 through openings provided in the insulating layer 118, the insulating layer 110, and the insulating layer 103.

[0183] [Configuration Example 2-3] 6A is a top view of the transistor 100B, FIG. 6B is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 6C is a cross-sectional view of the transistor 100B in the channel width direction.

[0184] The transistor 100B differs from the transistor 100 illustrated in Structural example 2-1 mainly in that the insulating layer 110 has a different configuration and that an insulating layer 116 is included.

[0185] The insulating layer 110 is processed so that its top surface shape generally matches those of the conductive layer 112 and the metal oxide layer 114. The insulating layer 110 can be formed by processing using a resist mask for processing the conductive layer 112 and the metal oxide layer 114, for example.

[0186] The insulating layer 116 is provided in contact with the top surface and side surfaces of the semiconductor layer 108 that are not covered with the conductive layer 112, the metal oxide layer 114, and the insulating layer 110. The insulating layer 116 is provided to cover the top surface of the insulating layer 103, the side surfaces of the insulating layer 110, the side surfaces of the metal oxide layer 114, and the top surface and side surfaces of the conductive layer 112.

[0187] The insulating layer 116 has a function of lowering the resistance of the low-resistance region 108n. As the insulating layer 116, an insulating film capable of supplying impurities to the low-resistance region 108n by heating during or after the formation of the insulating layer 116 can be used. Alternatively, an insulating film capable of generating oxygen vacancies in the low-resistance region 108n by heating during or after the formation of the insulating layer 116 can be used.

[0188] For example, an insulating film that functions as a supply source for supplying impurities to the low-resistance region 108n can be used as the insulating layer 116. In this case, the insulating layer 116 is preferably a film that releases hydrogen by heating. By forming such an insulating layer 116 in contact with the semiconductor layer 108, impurities such as hydrogen can be supplied to the low-resistance region 108n, and the resistance of the low-resistance region 108n can be reduced.

[0189] The insulating layer 116 is preferably formed using a gas containing an impurity element such as a hydrogen element as a deposition gas. The lower the deposition temperature of the insulating layer 116, the more the impurity element can be effectively supplied to the semiconductor layer 108. The deposition temperature of the insulating layer 116 can be, for example, 200° C. or higher and 500° C. or lower, preferably 220° C. or higher and 450° C. or lower, more preferably 230° C. or higher and 400° C. or lower.

[0190] Furthermore, by forming the insulating layer 116 under reduced pressure and by heating, it is possible to promote desorption of oxygen from the regions that will become the low-resistance regions 108n in the semiconductor layer 108. By supplying impurities such as hydrogen to the semiconductor layer 108 in which many oxygen vacancies have been formed, the carrier density in the low-resistance regions 108n is increased, and the resistance of the low-resistance regions 108n can be more effectively reduced.

[0191] For example, an insulating film containing a nitride, such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide, can be suitably used as the insulating layer 116. In particular, silicon nitride has a blocking property against hydrogen and oxygen, and can therefore prevent both diffusion of hydrogen from the outside to the semiconductor layer and elimination of oxygen from the semiconductor layer to the outside, thereby realizing a highly reliable transistor.

[0192] The insulating layer 116 may be an insulating film having a function of absorbing oxygen in the semiconductor layer 108 and generating oxygen vacancies. In particular, the insulating layer 116 is preferably formed using a metal nitride such as aluminum nitride.

[0193] In addition, when a metal nitride is used, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is preferable to include aluminum or titanium. For example, an aluminum nitride film formed by a reactive sputtering method using aluminum as a sputtering target and a gas containing nitrogen as a deposition gas can be made into a film having extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the deposition gas. Therefore, by providing an insulating film containing such a metal nitride in contact with a semiconductor layer, not only can the resistance of the semiconductor layer be reduced, but also oxygen can be suitably prevented from being released from the semiconductor layer and hydrogen can be suitably prevented from diffusing into the semiconductor layer.

[0194] When aluminum nitride is used as the metal nitride, the thickness of the insulating layer containing the aluminum nitride is preferably 5 nm or more. Even with such a thin film, it is possible to achieve both high blocking properties against hydrogen and oxygen and a function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer may be as thick as desired, but in consideration of productivity, it is preferable to set the thickness to 500 nm or less, preferably 200 nm or less, and more preferably 50 nm or less.

[0195] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is a real number greater than 0 and equal to or less than 2, preferably, x is a real number greater than 0.5 and equal to or less than 1.5) is preferably used. This allows the film to have excellent insulating properties and excellent thermal conductivity, thereby improving the dissipation of heat generated when the transistor 100B is driven.

[0196] Alternatively, the insulating layer 116 can be an aluminum titanium nitride film, a titanium nitride film, or the like.

[0197] By providing such an insulating layer 116 in contact with the low-resistance region 108n, the insulating layer 116 can absorb oxygen in the low-resistance region 108n and form oxygen vacancies in the low-resistance region 108n. In addition, by performing heat treatment after forming such an insulating layer 116, a large number of oxygen vacancies can be formed in the low-resistance region 108n, and the resistance can be reduced. In addition, when a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 may absorb oxygen in the semiconductor layer 108, and as a result, a layer containing an oxide of a metal element (e.g., aluminum) contained in the insulating layer 116 may be formed between the insulating layer 116 and the low-resistance region 108n.

[0198] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, a region where indium oxide is precipitated or a region with a high concentration of indium may be formed near the interface of the low-resistance region 108n on the insulating layer 116 side. This allows the low-resistance region 108n to have an extremely low resistance. The presence of such a region may be observed by an analysis method such as X-ray photoelectron spectroscopy (XPS).

[0199] Note that, although an example in which the insulating layer 116 is used as a film for reducing the resistance of part of the semiconductor layer 108 has been described here, the insulating layer 118 may be provided in contact with part of the semiconductor layer 108 to reduce the resistance of the part of the semiconductor layer 108. That is, a structure in which the insulating layer 116 is not provided may also be used. In this case, an insulating film containing oxide, such as a silicon oxide film or a silicon oxynitride film, may also be used as the insulating layer 118 in contact with the part of the semiconductor layer 108.

[0200] [Configuration Example 2-4] 7A is a top view of a transistor 100C, FIG. 7B is a cross-sectional view of the transistor 100C in a channel length direction, and FIG. 7C is a cross-sectional view of the transistor 100C in a channel width direction.

[0201] The transistor 100C is an example in which the conductive layer 106 functioning as a first gate electrode, as exemplified in Structural Example 2-2, is provided in the transistor 100B exemplified in Structural Example 2-3.

[0202] With such a structure, a transistor with high on-state current can be obtained, or a transistor whose threshold voltage can be controlled can be obtained.

[0203] [Variation 1 of Configuration Example 2] Although the semiconductor layer 108 is a single layer in the above-described Structure Examples 2-1 to 2-4, it is preferable that the semiconductor layer 108 have a stacked structure in which the semiconductor layer 108a and the semiconductor layer 108b are stacked.

[0204] A transistor 100_a shown in Fig. 8A is an example of the transistor 100 illustrated in Configuration example 2-1 in which the semiconductor layer 108 has a stacked structure. In Fig. 8A, a cross section in the channel length direction is shown to the left of the dashed dotted line, and a cross section in the channel width direction is shown to the right of the dashed dotted line.

[0205] Similarly, a transistor 100A_a shown in Figure 8(B), a transistor 100B_a shown in Figure 8(C), and a transistor 100C_a shown in Figure 8(D) are examples of transistor 100A, transistor 100B, and transistor 100C, respectively, in which the semiconductor layer 108 has a stacked structure.

[0206] [Variation 2 of Configuration Example 2] As described above, the metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 can be removed after oxygen is supplied to the insulating layer 110. Alternatively, a structure in which the metal oxide layer 114 is not used can be used.

[0207] A transistor 100_b illustrated in FIG. 9A is an example of the transistor 100_a illustrated in FIG. 8A in which the metal oxide layer 114 is removed or not used.

[0208] Similarly, a transistor 100A_b shown in Figure 9(B), a transistor 100B_b shown in Figure 9(C), and a transistor 100C_b shown in Figure 9(D) are examples of transistor 100A_a, transistor 100B_a, or transistor 100C_a, respectively, in which the metal oxide layer 114 has been removed or no metal oxide layer 114 is used.

[0209] [Variation 3 of Configuration Example 2] As described above, in the transistors 100B and 100C, the insulating layer 116 may not be provided and the insulating layer 118 may be in contact with part of the semiconductor layer 108.

[0210] A transistor 100B_c shown in Fig. 10A and a transistor 100C_c shown in Fig. 10B are examples of the transistors 100B and 100C, respectively, that do not include the insulating layer 116. A transistor 100B_d shown in Fig. 10C and a transistor 100C_d shown in Fig. 10D are examples of the transistors that do not include the insulating layer 116 and the metal oxide layer 114, respectively.

[0211] [Production method example 1] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below, taking the transistor 100A described in Structure Example 2-2 as an example.

[0212] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device can be formed by sputtering, CVD, vacuum deposition, PLD, ALD, etc. CVD methods include PECVD and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD: Metal Organic CVD).

[0213] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0214] Furthermore, when processing the thin film constituting the semiconductor device, the thin film can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0215] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0216] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0217] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0218] 11A to 13B show cross sections of the transistor 100A in the channel length direction and the channel width direction at each stage of a manufacturing process.

[0219] [Formation of Conductive Layer 106] A conductive film is formed over a substrate 102 and processed by etching to form a conductive layer 106 that functions as a gate electrode (FIG. 11A).

[0220] 11A, the conductive layer 106 is preferably processed so that its end portion has a tapered shape, which can improve the step coverage of the insulating layer 103 to be formed next.

[0221] Furthermore, by using a conductive film containing copper as the conductive layer 106, wiring resistance can be reduced. For example, when the conductive film is applied to a large display device or a display device with high resolution, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used for the conductive layer 106, the insulating layer 103 prevents copper from diffusing toward the semiconductor layer 108, so that a highly reliable transistor can be realized.

[0222] [Formation of insulating layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 11(B)). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0223] Here, the insulating layer 103 is formed by stacking an insulating film 103a, an insulating film 103b, and an insulating film 103c.

[0224] In particular, it is preferable to form the insulating films constituting the insulating layer 103 by the PECVD method. As for the method for forming the insulating layer 103, the description of the above-mentioned configuration example 1 can be cited.

[0225] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, a plasma treatment or a heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method or an ion implantation method.

[0226] [Formation of Semiconductor Layer 108] Next, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 11(C)).

[0227] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

[0228] The metal oxide film 108f is preferably a dense film with as few defects as possible. The metal oxide film 108f is preferably a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable to use a metal oxide film having crystallinity as the metal oxide film 108f.

[0229] In addition, when forming the metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter, also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with increased on-current can be obtained.

[0230] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and the denser the metal oxide film can be formed, whereas the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be formed.

[0231] The deposition conditions for the metal oxide film are a substrate temperature of room temperature or higher and 250° C. or lower, preferably room temperature or higher and 200° C. or lower, and more preferably room temperature or higher and 140° C. or lower. For example, a substrate temperature of room temperature or higher and lower than 140° C. is preferable because it increases productivity. In addition, by depositing a metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

[0232] Before forming the metal oxide film 108f, at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103 and a treatment for supplying oxygen into the insulating layer 103 is preferably performed. For example, a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, oxygen can be supplied to the insulating layer 103 by a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). When a plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 103 are suitably removed. After such a treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 103 to the air.

[0233] In addition, in the case where the semiconductor layer 108 has a stacked structure in which a plurality of semiconductor layers are stacked, it is preferable to form a metal oxide film first and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0234] Subsequently, the metal oxide film 108f is partially etched to form an island-shaped semiconductor layer 108 (FIG. 11(D)).

[0235] The metal oxide film 108f may be processed by wet etching or dry etching, or both. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner. For example, the insulating film 103c of the insulating layer 103 may be removed by etching, and the surface of the insulating film 103b may be exposed.

[0236] Here, heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108. The heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, reduce defects, improve crystallinity, etc.).

[0237] Furthermore, the heat treatment can also supply oxygen from the insulating layer 103 to the metal oxide film 108f or the semiconductor layer 108. In this case, it is preferable to perform the heat treatment before processing into the semiconductor layer 108.

[0238] The temperature of the heat treatment can typically be 150° C. or higher and lower than the strain point of the substrate, or 200° C. or higher and 500° C. or lower, or 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

[0239] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, the heat treatment can be performed in an atmosphere containing oxygen after the heat treatment in the above atmosphere. Alternatively, the heat treatment can be performed in a dry air atmosphere. Note that it is preferable that the heat treatment atmosphere does not contain hydrogen, water, or the like as much as possible. The heat treatment can be performed using an electric furnace, an RTA (Rapid Thermal Anneal) device, or the like. The heat treatment time can be shortened by using an RTA device.

[0240] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0241] [Formation of insulating layer 110] Subsequently, an insulating layer 110 is formed to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 11(E)).

[0242] Here, the insulating layer 110 is formed by stacking an insulating film 110a, an insulating film 110b, and an insulating film 110c.

[0243] In particular, it is preferable to form each of the insulating films constituting the insulating layer 110 by the PECVD method. As for the method of forming each of the layers constituting the insulating layer 110, the description of the above configuration example 1 can be applied.

[0244] In addition, before the insulating layer 110 is formed, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, and a highly reliable transistor can be realized. This is particularly preferable when the surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating layer 110. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. In addition, it is preferable to perform the plasma treatment and the formation of the insulating layer 110 in succession without exposure to the air.

[0245] Here, heat treatment is preferably performed after the insulating layer 110 is formed. Hydrogen or water contained in the insulating layer 110 or adsorbed to the surface of the insulating layer 110 can be removed by the heat treatment. In addition, defects in the insulating layer 110 can be reduced.

[0246] The heat treatment conditions may be as described above.

[0247] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0248] [Formation of Metal Oxide Film 114f] Next, a metal oxide film 114f is formed on the insulating layer 110 (FIG. 12(A)).

[0249] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. In this way, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f. Note that oxygen may be supplied to the semiconductor layer 108 during the formation of the metal oxide film 114f.

[0250] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that for the semiconductor layer 108, the above description can be used.

[0251] For example, the metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, an aluminum oxide film can be formed.

[0252] During deposition of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber is, the more oxygen can be supplied to the insulating layer 110. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and further preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure in the deposition chamber as close to 100% as possible.

[0253] In this manner, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f, and oxygen can be prevented from being released from the insulating layer 110. As a result, an extremely large amount of oxygen can be trapped in the insulating layer 110.

[0254] After the metal oxide film 114f is formed, heat treatment is preferably performed. By the heat treatment, oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. By performing heating while the insulating layer 110 is covered with the metal oxide film 114f, oxygen is prevented from being released from the insulating layer 110 to the outside, and a large amount of oxygen can be supplied to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0255] The heat treatment conditions may be as described above.

[0256] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0257] After the metal oxide film 114f is formed or after the heat treatment, the metal oxide film 114f may be removed.

[0258] [Formation of opening 142] Next, the metal oxide film 114f, the insulating layer 110, and a part of the insulating layer 103 are etched to form an opening 142 reaching the conductive layer 106 (FIG. 12(B)). This allows the conductive layer 106 and the conductive layer 112 to be formed later to be electrically connected to each other through the opening 142.

[0259] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Subsequently, a conductive film 112f which will become the conductive layer 112 is formed on the metal oxide film 114f (FIG. 12(C)).

[0260] The conductive film 112f is preferably formed using a low-resistance metal or alloy material. In addition, the conductive film 112f is preferably formed using a material that does not easily release hydrogen and from which hydrogen does not easily diffuse. In addition, the conductive film 112f is preferably formed using a material that does not easily oxidize.

[0261] For example, the conductive film 112f is preferably formed by a sputtering method using a sputtering target containing a metal or an alloy.

[0262] For example, the conductive film 112f is preferably a stacked film in which a conductive film which is resistant to oxidation and through which hydrogen does not easily diffuse and a conductive film with low resistance are stacked.

[0263] Then, the conductive film 112f and the metal oxide film 114f are partly etched to form the conductive layer 112 and the metal oxide layer 114. The conductive film 112f and the metal oxide film 114f are preferably processed using the same resist mask. Alternatively, the metal oxide film 114f may be etched using the etched conductive layer 112 as a hard mask.

[0264] It is particularly preferable to use a wet etching method for etching the conductive film 112f and the metal oxide film 114f.

[0265] This makes it possible to form the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same.

[0266] In this manner, by forming a structure in which the upper surface and side surfaces of the semiconductor layer 108 and the insulating layer 103 are covered without etching the insulating layer 110, it is possible to prevent a part of the semiconductor layer 108 or the insulating layer 103 from being etched and thinned when the conductive film 112f, etc. are etched.

[0267] [Fueling of impurity elements] Next, a process of supplying (also referred to as adding or injecting) the impurity element 140 to the semiconductor layer 108 through the insulating layer 110 is performed using the conductive layer 112 as a mask ( FIG. 12D ). As a result, a low-resistance region 108n can be formed in a region of the semiconductor layer 108 that is not covered with the conductive layer 112. At this time, it is preferable to determine conditions for the process of supplying the impurity element 140 in consideration of the material and thickness of the conductive layer 112 and the like that serve as a mask so that the impurity element 140 is not supplied to a region of the semiconductor layer 108 that overlaps with the conductive layer 112 as much as possible. As a result, a channel formation region in which the impurity concentration is sufficiently reduced can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 112.

[0268] The impurity element 140 can be preferably supplied by a plasma ion doping method or an ion implantation method. These methods can control the concentration profile in the depth direction with high precision by the ion acceleration voltage, dose amount, etc. By using the plasma ion doping method, productivity can be improved. In addition, by using the ion implantation method using mass separation, the purity of the supplied impurity element can be increased.

[0269] In the supplying process of the impurity element 140, it is preferable to control the process conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 110, or in a portion close to the interface in the semiconductor layer 108, or in a portion close to the interface in the insulating layer 110. In this way, the impurity element 140 can be supplied at an optimal concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0270] Examples of the impurity element 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0271] As the source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically, B2H6 gas or BF3 gas can be used. When supplying phosphorus, typically, PH3 gas can be used. Also, a mixed gas in which these source gases are diluted with a rare gas may be used.

[0272] Other examples of the source gas that can be used include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to gas, and a solid or liquid that has been heated and vaporized may also be used.

[0273] The addition of the impurity element 140 can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 110 and the semiconductor layer .

[0274] For example, when boron is added by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 5 kV to 100 kV, preferably 7 kV to 70 kV, and more preferably 10 kV to 50 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 It can be in the following range:

[0275] When phosphorus ions are added by ion implantation or plasma ion doping, the acceleration voltage can be, for example, in the range of 10 kV to 100 kV, preferably 30 kV to 90 kV, and more preferably 40 kV to 80 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than or equal to 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 More than 3×10 16 ions / cm 2 It can be in the following range:

[0276] The method of supplying the impurity element 140 is not limited to this, and may be, for example, a plasma treatment or a treatment using thermal diffusion by heating. In the case of the plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used.

[0277] In one embodiment of the present invention, the impurity element 140 can be supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, damage to the semiconductor layer 108 when the impurity element 140 is supplied can be reduced, and loss of crystallinity can be suppressed. Therefore, this is preferable in the case where electrical resistance increases due to a decrease in crystallinity.

[0278] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed covering the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 (FIG. 13(A)).

[0279] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, impurities contained in the low-resistance region 108n and the like may diffuse to the peripheral portion including the channel formation region of the semiconductor layer 108, and the electrical resistance of the low-resistance region 108n may increase. Therefore, the film formation temperature of the insulating layer 118 may be determined taking these factors into consideration.

[0280] For example, the deposition temperature of the insulating layer 118 is set to, for example, 150° C. to 400° C., preferably 180° C. to 360° C., and more preferably 200° C. to 250° C. By depositing the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0281] After the insulating layer 118 is formed, heat treatment may be performed. The heat treatment may make the low-resistance region 108n more stable and low-resistance. For example, the heat treatment may cause the impurity element 140 to diffuse appropriately and become locally uniform, forming the low-resistance region 108n having an ideal impurity element concentration gradient. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurity element 140 may diffuse into the channel formation region, which may cause deterioration in the electrical characteristics and reliability of the transistor.

[0282] The heat treatment conditions may be as described above.

[0283] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, if there is a high-temperature process (e.g., a film formation process) in a later step, the heat treatment may be combined with the heat treatment.

[0284] [Formation of Openings 141a and 141b] Next, the insulating layer 118 and the insulating layer 110 are partially etched to form the opening 141a and the opening 141b that reach the low-resistance region 108n.

[0285] [Formation of Conductive Layer 120a and Conductive Layer 120b] Next, a conductive film is formed over the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (FIG. 13B).

[0286] Through the above steps, the transistor 100A can be manufactured. For example, when the transistor 100A is used in a pixel of a display device, a subsequent step of forming one or more of a protective insulating layer, a planarization layer, a pixel electrode, and a wiring may be added.

[0287] This concludes the description of Preparation Method 1.

[0288] Note that when the transistor 100 illustrated in Configuration Example 2-1 is manufactured, the step of forming the conductive layer 106 and the step of forming the opening 142 in the above-described Manufacturing Method Example 1 may be omitted. The transistor 100 and the transistor 100A can be formed over the same substrate through the same steps.

[0289] [Production method example 2] The following describes an example in which some steps are different from those in Manufacturing Method Example 1. Here, the transistor 100C illustrated in Configuration Example 2-4 is taken as an example.

[0290] In the following, explanations of the parts that overlap with the above-mentioned Preparation Method Example 1 will be omitted, and differences will be explained in detail.

[0291] First, the conductive layer 106, the insulating layer 103, the semiconductor layer 108, the insulating layer 110, the metal oxide film 114f, and the conductive film 112f are formed in this order in a manner similar to that of Manufacturing Method Example 1. A cross-sectional view at this stage is shown in FIG.

[0292] Next, the conductive film 112f and the metal oxide film 114f are partly etched to form the conductive layer 112 and the metal oxide layer 114, and further the insulating layer 110 is partly etched to expose a part of the semiconductor layer 108 (FIG. 14(B)). As a result, the conductive layer 112, the metal oxide layer 114, and the insulating layer 110, which have approximately the same top surface shape, can be formed.

[0293] The insulating layer 110 is preferably etched using a resist mask for etching the conductive film 112f. The insulating layer 110 may be etched in the same step as the etching of the conductive film 112f and the metal oxide film 114f, or may be etched by a different etching method after the etching of the conductive film 112f and the metal oxide film 114f.

[0294] For example, the conductive film 112f and the metal oxide film 114f can be etched by a wet etching method using the same etchant, and then the insulating layer 110 can be etched by a dry etching method. In particular, when the conductive film 112f and the metal oxide film 114f are processed by a dry etching method, a reaction product containing metal is generated, which may contaminate the semiconductor layer 108 and the insulating layer 110. Therefore, it is preferable to process the conductive film 112f and the metal oxide film 114f by a wet etching method before etching the insulating layer 110.

[0295] Depending on the etching conditions, the ends of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 may not coincide with each other. For example, the end of at least one of the conductive layer 112 and the metal oxide layer 114 may be located inside or outside the end of the insulating layer 110.

[0296] Furthermore, when the insulating layer 110 is etched, a part of the exposed semiconductor layer 108 may be etched and thinned. At this time, the semiconductor layer 108 may have a shape in which the thickness of the low-resistance region 108n is thinner than the thickness of the channel formation region.

[0297] Furthermore, when the insulating layer 110 is etched, a part of the insulating layer 103 that is not covered with the semiconductor layer 108 may be etched and thinned. For example, the insulating film 103c of the insulating layer 103 may disappear.

[0298] Next, an insulating layer 116 is formed in contact with the exposed portion of the semiconductor layer 108, and then an insulating layer 118 is formed (FIG. 14(C)). By forming the insulating layer 116, the exposed portion of the semiconductor layer 108 has a low resistance, and a low-resistance region 108n is formed.

[0299] The insulating layer 116 can be an insulating film that releases an impurity element having a function of reducing the resistance of the semiconductor layer 108. In particular, it is preferable to use an inorganic insulating film such as a silicon nitride film, a silicon nitride oxide film, or a silicon oxynitride film that can release hydrogen. In this case, it is preferable to use a plasma CVD method using a deposition gas containing hydrogen because hydrogen can be supplied to the semiconductor layer 108 even during the deposition of the insulating layer 116.

[0300] For example, when silicon nitride is used as the insulating layer 116, it is preferable to form the insulating layer 116 by a PECVD method using a mixed gas containing a silicon-containing gas such as silane and a nitrogen-containing gas such as ammonia or nitrous oxide as a deposition gas. In this case, it is preferable that the silicon nitride film to be formed contains hydrogen. This allows hydrogen in the insulating layer 116 to diffuse into the semiconductor layer 108, making it easy to reduce the resistance of a part of the semiconductor layer 108.

[0301] Alternatively, an insulating film having a function of generating oxygen vacancies in the semiconductor layer 108 can be used. In particular, it is preferable to use an insulating film containing a metal nitride. For example, it is preferable to form the insulating layer 116 by a reactive sputtering method using a sputtering target containing a metal and a mixed gas of nitrogen gas and a diluent gas such as a rare gas as a deposition gas. This makes it easy to control the film quality of the insulating layer 116 by controlling the flow rate ratio of the deposition gas.

[0302] For example, when an aluminum nitride film formed by reactive sputtering using an aluminum target is used as the insulating layer 116, the flow rate of nitrogen gas relative to the total flow rate of the film formation gas is preferably 30% or more and 100% or less, more preferably 40% or more and 100% or less, and even more preferably 50% or more and 100% or less.

[0303] Here, the insulating layers 116 and 118 are preferably formed in succession without exposure to the air.

[0304] Note that in the case where the insulating layer 118 is provided in contact with the semiconductor layer 108, the step of forming the insulating layer 116 may be omitted.

[0305] Heat treatment may be performed after the insulating layer 116 or the insulating layer 118 is formed. The heat treatment can promote a decrease in resistance of the low-resistance region 108n.

[0306] The heat treatment conditions may be as described above.

[0307] If the heat treatment is unnecessary, it is not necessary to perform it. Also, the heat treatment may not be performed here, and may be combined with a heat treatment performed in a later step. Also, there are cases where the heat treatment may be combined with a high-temperature treatment in a later step (e.g., a film formation step, etc.).

[0308] Next, openings 141a and 141b are formed in the insulating layers 118 and 116, respectively, so as to reach the low-resistance regions 108n.

[0309] Next, the conductive layer 120a and the conductive layer 120b are formed over the insulating layer 118 in a manner similar to that of Manufacturing Method Example 1 (FIG. 14D).

[0310] Through the above steps, the transistor 100C can be manufactured.

[0311] Note that when the transistor 100B illustrated in Structure Example 2-3 is manufactured, the steps of forming the conductive layer 106 and the opening 142 in the above-described Manufacturing Method Example 2 may be omitted. The transistors 100B and 100C can be formed over the same substrate through the same steps.

[0312] [Components of Semiconductor Devices] The components included in the semiconductor device of this embodiment will be described below.

[0313] 〔substrate〕 There are no significant limitations on the material of the substrate 102, but the substrate must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may be used as the substrate 102.

[0314] A flexible substrate may be used as the substrate 102, and the semiconductor device may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the semiconductor device. The peeling layer can be used to separate the semiconductor device from the substrate 102 after a part or whole of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate. In this case, the semiconductor device can be transferred to a substrate having poor heat resistance or a flexible substrate.

[0315] [Conductive Film] The conductive layer 112 and the conductive layer 106 which function as a gate electrode, and the conductive layer 120a which functions as one of a source electrode or a drain electrode, and the conductive layer 120b which functions as the other electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, or an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements.

[0316] In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b may be made of an oxide conductor or a metal oxide such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0317] Here, an oxide conductor (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor.

[0318] Alternatively, the conductive layer 112 or the like may have a stacked structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. In this case, it is preferable to use a conductive film containing an oxide conductor on the side in contact with an insulating layer that functions as a gate insulating film.

[0319] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b preferably contain one or more of the above-mentioned metal elements selected from titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferably used. The tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself, and therefore can be preferably used as a conductive film in contact with the semiconductor layer 108 or in the vicinity of the semiconductor layer 108.

[0320] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of metal elements in a sputtering target used to form the In-M-Zn oxide film is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M Examples of the atomic ratio include In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=10:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. In the above, when two or more elements are contained as the element M, the proportion of M in the above atomic ratio corresponds to the sum of the numbers of atoms of the two or more metal elements.

[0321] In addition, it is preferable to use a target containing a polycrystalline oxide as the sputtering target because it is easy to form the semiconductor layer 108 having crystallinity. The atomic ratio of the semiconductor layer 108 to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0322] When the atomic ratio is described as In:Ga:Zn=4:2:3 or thereabout, this includes the case where, when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When the atomic ratio is described as In:Ga:Zn=5:1:6 or thereabout, this includes the case where, when In is 5, Ga is greater than 0.1 and 2 or less, and Zn is greater than 5 and 7 or less. When the atomic ratio is described as In:Ga:Zn=1:1:1 or thereabout, this includes the case where, when In is 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0323] The energy gap of the semiconductor layer 108 is 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon, the off-state current of the transistor can be reduced.

[0324] In addition, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure, which will be described later. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC structure has the lowest density of defect states.

[0325] In the following, we explain about CAAC (c-axis aligned crystal). CAAC is an example of a crystal structure.

[0326] The CAAC structure is one of the crystal structures of thin films having multiple nanocrystals (crystal regions with a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films having a CAAC structure have the characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface on which it is formed, or the normal direction of the thin film surface.

[0327] CAAC-OS (Oxide Semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that the decrease in electron mobility caused by the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are resistant to heat and have high reliability.

[0328] Here, in crystallography, it is common to take a unit cell with a specific axis as the c-axis for the three axes (crystal axes) of the a-axis, b-axis, and c-axis that constitute the unit cell. In particular, in crystals having a layered structure, it is common to take two axes parallel to the plane direction of the layer as the a-axis and b-axis, and an axis intersecting the layer as the c-axis. A representative example of such a crystal having a layered structure is graphite, which is classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, a crystal of InGaZnO4 having a layered YbFe2O4 type crystal structure can be classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0329] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly identified in an image observed by TEM. The crystal parts included in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals having a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in an image observed by TEM, for example, in an nc-OS film, crystal grain boundaries may not be clearly identified.

[0330] The nc-OS film has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus using X-rays with a diameter larger than that of the crystal parts, no peak indicating a crystal plane is detected in the out-of-plane analysis. When the nc-OS film is subjected to electron beam diffraction (also called selected area electron beam diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal parts, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron diffraction (also known as nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to or smaller than the size of the crystal part, a ring-shaped region of high brightness is observed in a circular pattern, and multiple spots are sometimes observed within the ring-shaped region.

[0331] The nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film does not have regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier density and higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit high field-effect mobility.

[0332] The nc-OS film can be formed by lowering the oxygen flow rate ratio during film formation compared to the CAAC-OS film. Also, the nc-OS film can be formed by lowering the substrate temperature during film formation compared to the CAAC-OS film. For example, the nc-OS film can be formed at a relatively low substrate temperature (for example, 130°C or lower) or without heating the substrate, so it is suitable for use on large glass substrates or resin substrates, and can increase productivity.

[0333] An example of the crystal structure of a metal oxide will be described. A metal oxide formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) with a substrate temperature of 100°C to 130°C tends to have either a crystalline structure of nc (nano crystal) or CAAC, or a mixed structure of these. On the other hand, a metal oxide formed with a substrate temperature of room temperature (RT) tends to have an nc crystalline structure. Note that room temperature (RT) here includes the temperature when the substrate is not intentionally heated.

[0334] [Metal oxide composition] A structure of a cloud-aligned composite (CAC)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described below.

[0335] Note that CAAC (c-axis aligned crystal) represents an example of a crystal structure, and CAC (Cloud-Aligned Composite) represents an example of a function or material configuration.

[0336] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole has a function as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) that become carriers, and the insulating function is a function of not flowing electrons that become carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0337] Moreover, the CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0338] In addition, in the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0339] In addition, the CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are caused to flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force in the on state of the transistor, that is, a large on-current and a high field effect mobility can be obtained.

[0340] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0341] The above is an explanation of the configuration of the metal oxide.

[0342] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0343] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0344] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[0345] [Configuration example] 15A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 bonded together with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided over the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0346] Further, an FPC terminal portion 708 to which an FPC 716 (Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716 via the FPC terminal portion 708 and signal lines 710.

[0347] There may be a plurality of gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0348] The transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 can be the transistors that are the semiconductor device of one embodiment of the present invention.

[0349] Examples of the display element provided in the pixel unit 702 include a liquid crystal element and a light-emitting element. Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element. Examples of the light-emitting element include a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Examples of the light-emitting element include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, and a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type can also be used.

[0350] A display device 700A shown in FIG. 15B is an example of a display device that uses a flexible resin layer 743 instead of the first substrate 701 and can be used as a flexible display.

[0351] In the display device 700A, the pixel portion 702 is not rectangular, but has arc-shaped corners. As shown in region P1 in FIG. 15B, the pixel portion 702 and the resin layer 743 have cutouts formed by cutting out parts of the pixel portion 702 and the resin layer 743. A pair of gate driver circuit units 706 are provided on both sides of the pixel portion 702. The gate driver circuit units 706 are provided at the corners of the pixel portion 702 along the arc-shaped contour.

[0352] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. A part of the resin layer 743 including the FPC terminal portion 708 can be folded back to the rear side in a region P2 in Fig. 15(B) by folding back a part of the resin layer 743. With the FPC 716 overlapping the rear side of the pixel portion 702, the display device 700A can be mounted on an electronic device, thereby saving space in the electronic device.

[0353] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. In this case, the source driver circuit unit 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

[0354] 15C is a display device that can be suitably used in electronic devices having a large screen, such as television devices, monitor devices, personal computers (including notebook and desktop computers), tablet terminals, and digital signage.

[0355] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0356] The multiple source driver ICs 721 are each attached to an FPC 723. One terminal of each of the multiple FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0357] On the other hand, the gate driver circuit portion 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0358] With this configuration, a large-sized, high-resolution display device can be realized. For example, a display device with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more can be realized. Also, a display device with an extremely high resolution such as 4K2K or 8K4K resolution can be realized.

[0359] [Cross-section example] A configuration using liquid crystal elements as display elements and a configuration using EL elements will be described below with reference to Figs. 16 to 19. Figs. 16 to 18 are cross-sectional views taken along dashed line QR of display device 700 shown in Fig. 15(A). Fig. 19 is a cross-sectional view taken along dashed line ST of display device 700A shown in Fig. 15(B). Figs. 16 and 17 show configurations using liquid crystal elements as display elements, and Figs. 18 and 19 show configurations using EL elements.

[0360] [Description of common parts of the display device] 16 to 19 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. FIG. 17 illustrates a case where the capacitor 790 is not included.

[0361] The transistors described in Embodiment 1 can be used as the transistors 750 and 752.

[0362] The transistor used in this embodiment has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be reduced. Thus, the retention time of an electric signal such as an image signal can be increased, and the writing interval of the image signal can be set to be long. Thus, the frequency of a refresh operation can be reduced, which leads to an effect of reducing power consumption.

[0363] In addition, the transistor used in this embodiment mode can be driven at high speed because it has a relatively high field effect mobility. For example, by using such a transistor capable of high speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. That is, a configuration without using a driver circuit formed using a silicon wafer or the like is possible, and the number of components in the display device can be reduced. In addition, by using a transistor capable of high speed driving in the pixel portion, a high-quality image can be provided.

[0364] The capacitor 790 shown in FIG. 16, FIG. 18, and FIG. 19 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has a low resistance like the source and drain regions of the transistor 750. In addition, a part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. In addition, a wiring obtained by processing the same film as the source and drain electrodes of the transistor is connected to the upper electrode.

[0365] In addition, a planarization insulating film 770 is provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0366] The transistor 750 in the pixel portion 702 and the transistor 752 in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them and a bottom-gate transistor may be used for the other. Note that, like the source driver circuit portion 704, the gate driver circuit portion 706 may also use a transistor having the same structure as the transistor 750 or a transistor having a different structure.

[0367] The signal line 710 is formed of the same conductive film as the source and drain electrodes of the transistor 750 and the transistor 752. In this case, it is preferable to use a low-resistance material such as a material containing copper because signal delays caused by wiring resistance are small and display on a large screen is possible.

[0368] The FPC terminal portion 708 includes a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed using the same conductive film as the source and drain electrodes of the transistor 750 and the transistor 752.

[0369] A flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 750 or the like.

[0370] In addition, on the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0371] [Example of the configuration of a display device using a liquid crystal element] A display device 700 shown in FIG. 16 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over a planarization insulating film 770 and functions as a pixel electrode.

[0372] A material that transmits or reflects visible light can be used for the conductive layer 772. As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a reflective material, for example, a material containing aluminum, silver, or the like can be used.

[0373] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich a liquid crystal element.

[0374] 17 shows an example of a display device 700 using a horizontal electric field (e.g., FFS mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0375] 17, a storage capacitor can be formed using a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0376] 16 and 17, an alignment film may be provided in contact with the liquid crystal layer 776. Optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0377] Thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. In addition, when the in-plane switching mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0378] In addition, the liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0379] Also, a scattering type liquid crystal using a polymer dispersed type liquid crystal or a polymer network type liquid crystal can be used for the liquid crystal layer 776. In this case, a configuration for performing black and white display without providing the colored film 736, or a configuration for performing color display using the colored film 736 can be used.

[0380] Furthermore, as a method for driving the liquid crystal element, a time-division display method (also called a field sequential driving method) that performs color display based on a time-sequential additive color mixing method may be applied. In this case, the color film 736 may not be provided. When the time-division display method is used, there is an advantage that the aperture ratio of the pixel can be improved and the resolution can be increased because there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue).

[0381] [Display device using light-emitting element] 18 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes a light-emitting material such as an organic compound or an inorganic compound.

[0382] As the light-emitting material, a fluorescent material, a phosphorescent material, a thermally activated delayed fluorescence (TADF) material, an inorganic compound (such as a quantum dot material), or the like can be used.

[0383] 18, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element that has a light-transmitting conductive film 788. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0384] The colored film 736 is provided at a position overlapping with the light-emitting element 782. The light-shielding film 738 is provided at a position overlapping with the insulating film 730, in the lead-out wiring portion 711, and in the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when the EL layer 786 is formed by coloring, the colored film 736 may not be provided.

[0385] A configuration of a display device that can be suitably applied to a flexible display is shown in Fig. 19. Fig. 19 is a cross-sectional view taken along dashed line ST in the display device 700A shown in Fig. 15(B).

[0386] 19 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 instead of the first substrate 701 shown in FIG. 19. A transistor 750, a capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.

[0387] The support substrate 745 is a substrate that contains an organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer that contains an organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0388] 19 has a protective layer 740 instead of the second substrate 705 shown in FIG. 18. The protective layer 740 is bonded to the sealing film 732. A glass substrate, a resin film, or the like can be used as the protective layer 740. In addition, an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be used as the protective layer 740.

[0389] An EL layer 786 included in the light-emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By creating the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using the colored film 736. A protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably an inorganic insulating film. A stacked structure including at least one inorganic insulating film and at least one organic insulating film is more preferably used.

[0390] FIG. 19 also shows a bendable region P2. In the region P2, in addition to the support substrate 745 and the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. By providing as little inorganic insulating film as possible in the bendable region P2 and by using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are laminated, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0391] [Example of configuration in which an input device is provided on a display device] An input device may be provided in the display device 700 or the display device 700A shown in Figures 16 to 19. As the input device, for example, a touch sensor or the like can be given.

[0392] For example, various types of sensors can be used, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, a pressure sensitive type, etc. Alternatively, two or more of these types may be used in combination.

[0393] The touch panel may have a configuration such as an in-cell type touch panel in which an input device is formed between a pair of substrates, a so-called on-cell type touch panel in which an input device is formed on the display device 700, or a so-called out-cell type touch panel in which an input device is attached to the display device 700.

[0394] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0395] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0396] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0397] 20A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0398] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0399] The pixel section 502 has a plurality of pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element.

[0400] The driver circuit unit 504 has driver circuits such as a gate driver 504a that outputs scanning signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may have at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b may also be configured using a shift register.

[0401] The terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0402] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 20(A) is connected to various wirings, such as a gate line GL that is a wiring between a gate driver 504a and a pixel circuit 501, or a data line DL that is a wiring between a source driver 504b and a pixel circuit 501. Note that in Fig. 20(A), the protection circuit 506 is hatched to distinguish it from the pixel circuit 501.

[0403] In addition, the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel unit 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (e.g., a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate on which the pixel unit 502 is provided by COG or TAB (Tape Automated Bonding).

[0404] 20B and 20C show examples of the configuration of a pixel circuit that can be applied to the pixel circuit 501. In FIG.

[0405] 20B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0406] The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the multiple pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0407] 20C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0408] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. A current flowing through the light emitting element 572 is controlled in accordance with a potential applied to the gate of the transistor 554, thereby controlling the light emission luminance of the light emitting element 572.

[0409] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples or drawings.

[0410] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0411] (Embodiment 4) A pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described below. The transistors described in the first embodiment can be used as the transistors used in the pixel circuits described below.

[0412] [Circuit configuration] 21A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0413] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0414] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be used.

[0415] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0416] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Also, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed according to the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0417] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistors M1 and M2. Therefore, the potential of the node N1 or the node N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period during which the potential of each node is held is short (specifically, when the frame frequency is 30 Hz or more), a transistor including a semiconductor such as silicon may be used.

[0418] [Driving method example] Next, an example of an operation method of the pixel circuit 400 will be described with reference to Fig. 21(B). Fig. 21(B) is a timing chart relating to the operation of the pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, threshold voltages of transistors, and the like will not be taken into consideration here.

[0419] 21B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0420] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supplies.

[0421] The node N1 is connected to a potential V ref The node N2 is supplied with a first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0422] [Period T2] In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0423] The node N1 receives a second data potential V data At this time, the second data potential V data In response to this, the potential of the node N2 changes by a potential dV. w The potential obtained by adding the second data potential V to the potential dV is input. Note that, although the potential dV is shown to be a positive value in FIG. 21B, it may be a negative value. That is, the second data potential V data is the potential V ref It may be lower.

[0424] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential becomes close to

[0425] In this manner, the pixel circuit 400 can combine two types of data signals to generate a potential to be supplied to the circuit 401 including a display element, and therefore, gray scale correction can be performed within the pixel circuit 400.

[0426] In addition, the pixel circuit 400 can generate a potential that exceeds the maximum potential that can be supplied by a source driver connected to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. When a liquid crystal element is used, overdrive driving or the like can be realized.

[0427] [Example of application] [Example using liquid crystal element] A pixel circuit 400LC shown in Fig. 21C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0428] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0429] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted.

[0430] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, and therefore can, for example, realize high-speed display by overdrive driving, apply a liquid crystal material with a high driving voltage, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct the gradation according to the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0431] [Example using light-emitting element] The pixel circuit 400EL shown in Fig. 21D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0432] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and a drain connected to the potential V H The other electrode of the capacitor C2 is connected to a wiring to which a potential V comThe light-emitting element EL has the other electrode connected to a wiring that is supplied with a potential V L Connect with the wiring given.

[0433] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if not required.

[0434] In this embodiment, the anode side of the light-emitting element EL is connected to the transistor M3, but the cathode side of the light-emitting element EL may be connected to the transistor M3. H and potential V L The value of can be changed appropriately.

[0435] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, and thus, for example, HDR display can be realized. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0436] Note that the present invention is not limited to the circuits illustrated in FIGS. 21C and 21D, and a configuration in which a transistor, a capacitor, or the like is added may be used.

[0437] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0438] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0439] A display module 6000 shown in FIG. 22A includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0440] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0441] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately according to the size of the display device 6006.

[0442] The display device 6006 may have a function as a touch panel.

[0443] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0444] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0445] FIG. 22B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor.

[0446] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. Also, in an area surrounded by an upper cover 6001 and a lower cover 6002, a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) are provided.

[0447] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guiding portion 6017a and a light guiding portion 6017b.

[0448] Light 6018 emitted from the light-emitting unit 6015 passes through the light-guiding unit 6017a, the upper part of the display device 6006, and the light-guiding unit 6017b to reach the light-receiving unit 6016. When the light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected.

[0449] A plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. This makes it possible to obtain information on the position where a touch operation is performed.

[0450] The light emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light receiving unit 6016 may be a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts it into an electric signal. Preferably, a photodiode that can receive infrared light may be used.

[0451] The light guiding portion 6017a and the light guiding portion 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, and it is possible to prevent external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, if a resin that absorbs visible light and transmits infrared light is used, it is possible to more effectively prevent the touch sensor from malfunctioning.

[0452] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0453] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0454] An electronic device 6500 shown in FIG. 23A is a portable information terminal that can be used as a smartphone.

[0455] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0456] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0457] FIG. 23B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0458] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0459] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0460] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0461] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0462] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0463] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured according to one embodiment of the present invention will be described.

[0464] The electronic devices exemplified below each have a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices have high resolution. In addition, the electronic devices can have both high resolution and a large screen.

[0465] The display portion of the electronic device according to one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0466] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0467] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0468] FIG. 24A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0469] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. In addition, a detachable lens 8006 is attached to the camera 8000.

[0470] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0471] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0472] The housing 8001 has a mount having electrodes, and can be connected to a strobe device or the like in addition to the finder 8100 .

[0473] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0474] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0475] The button 8103 has a function such as a power button.

[0476] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0477] FIG. 24B is a diagram showing the external appearance of the head mounted display 8200.

[0478] The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 includes a built-in battery 8206.

[0479] A cable 8205 supplies power from a battery 8206 to a main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes a camera and can use information on the movements of the user's eyeballs and eyelids as an input means.

[0480] The mounting unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that contact the user, capable of detecting a current that flows with the movement of the user's eyeballs. The mounting unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The mounting unit 8201 may also have various sensors, such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 according to the movement of the user's head.

[0481] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0482] 24C, 24D, and 24E are diagrams showing the external appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0483] A user can view the display on the display unit 8302 through the lens 8305. Note that it is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing another image displayed in a different area of ​​the display unit 8302 through the lens 8305, it is possible to perform three-dimensional display using parallax. Note that the present invention is not limited to a configuration in which one display unit 8302 is provided, and two display units 8302 may be provided, with one display unit being provided for each eye of the user.

[0484] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition, so that a user cannot see pixels even when the image is enlarged using a lens 8305 as in FIG.

[0485] The electronic devices shown in Figures 25(A) to 25(G) have a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0486] 25(A) to 25(G) have various functions. For example, the electronic devices may have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded on a recording medium, and the like. Note that the functions of the electronic devices are not limited to these, and the electronic devices may have various functions. The electronic devices may have multiple display units. In addition, the electronic devices may have a function of providing a camera or the like in order to capture still images or videos and store them in a recording medium (external or built-in to the camera), a function of displaying the captured images on the display unit, and the like.

[0487] The electronic devices shown in FIGS. 25A to 25G will be described in detail below.

[0488] 25A is a perspective view of a television set 9100. The television set 9100 can incorporate a display portion 9001 having a large screen, for example, a screen size of 50 inches or more, or 100 inches or more.

[0489] FIG. 25B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 25B shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mails, SNS, and phone calls, titles of e-mails and SNS, sender names, date and time, time, remaining battery level, and antenna reception strength. Alternatively, the icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0490] 25(C) is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of a display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and determine, for example, whether to answer a call.

[0491] 25D is a perspective view showing a wristwatch-type mobile information terminal 9200. The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with a headset capable of wireless communication, for example. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0492] 25(E), 25(F), and 25(G) are perspective views showing a foldable mobile information terminal 9201. FIG. 25(E) shows the mobile information terminal 9201 in an unfolded state, FIG. 25(G) shows the mobile information terminal 9201 in a folded state, and FIG. 25(F) shows the mobile information terminal 9201 in a state in the middle of changing from one of FIG. 25(E) and FIG. 25(G) to the other. The mobile information terminal 9201 is highly portable when folded, and is highly viewable due to a seamless wide display area when unfolded. A display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0493] 26A shows an example of a television set. A television set 7100 includes a display unit 7500 built in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0494] 26A can be operated using an operation switch provided on a housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television set 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0495] The television device 7100 may also include a television broadcast receiver and a communication device for network connection.

[0496] 26B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0497] FIG. 26(C) and FIG. 26(D) show an example of digital signage.

[0498] 26C includes a housing 7301, a display portion 7500, a speaker 7303, and the like. The digital signage 7300 may further include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0499] 26D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0500] The larger the display unit 7500, the more information can be provided at one time, and the larger the display area, the more easily it catches people's attention, which has the effect of increasing the effectiveness of advertising, for example.

[0501] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes, but also for providing information desired by the user, such as route information, traffic information, and commercial facility guide information.

[0502] 26(C) and 26(D), the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0503] Furthermore, a game using the information terminal 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0504] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS.

[0505] Although the electronic device in this embodiment has a display portion, one embodiment of the present invention can also be applied to an electronic device that does not have a display portion.

[0506] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. EXAMPLES

[0507] Below, a sample including an insulating film that can be used for a transistor of one embodiment of the present invention was prepared, and the amount of hydrogen released from the insulating film and the oxygen permeability of the insulating film were evaluated by thermal desorption spectrometry (TDS). The results are described below.

[0508] [Example 1-1] [Sample Preparation] First, a silicon oxynitride film with a thickness of about 100 nm was formed as an insulating film on a glass substrate by plasma CVD. Three samples (samples A1 to A3) were fabricated using different insulating film formation conditions.

[0509] The silicon nitride oxide film of Sample A1 was formed under the conditions of silane gas, nitrogen gas, ammonia gas, and nitrous oxide gas flow rates of 150 sccm, 5000 sccm, 100 sccm, and 100 sccm, respectively, pressure of 200 Pa, film formation power of 2000 W, and substrate temperature of 350°C.

[0510] The silicon nitride oxide films of Samples A2 and A3 were formed under the same conditions as those for Sample A1 except that the flow rates of the dinitrogen monoxide gas were 500 sccm and 1000 sccm, respectively.

[0511] In this manner, Samples A1 to A3 in which an insulating film was formed on a glass substrate were manufactured.

[0512] [TDS analysis] The above samples A1 to A3 were each subjected to TDS analysis at a temperature rise rate of 30° C. / min.

[0513] Figures 27(A) to 27(C) show the results of TDS analysis for samples (referred to as Samples) A1 to A3, respectively. Figures 27(A) to 27(C) show the results for the mass-to-charge ratio (M / z)2 corresponding to hydrogen molecules. The horizontal axis is the substrate temperature (Sub. Temp.) and the vertical axis is the detection intensity (Intensity). Each figure also shows the quantitative value of the desorption amount per unit volume.

[0514] It was confirmed that the amount of hydrogen molecules desorbed from the insulating film was small for each sample, and that the amount of hydrogen molecules desorbed decreased as the flow rate of nitrous oxide gas during film formation increased.

[0515] [Example 1-2] In the following, a sample in which a silicon nitride oxide film was formed on a silicon oxynitride film that releases oxygen when heated was prepared, and the oxygen permeability of the silicon nitride oxide film was evaluated by TDS analysis.

[0516] [Sample Preparation] First, a silicon oxynitride film having a thickness of about 100 nm was formed on a glass substrate by plasma CVD.

[0517] Next, a metal oxide film was formed on the silicon oxynitride film by a sputtering method, and then oxygen was supplied into the silicon oxynitride film by performing oxygen radical treatment, and the metal oxide film was then removed by etching.

[0518] Subsequently, a silicon nitride oxide film was formed on the silicon oxynitride film by plasma CVD to a thickness of about 100 nm. Three samples (samples B1 to B3) were fabricated using different conditions for forming the silicon nitride oxide film.

[0519] The silicon oxynitride films of Samples B1, B2, and B3 were formed under the same conditions as those of Samples A1, A2, and A3, respectively.

[0520] In this manner, a sample was fabricated in which a silicon nitride oxide film was stacked on a silicon oxynitride film that releases oxygen when heated.

[0521] [TDS analysis] Figures 27(D) to 27(F) show the results of TDS analysis of samples B1 to B3, respectively. Figures 27(D) to 27(F) show the results for a mass-to-charge ratio of 32, which corresponds to oxygen molecules. Each figure also shows the quantitative value of the amount of desorption per unit volume. Each figure also shows the TDS analysis result of a silicon oxynitride film in the case where a silicon nitride oxide film is not formed, with a dashed line.

[0522] It can be confirmed that the formation of a silicon nitride oxide film in each sample suppresses the desorption of oxygen molecules. In other words, it is found that the silicon nitride oxide film has oxygen blocking properties. In particular, it was confirmed that sample B1, which had the lowest flow rate of nitrous oxide gas during film formation, exhibited extremely high oxygen blocking properties.

[0523] From the above, it was confirmed that the silicon nitride oxide film manufactured in this embodiment has an extremely small amount of hydrogen desorption and has an oxygen blocking property. By using such a silicon nitride oxide film as the insulating layer 103 shown in Embodiment 1, particularly the insulating film 103a, a highly reliable transistor can be realized. EXAMPLES

[0524] In the following, transistors having different insulating layer configurations that form a surface on which a semiconductor layer is formed are manufactured, and the results of evaluating the electrical characteristics and reliability of the transistors are described.

[0525] [Sample preparation] The structure of the manufactured transistor can be that of the transistor 100C described in Embodiment 1 as an example.

[0526] First, a tungsten film having a thickness of about 100 nm was formed on a glass substrate by sputtering, and then processed to obtain a first gate electrode.

[0527] Next, a first gate insulating layer was formed. Four samples (samples C1 to C4) having different configurations of the first gate insulating layer were fabricated.

[0528] The first gate insulating layers of Samples C1 to C3 each had a stacked structure of a silicon nitride film with a thickness of about 30 nm, a silicon nitride oxide film with a thickness of about 280 nm, and a silicon oxynitride film with a thickness of about 20 nm.

[0529] The silicon nitride film was formed under the conditions of silane gas, nitrogen gas, and ammonia gas flow rates of 290 sccm, 2000 sccm, and 2000 sccm, respectively, pressure of 200 Pa, film formation power of 3000 W, and substrate temperature of 350°C.

[0530] The silicon oxynitride film was formed under the conditions of a silane gas and a nitrous oxide gas flow rate of 100 sccm and 4000 sccm, respectively, a pressure of 200 Pa, a film-forming power of 2000 W, and a substrate temperature of 350°C.

[0531] The silicon nitride oxide film of Sample C1 was formed under the same conditions as Sample A1 described in Example 1-1 above. The silicon nitride oxide film of Sample C2 was formed under the same conditions as Sample A2. The silicon nitride oxide film of Sample C3 was formed under the same conditions as Sample A3.

[0532] The first gate insulating layer of sample C4 had a laminated structure of a first silicon nitride film with a thickness of about 200 nm, a second silicon nitride film with a thickness of about 100 nm, and a silicon oxynitride film with a thickness of about 20 nm.

[0533] The first silicon nitride film was formed under the same conditions as those for the silicon nitride film in the above-mentioned sample C1 and the like.

[0534] The second silicon nitride film was formed under the conditions of silane gas, nitrogen gas, and ammonia gas flow rates of 150 sccm, 5000 sccm, and 100 sccm, respectively, pressure of 200 Pa, film formation power of 2000 W, and substrate temperature of 350°C.

[0535] The silicon oxynitride film was formed under the same conditions as those for the silicon oxynitride film in the above-mentioned sample C1 and the like.

[0536] Next, a metal oxide film with a thickness of about 30 nm was formed on the first gate insulating layer, and then processed to obtain a semiconductor layer. The metal oxide film was formed by sputtering using a sputtering target with an atomic ratio of metal elements of In:Ga:Zn=1:1:1. Then, a heat treatment was performed at 370°C for 1 hour.

[0537] Next, a silicon oxynitride film having a thickness of about 140 nm, which serves as a second gate insulating layer, was formed by plasma CVD.

[0538] Next, as a conductive film to be the second gate electrode, an indium zinc oxide film with a thickness of about 20 nm, a copper film with a thickness of about 100 nm, and an indium zinc oxide film with a thickness of about 30 nm were formed by sputtering. After that, each conductive film and the silicon oxynitride film were processed to obtain a second gate electrode and a second gate insulating layer.

[0539] Next, a silicon oxynitride film with a thickness of about 300 nm was formed by plasma CVD as a protective insulating layer covering the transistor. After that, a part of the protective insulating layer was opened by etching, and a molybdenum film was formed by sputtering, and then processed to obtain source and drain electrodes. After that, an acrylic film with a thickness of about 1.5 μm was formed as a flat film, and a heat treatment was performed under the conditions of a nitrogen atmosphere at a temperature of 250°C for 1 hour.

[0540] Through the above steps, samples C1 to C4, each having a transistor formed on a glass substrate, were obtained.

[0541] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistors were measured for Samples C1 to C4 fabricated as described above.

[0542] The Id-Vg characteristics of the transistor were measured under the following conditions: the voltage applied to the gate electrode (hereinafter also referred to as the gate voltage (VG)) was −15 V to +20 V in increments of 0.25 V. The voltage applied to the source electrode (hereinafter also referred to as the source voltage (VS)) was 0 V (comm), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (VD)) was 0.1 V and 10 V.

[0543] Here, the Id-Vg characteristics were measured when the same gate voltage was applied to the first gate electrode and the second gate electrode.

[0544] The measured transistors were dual-gate transistors with a channel length of 2 μm and a channel width of 3 μm. The number of measurements was 20 for each sample.

[0545] 28A to 28D show the Id-Vg characteristics of Samples C1 to C4, respectively. In each figure, two Id-Vg characteristics when the drain voltage is 0.1 V and 10 V are shown together.

[0546] As shown in FIGS. 28A to 28D, it can be confirmed that good electrical characteristics with little variation are obtained in all the samples.

[0547] [Reliability assessment] Next, a GBT test was performed to evaluate the reliability of the above transistor. In the GBT test, the substrate on which the transistor is formed is kept at 60°C, 0V is applied to the source and drain of the transistor, and 20V or -20V is applied to the gate, and this state is maintained for one hour. Here, the PBTS test is particularly shown.

[0548] Fig. 29 shows the variation (ΔVth) of the threshold voltage after the PBTS test in samples C1 to C4. Fig. 29 shows the case where the same stress is applied to the first gate electrode and the second gate electrode (Dual Stress), the case where stress is applied only to the second gate electrode (Top Stress), and the case where stress is applied only to the first gate electrode (Bottom Stress) for each sample.

[0549] 29, it can be seen that the variation in threshold voltage is smaller in Sample C1, Sample C2, and Sample C3 than in Sample C4. This confirms that a highly reliable transistor can be realized by using a silicon nitride oxide film for the first gate insulating layer.

[0550] In addition, when comparing the results of the Bottom Stress of Samples C1, C2, and C3, there is a tendency that the variation in threshold voltage decreases in the order of Samples C1, C2, and C3. From this result and the result of Example 1-1, it is inferred that the variation in threshold voltage can be suppressed by using a silicon nitride oxide film that releases less hydrogen.

[0551] From the above, it was confirmed that by using a silicon nitride oxide film that is not likely to release hydrogen and through which oxygen is not likely to diffuse as the first gate insulating layer, a transistor with small characteristic variation, good electrical characteristics, and high reliability can be realized. [Explanation of symbols]

[0552] 10, 10A to 10E: transistors, 100, 100A to 100C: transistors, 102: substrate, 103: insulating layer, 103a to 103c: insulating films, 106: conductive layer, 108, 108a, 108b: semiconductor layer, 108f: metal oxide film, 108n: low resistance region, 110, 110a to 110c: insulating film, 112: conductive layer, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide film, 116, 118: insulating layer, 120a, 120b: conductive layer, 140: impurity element, 141a, 141b, 142: openings

Claims

1. A semiconductor device comprising: a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer; the semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order on the first insulating layer; the first insulating layer has a laminated structure in which a first insulating film, a second insulating film, and a third insulating film are laminated in this order; The second insulating film has a thickness greater than that of the first insulating film, the second insulating film has a thickness greater than a thickness of the third insulating film; the second insulating layer includes an oxide; the semiconductor layer contains indium and oxygen; the third insulating film has a portion in contact with the semiconductor layer, the first insulating film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; the second insulating film contains silicon, nitrogen, and oxygen; the second insulating film contains more oxygen than the first insulating film and less oxygen than the third insulating film; the second insulating film contains less nitrogen than the first insulating film and more nitrogen than the third insulating film.

2. A semiconductor device comprising: a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer; the semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order on the first insulating layer; the first insulating layer has a laminated structure in which a first insulating film, a second insulating film, and a third insulating film are laminated in this order; the second insulating layer has a laminated structure in which a fourth insulating film, a fifth insulating film, and a sixth insulating film are laminated in this order; the second insulating film has a thickness greater than that of the first insulating film; the second insulating film has a thickness greater than a thickness of the third insulating film; the semiconductor layer contains indium and oxygen; the third insulating film has a portion in contact with the semiconductor layer, the fourth insulating film has a portion in contact with the semiconductor layer, the first insulating film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; the second insulating film contains silicon, nitrogen, and oxygen; the second insulating film contains more oxygen than the first insulating film and less oxygen than the third insulating film; the nitrogen contained in the second insulating film is less than that contained in the first insulating film and is more than that contained in the third insulating film; the fourth insulating film includes an oxide; the fifth insulating film includes an oxide; the sixth insulating film includes an oxide; the fourth insulating film has a film density higher than the film density of the fifth insulating film; A semiconductor device, wherein the sixth insulating film has a film density higher than the film density of the fifth insulating film.

3. In claim 1 or 2, the thickness of the second insulating film is 2 times or more and 20 times or less than the thickness of the first insulating film; the thickness of the second insulating film is 2 times or more and 20 times or less than the thickness of the third insulating film; A semiconductor device, wherein the thickness of the second insulating film is 50% or more and 95% or less of a total thickness of the first insulating layer.

4. In any one of claims 1 to 3, the semiconductor layer comprises M (wherein M is one or more elements selected from aluminum, gallium, yttrium, and tin) and zinc; The semiconductor layer has a region in which the indium content is higher than the M content.

5. In any one of claims 1 to 4, a metal oxide layer between the second insulating layer and the first conductive layer; The semiconductor device, wherein the metal oxide layer contains one or more elements selected from the group consisting of aluminum, hafnium, tin, indium, gallium, and zinc.

6. A semiconductor device comprising: a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer; the semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order on the first insulating layer; the first insulating layer has a laminated structure in which a first insulating film, a second insulating film, and a third insulating film are laminated in this order; the semiconductor layer has a laminated structure in which a first metal oxide film and a second metal oxide film are laminated in this order; The second insulating film has a thickness greater than that of the first insulating film, the second insulating film has a thickness greater than a thickness of the third insulating film; the second insulating layer includes an oxide; the first metal oxide film and the second metal oxide film each contain indium and oxygen; the second insulating layer has a portion in contact with the second metal oxide film, the third insulating film has a portion in contact with the first metal oxide film, the first insulating film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; the second insulating film contains silicon, nitrogen, and oxygen; the second insulating film contains more oxygen than the first insulating film and less oxygen than the third insulating film; the second insulating film contains less nitrogen than the first insulating film and more nitrogen than the third insulating film.

7. A semiconductor device comprising: a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer; the semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order on the first insulating layer; the first insulating layer has a laminated structure in which a first insulating film, a second insulating film, and a third insulating film are laminated in this order; the second insulating layer has a laminated structure in which a fourth insulating film, a fifth insulating film, and a sixth insulating film are laminated in this order; the semiconductor layer has a laminated structure in which a first metal oxide film and a second metal oxide film are laminated in this order; The second insulating film has a thickness greater than that of the first insulating film, the second insulating film has a thickness greater than a thickness of the third insulating film; the second insulating layer includes an oxide; the first metal oxide film and the second metal oxide film each contain indium and oxygen; the second insulating layer has a portion in contact with the second metal oxide film, the third insulating film has a portion in contact with the first metal oxide film, the first insulating film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; the second insulating film contains silicon, nitrogen, and oxygen; the second insulating film contains more oxygen than the first insulating film and less oxygen than the third insulating film; the second insulating film contains less nitrogen than the first insulating film and more nitrogen than the third insulating film; the fourth insulating film includes an oxide; the fifth insulating film includes an oxide; the sixth insulating film includes an oxide; the fourth insulating film has a film density higher than the film density of the fifth insulating film; A semiconductor device, wherein the sixth insulating film has a film density higher than the film density of the fifth insulating film.

8. In claim 6 or 7, the thickness of the second insulating film is 2 times or more and 20 times or less than the thickness of the first insulating film; the thickness of the second insulating film is 2 times or more and 20 times or less than the thickness of the third insulating film; A semiconductor device, wherein the thickness of the second insulating film is 50% or more and 95% or less of a total thickness of the first insulating layer.

9. In any one of claims 6 to 8, the first metal oxide film contains gallium and zinc; the second metal oxide film contains gallium and zinc; The second metal oxide film has a region having a higher indium content and a lower gallium content than the first metal oxide film.

10. In any one of claims 6 to 8, the first metal oxide film contains gallium and zinc; The second metal oxide film does not contain gallium.

11. In any one of claims 6 to 10, a metal oxide layer between the second insulating layer and the first conductive layer; The semiconductor device, wherein the metal oxide layer contains one or more elements selected from the group consisting of aluminum, hafnium, tin, indium, gallium, and zinc.

Images