Semiconductor device and electronic device

Abstract

To provide a semiconductor apparatus capable of performing product-sum calculations with low power consumption.SOLUTION: A circuit MC included in a circuit MP included in a semiconductor apparatus comprises transistors M1 to M4 and a capacitive element C1, and configures a holding unit HC with the transistor M1 and the capacitive element C1. The transistors M1 to M4 are multi-gate n-channel transistors having gates above and below a channel, and each of the transistors M1 to M4 has a first gate and a second gate. By manufacturing the transistors using semiconductor substrates, single crystal substrates, SOI substrates, or the like, it is possible to manufacture the transistors with small variations in characteristics, size, shape, or the like, high current capacity, and small size. By configuring the circuit with such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is actively progressing. Such integrated circuits incorporate the mechanisms of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to perform parallel processing with extremely low power consumption compared to the von Neumann architecture, which consumes more power as the processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using SRAM (Static Random Access Memory). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-Patent Document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In an artificial neural network, a calculation is performed in which the connection strength (sometimes called a weighting coefficient) of a synapse connecting two neurons is multiplied by a signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, it is necessary to multiply and add up the connection strength of each synapse between a plurality of first neurons in the first layer and one of the second neurons in the second layer and each signal input from a plurality of first neurons in the first layer to one of the second neurons in the second layer, and the number of connection strengths and the number of parameters indicating the signals are determined according to the scale of the artificial neural network. In other words, in an artificial neural network, the number of circuits corresponding to "neurons" and "synapses" increases as the number of layers and the number of neurons increase, and the amount of calculations may become enormous.

[0007] As the number of circuits constituting a chip increases, the power consumption increases and the amount of heat generated during operation of the device also increases. In particular, the higher the amount of heat generated, the more it affects the characteristics of the circuit elements contained in the chip, so it is preferable for the circuits constituting the chip to have circuit elements that are less susceptible to temperature effects.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like in which a hierarchical artificial neural network is constructed.Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption.Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to the influence of environmental temperature.Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

[0009] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, in which the first circuit has a first holding node and the second circuit has a second holding node, the first circuit is electrically connected to a first input wiring, a second input wiring, a first wiring, and a second wiring, the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and a second wiring, the first circuit has a function of holding a first potential corresponding to first data in the first holding node, the second circuit has a function of holding a second potential corresponding to the first data in the second holding node, and the first circuit has a function of outputting a current corresponding to the first potential to the first wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, and a function of not outputting a current corresponding to the first potential to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, and the second circuit has a function of outputting a current corresponding to the second potential to the second wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, a function of outputting a current corresponding to the second potential to the first wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring, and a function of not outputting a current corresponding to the second potential to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring.

[0011] (2) Alternatively, according to one aspect of the present invention, in the configuration (1) above, the first circuit includes first to fourth transistors and a first capacitance element, the second circuit includes fifth to eighth transistors and a second capacitance element, the first holding node is electrically connected to a first terminal of the first transistor, a gate of the second transistor, and a first terminal of the first capacitance element, the first terminal of the second transistor is electrically connected to a second terminal of the first capacitance element, the second terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor, the gate of the third transistor is electrically connected to a first input wiring, the gate of the fourth transistor is electrically connected to a second input wiring, and the second terminal of the third transistor is electrically connected to the first wiring. a second terminal of the fourth transistor electrically connected to the second wiring; a second holding node electrically connected to a first terminal of the fifth transistor, a gate of the sixth transistor, and a first terminal of the second capacitance element; a first terminal of the sixth transistor electrically connected to a second terminal of the second capacitance element; a second terminal of the sixth transistor electrically connected to a first terminal of the seventh transistor and a first terminal of the eighth transistor; a gate of the seventh transistor electrically connected to a first input wiring; a gate of the eighth transistor electrically connected to a second input wiring; a second terminal of the seventh transistor electrically connected to the second wiring; and a second terminal of the eighth transistor electrically connected to the first wiring.

[0012] (3) Alternatively, one aspect of the present invention is the transistor according to (1) above, wherein the first circuit includes first to fourth transistors, a ninth transistor, and a first capacitance element, and the second circuit includes fifth to eighth transistors, a tenth transistor, and a second capacitance element, wherein the first holding node is electrically connected to a first terminal of the first transistor, a gate of the second transistor, a gate of the ninth transistor, and a first terminal of the first capacitance element, a second terminal of the first capacitance element is electrically connected to a first terminal of the second transistor and a first terminal of the ninth transistor, a second terminal of the second transistor is electrically connected to a first terminal of the third transistor, a second terminal of the ninth transistor is electrically connected to a first terminal of the fourth transistor, a gate of the third transistor is electrically connected to a first input wiring, a gate of the fourth transistor is electrically connected to a second input wiring, and a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor. a second terminal of the fourth transistor electrically connected to the second wiring; a second holding node electrically connected to a first terminal of the fifth transistor, a gate of the sixth transistor, a gate of the tenth transistor, and a first terminal of the second capacitance element; a second terminal of the second capacitance element electrically connected to the first terminal of the sixth transistor and the first terminal of the tenth transistor; a second terminal of the sixth transistor electrically connected to a first terminal of the seventh transistor; a second terminal of the tenth transistor electrically connected to a first terminal of the eighth transistor; a gate of the seventh transistor electrically connected to a first input wiring; a gate of the eighth transistor electrically connected to a second input wiring; a second terminal of the seventh transistor electrically connected to the second wiring; and a second terminal of the eighth transistor electrically connected to the first wiring.

[0013] (4) Alternatively, according to one embodiment of the present invention, in the configuration of (1) above, the first circuit includes first to fourth transistors, a first logic circuit, and a second logic circuit, and the second circuit includes fifth to eighth transistors, a third logic circuit, and a fourth logic circuit, each of the first to fourth logic circuits having a function of outputting, from an output terminal, an inverted signal of a signal input to an input terminal thereof, the first holding node is electrically connected to an input terminal of the first logic circuit, an output terminal of the second logic circuit, a first terminal of the first transistor, and a gate of the second transistor, the output terminal of the first logic circuit is electrically connected to an input terminal of the second logic circuit, the second terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor, the gate of the third transistor is electrically connected to a first input wiring, and the gate of the fourth transistor is electrically connected to a first input wiring. a second terminal of the third transistor electrically connected to the first wiring, a second terminal of the fourth transistor electrically connected to the second wiring, a second hold node electrically connected to an input terminal of the third logic circuit, an output terminal of the fourth logic circuit, a first terminal of the fifth transistor, and a gate of the sixth transistor, the output terminal of the third logic circuit electrically connected to an input terminal of the fourth logic circuit, a second terminal of the sixth transistor electrically connected to a first terminal of the seventh transistor and a first terminal of the eighth transistor, a gate of the seventh transistor electrically connected to the first input wiring, a gate of the eighth transistor electrically connected to the second input wiring, a second terminal of the seventh transistor electrically connected to the second wiring, and a second terminal of the eighth transistor electrically connected to the first wiring.

[0014] (5) Alternatively, according to one embodiment of the present invention, in the configuration of (1) above, the first circuit includes first to fourth transistors, a first logic circuit, and a second logic circuit, and the second circuit includes sixth to eighth transistors, each of the first logic circuit and the second logic circuit has a function of outputting, from an output terminal, an inverted signal of a signal input to an input terminal, the first holding node is electrically connected to an input terminal of the first logic circuit, an output terminal of the second logic circuit, a first terminal of the first transistor, and a gate of the second transistor, the output terminal of the first logic circuit is electrically connected to an input terminal of the second logic circuit, the second terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor, and the gate of the third transistor is electrically connected to a first input wiring. a gate of the fourth transistor is electrically connected to a second input wiring, a second terminal of the third transistor is electrically connected to the first wiring, a second terminal of the fourth transistor is electrically connected to the second wiring, a second hold node is electrically connected to an input terminal of the second logic circuit, an output terminal of the first logic circuit, and a gate of the sixth transistor, the second terminal of the sixth transistor is electrically connected to a first terminal of the seventh transistor and a first terminal of the eighth transistor, a gate of the seventh transistor is electrically connected to the first input wiring, a gate of the eighth transistor is electrically connected to the second input wiring, a second terminal of the seventh transistor is electrically connected to the second wiring, and a second terminal of the eighth transistor is electrically connected to the first wiring.

[0015] (6) Alternatively, one embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, in which the first circuit has a first load circuit, and the second circuit has a second load circuit, each of the first load circuit and the second load circuit has a first terminal and a second terminal, and each of the first load circuit and the second load circuit has a function of changing a resistance value between the first terminal and the second terminal in accordance with first data, the first circuit is electrically connected to a first input wiring, a second input wiring, the first wiring, and a second wiring, the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and a second wiring, the first circuit has a function of outputting a current corresponding to a resistance value of the first load circuit to the first wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, and a function of not outputting a current corresponding to the resistance value of the first load circuit to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, wherein the second circuit has a function of outputting a current corresponding to the resistance value of the second load circuit to the second wiring when a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, a function of outputting a current corresponding to the resistance value of the second load circuit to the first wiring when a low-level potential is input to the first input wiring and a high-level potential is input to the second input wiring, and a function of not outputting a current corresponding to the resistance value of the second load circuit to the first wiring and the second wiring when a low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring.

[0016] (7) Alternatively, one embodiment of the present invention is a semiconductor device in which, in the configuration of (6) above, the first circuit includes a third transistor and a fourth transistor, the second circuit includes a seventh transistor and an eighth transistor, a first terminal of the first load circuit is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor, a gate of the third transistor is electrically connected to a first input wiring, a gate of the fourth transistor is electrically connected to a second input wiring, a second terminal of the third transistor is electrically connected to the first wiring, a second terminal of the fourth transistor is electrically connected to the second wiring, a first terminal of the second load circuit is electrically connected to a first terminal of the seventh transistor and a first terminal of the eighth transistor, a gate of the seventh transistor is electrically connected to the first input wiring, a gate of the eighth transistor is electrically connected to the second input wiring, a second terminal of the seventh transistor is electrically connected to the second wiring, and a second terminal of the eighth transistor is electrically connected to the first wiring.

[0017] (8) Alternatively, one embodiment of the present invention is a semiconductor device in the above configuration (7), in which the first circuit has a first transistor, the second circuit has a second transistor, a first terminal of the first transistor is electrically connected to a first terminal of a first load circuit, and a first terminal of the second transistor is electrically connected to a first terminal of a second load circuit.

[0018] (9) Alternatively, one embodiment of the present invention is a semiconductor device having any one of the above configurations (6) to (8), in which the first load circuit has any one of a resistance change element, an MTJ element, and a phase change memory, and the second load circuit has any one of a resistance change element, an MTJ element, and a phase change memory.

[0019] (10) Alternatively, one embodiment of the present invention is a semiconductor device having any one of the configurations (1) to (9) above, including a third circuit and a fourth circuit. The third circuit has a function of inputting a potential corresponding to second data to each of the first input wiring and the second input wiring, and the fourth circuit has a function of comparing currents flowing from each of the first wiring and the second wiring, and outputting a potential corresponding to a product of the first data and the second data from an output terminal of the fourth circuit.

[0020] (11) Another embodiment of the present invention is an electronic device that includes the semiconductor device described above in any one of (1) to (10) and performs calculations on a neural network using the semiconductor device.

[0021] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may have semiconductor devices.

[0022] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in a figure or text other than the connection relationship shown in the figure or text. X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0023] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display element, a light-emitting element, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0024] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0025] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the cases where X and Y are electrically connected (i.e., when they are connected with another element or circuit between them), where X and Y are functionally connected (i.e., when they are connected with another circuit between them), and where X and Y are directly connected (i.e., when they are connected without another element or circuit between them). In other words, when it is explicitly stated that X and Y are electrically connected, this is the same as when it is explicitly stated that they are simply connected.

[0026] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0027] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0028] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain can be replaced. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0029] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0030] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0031] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is described as a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0032] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0033] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", may be used for convenience in order to explain the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0034] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0035] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, it is possible to replace the terms "film" and "layer" with other terms without using them. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0036] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0037] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0038] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. When an impurity is included, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may decrease, crystallinity may decrease, and so on. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, transition metals other than the main component, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, the impurity that changes the characteristics of the semiconductor may be, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, and the like.

[0039] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0040] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0041] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive. Effect of the Invention

[0042] According to one embodiment of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device that is not easily affected by the temperature of the environment can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0043] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0044] [Figure 1] 1A and 1B are diagrams for explaining a hierarchical neural network. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of the semiconductor device. [Diagram 3] 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 4] 4A, 4B, 4C, 4D, 4E, and 4F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Diagram 5] 5A, 5B, 5C, 5D, 5E, and 5F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 8]FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] 9A, 9B, and 9C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 10] 10A and 10B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 11] 11A and 11B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 12] 12A and 12B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 13] 13A, 13B, and 13C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 14] 14A, 14B, and 14C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 15] 15A, 15B, and 15C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 16] 16A and 16B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 18] 18A, 18B, 18C, and 18D are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 19] FIG. 19 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 20] 20A and 20B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 22] 22A, 22B, and 22C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 23] 23A, 23B, and 23C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 24] 24A and 24B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Diagram 25] 25A and 25B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 26] 26A and 26B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 27] 27A and 27B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 28] FIG. 28 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 29] FIG. 29 is a cross-sectional view showing a configuration example of a semiconductor device. [Diagram 30] 30A, 30B, and 30C are cross-sectional views showing examples of the structure of a transistor. [Diagram 31] 31A, 31B, and 31C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 32] 32A, 32B, and 32C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 33] 33A, 33B, and 33C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 34] 34A, 34B, and 34C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 35] 35A, 35B, and 35C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 36] 36A and 36B are a top view and a perspective view illustrating an example of a structure of a transistor. [Figure 37] 37A and 37B are cross-sectional views showing examples of the structure of a transistor. [Figure 38] 38A, 38B, and 38C are a top view and a perspective view showing a structural example of a capacitive element. [Figure 39] 39A, 39B, and 39C are a top view and a perspective view showing a structural example of a capacitive element. [Diagram 40]40A, 40B, 40C, and 40D are perspective views showing examples of a semiconductor wafer and an electronic component. [Diagram 41] FIG. 41 is a perspective view showing an example of an electronic device. [Diagram 42] FIG. 42A is a front view showing an example of an electronic device, and FIGS. 42B and 42C are perspective views showing examples of the electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] In an artificial neural network (hereafter referred to as a neural network), the strength of synapses can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining the strength of connections is sometimes called "learning."

[0046] In addition, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), it is possible for the network to output new information based on the connection strengths. In this way, the process of outputting new information based on given information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0047] Examples of neural network models include the Hopfield type and hierarchical type. In particular, a neural network with a multi-layer structure is sometimes called a "deep neural network" (DNN), and machine learning using a deep neural network is sometimes called "deep learning."

[0048] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be called an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be called a metal oxide semiconductor. In addition, when an OS FET or an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0049] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0050] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0051] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0052] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0053] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0054] The embodiments described in this specification are described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in perspective views, etc., the description of some components may be omitted in order to ensure the clarity of the drawings.

[0055] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, "[n]”, "[m,n]”, etc. may be added to the symbol.

[0056] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0057] (Embodiment 1) In this embodiment, an arithmetic circuit that performs arithmetic operations of a neural network, which is a semiconductor device of one embodiment of the present invention, will be described.

[0058] <Hierarchical neural network> First, a hierarchical neural network will be described. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. FIG. 1A shows an example of a hierarchical neural network 100, which has a first layer to an Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. FIG. 1A shows the (k-1)th layer and the kth layer (where k is an integer of 3 or more and R-1 or less) as intermediate layers, and does not show the other intermediate layers.

[0059] Each layer of the neural network 100 has one or more neurons. In FIG. 1A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer equal to or greater than 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0060] In addition, in Figure 1A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R)In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0061] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output to and from each neuron. j (k) We are focusing on:

[0062] Figure 1B shows the kth layer of neurons N j (k) and neuron N j (k) The input signal to neuron N j (k) 4 shows a signal output from the

[0063] Specifically, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) The output signals of each (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0064] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse that connects those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient before being input to a neuron in the next layer. If i is an integer between 1 and m, then the (k-1)th layer neuron N i (k-1) and the kth layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the kth layer neuron N j (k) The signal input to can be expressed by equation (1.1).

[0065]

number

[0066] That is, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) For w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1)At this time, the kth layer neuron N j (k) The sum of the signals input to j (k) becomes equation (1.2).

[0067]

number

[0068] Neuron N j (k) u j (k) Depending on j (k) Here, neuron N j (k) Output signal z from j (k) is defined as follows:

[0069]

number

[0070] The function f(u j (k) ) is an activation function in a hierarchical neural network, and can be a step function, a linear ramp function, a sigmoid function, etc. The activation function can be the same for all neurons or different. In addition, the activation functions of neurons can be the same or different for each layer.

[0071] Incidentally, the signals output by the neurons in each layer may be analog values ​​or digital values. The digital values ​​may be, for example, binary or ternary. In the case of analog values, for example, a linear ramp function or a sigmoid function may be used as the activation function. In the case of binary digital values, for example, a step function whose output is -1 or 1, or 0 or 1 may be used. Furthermore, the signals output by the neurons in each layer may be ternary or more, in which case, for example, a step function whose output is -1, 0, or 1, or a step function whose output is 0, 1, or 2 may be used as the activation function.

[0072] In neural network 100, an input signal is input to the first layer (input layer), and each layer from the first layer (input layer) to the last layer (output layer) generates an output signal based on the signal input from the previous layer using formulas (1.1) to (1.3) and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0073] <Example of arithmetic circuit configuration> Here, an example of a calculation circuit capable of performing the calculations of formula (1.2) and formula (1.3) in the above-mentioned neural network 100 will be described. In the calculation circuit, as an example, the weight coefficient of the synapse circuit of the neural network 100 is set to a binary value (a combination of "-1" and "+1", or a combination of "0" and "+1", etc.) or a ternary value (a combination of "-1", "0", "1", etc.), and the activation function of the neuron is set to a function that outputs a binary value (a combination of "-1" and "+1", or a combination of "0" and "+1", etc.) or a ternary value (a combination of "-1", "0", "1", etc.). In addition, in this specification, one of the weight coefficient and the value of the signal input from the neuron of the previous layer to the neuron of the next layer (sometimes referred to as a calculation value) is referred to as first data, and the other is referred to as second data.

[0074] 2 is a semiconductor device having an array part ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 110 is a neuron N1 in the kth layer in FIG. 1A and FIG. 1B. (k) Neuron N n (k) The signal z1 input to (k-1) ~z m (k-1) and neuron N1 (k) Neuron N n (k) The signal z1 output from each (k) ~z n (k) This is a circuit that generates the following:

[0075] The entire arithmetic circuit 110 or a part thereof may be used for purposes other than neural networks and AI. For example, when performing multiply-and-accumulate processing or matrix processing in calculations for graphics or scientific calculations, the entire arithmetic circuit 110 or a part thereof may be used for the processing. In other words, the entire arithmetic circuit 110 or a part thereof may be used not only for AI calculations but also for general calculations.

[0076] For example, the circuit ILD is electrically connected to wirings IL[1] to IL[n] and wirings ILB[1] to ILB[n]. For example, the circuit WLD is electrically connected to wirings WLS[1] to WLS[m]. For example, the circuit XLD is electrically connected to wirings XLS[1] to XLS[m]. For example, the circuit AFP is electrically connected to wirings OL[1] to OL[n] and wirings OLB[1] to OLB[n].

[0077] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. For example, the circuits MP are arranged in a matrix of m rows and n columns in the array unit ALP. In addition, in FIG. 2, the circuit MP located in the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) is represented as the circuit MP[i,j]. However, in FIG. 2, only the circuit MP[1,1], the circuit MP[m,1], the circuit MP[i,j], the circuit MP[1,n], and the circuit MP[m,n] are illustrated, and the other circuits MPC are omitted from the illustration.

[0078] As an example, the circuit MP[i,j] is electrically connected to a wiring IL[j], a wiring ILB[j], a wiring WLS[i], a wiring XLS[i], a wiring OL[j], and a wiring OLB[j].

[0079] A circuit MP[i,j] is, for example, a network of neurons N i (k-1) and neuron N j (k) Specifically, the circuit MP[i,j] holds information (such as a potential, a resistance value, or a current value) corresponding to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j]. The circuit MP[i,j] also holds information corresponding to the first data (weighting coefficient) input from the neuron N i (k-1) The signal z output from i (k-1) (sometimes called the other of the first data and the second data. Here, called the second data) and the first data. As a specific example, the circuit MP[i,j] receives the second data z i (k-1)By inputting the first data and the second data, information (e.g., a current, a voltage, etc.) according to the product of the first data and the second data, or information (e.g., a current, a voltage, etc.) related to the product of the first data and the second data is output to the wiring OL[j] and the wiring OLB[j]. Note that, although an example in which the wiring IL[j] and the wiring ILB[j] are arranged has been shown, one embodiment of the present invention is not limited to this. Only one of the wiring IL[j] and the wiring ILB[j] may be arranged. Note that, although an example in which the wiring OL[j] and the wiring OLB[j] are arranged has been shown, one embodiment of the present invention is not limited to this. Only one of the wiring OL[j] and the wiring OLB[j] may be arranged.

[0080] <<Circuit ILD>> For example, the circuit ILD transmits first data w1, which is a weighting coefficient, to each of the circuits MP[1,1] to MP[m,n] via the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n]. (k-1) 1 (k) Or even w m (k-1) n (k) As a specific example, the circuit ILD has a function of inputting information (e.g., potential, resistance value, current value, etc.) corresponding to the circuit MP[i,j]. i (k-1) j (k) Information corresponding to the above (for example, a potential, a resistance value, or a current value) is supplied via the wiring IL[j] and the wiring ILB[j].

[0081] <<Circuit WLD>> For example, the circuit WLD has a function of selecting a circuit MP to which information (e.g., potential, resistance, current, etc.) corresponding to the first data input from the circuit ILD is to be written. For example, when writing information (e.g., potential, resistance, current, etc.) to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array portion ALP, the circuit WLD may supply a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] to the wiring WLS[i], and may supply a potential for turning off the write switching elements included in the circuits MP other than the i-th row to the wiring WLS. Note that although an example in which the wiring WLS[i] is provided has been shown, one embodiment of the present invention is not limited thereto. For example, the wiring WLS[i] may be provided as a plurality of wirings.

[0082] <<Circuit XLD>> For example, the circuit XLD is connected to the neuron N1 (k-1) Neuron N m (k) The second data z1 corresponds to the calculated value output from (k-1) ~z m (k-1) Specifically, the circuit XLD provides the neurons N i (k-1) The second data z output from i (k-1) Information (for example, a potential, a current value, and the like) corresponding to the wiring XLS[i] is supplied by the wiring XLS[i]. Note that although the example in which the wiring XLS[i] is disposed is shown, one embodiment of the present invention is not limited to this. For example, the wiring XLS[i] may be disposed as a plurality of wirings.

[0083] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. For example, the circuit ACTF[j] is electrically connected to each of the wirings OL[j] and OLB[j]. For example, the circuit ACTF[j] generates a signal according to the respective pieces of information (e.g., potential, current value, etc.) input from the wirings OL[j] and OLB[j]. For example, the circuit ACTF[j] compares the respective pieces of information (e.g., potential, current value, etc.) input from the wirings OL[j] and OLB[j], and generates a signal according to the comparison result. The signal is input to the neuron N j (k) The signal z output from j (k) That is, the circuits ACTF[1] to ACTF[n] function as, for example, circuits that perform the calculation of the activation function of the neural network described above. However, one embodiment of the present invention is not limited to this. For example, the circuits ACTF[1] to ACTF[n] may have a function of converting an analog signal into a digital signal. Alternatively, the circuits ACTF[1] to ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting an output impedance. Note that, although an example in which the circuit ACTF is provided has been shown, one embodiment of the present invention is not limited to this. The circuit ACTF may not be provided.

[0084] The circuits ACTF[1] to ACTF[n] may have a circuit configuration shown in FIG. 3A, for example. FIG. 3A shows an example in which a signal z j (k) Specifically, FIG. 3A shows a circuit that generates an output signal z j (k) 4 shows an example of an activation function calculation circuit that outputs

[0085] In FIG. 3A, the circuit ACTF[j] has a resistor RE, a resistor REB, and a comparator CMP. The resistor RE and the resistor REB have a function of converting a current into a voltage. Therefore, as long as the resistor or circuit has a function of converting a current into a voltage, it is not limited to a resistor. The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the second input terminal of the comparator CMP. In addition, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor RE and the second terminal of the resistor REB may be connected to the same wiring. Or, they may be connected to different wirings having the same potential.

[0086] It is preferable that the resistance values ​​of the resistor element RE and the resistor element REB are equal to each other. For example, it is preferable that the difference between the resistance values ​​of the resistor element RE and the resistor element REB is within 10%, more preferably within 5%. However, one aspect of the present invention is not limited to this. In some cases or depending on the situation, the resistance values ​​of the resistor element RE and the resistor element REB may be different from each other.

[0087] As an example, the wiring VAL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential VDD, a low-level potential VSS, a ground potential (GND), or the like. It is preferable that the constant voltage is appropriately set according to the configuration of the circuit MP. For example, a pulse signal may be supplied to the wiring VAL instead of a constant voltage.

[0088] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMP. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the second input terminal of the comparator CMP.

[0089] As an example, the comparator CMP has a function of comparing the voltages input to the first input terminal and the second input terminal, and outputting a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP can output a high-level potential from the output terminal of the comparator CMP when the voltage input to the second input terminal is higher than the voltage input to the first input terminal, and can output a low-level potential from the output terminal of the comparator CMP when the voltage input to the first input terminal is higher than the voltage input to the second input terminal. In other words, the potentials output from the output terminal of the comparator CMP are two, a high-level potential and a low-level potential, so that the output signal z output by the circuit ACTF[j] j (k) For example, the high level potential and the low level potential output from the output terminal of the comparator CMP are expressed as the output signal z j (k) In some cases, the high level potential and the low level potential output from the output terminal of the comparator CMP correspond to the output signal z j (k) may correspond to "+1" and "0".

[0090] Although the circuit ACTF[j] in FIG. 3A uses the resistor elements RE and REB, any element or circuit having a function of converting a current into a voltage may be used, and is not limited to resistor elements. Therefore, the resistor elements RE and REB in the circuit ACTF[j] in FIG. 3A can be replaced with other circuit elements. For example, the circuit ACTF[j] shown in FIG. 3B is a circuit in which the resistor elements RE and REB included in the circuit ACTF[j] in FIG. 3A are replaced with capacitor elements CE and CEB, and can perform substantially the same operation as the circuit ACTF[j] in FIG. 3A. Note that the capacitance values ​​of the capacitor elements CE and CEB are preferably equal to each other. For example, it is desirable that the difference between the capacitance values ​​of the capacitor elements CE and CEB is within 10%, more preferably within 5%. However, one embodiment of the present invention is not limited thereto. Note that a circuit for initializing charges stored in the capacitor elements CE and CEB may be provided. For example, a switch may be provided in parallel with the capacitor element CE. That is, the second terminal of the switch may be connected to the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitance element CE, the wiring OL[j], and the first input terminal of the comparator CMP. Alternatively, the second terminal of the switch may be connected to a wiring different from the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitance element CE, the wiring OL[j], and the first input terminal of the comparator CMP. In addition, the circuit ACTF[j] shown in FIG. 3C is a circuit in which the resistance elements RE and REB included in the circuit ACTF[j] of FIG. 3A are replaced with diode elements DE and DEB, and can perform substantially the same operation as the circuit ACTF[j] of FIG. 3A. It is desirable to appropriately change the orientation (anode and cathode connection points) of the diode elements DE and DEB depending on the magnitude of the potential of the wiring VAL.

[0091] Also, the comparator CMP included in the circuit ACTF[j] in Figures 3A to 3C can be replaced with an operational amplifier OP, for example. The circuit ACTF[j] shown in Figure 3D shows a circuit diagram in which the comparator CMP of the circuit ACTF[j] in Figure 3A is replaced with an operational amplifier OP.

[0092] Also, the circuit ACTF[j] of FIG. 3B may be provided with switches S01a and S01b. This allows the circuit ACTF[j] to hold potentials corresponding to the currents input from the wiring OL[j] and wiring OLB[j] to the capacitance elements CE and CEB, respectively. As an example of a specific circuit, as shown in FIG. 3E, the wiring OL[j] is electrically connected to the first terminal of the switch S01a, the first terminal of the capacitance element CE and the first input terminal of the comparator CMP are electrically connected to the second terminal of the switch S01a, the wiring OLB[j] is electrically connected to the first terminal of the switch S01b, and the first terminal of the capacitance element CEB and the second input terminal of the comparator CMP are electrically connected to the second terminal of the switch S01b. In the circuit ACTF[j] of FIG. 3E, when the potentials of the wiring OL[j] and wiring OLB[j] are input to the first and second input terminals of the comparator CMP, respectively, this can be done by turning on the switches S01a and S01b. Then, by turning off the switches S01a and S01b, the potentials input to the first and second input terminals of the comparator CMP can be held in the capacitors CE and CEB. The switches S01a and S01b can be, for example, electrical switches such as analog switches and transistors. The switches S01a and S01b can be, for example, mechanical switches. When transistors are used as the switches S01a and S01b, the transistors can be OS transistors or transistors having silicon in a channel formation region (hereinafter, referred to as Si transistors). Alternatively, the voltage values ​​of the capacitors CE and CEB can be controlled by controlling the period during which the switches S01a and S01b are kept on. For example, when the current value flowing through the capacitance elements CE and CEB is large, the period during which the switches S01a and S01b are kept on can be shortened to prevent the voltage values ​​of the capacitance elements CE and CEB from becoming too large.

[0093] 3A to 3C and 3E, the comparator CMP included in the circuit ACTF[j] may be, for example, a chopper type comparator. The comparator CMP shown in FIG. 3F is a chopper type comparator, and the comparator CMP has switches S02a, S02b, and S03, a capacitance element CC, and an inverter circuit INV3. The switches S02a, S02b, and S03 may be mechanical switches, OS transistors, Si transistors, or other transistors, similar to the above-mentioned switches S01a and S01b.

[0094] A first terminal of the switch S02a is electrically connected to the terminal VinT, a first terminal of the switch S02b is electrically connected to the terminal VrefT, and a second terminal of the switch S02a is electrically connected to the second terminal of the switch S02b and the first terminal of the capacitance element CC. The second terminal of the capacitance element CC is electrically connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3 and the second terminal of the switch S03.

[0095] The terminal VinT functions as a terminal for inputting an input potential to the comparator CMP, the terminal VrefT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal VoutT functions as a terminal for outputting an output potential from the comparator CMP. The terminal VinT can correspond to one of the first terminal or the second terminal of the comparator CMP in Figures 3A to 3C and 3E, and the terminal VrefT can correspond to the other of the first terminal or the second terminal of the comparator CMP in Figures 3A to 3C and 3E.

[0096] The circuit ACTF[j] of FIG. 3A to FIG. 3E outputs an output signal z j (k) The activation function ACTF[j] outputs the output signal z j (k) Alternatively, the signal may be output as three or more values ​​or as an analog value.

[0097] 4A to 4F show a signal z in response to a current input from the wiring OL[j] and the wiring OLB[j]. j (k) is a circuit that generates an output signal z represented by a ternary value. j (k) 4 shows an example of an activation function calculation circuit that outputs

[0098] The circuit ACTF[j] shown in FIG. 4A includes a resistor RE, a resistor REB, a comparator CMPa, and a comparator CMPb. The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMPa, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the first input terminal of the comparator CMPb. In addition, the second input terminal of the comparator CMPa and the second input terminal of the comparator CMPb are electrically connected to the wiring VrefL. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0099] The wire VrefL is a constant voltage V ref It acts as a wiring that provides V ref It is preferable that V is, for example, equal to or higher than GND and equal to or lower than VDD. ref V may be at a potential lower than GND or higher than VDD. ref is treated as a reference potential (potential for comparison) in comparators CMPa and CMPb.

[0100] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMPa. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the first input terminal of the comparator CMPb.

[0101] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal, and outputs a signal from the output terminal of the comparator CMPa according to the comparison result. For example, the comparator CMPa detects that the voltage input to the second input terminal (V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPa, and the voltage (V ref ) the voltage input to the first input terminal is higher than the low level potential, a low level potential can be output from the output terminal of the comparator CMPa.

[0102] Similar to the comparator CMPa, the comparator CMPb compares the voltages input to the first input terminal and the second input terminal, and outputs a signal from the output terminal of the comparator CMPb according to the comparison result. For example, the comparator CMPb detects that the voltage input to the second input terminal (V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPb, and the voltage (V ref ) is higher than the voltage input to the first input terminal, a low-level potential can be output from the output terminal of the comparator CMPb.

[0103] At this time, a ternary output signal z j (k) For example, when a high-level potential is output from the output terminal of the comparator CMPa and a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) is set to "+1", and when a low level potential is output from the output terminal of the comparator CMPa and a high level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) is set to "-1", and when a low level potential is output from the output terminal of the comparator CMPa and a low level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) can be set to "+0".

[0104] Moreover, the circuit ACTF[j] is not limited to the circuit configuration shown in FIG. 4A, and can be modified according to circumstances. For example, in the circuit ACTF[j] of FIG. 4A, if it is desired to combine the two output results of the comparators CMPa and CMPb into one signal, a conversion circuit TRF can be provided in the circuit ACTF[j]. The circuit ACTF[j] of FIG. 4B is a configuration example in which a conversion circuit TRF is provided in the circuit ACTF[j] of FIG. 4A, and the output terminals of the comparators CMPa and CMPb are electrically connected to the input terminals of the conversion circuit TRF. A specific example of the conversion circuit TRF is a digital-to-analog conversion circuit (in this case, a signal z j (k) is an analog value.)

[0105] Also, for example, in Fig. 4A, the wiring VrefL electrically connected to the second input terminals of the comparators CMPa and CMPb may be replaced with separate wirings Vref1L and Vref2L. The circuit ACTF[j] in Fig. 4C has a configuration in which the second terminal of the comparator CMPa included in the circuit ACTF[j] in Fig. 4A is electrically connected to the wiring Vref1L instead of the wiring VrefL, and the second terminal of the comparator CMPb is electrically connected to the wiring Vref2L instead of the wiring VrefL. By setting the potentials input to the wirings Vref1L and Vref2L to different values, the reference potentials in the comparators CMPa and CMPb can be set separately.

[0106] Also, for example, an amplifier circuit or an impedance conversion circuit may be used as a configuration different from the circuit ACTF[j] of Figures 4A to 4C. For example, the circuit ACTF[j] shown in Figure 4D can be applied to the circuit AFP of the arithmetic circuit 110 of Figure 2. The circuit ACTF[j] of Figure 4D has a resistor RE, a resistor REB, an operational amplifier OPa, and an operational amplifier OPb, and functions as an amplifier circuit.

[0107] The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the non-inverting input terminal of the operational amplifier OPb. The inverting input terminal of the operational amplifier OPa is electrically connected to the output terminal of the operational amplifier OPa, and the inverting input terminal of the operational amplifier OPb is electrically connected to the output terminal of the operational amplifier OPb. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0108] In other words, the operational amplifiers OPa and OPb included in the circuit ACTF[j] in Fig. 4D are connected as voltage followers. As a result, the potential output from the output terminal of the operational amplifier OPa is approximately equal to the potential input to the non-inverting input terminal of the operational amplifier OPa, and the potential output from the output terminal of the operational amplifier OPb is approximately equal to the potential input to the non-inverting input terminal of the operational amplifier OPb. In this case, the output signal z j (k) are output from the circuit ACTF[j] as two analog values. The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminals of the comparator CMP. The output from the comparator CMP is then used as the output signal z j (k) It is also possible to use the following.

[0109] Also, for example, an integrating circuit, a current-voltage conversion circuit, etc. may be used as a configuration different from the circuit ACTF[j] of Figures 4A to 4D. Furthermore, an integrating circuit, a current-voltage conversion circuit, etc. may be configured using an operational amplifier. As an example, the circuit ACTF[j] shown in Figure 4E can be applied to the circuit AFP of the arithmetic circuit 110 of Figure 2. The circuit ACTF[j] of Figure 4E has an operational amplifier OPa, an operational amplifier OPb, a load element LEa, and a load element LEb.

[0110] The wiring OL[j] is electrically connected to a first input terminal (e.g., inverting input terminal) of the operational amplifier OPa and a first terminal of the load element LEa, and the wiring OLB[j] is electrically connected to a first input terminal (e.g., inverting input terminal) of the operational amplifier OPb and a first terminal of the load element LEb. In addition, the second input terminal (e.g., non-inverting input terminal) of the operational amplifier OPa is electrically connected to the wiring Vref1L, and the second input terminal (e.g., non-inverting input terminal) of the operational amplifier OPb is electrically connected to the wiring Vref2L. The second terminal of the load element LEa is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load element LEa is electrically connected to the output terminal of the operational amplifier OPb.

[0111] In addition, the wiring Vref1L and the wiring Vref2L function as wirings that supply voltages equal to or different from each other. Therefore, the wiring Vref1L and the wiring Vref2L can be integrated into one wiring.

[0112] In the circuit ACTF[j] of FIG. 4E, the load elements LEa and LEb can be, for example, resistive elements and capacitive elements. In particular, by using capacitive elements as the load elements LEa and LEb, the operational amplifier OPa and the load element LEa, and the operational amplifier OPb and the load element LEb each function as an integrating circuit. That is, a charge is stored in each of the capacitive elements (load elements LEa, LEb) according to the amount of current flowing through the wiring OL[j] or wiring OLB[j]. That is, the current flowing from the wiring OL[j] and wiring OLB[j] is integrated by the integrating circuit, and the amount of current is converted into a voltage, which is output as a signal z j (k) The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminals of the comparator CMP. Then, the output from the comparator CMP is output as the output signal z j (k)A circuit for initializing the charges stored in the capacitive elements of the load elements LEa and LEb may be provided. For example, a switch may be provided in parallel with the load element LEa (capacitive element). That is, a second terminal of the switch may be connected to the output terminal of the operational amplifier OPa, and a first terminal of the switch may be connected to the wiring OL[j] and a first input terminal (for example, an inverting input terminal) of the operational amplifier OPa.

[0113] In addition, in the circuit ACTF[j] of Figure 4E, if you want to convert the current flowing from the wiring OL[j] and wiring OLB[j] into a voltage and output it, the load elements LEa and LEb can be resistive elements other than capacitive elements.

[0114] Also, for example, as a configuration different from the circuit ACTF[j] of Figures 4A to 4E, a circuit ACTF[j] shown in Figure 4F can be applied to the circuit AFP of the arithmetic circuit 110 of Figure 2. The circuit ACTF[j] of Figure 4F has a resistive element RE, a resistive element REB, an analog-digital conversion circuit ADCa, and an analog-digital conversion circuit ADCb.

[0115] The wiring OL[j] is electrically connected to the input terminal of the analog-digital conversion circuit ADCa and the first terminal of the resistor RE, and the wiring OLB[j] is electrically connected to the input terminal of the analog-digital conversion circuit ADCb and the first terminal of the resistor REB. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0116] In the circuit ACTF[j] of FIG. 4F, the potentials of the first terminals of the resistor elements RE and REB are determined according to the currents flowing from the wiring OL[j] and wiring OLB[j]. The circuit ACTF[j] then converts the analog potentials into digital values ​​of two or more values ​​(e.g., 256 values) using the analog-to-digital conversion circuits ADCa and ADCb, and outputs the signal z j (k) It has the function of outputting as

[0117] 4A to 4F can be replaced with the capacitance elements CE and CEB, or the diode elements DE and DEB, as in the case of Fig. 3B and Fig. 3C. In particular, when the resistance elements RE and REB shown in Fig. 4A to 4F are replaced with the capacitance elements CE and CEB, the potential input from the wiring OL[j] and wiring OLB[j] can be held by providing the switches S01a and S01b as in the case of Fig. 3E.

[0118] 2, the number of wirings electrically connected to the circuit MP[i,j] can be changed depending on the circuit configuration of the circuit MP[i,j]. For example, in the arithmetic circuit 110 in FIG. 2, the wiring WLS[i] electrically connected to the circuit MP[i,j] can be one or more wirings. Also, for example, the wiring XLS[i] electrically connected to the circuit MP[i,j] can be one or more wirings.

[0119] <<Circuit MP>> Next, a configuration example of the circuit MP[i,j] included in the arithmetic circuit 110 will be described.

[0120] FIG. 5A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 110, and the circuit MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MC and the circuit MCr are circuits that calculate the product of a weighting coefficient and an input signal (operation value) of a neuron in the circuit MP. The circuit MC can have the same configuration as the circuit MCr, or a different configuration from the circuit MCr. Therefore, the circuit MCr is given the symbol "r" to distinguish it from the circuit MC. In addition, the symbols of the circuit elements included in the circuit MCr, which will be described later, are also given the symbol "r".

[0121] For example, the circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each have a function of holding information (for example, potential, resistance value, current value, etc.). Note that the first data w i (k-1) j (k) is determined according to the information (e.g., potential, resistance value, current value, etc.) held in each of the holding units HC and HCr. i (k-1) j (k) The wiring IL[j] and the wiring ILB[j] are electrically connected to each other and supply information (for example, a potential, a resistance value, a current value, or the like) according to the input signal.

[0122] The wiring WL[i] shown in FIG. 5A corresponds to the wiring WLS[i] in FIG. 2. The wiring WL[i] is electrically connected to each of the holding units HC and the holding unit HCr. The first data w i (k-1) j (k) When writing information (for example, a potential, a resistance value, a current value, etc.) according to the first data w, a predetermined potential is supplied to the wiring WL[i], thereby bringing the wiring IL[j] and the holding unit HC into a conductive state, and bringing the wiring ILB[j] and the holding unit HCr into a conductive state. i (k-1) j (k) By supplying a potential corresponding to the data w, the potential can be input to each of the holding units HC and HCr. After that, a predetermined potential is supplied to the wiring WL[i] to put the wiring IL[j] and the holding unit HC in a non-conductive state, and also put the wiring ILB[j] and the holding unit HCr in a non-conductive state. Then, the first data w is input to each of the holding units HC and HCr. i (k-1) j (k) Each potential according to the above is maintained.

[0123] For example, the first data i (k-1) j (k) Consider the case where the first data w can take one of the three values ​​"-1", "0", or "1". i (k-1) j (k) When the first data w is "1", for example, the holding unit HC holds a high level potential and the holding unit HCr holds a low level potential. i (k-1) j (k) When the first data w is "-1", for example, the holding unit HC holds a low level potential and the holding unit HCr holds a high level potential. i (k-1) j (k) When the first data w is "0", as an example, a low level potential is held in the holding unit HC, and a low level potential is held in the holding unit HCr. i (k-1) j (k) Let us consider the case where the first data w is an analog value, specifically, a "negative analog value", "0", or a "positive analog value". i (k-1) j (k) When the first data w is a "positive analog value", for example, a high-level analog potential is held in the holding unit HC, and a low-level potential is held in the holding unit HCr. i (k-1) j (k) When the first data w is a "negative analog value", for example, a low level potential is held in the holding unit HC, and a high level analog potential is held in the holding unit HCr. i (k-1) j (k) When the first data w is "0", for example, a low level potential is held in the holding unit HC, and a low level potential is held in the holding unit HCr. Note that the analog value may be a multi-bit (multi-value) digital value. That is, for example, the first data wi (k-1) j (k) is "1", "2", or "3", for example, the holding unit HC holds a high-level potential having a potential corresponding to "1", "2", or "3", and the holding unit HCr holds a low-level potential. i (k-1) j (k) When the first data w is "-1", "-2", or "-3", for example, the holding unit HC holds a low level potential, and the holding unit HCr holds a high level potential corresponding to the absolute values ​​of "-1", "-2", or "-3", that is, "1", "2", or "3". i (k-1) j (k) When is "0", as an example, a low level potential is held in the holding unit HC, and a low level potential is held in the holding unit HCr.

[0124] As an example, the circuit MC has a function of outputting a current, a voltage, etc., corresponding to the information (e.g., potential, resistance value, current value, etc.) held in the holding unit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current, a voltage, etc., corresponding to the information (e.g., potential, resistance value, current value, etc.) held in the holding unit HCr to the other of the wiring OL[j] or the wiring OLB[j]. For example, when a high-level potential is held in the holding unit HC, the circuit MC outputs a current having a first current value, and when a low-level potential is held in the holding unit HC, the circuit MC outputs a current having a second current value. Similarly, when a high-level potential is held in the holding unit HCr, the circuit MCr outputs a current having a first current value, and when a low-level potential is held in the holding unit HCr, the circuit MCr outputs a current having a second current value. The magnitudes of the first current value and the second current value depend on the configurations of the circuit MC, the circuit MCr, the holding unit HC, the holding unit HCr, etc., and the first data w i (k-1) j (k)For example, the first current value may be greater than or less than the second current value. Furthermore, one of the first current value and the second current value may be zero current, i.e., the current value is 0. Alternatively, the current having the first current value and the current having the second current value may flow in different directions. In particular, for example, when the first data w i (k-1) j (k) When the first data w takes one of the three values ​​of "-1", "0", and "1", it is preferable to configure the circuit MC and the circuit MCr so that either the first current value or the second current value is 0. i (k-1) j (k) takes an analog value, for example, a “negative analog value”, “0”, or a “positive analog value”, the first current value or the second current value can also take an analog value, for example.

[0125] In this specification, the current, voltage, etc. corresponding to the information (e.g., potential, resistance value, current value, etc.) stored in the holding unit HC and the holding unit HCr may be a positive current, voltage, etc., a negative current, voltage, etc., or a mixture of both positive and negative. In other words, for example, the above description "has a function of outputting a current, voltage, etc. corresponding to the information (e.g., potential, resistance value, current value, etc.) held in the holding unit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current, voltage, etc. corresponding to the information (e.g., potential, resistance value, current value, etc.) held in the holding unit HCr to the other of the wiring OL[j] or the wiring OLB[j]" can be rephrased as "has a function of discharging a current, voltage, etc. corresponding to the information (e.g., potential, resistance value, current value, etc.) held in the holding unit HC from one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of discharging a current corresponding to the potential held in the holding unit HCr from the other of the wiring OL[j] or the wiring OLB[j]."

[0126] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 5A correspond to the wiring XLS[i] in FIG. 2. Note that the second data z i (k-1) For example, the second data z i (k-1) Each potential according to the above is input.

[0127] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j], and the circuit MCr is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MC and the circuit MCr transmit the first data w i (k-1) j (k) and the second data z i (k-1) A current, potential, etc. according to the product of and is output. As a specific example, the output destination of the current from the circuits MC and MCr is determined by the potential of the wiring X1L[i] and the wiring X2L[i]. For example, each of the circuits MC and MCr is configured such that the current output from the circuit MC flows to one of the wiring OL[j] or the wiring OLB[j], and the current output from the circuit MCr flows to the other of the wiring OL[j] or the wiring OLB[j]. In other words, the currents output from the circuits MC and MCr do not flow to the same wiring, but to different wirings. Note that, as an example, there are cases where the current does not flow from the circuits MC and MCr to either the wiring OL[j] or the wiring OLB[j].

[0128] For example, the second data z i (k-1) Consider the case where the second data z can take one of the three values ​​"-1", "0", or "1". i (k-1)When the second data z i (k-1) When the second data z i (k-1) When is "0", in order to prevent the currents output by the circuits MC and MCr from flowing through either the wiring OL[j] or the wiring OLB[j], the circuit MP brings the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] into a non-conductive state.

[0129] Here is an example of the above operations. i (k-1) j (k) When the value is "1", the circuit MC outputs a current, and the first data w i (k-1) j (k) If the second data z i (k-1) When the second data z is “1”, the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] are in a conductive state. i (k-1) When the first data w is "-1", the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] are in a conductive state. i (k-1) j (k) and the second data z i (k-1) If the product of the first data w is a positive value, a current is output to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1)If the product of the first data w is a negative value, a current is output to the wiring OLB[j]. i (k-1) j (k) and the second data z i (k-1) If the product has a value of zero, no current will be output in either wire.

[0130] To take the above example as a specific example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i,j] having a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MCr to the wiring OLB[j]. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OL[j]. i (k-1) j (k) is "0", and the second data z i (k-1) is "1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OL[j], and no current flows from the circuit MCr to the wiring OLB[j].

[0131] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "-1", a current I1[i,j] having a first current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) is "-1", and the second data z i (k-1) is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OLB[j]. i (k-1) j (k) is "0", and the second data z i (k-1) is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OLB[j], and no current flows from the circuit MCr to the wiring OL[j].

[0132] In addition, the second data z i (k-1) When the first data w is "0", for example, the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly, the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Therefore, the first data w i (k-1)j (k) Whatever the value of is, no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0133] Thus, as an example, the first data w i (k-1) j (k) and the second data z i (k-1) When the product of w and is a positive value, a current flows through the wiring OL[j] from either the circuit MC or the circuit MCr. i (k-1) j (k) When the value is positive, a current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the first data w is a negative value, a current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) When the product of w and is a negative value, a current flows through the wiring OLB[j] from either the circuit MC or the circuit MCr. i (k-1) j (k) When the value is positive, a current flows from the circuit MC to the wiring OLB[j], and the first data w i (k-1) j (k)When is a negative value, a current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from the multiple circuits MC or the circuit MCr connected to the wiring OL[j] flows to the wiring OL[j]. That is, a current having a value obtained by summing up the positive values ​​flows in the wiring OL[j]. On the other hand, the sum of the currents output from the multiple circuits MC or the circuit MCr connected to the wiring OLB[j] flows to the wiring OLB[j]. That is, a current having a value obtained by summing up the negative values ​​flows in the wiring OLB[j]. As a result of the above operation, the total current value flowing in the wiring OL[j], that is, the sum of the positive values, and the total current value flowing in the wiring OLB[j], that is, the sum of the negative values, are used to perform a product-sum operation. For example, when the total current value flowing in the wiring OL[j] is greater than the total current value flowing in the wiring OLB[j], it can be determined that the product-sum operation results in a positive value. When the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation is a negative value. When the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the product-sum operation is zero.

[0134] In addition, the second data z i (k-1) The same operation can be performed when the first data w is one of two values ​​of "-1", "0", and "1", for example, the two values ​​of "-1" and "1", or the two values ​​of "0" and "1". i (k-1) j (k) The same operation can be performed when the value is any one of the two values ​​"-1", "0", and "1", for example, when the value is "-1" and "1", or when the value is "0" and "1".

[0135] In addition, the first data i (k-1) j (k)may take an analog value or a multi-bit (multiple-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may be, for example, the first data w i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0136] Next, an example of a modification of the circuit MP[i,j] in Fig. 5A will be described. Note that, for the modification of the circuit MP[i,j], the parts different from the circuit MP[i,j] in Fig. 5A will be mainly described, and the parts common to the circuit MP[i,j] in Fig. 5A may be omitted.

[0137] The circuit MP[i,j] shown in Fig. 5B is a modified example of the circuit MP[i,j] in Fig. 5A. The circuit MP[i,j] in Fig. 5B has a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in Fig. 5A. However, the circuit MP[i,j] in Fig. 5B differs from the circuit MP[i,j] in Fig. 5A in that the circuit MCr does not include a holding unit HCr.

[0138] 5B does not need to have a wiring ILB[j] for supplying a potential to be held in the holding unit HCr because the circuit MCr does not need to have a holding unit HCr. In addition, the circuit MCr does not need to be electrically connected to the wiring WL[i].

[0139] In the circuit MP[i,j] of FIG. 5B, the holding unit HC included in the circuit MC is electrically connected to the circuit MCr. That is, the circuit MP[i,j] of FIG. 5B is configured such that the circuit MCr and the circuit MC share the holding unit HC. As an example, an inverted signal of the signal held in the holding unit HC can be supplied from the holding unit HC to the circuit MCr. This allows the circuit MC and the circuit MCr to perform different operations. Alternatively, it is possible to make the internal circuit configurations of the circuit MC and the circuit MCr different, so that the magnitude of the output current of the circuit MC and the circuit MCr is different for the same signal held in the holding unit HC. Here, the first data w i (k-1) j (k) The potential corresponding to the second data z i (k-1) By supplying a potential corresponding to the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0140] Note that the arithmetic circuit 110 to which the circuit MP in Fig. 5B is applied can be changed to a circuit configuration of an arithmetic circuit 120 shown in Fig. 6. The arithmetic circuit 120 has a configuration in which the wirings ILB[1] to ILB[m] are removed from the arithmetic circuit 110 in Fig. 2.

[0141] The circuit MP[i,j] shown in Fig. 5C is a modified example of the circuit MP[i,j] in Fig. 5A, and specifically, is a configuration example of the circuit MP[i,j] that can be applied to the arithmetic circuit 120 in Fig. 6. The circuit MP[i,j] in Fig. 5C has a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in Fig. 5A. However, the circuit MP[i,j] in Fig. 5C and the circuit MP[i,j] in Fig. 5A have different configurations of electrically connected wiring.

[0142] The wiring W1L[i] and the wiring W2L[i] shown in Fig. 5C correspond to the wiring WLS[i] in Fig. 6. The wiring W1L[i] is electrically connected to the holding unit HC, and the wiring W2L[i] is electrically connected to the holding unit HCr.

[0143] Moreover, the wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr.

[0144] In the circuit MP[i,j] of FIG. 5C, when the holding unit HC and the holding unit HCr hold different potentials, it is preferable to hold the potentials in the holding unit HC and the holding unit HCr in sequence, not simultaneously. For example, the first data w i (k-1) j (k) Consider a case where the data can be expressed by holding a first potential in the holding unit HC and a second potential in the holding unit HCr. First, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i] to bring the holding unit HC and the wiring IL[j] into a conductive state, and bring the holding unit HCr and the wiring IL[j] into a non-conductive state. Next, the first potential can be applied to the holding unit HC by supplying the first potential to the wiring IL[j]. After that, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i] to bring the holding unit HC and the wiring IL[j] into a non-conductive state, and bring the holding unit HCr and the wiring IL[j] into a conductive state. Then, the second potential can be applied to the holding unit HCr by supplying the second potential to the wiring IL[j]. As a result, the circuit MP[i,j] stores w as the first data. i (k-1) j (k) can be set.

[0145] In addition, when the holding unit HC and the holding unit HCr hold approximately the same potential (the first data w i (k-1) j (k)is set by holding approximately equal potentials in the holding units HC and HCr, respectively), a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i] so that a conductive state is established between the holding unit HC and the wiring IL[j] and a conductive state is established between the holding unit HCr and the wiring IL[j], and then the potential is supplied to the wiring IL[j].

[0146] The circuit MP[i,j] in FIG. 5C stores the first data w i (k-1) j (k) The potential corresponding to the second data z i (k-1) By supplying a potential corresponding to the first data w to the wiring X1L[i] and the wiring X2L[i], the first data w is supplied to the wiring OL[j] and the wiring OLB[j] in the same manner as in the circuit MP[i,j] of FIG. 5A. i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0147] The circuit MP[i,j] shown in Fig. 5D is a modified example of the circuit MP[i,j] in Fig. 5A. The circuit MP[i,j] in Fig. 5D has a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in Fig. 5A. However, the circuit MP[i,j] in Fig. 5D and the circuit MP[i,j] in Fig. 5A have different configurations of electrically connected wiring.

[0148] The wiring IOL[j] in Fig. 5D functions as a single wiring obtained by combining the wiring IL[j] and wiring OL[j] in Fig. 5A, and the wiring IOLB[j] in Fig. 5D functions as a single wiring obtained by combining the wiring ILB[j] and wiring OLB[j] in Fig. 5A. Therefore, the wiring IOL[j] is electrically connected to the holding unit HC, the circuit MC, and the circuit MCr, and the wiring IOLB[j] is electrically connected to the holding unit HCr, the circuit MC, and the circuit MCr.

[0149] The circuit MP[i,j] in FIG. 5D is provided with the first data w i (k-1) j (k) When holding the first data w, first, a predetermined potential is input to the wiring X1L[i] and the wiring X2L[i] so that the circuit MC and the wiring IOL[j] and the circuit MC and the wiring IOLB[j] are in a non-conductive state, and the circuit MCr and the wiring IOL[j] and the circuit MCr and the wiring IOL[j] are in a non-conductive state. After that, a predetermined potential is input to the wiring WL[i] to bring the holding unit HC and the wiring IOL[j] into a conductive state, and bring the holding unit HCr and the wiring IOLB[j] into a conductive state, and to store the first data w in each of the wiring IOL[j] and the wiring IOLB[j]. i (k-1) j (k) By supplying each potential according to the data w, each potential can be input to the holding unit HC and the holding unit HCr. Then, by inputting a predetermined potential to the wiring WL[i] so that the holding unit HC and the wiring IOL[j] are in a non-conductive state and the holding unit HCr and the wiring IOLB[j] are in a non-conductive state, the first data w is input to each of the holding unit HC and the holding unit HCr. i (k-1) j (k) It is possible to hold each potential according to the

[0150] The first data w is stored in each of the holding unit HC and the holding unit HCr. i (k-1) j (k) After holding the potential according to the second data z i (k-1) By supplying a potential corresponding to the first data w to the wiring X1L[i] and the wiring X2L[i], the first data w is supplied to the wiring OL[j] and the wiring OLB[j] in the same manner as in the circuit MP[i,j] of FIG. 5A. i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0151] Note that the arithmetic circuit 110 to which the circuit MP in FIG. 5D is applied can be changed to a circuit configuration of the arithmetic circuit 130 shown in FIG. 7. The arithmetic circuit 130 has a configuration in which the wirings IL[1] to IL[n] and the wirings OL[1] to OL[n] in the arithmetic circuit 110 in FIG. 2 are grouped together as wirings IOL[1] to IOL[n], and the wirings ILB[1] to ILB[n] and the wirings OLB[1] to OLB[n] are grouped together as wirings IOLB[1] to IOL[n]. In addition, in the arithmetic circuit 130, the wirings IOL[1] to IOL[n] and the wirings IOLB[1] to IOL[n] are electrically connected to the circuit ILD. That is, the wirings IOL[j] and IOLB[j] are used to transmit the first data w i (k-1) j (k) and a current line for supplying current to the circuit ACTF[j]. In this case, the first data w i (k-1) j (k) When transmitting, it is preferable that the circuit ILD brings the circuit ILD and the wiring IOL[j] into a conductive state and the circuit ILD and the wiring IOL[j] into a non-conductive state, and the circuit ACTF[j] brings the circuit ACTF[j] and the wiring IOL[j] into a non-conductive state and the circuit ACTF[i] and the wiring IOL[j] into a non-conductive state. When supplying a current to the circuit ACTF[j], it is preferable that the circuit ILD brings the circuit ILD and the wiring IOL[j] into a non-conductive state and the circuit ACTF[j] and the wiring IOL[j] into a conductive state, and the circuit ACTF[j] brings the circuit ACTF[j] and the wiring IOL[j] into a conductive state and the circuit ACTF[j] and the wiring IOL[j] into a conductive state.

[0152] The circuit MP[i,j] shown in Fig. 5E is a modified example of the circuit MP[i,j] in Fig. 5A, and specifically, is a configuration example of the circuit MP[i,j] that can be applied to the arithmetic circuit 110 in Fig. 2. The circuit MP[i,j] in Fig. 5E includes a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in Fig. 5A. However, the circuit MP[i,j] in Fig. 5E differs from the circuit MP[i,j] in Fig. 5A in that the circuit MC is not electrically connected to the wiring OLB[j] and the circuit MCr is not electrically connected to the wiring OL[j].

[0153] The wiring WL[i] shown in Fig. 5E corresponds to the wiring WLS[i] in Fig. 2. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0154] Moreover, the wiring XL[i] shown in Fig. 5E corresponds to the wiring XLS[i] in Fig. 2. The wiring XL[i] is electrically connected to the circuit MC and the circuit MCr.

[0155] As described above, in the circuit MP[i,j] in Fig. 5E, the circuit MC is not electrically connected to the wiring OLB[j], and the circuit MCr is not electrically connected to the wiring OL[j]. In other words, unlike the circuits MP[i,j] in Fig. 5A to Fig. 5D, the circuit MP[i,j] in Fig. 5E is configured such that the current output from the circuit MC does not flow to the wiring OLB[j], and the current output from the circuit MCr does not flow to the wiring OL[j].

[0156] Therefore, the circuit MP[i,j] of FIG. 5E receives the second data z i (k-1) It is preferable to apply the second data z to the arithmetic circuit when the second data z i (k-1) is “1”, the circuit MP brings the circuit MC and the wiring OL[j] into a conductive state, and brings the circuit MCr and the wiring OLB[j] into a conductive state. i (k-1)When the value is "0", the circuit MP brings the circuit MC and the wiring OL[j] into a non-conductive state and brings the circuit MCr and the wiring OLB[j] into a non-conductive state so that the currents output by the circuits MC and MCr do not flow to either the wiring OL[j] or the wiring OLB[j].

[0157] The circuit MP[i,j] in FIG. 5E is applied to the arithmetic circuit 110 to obtain, for example, the first data w i (k-1) j (k) takes one of the three values ​​"-1", "0", or "1", and the second data z i (k-1) The circuit MP[i,j] in FIG. 5E can perform calculations when the first data w i (k-1) j (k) The first data w can be operated even when it is one of two values ​​of "-1", "0", and "1", for example, when it is two values ​​of "-1" and "1", or when it is two values ​​of "0" and "1". i (k-1) j (k) may take an analog value or a multi-bit (multiple-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may be, for example, the first data w i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0158] The circuit MP[i,j] shown in FIG. 5F is configured such that the first data w i (k-1) j (k) and the second data z i (k-1)5F is a circuit capable of outputting a current according to the product of and The circuit MP[i,j] in FIG.

[0159] The circuit MP[i,j] in FIG. 5F includes a circuit MC, a circuit MCr, and a transistor MZ.

[0160] A first terminal of the transistor MZ is electrically connected to a first terminal of the circuit MC and a first terminal of the circuit MCr. A second terminal of the transistor MZ is electrically connected to the wiring VL. A gate of the transistor MZ is electrically connected to the wiring XL[i].

[0161] For example, the wiring VL functions as a wiring that applies a constant voltage. The constant voltage is preferably determined by the configuration of the circuit MP[i,j], the arithmetic circuit 110, etc. The constant voltage may be, for example, a high-level potential VDD, a low-level potential VSS, a ground potential, or the like.

[0162] Moreover, the wiring WL[i] shown in Fig. 5F corresponds to the wiring WLS[i] in the arithmetic circuit 110 in Fig. 2. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0163] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. The wiring OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0164] Moreover, the wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HCr.

[0165] In the circuit MP[i,j] of Figure 5F, for the operation when a potential corresponding to the first data is held in each of the holding unit HC and the holding unit HCr, please refer to the explanation of the operation of holding a potential corresponding to the first data in the circuit MP[i,j] of Figure 5A.

[0166] In the circuit MP[i,j] of FIG. 5F, the circuit MC has a function of flowing a current corresponding to the potential held in the holding unit HC between the first and second terminals of the circuit MC when a constant voltage provided by the wiring VL is supplied to the first terminal of the circuit MC. Also, the circuit MCr has a function of flowing a current corresponding to the potential held in the holding unit HCr between the first and second terminals of the circuit MCr when a constant voltage provided by the wiring VL is supplied to the first terminal of the circuit MC. In other words, when the first data w is stored in each of the holding units HC and HCr of the circuit MP[i,j], i (k-1) j (k) By holding a potential according to the potential, it is possible to determine the amount of current flowing between the first terminal and the second terminal of the circuit MC and the amount of current flowing between the first terminal and the second terminal of the circuit MCr. Note that when the constant voltage provided by the wiring VL is not supplied to the first terminal of the circuit MC (circuit MCr), the circuit MC (circuit MCr) may, for example, not allow a current to flow between the first terminal and the second terminal of the circuit MC (circuit MCr).

[0167] For example, the first data w of "1" is stored in each of the storage units HC and HCr. i (k-1) j (k) When a potential according to is held, a constant voltage is applied to the circuit MC via the wiring VL, causing the circuit MC to pass a predetermined current between the first and second terminals of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. Note that, at this time, the circuit MCr does not pass a current between the first and second terminals of the circuit MCr. Therefore, no current flows between the circuit MCr and the wiring OLB. Also, for example, when the first data w of "-1" is stored in each of the holding units HC and HCr, i (k-1) j (k)When a potential according to is held, a constant voltage is applied to the circuit MC via the wiring VL, causing the circuit MCr to pass a predetermined current between the first and second terminals of the circuit MCr. Therefore, a current flows between the circuit MCr and the wiring OLB. Note that, at this time, the circuit MC does not pass a current between the first and second terminals of the circuit MC. Therefore, no current flows between the circuit MC and the wiring OL. Also, for example, when the first data w of "0" is stored in each of the holding units HC and HCr, i (k-1) j (k) When a potential according to is held, regardless of whether a constant voltage of the wiring VL is applied to the circuits MC and MCr, the circuit MC does not pass a current between the first and second terminals of the circuit MC, and the circuit MCr does not pass a current between the first and second terminals of the circuit MCr. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OLB.

[0168] In the circuit MP[i,j] of FIG. 5F, the first data w i (k-1) j (k) For a specific example of the potential corresponding to, please refer to the description of the circuit MP[i,j] in Fig. 5A. In the circuit MP[i,j] in Fig. 5F, the holding unit HC and the holding unit HCr have a function of holding information such as a current and a resistance value instead of a potential, similar to the circuit MP[i,j] in Fig. 5A, and the circuit MC and the circuit MCr may have a function of flowing a current corresponding to the information.

[0169] The wiring XL[i] shown in FIG. 5F corresponds to the wiring XLS[i] in the arithmetic circuit 110 in FIG. 2. Note that the second data z i (k-1) For example, the potential, current, etc. of the wiring XL[i] are determined. Therefore, the gate of the transistor MZ is connected to the second data z i (k-1) A potential according to the input is input.

[0170] For example, the second data z i (k-1) Consider the case where the second data z takes one of two values, “0” or “1”. i (k-1) When the second data z i (k-1) When the second data z i (k-1) When the second data z i (k-1) When is "0", the constant voltage is not applied to the circuit MC and the circuit MCr from the line VL.

[0171] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", a current flows between the circuit MC and the wiring OL, and a current does not flow between the circuit MCr and the wiring BLB. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "1", no current flows between the circuit MC and the wiring OL, and a current flows between the circuit MCr and the wiring OLB. i (k-1) j (k) is "0", and the second data z i (k-1)When the second data z i (k-1) If it is "0", the first data w i (k-1) j (k) Regardless of whether the signal level is "-1," "0," or "1," no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB.

[0172] That is, the circuit MP[i,j] in FIG. 5F is similar to the circuit MP[i,j] in FIG. 5E in that, for example, the first data w i (k-1) j (k) takes one of the three values ​​"-1", "0", or "1", and the second data z i (k-1) The circuit MP[i,j] in FIG. 5F can perform an operation in which the first data w i (k-1) j (k) The first data w can be operated even when it is one of two values ​​of "-1", "0", and "1", for example, when it is two values ​​of "-1" and "1", or when it is two values ​​of "0" and "1". i (k-1) j (k) may take an analog value or a multi-bit (multiple-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may be, for example, the first data w i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0173] <Example of operation of the arithmetic circuit> Next, a description will be given of an operation example of the arithmetic circuit 110 in Fig. 2. In the description of this operation example, the arithmetic circuit 110 shown in Fig. 8 will be used as an example.

[0174] The arithmetic circuit 110 in Fig. 8 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 110 in Fig. 2. In other words, the arithmetic circuit 110 in Fig. 8 is a circuit that is equivalent to the neuron N j (k) The input to neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) 8 corresponds to a circuit that performs a multiplication and accumulation operation of and an activation function operation using the result of the multiplication and accumulation operation. Furthermore, the circuit MP included in the array unit ALP of the arithmetic circuit 110 in FIG. 8 is assumed to be the circuit MP in FIG. 5A.

[0175] First, in the arithmetic circuit 110, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) The first data w i (k-1) j (k)The method of setting the first data is as follows: the circuit WLD sequentially inputs predetermined potentials to the wirings WLS[1] to WLS[m] to sequentially select the circuits MP[1,j] to MP[m,j], and supplies a potential corresponding to the first data from the circuit ILD to the holding unit HC of the circuit MC and the holding unit HCr of the circuit MCr included in the selected circuit MP via the wirings IL[j] and ILB[j]. After the potential is supplied, the circuit WLD deselects each of the circuits MP[1,j] to MP[m,j], thereby storing the first data w1 in the holding unit HC of the circuit MC and the holding unit HCr of the circuit MCr included in each of the circuits MP[1,j] to MP[m,j]. (k-1) j (k) Or even w m (k-1) j (k) As an example, the potential according to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) When each of the first data w1 takes a positive value, a value corresponding to the positive value is input to the holding unit HC, and a value equivalent to zero is input to the holding unit HCr. (k-1) j (k) Or even w m (k-1) j (k) When each of the above takes a negative value, a value equivalent to zero is input to the holding unit HC, and a value according to the absolute value of the negative value is input to the holding unit HCr.

[0176] Next, the circuit XLD supplies second data z1 (k-1) ~z m (k-1) As a specific example, the second data z1 is supplied to the wiring X1L[i] and the wiring X2L[i]. (k-1)is supplied. Note that the wiring X1L[i] and the wiring X2L[i] correspond to the wiring XLS[i] of the arithmetic circuit 110 shown in FIG.

[0177] The second data z1 input to each of the circuits MP[1,j] to MP[m,j] (k-1) ~z m (k-1) In accordance with the second data z i (k-1) Depending on the second data z1, the state may be one of the following: "the circuit MC and the wiring OL[j] are electrically connected, and the circuit MCr and the wiring OLB[j] are electrically connected", "the circuit MC and the wiring OLB[j] are electrically connected, and the circuit MCr and the wiring OL[j] are electrically connected", and "the circuit MC and the circuit MCr are not electrically connected to the wiring OL[j] and the wiring OLB[j], respectively". (k-1) When the second data z1 is a positive value, a value that can bring the circuit MC and the wiring OL[j] into a conductive state and can bring the circuit MCr and the wiring OLB[j] into a conductive state is input to the wiring X1L[1]. A value that can bring the circuit MC and the wiring OLB[j] into a non-conductive state and can bring the circuit MCr and the wiring OL[j] into a non-conductive state is input to the wiring X2L[1]. Then, the second data z1 (k-1) When the second data z1 is a negative value, a value that can bring the circuit MC and the wiring OLB[j] into a conductive state and can bring the circuit MCr and the wiring OL[j] into a conductive state is input to the wiring X1L[1]. A value that can bring the circuit MC and the wiring OL[j] into a non-conductive state and can bring the circuit MCr and the wiring OLB[j] into a non-conductive state is input to the wiring X2L[1]. (k-1)When the value of zero is taken for , a value that can bring about a non-conductive state between the circuit MC and the wiring OLB[j] and a non-conductive state between the circuit MCr and the wiring OL[j] is input to the wiring X1L[1]. Then, a value that can bring about a non-conductive state between the circuit MC and the wiring OL[j] and a non-conductive state between the circuit MCr and the wiring OLB[j] is input to the wiring X2L[1].

[0178] The second data z input to the circuit MP[i,j] i (k-1) In response to the first data w set in the circuit MP[i,j], a conductive state or a non-conductive state is determined between the circuit MC and the circuit MCr included in the circuit MP[i,j] and the wiring OL[j] and the circuit OLB[j], thereby inputting and outputting a current between the circuit MC and the wiring OL[j] and the wiring OLB[j]. Furthermore, the amount of the current is determined based on the first data w set in the circuit MP[i,j]. i (k-1) j (k) and / or second data z i (k-1) It depends on.

[0179] For example, in the circuit MP[i,j], the current flowing from the wiring OL[j] to the circuit MC or the circuit MCr is I[i,j], and the current flowing from the wiring OLB[j] to the circuit MC or the circuit MCr is I B [i,j]. Let I be the current flowing from the circuit ACTF[j] to the wiring OL[j]. out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] is I Bout [j], then I out [j] and I Bout [j] can be expressed by the following formula:

[0180]

number

[0181] In the circuit MP[i,j], for example, the first data w i (k-1)j (k) When the first data w is "+1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1). i (k-1) j (k) When the first data w is "-1", the circuit MC outputs I(-1) and the circuit MCr outputs I(+1). i (k-1) j (k) When is "0", the circuit MC outputs I(-1) and the circuit MCr outputs I(-1).

[0182] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) is “+1”, a state is taken in which “the circuit MC and the wiring OL[j] are conductive, the circuit MCr and the wiring OLB[j] are conductive, the circuit MC and the wiring OLB[j] are non-conductive, and the circuit MCr and the wiring OL[j] are non-conductive”, and the second data z i (k-1) is “−1”, a state is taken in which “the circuit MC and the wiring OLB[j] are electrically connected, the circuit MCr and the wiring OL[j] are electrically connected, the circuit MC and the wiring OL[j] are not electrically connected, and the circuit MCr and the wiring OLB[j] are not electrically connected” and the second data z i (k-1) is "0", "there is non-conduction between the circuit MC and the wiring OL[j], and between the circuit MC and the wiring OLB[j], there is non-conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j], there is non-conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j], and there is non-conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j]."

[0183] At this time, in the circuit MP[i,j], a current I[i,j] flows from the wiring OL[j] to the circuit MC or the circuit MCr, and a current I B[i,j] is as shown in the table below. In some cases, the circuit MP[i,j] may be configured so that the amount of current I(-1) is 0. The current I[i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0184] [Table 1]

[0185] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [j] and I Bout By inputting each of the inputs I[j] to the circuit ACTF[j], the circuit ACTF[j] can be configured as follows: out [j] and I Bout [j]. The circuit ACTF[j] may, for example, select neurons N j (k) The signal z sent to the (k+1)th layer neuron j (k) Output.

[0186] As an example, the arithmetic circuit 110 of FIG. j (k) The input to neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k)8, by providing n rows of circuits MP, a circuit equivalent to the arithmetic circuit 110 of FIG. 2 can be configured. In other words, the arithmetic circuit 110 of FIG. 2 can perform a multiplication and accumulation operation of the neurons N1 and N2, and an activation function calculation using the result of the multiplication and accumulation operation. (k) Neuron N n (k) In each of the above, the product-sum operation and the operation of the activation function using the result of the product-sum operation can be performed simultaneously.

[0187] <<Examples of changes to circuits included in arithmetic circuits>> As one example, some or all of the transistors included in each of the above-described array portion ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit MP, and the like are preferably OS transistors. For example, in the case of a transistor for which it is desired to reduce its off-state current, as a specific example, a transistor having a function of retaining charge accumulated in a capacitor is preferably an OS transistor. In particular, when an OS transistor is used as the transistor, it is more preferable that the OS transistor has the structure of the transistor described in Embodiment 3. However, one embodiment of the present invention is not limited thereto.

[0188] Moreover, the transistors included in the array part ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, and the like may be, other than the OS transistors, transistors including silicon in the channel formation region (hereinafter referred to as Si transistors). As the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, and the like can be used. As the transistors other than the OS transistors and the Si transistors, for example, transistors having a semiconductor such as Ge as an active layer, transistors having a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe as an active layer, transistors having a carbon nanotube as an active layer, transistors having an organic semiconductor as an active layer, and the like can be used.

[0189] Note that, in the metal oxide of the semiconductor layer of the OS transistor, an n-type semiconductor can be fabricated using a metal oxide containing indium (e.g., In oxide) or a metal oxide containing zinc (e.g., Zn oxide), but it may be difficult to fabricate a p-type semiconductor in terms of mobility and reliability. Therefore, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 may be configured such that OS transistors are used as n-channel transistors included in the array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, and the like, and Si transistors are used as p-channel transistors.

[0190] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0191] (Embodiment 2) In this embodiment mode, a specific configuration example of the circuit MP described in Embodiment Mode 1 will be described.

[0192] In addition, in embodiment 1, the symbols of the circuits MP are accompanied by [1,1], [i,j], [m,n], etc. to indicate their positions within the array section ALP, but in this embodiment, unless otherwise specified, the notations [1,1], [i,j], [m,n], etc. are omitted from the symbols of the circuits MP.

[0193] <Configuration example 1> First, an example of a circuit configuration applicable to the circuit MP of Fig. 5A will be described. The circuit MP shown in Fig. 9A is an example of the configuration of the circuit MP of Fig. 5A, and the circuit MC included in the circuit MP of Fig. 9A has, as an example, transistors M1 to M4 and a capacitance element C1. For example, the transistor M1 and the capacitance element C1 constitute a holding unit HC.

[0194] The transistors M1 to M4 shown in FIG. 9A are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of the transistors M1 to M4 has a first gate and a second gate. However, in this specification and the like, for convenience, the first gate is described as a gate (sometimes referred to as a front gate) and the second gate is described as a back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification and the like, the term "gate" can be interchanged with the term "back gate". Similarly, the term "back gate" can be interchanged with the term "gate". As a specific example, a connection configuration in which "the gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring".

[0195] Furthermore, the semiconductor device according to one embodiment of the present invention does not depend on the connection configuration of the backgate of the transistor. In each of the transistors M1 to M4 illustrated in FIG. 9A, the backgate is illustrated, but the connection configuration of the backgate is not illustrated. However, the electrical connection destination of the backgate can be determined at the design stage. For example, in a transistor having a backgate, the gate and the backgate may be electrically connected to increase the on-current of the transistor. That is, for example, in each of the transistors M1 to M4, the gate and the backgate may be electrically connected. For example, in a transistor having a backgate, a wiring electrically connected to an external circuit or the like may be provided to change the threshold voltage of the transistor or reduce the off-current of the transistor, and a potential may be applied to the backgate of the transistor by the external circuit or the like. Note that this is true not only for FIG. 9A but also for transistors described in other parts of the specification or transistors illustrated in other drawings.

[0196] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistor included in the semiconductor device. For example, the transistors M1 to M4 and the transistors M1r to M4r shown in FIG. 9A may have a structure without a backgate, that is, a single-gate structure, as shown in FIG. 9C. Some of the transistors may have a backgate, and other transistors may not have a backgate. This applies not only to the circuit diagram shown in FIG. 9A, but also to transistors described in other parts of the specification or transistors shown in other drawings.

[0197] In addition, in this specification and the like, transistors with various structures can be used as the transistor. Therefore, the type of the transistor used is not limited. As an example of the transistor, a transistor having single crystal silicon, or a transistor having a non-single crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, or semi-amorphous) silicon, or the like can be used. Alternatively, a thin film transistor (TFT) in which such a semiconductor is thinned can be used. There are various advantages in using a TFT. For example, since the TFT can be manufactured at a lower temperature than the case of single crystal silicon, the manufacturing cost can be reduced or the manufacturing equipment can be enlarged. Since the manufacturing equipment can be enlarged, the TFT can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, the display devices can be manufactured at low cost. Alternatively, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, the transistor can be manufactured on a substrate having light-transmitting properties. Alternatively, the light transmission in the display element can be controlled by using a transistor on a substrate having light-transmitting properties. Alternatively, since the film thickness of the transistor is thin, a part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.

[0198] As an example of the transistor, a transistor having a compound semiconductor (e.g., SiGe, GaAs, etc.) or an oxide semiconductor (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.) can be used. Alternatively, a thin film transistor in which these compound semiconductors or these oxide semiconductors are thinned can be used. This allows the manufacturing temperature to be lowered, so that it is possible to manufacture a transistor at room temperature, for example. As a result, a transistor can be formed directly on a substrate with low heat resistance, such as a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors can be used not only for the channel portion of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistor elements, pixel electrodes, or electrodes having light-transmitting properties. Since they can be formed or deposited simultaneously with the transistor, costs can be reduced.

[0199] As an example of a transistor, a transistor formed by an inkjet method or a printing method can be used. These methods allow manufacturing at room temperature, at a low degree of vacuum, or on a large substrate. Therefore, since manufacturing is possible without using a mask (reticle), the layout of the transistor can be easily changed. Alternatively, since manufacturing is possible without using a resist, material costs can be reduced and the number of steps can be reduced. Alternatively, since a film can be applied only to a necessary portion, materials are not wasted and costs can be reduced compared to a manufacturing method in which a film is formed on the entire surface and then etched.

[0200] As an example of a transistor, a transistor having an organic semiconductor or a carbon nanotube can be used. This allows a transistor to be formed on a substrate that can be bent. A device using a transistor having an organic semiconductor or a carbon nanotube can be made resistant to impacts.

[0201] It should be noted that transistors of various other structures can be used as the transistors. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as the transistors. By using MOS transistors as the transistors, the size of the transistors can be reduced. Thus, a large number of transistors can be mounted. By using bipolar transistors as the transistors, a large current can be passed. Thus, the circuit can be operated at high speed. It should be noted that MOS transistors and bipolar transistors may be mixed and formed on one substrate. This allows low power consumption, miniaturization, high speed operation, etc. to be realized.

[0202] As an example of a transistor, a transistor having a structure in which gate electrodes are arranged above and below an active layer can be applied. By adopting a structure in which gate electrodes are arranged above and below an active layer, a circuit configuration in which multiple transistors are connected in parallel is obtained. This increases the channel formation region, making it possible to increase the current value. Alternatively, by adopting a structure in which gate electrodes are arranged above and below an active layer, it becomes easier to form a depletion layer, making it possible to improve the S value.

[0203] As an example of a transistor, a transistor having a structure in which a gate electrode is disposed above an active layer, a structure in which a gate electrode is disposed below an active layer, a positive staggered structure, an inverted staggered structure, a structure in which a channel region is divided into a plurality of regions, a structure in which active layers are connected in parallel, or a structure in which active layers are connected in series can be used. Alternatively, the transistor can have various configurations, such as a planar type, a FIN type, a TRI-GATE type, a top gate type, a bottom gate type, and a double gate type (gates are disposed above and below the channel).

[0204] As an example of a transistor, a transistor having a structure in which a source electrode or a drain electrode overlaps with an active layer (or a part of it) can be used. By using a structure in which a source electrode or a drain electrode overlaps with an active layer (or a part of it), it is possible to prevent unstable operation due to charge accumulation in a part of the active layer.

[0205] As an example of a transistor, a structure with an LDD region can be applied. By providing the LDD region, it is possible to reduce the off-current or improve the breakdown voltage (improve reliability) of the transistor. In addition, by providing the LDD region, even if the voltage between the drain and source changes when operating in the saturation region, the drain current does not change much, and it is possible to obtain voltage-current characteristics with a flat slope.

[0206] For example, in the present specification and the like, a transistor can be formed using various substrates. The type of substrate is not limited to a specific one. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, base films, and the like include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, for example, there is a synthetic resin such as acrylic. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate, a transistor with small variations in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured using such transistors, it is possible to reduce the power consumption of the circuit or to increase the integration of the circuit.

[0207] Alternatively, a flexible substrate may be used as the substrate, and the transistor may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistor. The peeling layer can be used to separate the semiconductor device from the substrate after a part or whole of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate. In this case, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. Note that the above-mentioned peeling layer may be, for example, a laminated structure of inorganic films of a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate.

[0208] That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on the other substrate. Examples of substrates onto which transistors are transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), leather substrates, or rubber substrates. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are not easily broken, impart heat resistance, and reduce weight or thickness.

[0209] It is possible to form all of the circuits required to realize a given function on the same substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, etc.). This makes it possible to reduce costs by reducing the number of components, or to improve reliability by reducing the number of connections to the circuit components.

[0210] It is possible that all of the circuits required to realize the predetermined function are not formed on the same substrate. That is, a part of the circuit required to realize the predetermined function is formed on one substrate, and another part of the circuit required to realize the predetermined function is formed on another substrate. For example, a part of the circuit required to realize the predetermined function is formed on a glass substrate, and another part of the circuit required to realize the predetermined function is formed on a single crystal substrate (or an SOI substrate). Then, the single crystal substrate (also called an IC chip) on which another part of the circuit required to realize the predetermined function is formed can be connected to the glass substrate by COG (Chip On Glass), and the IC chip can be arranged on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate by TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), a printed circuit board, or the like. In this way, by forming a part of the circuit on the same substrate as the pixel portion, it is possible to reduce the cost by reducing the number of components, or to improve the reliability by reducing the number of connections with the circuit components. In particular, circuits with high drive voltages or high drive frequencies often consume a lot of power. Therefore, such circuits are formed on a substrate (such as a single crystal substrate) separate from the pixel section to form an IC chip. By using this IC chip, it is possible to prevent an increase in power consumption.

[0211] In the circuit MP of FIG. 9A, the first terminal of the transistor M1 is electrically connected to the wiring IL. The second terminal of the transistor M1 is electrically connected to the first terminal of the capacitance element C1 and the gate of the transistor M2. The gate of the transistor M1 is electrically connected to the wiring WL. The first terminal of the transistor M2 is electrically connected to the second terminal of the capacitance element C1 and the wiring VL. The second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M3 and the first terminal of the transistor M4. The second terminal of the transistor M3 is electrically connected to the wiring OL. The gate of the transistor M3 is electrically connected to the wiring X1L. The second terminal of the transistor M4 is electrically connected to the wiring OLB. The gate of the transistor M4 is electrically connected to the wiring X2L. Note that, as shown in FIG. 9B, the second terminal of the capacitance element C1 may be electrically connected to another wiring VLm instead of the wiring VL. Similarly, the second terminal of the capacitance element C1r may be electrically connected to another wiring VLmr instead of the wiring VLr. Note that in the circuit diagrams of the other drawings as well as in FIG. 9A, the second terminal of the capacitance element C1 may be electrically connected to another wiring VLm instead of the wiring VL. In FIG. 9B, for example, the wiring VL and the wiring VLr may be one and the same wiring, and the wiring VLm and the wiring VLmr may be one and the same wiring (not shown).

[0212] In the holding unit HC shown in FIG. 9A, the electrical connection point between the second terminal of the transistor M1, the first terminal of the capacitive element C1, and the gate of the transistor M2 is defined as a node nd1.

[0213] As described in the first embodiment, the holding unit HC has a function of holding a potential corresponding to the first data w, for example. The potential is held in the holding unit HC included in the circuit MC in FIG. 9A by inputting the potential from the wiring IL and writing it in the capacitor C1 when the transistor M1 is turned on, and then turning off the transistor M1. This allows the potential of the node nd1 to be held as a potential corresponding to the first data.

[0214] In order to hold the potential of the node nd1 for a long time, it is preferable to use a transistor with low off-state current as the transistor M1. For example, an OS transistor can be used as the transistor with low off-state current. Alternatively, a transistor having a back gate may be used as the transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side and reduce the off-state current.

[0215] The circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" in order to distinguish them from the circuit elements of the circuit MC.

[0216] A connection configuration in the circuit MCr that is different from that in the circuit MC will be described. A second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL, and a second terminal of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB. A first terminal of the transistor M2 is electrically connected to the wiring VLr.

[0217] In an operation example described later, in order to simply explain the current flowing in and out of the circuit MP, both ends of the wiring OL shown in FIG. 9A are referred to as nodes ina and outa, and both ends of the wiring OLB are referred to as nodes inb and outb.

[0218] For example, the wiring VL functions as a wiring that supplies a constant voltage. When the transistor M2 or the transistor M2r is an n-channel transistor, the constant voltage can be, for example, a low-level potential VSS, a ground potential, or other low-level potentials. Similarly to the wiring VL, the wiring VLr functions as a wiring that supplies a constant voltage, and the constant voltage can be a low-level potential VSS, a ground potential, or other low-level potentials. In this case, when the circuits ACTF[1] to ACTF[n] of the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 shown in FIGS. 3A to 3E, 4A to 4D, and 4F are used, the constant voltage provided by the wiring VAL electrically connected to the circuits ACTF[1] to ACTF[n] is preferably a potential higher than the potential provided by the wiring VL and the wiring VLr, for example, VDD.

[0219] The constant voltage supplied by the wiring VLr may be different from or the same as the constant voltage supplied by the wiring VL. For example, when the constant voltages supplied by the wiring VL and the wiring VLr are substantially equal, the wiring VLr can be the same as the wiring VL as in the circuit MP of FIG. 10A.

[0220] The configuration of the circuit MP in FIG. 9A can be changed depending on the situation. For example, as shown in FIG. 10B, the transistors M2, M2r, M3, M3r, M4, and M4r in the circuit MP in FIG. 9A may be replaced with p-channel transistors, such as transistors M2p, M2pr, M3p, M3pr, M4p, and M4pr. In particular, when the transistors M2 and M2r are replaced with p-channel transistors, it is preferable that the constant voltage provided by the wiring VL is VDD, which is a high-level potential. In addition to this case, when the circuits ACTF[1] to ACTF[n] of the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 shown in FIG. 3A to FIG. 3E, FIG. 4A to FIG. 4D, and FIG. 4F are applied, it is preferable that the constant voltage provided by the wiring VAL electrically connected to the circuits ACTF[1] to ACTF[n] is ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of the current flow is also changed.

[0221] Similarly, the transistor M1 may be replaced with a p-channel transistor. In Fig. 10B, the transistors M2, M2r, M3, M3r, M4, and M4r in the circuit MP in Fig. 9A are replaced with p-channel transistors, that is, the transistors M2p, M2pr, M3p, M3pr, M4p, and M4pr, respectively, but one or more transistors selected from the transistors M2, M2r, M3, M3r, M4, and M4r in the circuit MP in Fig. 9A may be replaced with p-channel transistors.

[0222] Also, for example, as shown in FIG. 11A, the transistors M3, M3r, M4, and M4r of the circuit MP in FIG. 9A may be replaced with analog switches A3, A4, A3r, and A4r, respectively. Note that FIG. 11A also illustrates wiring X1LB and wiring X2LB for operating the analog switches A3, A4, A3r, and A4r. The wiring X1LB is electrically connected to the analog switches A3 and A3r, and the wiring X2LB is electrically connected to the analog switches A4 and A4r. The wiring X1LB receives an inverted signal of a signal input to the wiring X1L, and the wiring X2LB receives an inverted signal of a signal input to the wiring X2L. Also, as shown in FIG. 11B, the wiring X1L and the wiring X2L may be combined into a wiring XL, and the wiring X1LB and the wiring X2LB may be combined into a wiring XLB. As an example, the analog switch A3, the analog switch A4, the analog switch A3r, and the analog switch A4r may have a CMOS configuration using n-channel transistors and p-channel transistors.

[0223] Also, for example, as shown in FIG. 12A, the transistor M4 and the transistor M4r in the circuit MP in FIG. 9A may be replaced with p-channel transistors M4p and M4pr, respectively. In the circuit MP in FIG. 12A, the gate of the transistor M3 is electrically connected to the gate of the transistor M4p and the wiring XL. The wiring XL corresponds to the two wirings X1L and X2L in FIG. 9A combined into one. The polarities of the transistor M3 and the transistor M4p are different, and the gates of the transistor M3 and the transistor M4p are electrically connected to the wiring XL. Therefore, by applying a predetermined potential to the wiring XL, one of the transistor M3 and the transistor M4p can be turned on and the other of the transistor M3 and the transistor M4p can be turned off.

[0224] Also, for example, as shown in FIG. 12B, a transistor M2m and a transistor M2mr may be added to the circuit MP of FIG. 9A, and the electrical connection destinations of the first terminals of the transistor M4 and the transistor M4r may be changed. In the circuit MP of FIG. 12B, the first terminal of the transistor M2m is electrically connected to the second terminal of the capacitance element C1, the first terminal of the transistor M2, and the wiring VL, and the second terminal of the transistor M2m is electrically connected to the first terminal of the transistor M4. In the circuit MP of FIG. 9A, the second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M4, but in the circuit MP of FIG. 12B, the second terminal of the transistor M2 is not electrically connected to the first terminal of the transistor M4. In the circuit MP shown in FIG. 12B, the currents flowing through the transistors M3 and M4 are determined by the potentials of the gates of the transistors M2 and M2m, respectively. In one example, it is preferable that the sizes, for example, the channel length or the channel width, of the transistors M2 and M2m are equal to each other. Such a circuit configuration may enable an efficient layout and may also enable the currents flowing through the transistors M3 and M4 to be uniform.

[0225] <<Example of operation>> Next, an example of the operation of the circuit MP shown in FIG. 9A will be described.

[0226] 13A to 13C, 14A to 14C, and 15A to 15C are timing charts showing an operation example of the circuit MP, and each shows the fluctuation of the potentials of the wiring IL, the wiring ILB, the wiring WL, the wiring X1L, the wiring X2L, the node nd1, and the node nd1r. Note that in FIGS. 13A to 13C, 14A to 14C, and 15A to 15C, "high" indicates a high-level potential, and "low" indicates a low-level potential. The amount of current output from the wiring OL to the node outa (or from the node outa to the wiring OL) is expressed as I OL In addition, the amount of current output from the wiring OLB to the node outb (or from the node outb to the wiring OLB) is I OLBIn the timing charts shown in FIGS. 13A to 13C, 14A to 14C, and 15A to 15C, the current amount I OL , I OLB The change in is also shown.

[0227] In this operation example, the constant voltage applied by the wiring VL and the wiring VLr is VSS (low level potential). In this case, a current flows from the wiring VAL through the wiring OL to the wiring VL. Similarly, a current flows from the wiring VAL through the wiring OLB to the wiring VLr.

[0228] In this specification and the like, the terms "low-level potential" and "high-level potential" do not mean a specific potential, and the specific potential may be different if the wiring is different. For example, the low-level potential and the high-level potential held in the node nd1 and the node nd1r may be different from the low-level potential and the high-level potential applied to the wiring X1L and the wiring X2L, respectively.

[0229] Before describing the operation example, the weighting coefficient held by the circuit MP is defined as follows. When a high-level potential is held at the node nd1 of the holding unit HC and a low-level potential is held at the node nd1r of the holding unit HCr, the circuit MP holds a weighting coefficient of "+1". When a low-level potential is held at the node nd1 of the holding unit HC and a high-level potential is held at the node nd1r of the holding unit HCr, the circuit MP holds a weighting coefficient of "-1". When a low-level potential is held at the node nd1 of the holding unit HC and a low-level potential is held at the node nd1r of the holding unit HCr, the circuit MP holds a weighting coefficient of "0". The high-level potential held at the nodes nd1 and nd1r can be, for example, VDD or a potential slightly lower than VDD, and the low-level potential held at the nodes nd1 and nd1r can be, for example, VSS. The weighting coefficient can also be an analog value. In this case, for example, when the weighting coefficient is a "positive analog value," a high-level analog potential is held at the node nd1 of the holding unit HC, and a low-level potential is held at the node nd1r of the holding unit HCr. When the weighting coefficient is a "negative analog value," for example, a low-level potential is held at the node nd1 of the holding unit HC, and a high-level analog potential is held at the node nd1r of the holding unit HCr. When the weighting coefficient is "0," for example, a low-level potential is held at the node nd1 of the holding unit HC, and a low-level potential is held at the node nd1r of the holding unit HCr.

[0230] Moreover, the neuron signal (computed value) input to the circuit MP is defined as follows, for example. When a high-level potential is applied to the wiring X1L and a low-level potential is applied to the wiring X2L, a neuron signal of "+1" is input to the circuit MP. When a low-level potential is applied to the wiring X1L and a high-level potential is applied to the wiring X2L, a neuron signal of "-1" is input to the circuit MP. When a low-level potential is applied to the wiring X1L and a low-level potential is applied to the wiring X2L, a neuron signal of "0" is input to the circuit MP.

[0231] In addition, in this specification and the like, unless otherwise specified, the transistors M2 and M2r are considered to include the case where they finally operate in the saturation region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to include the case where they are appropriately biased to a voltage within the range in which they operate in the saturation region. However, one embodiment of the present invention is not limited to this. In order to reduce the amplitude value of the supplied voltage, the transistors M2 and M2r may operate in a linear region. Note that, when the weighting coefficient is an analog value, for example, the transistors M2 and M2r may operate in a mixture of the linear region and the saturation region depending on the magnitude of the weighting coefficient.

[0232] In this specification and the like, unless otherwise specified, the on-state of the transistors M1, M3, M4, M1r, M3r, and M4r includes the case where they ultimately operate in a linear region, that is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors includes the case where they are appropriately biased to a voltage within the range where they operate in a linear region.

[0233] Below, an example of the operation of the circuit MP will be described for each combination of values ​​that the weighting coefficients and neuron signals can take.

[0234] [Condition 1] First, as an example, consider a case where the weight coefficient w is "0" and the neuron signal (calculated value) input to the circuit MP is "+1." Fig. 13A is a timing chart of the circuit MP in this case.

[0235] Between time T1 and time T2, the wiring IL and the wiring ILB are supplied with an initialization potential V ini In FIG. 13A, V iniis shown as a potential higher than the low-level potential and lower than the high-level potential, ini may be set to a potential lower than the low-level potential or higher than the high-level potential. ini The initial potential V may be set to the same potential as the low-level potential or the high-level potential. ini The wirings IL and ILB may have different potentials. ini In other words, there is no need to provide a period between time T1 and time T2.

[0236] In addition, a low-level potential is input to the wiring WL from time T1 to time T2, so that the transistors M1 and M1r are both in an off state.

[0237] In addition, the potentials of the nodes nd1 and nd1r are not particularly determined between time T1 and time T2. In FIG. 13A, the potentials of the nodes nd1 and nd1r are higher than the low level potential, and V ini The potential is set to be lower than that of the

[0238] A low-level potential is input to the wiring X1L and the wiring X2L, so that the transistors M3, M4, M3r, and M4r are all in an off state.

[0239] Next, a high-level potential is input to the wiring WL between time T2 and time T3. As a result, the transistors M1 and M1r are turned on, and the wiring IL and the node nd1 are brought into electrical continuity, and the wiring ILB and the node nd1r are brought into electrical continuity. Therefore, the potentials of the nodes nd1 and nd1r are each V ini The potentials of the nodes nd1 and nd1r are initialized to the initial potential V iniIn other words, there is no need to provide a period between time T2 and time T3.

[0240] Between time T3 and time T4, a low-level potential is applied to each of the wiring IL and the wiring ILB, and "0" is input as the weighting coefficient w. Since a high-level potential has been continuously input to the wiring WL since before time T3, and "0" has been input as the weighting coefficient w, the transistors M1 and M1r are in the on state. Therefore, the potentials of the nodes nd1 and nd1r are low-level potentials.

[0241] A low-level potential is input to the wiring WL from time T4 to time T5, which turns off the transistors M1 and M1r, and the potentials of the nodes nd1 and nd1r are held by the capacitors C1 and C1r, respectively.

[0242] As a result of the operations from time T1 to time T5, the weighting coefficient of the circuit MP is set to "0".

[0243] As a result of the operations up to this point, the potentials of the gates of the transistors M2 and M2r become low-level potentials, and the potentials of the first terminals of the transistors M2 and M2r are VSS, so that the transistors M2 and M2r are both in the off state.

[0244] Between time T5 and time T6, for example, the wiring IL and the wiring ILB are supplied with an initialization potential V ini Note that this operation is not particularly necessary, so the initial potential V ini In other words, there is no need to provide a period from time T5 to time T6. Different potentials may be input to the wiring IL and the wiring ILB.

[0245] After time T6, a high-level potential is input to the wire X1L and a low-level potential is input to the wire X2L as the input of the neuron signal "+1" to the circuit MP. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings the circuit MC and the wire OL into a conductive state, and the circuit MCr and the wire OLB into a conductive state.

[0246] At this time, in the circuit MC, since the transistor M2 is in an off state, no current flows from the wiring OL to the wiring VL. In other words, the current I OL does not change before and after time T6. Similarly, in the circuit MCr, since the transistor M2r is in the off state, no current flows from the wiring OLB to the wiring VLr. In other words, the current I OLB Also, there is no change before and after time T6.

[0247] In this condition, the weighting coefficient is set to "0" and the neuron signal input to the circuit MP is set to "+1", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "0". The result of the product of the weighting coefficient and the neuron signal being "0" is that in the operation of the circuit MP, the current I OL and current I OLB corresponds to the case where each of the above does not change.

[0248] Note that once the weighting coefficient w is input, multiple product-sum calculation processes may be performed by changing only the calculated value without updating the value. In this case, since updating of the weighting coefficient w is not necessary, power consumption can be reduced. Note that in order to reduce the number of updates of the weighting coefficient w, it is necessary to hold the weighting coefficient w for a long period of time. In this case, for example, if an OS transistor is used, the weighting coefficient w can be held for a long period of time by utilizing its low off-current.

[0249] [Condition 2] Next, as an example, consider a case where the weight coefficient w is "+1" and the neuron signal (calculated value) input to the circuit MP is "+1." Fig. 13B is a timing chart of the circuit MP in this case.

[0250] The operation from time T1 to time T3 is similar to the operation from time T1 to time T3 in condition 1, so the explanation of the operation from time T1 to time T3 in condition 1 shall be taken into consideration.

[0251] Between time T3 and time T4, a high-level potential is applied to the wiring IL, a low-level potential is applied to the wiring ILB, and "1" is input as the weighting coefficient w. Since a high-level potential has been continuously input to the wiring WL since before time T3, and "1" has been input as the weighting coefficient w, the transistors M1 and M1r are in the on state. Therefore, the potential of the node nd1 becomes a high-level potential, and the potential of the node nd1r becomes a low-level potential.

[0252] A low-level potential is input to the wiring WL from time T4 to time T5, which turns off the transistors M1 and M1r, and the potentials of the nodes nd1 and nd1r are held by the capacitors C1 and C1r, respectively.

[0253] As a result of the operations from time T1 to time T5, the weighting coefficient of the circuit MP is set to "+1".

[0254] As a result of the operations up to this point, the potential of the gate of transistor M2 becomes a high-level potential, and the potential of the gate of transistor M2r becomes a low-level potential. In addition, since the potentials of the first terminals of transistors M2 and M2r are VSS, transistor M2 is in the on state, and transistor M2r is in the off state.

[0255] The operation from time T5 to time T6 is similar to the operation from time T5 to time T6 in condition 1, so the explanation of the operation from time T5 to time T6 in condition 1 shall be taken into consideration.

[0256] After time T6, a high-level potential is input to the wire X1L and a low-level potential is input to the wire X2L as the input of the neuron signal "+1" to the circuit MP. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings the circuit MC and the wire OL into a conductive state, and the circuit MCr and the wire OLB into a conductive state.

[0257] At this time, in the circuit MC, since the transistor M2 is in an on state, a current flows from the wiring OL to the wiring VL. That is, the current I OL increases after time T6 (in FIG. 13B, the current I OL The increase in current I is denoted as ΔI. On the other hand, in the circuit MCr, since the transistor M2r is in the off state, no current flows from the wiring OLB to the wiring VLr. In other words, the current I OLB does not change before and after time T6.

[0258] In this condition, the weighting coefficient w is set to "+1" and the neuron signal (computed value) input to the circuit MP is set to "+1", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "+1". The result of the product of the weighting coefficient and the neuron signal being "1" is that in the operation of the circuit MP, the current I OL changes, and the current I OLB corresponds to the case where does not change.

[0259] [Condition 3] Next, as an example, consider a case where the weighting coefficient w is "-1" and the neuron signal (calculated value) input to the circuit MP is "+1." Fig. 13C is a timing chart of the circuit MP in this case.

[0260] The operation from time T1 to time T3 is similar to the operation from time T1 to time T3 in condition 1, so the explanation of the operation from time T1 to time T3 in condition 1 shall be taken into consideration.

[0261] Between time T3 and time T4, a low-level potential is applied to the wiring IL, a high-level potential is applied to the wiring ILB, and "-1" is input as the weighting coefficient w. Since a high-level potential has been continuously input to the wiring WL since before time T3, the transistors M1 and M1r are in the on state. Therefore, "-1" is input as the weighting coefficient w, the potential of the node nd1 becomes a low-level potential, and the potential of the node nd1r becomes a high-level potential.

[0262] A low-level potential is input to the wiring WL from time T4 to time T5, which turns off the transistors M1 and M1r, and the potentials of the nodes nd1 and nd1r are held by the capacitors C1 and C1r, respectively.

[0263] As a result of the operations from time T1 to time T5, the weighting coefficient of the circuit MP is set to "-1".

[0264] As a result of the operations up to this point, the potential of the gate of transistor M2 becomes a low-level potential, and the potential of the gate of transistor M2r becomes a high-level potential. In addition, since the potentials of the first terminals of transistors M2 and M2r are VSS, transistor M2 is in the off state, and transistor M2r is in the on state.

[0265] The operation from time T5 to time T6 is similar to the operation from time T5 to time T6 in condition 1, so the explanation of the operation from time T5 to time T6 in condition 1 shall be taken into consideration.

[0266] After time T6, a high-level potential is input to the wire X1L and a low-level potential is input to the wire X2L as the input of the neuron signal "+1" to the circuit MP. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings the circuit MC and the wire OL into a conductive state, and the circuit MCr and the wire OLB into a conductive state.

[0267] At this time, in the circuit MC, since the transistor M2 is in an off state, no current flows from the wiring OL to the wiring VL. In other words, the current I OL does not change before and after time T6. On the other hand, in the circuit MCr, since the transistor M2r is in the on state, a current flows from the wiring OLB to the wiring VLr. That is, the current I OLB increases after time T6 (in FIG. 13C, the current I OLB The increase in is listed as ΔI.

[0268] In this condition, the weighting coefficient w is set to "-1" and the neuron signal (computed value) input to the circuit MP is set to "+1", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "-1". The result of the product of the weighting coefficient and the neuron signal being "-1" is that in the operation of the circuit MP, the current I OL does not change, and the current I OLB This corresponds to the case where changes.

[0269] [Condition 4] In this condition, as an example, consider the operation of the circuit MP when the weight coefficient w is set to "0" and the neuron signal (calculated value) input to the circuit MP is set to "-1." Figure 14A is a timing chart of the circuit MP in this case.

[0270] The operation from time T1 to time T6 is similar to the operation from time T1 to time T6 in condition 1, so the explanation of the operation from time T1 to time T6 in condition 1 shall be taken into consideration.

[0271] After time T6, a low-level potential is input to the wiring X1L and a high-level potential is input to the wiring X2L as an input of the neuron signal (computation value) "-1" to the circuit MP. As a result, the transistors M3 and M3r are turned off, and the transistors M4 and M4r are turned on. In other words, this operation brings the circuit MC and the wiring OLB into a conductive state, and the circuit MCr and the wiring OL into a conductive state.

[0272] At this time, in the circuit MC, since the transistor M2 is in an off state, no current flows from the wiring OLB to the wiring VL. In other words, the current I OLB does not change before and after time T6. Similarly, in the circuit MCr, since the transistor M2r is in the off state, no current flows from the wiring OL to the wiring VLr. In other words, the current I OL Also, there is no change before and after time T6.

[0273] In this condition, the weighting coefficient w is set to "0" and the neuron signal (computed value) input to the circuit MP is set to "-1", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "0". The result of the product of the weighting coefficient and the neuron signal being "0" is that in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the above changes, which is consistent with the result of the circuit operation under condition 1.

[0274] [Condition 5] In this condition, as an example, consider the operation of the circuit MP when the weight coefficient w is set to "+1" and the neuron signal (calculated value) input to the circuit MP is set to "-1." Figure 14B is a timing chart of the circuit MP in this case.

[0275] The operation from time T1 to time T6 is similar to the operation from time T1 to time T6 in condition 2, so the explanation of the operation from time T1 to time T6 in condition 2 shall be referred to.

[0276] After time T6, a low-level potential is input to the wiring X1L and a high-level potential is input to the wiring X2L as an input of the neuron signal (computation value) "-1" to the circuit MP. As a result, the transistors M3 and M3r are turned off, and the transistors M4 and M4r are turned on. In other words, this operation brings the circuit MC and the wiring OLB into a conductive state, and the circuit MCr and the wiring OL into a conductive state.

[0277] At this time, in the circuit MC, since the transistor M2 is in an on state, a current flows from the wiring OLB to the wiring VL. That is, the current I OLB increases after time T6 (in FIG. 14B, the current I OLB The increase in current I is denoted as ΔI. On the other hand, in the circuit MCr, since the transistor M2r is in the off state, no current flows from the wiring OL to the wiring VLr. In other words, the current I OL does not change before and after time T6.

[0278] In this condition, the weighting coefficient w is set to "+1" and the neuron signal (computed value) input to the circuit MP is set to "-1", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "-1". The result of the product of the weighting coefficient and the neuron signal being "-1" is that in the operation of the circuit MP, the current I OL does not change, and the current I OLB This corresponds to the case where changes, which is consistent with the result of the circuit operation in condition 3.

[0279] [Condition 6] In this condition, as an example, consider the operation of the circuit MP when the weight coefficient w is set to "-1" and the neuron signal (calculated value) input to the circuit MP is set to "-1." Figure 14C is a timing chart of the circuit MP in this case.

[0280] The operation from time T1 to time T6 is similar to the operation from time T1 to time T6 in condition 3, so the explanation of the operation from time T1 to time T6 in condition 3 shall be referred to.

[0281] After time T6, a low-level potential is input to the wiring X1L and a high-level potential is input to the wiring X2L as an input of the neuron signal (computation value) "-1" to the circuit MP. As a result, the transistors M3 and M3r are turned off, and the transistors M4 and M4r are turned on. In other words, this operation brings the circuit MC and the wiring OLB into a conductive state, and the circuit MCr and the wiring OL into a conductive state.

[0282] At this time, in the circuit MC, since the transistor M2 is in an off state, no current flows from the wiring OLB to the wiring VL. In other words, the current I OLB does not change before and after time T6. On the other hand, in the circuit MCr, since the transistor M2r is in the on state, a current flows from the wiring OL to the wiring VLr. That is, the current I OLincreases after time T6 (in FIG. 14C, the current I OL The increase in is listed as ΔI.

[0283] In this condition, the weighting coefficient w is set to "-1" and the neuron signal (computed value) input to the circuit MP is set to "-1", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "+1". The result of the product of the weighting coefficient and the neuron signal being "+1" is that in the operation of the circuit MP, the current I OL changes, and the current I OLB does not change, which is consistent with the result of the circuit operation under condition 2.

[0284] [Condition 7] In this condition, as an example, the operation of the circuit MP is considered under the condition 7 where the weight coefficient w is "0" and the neuron signal (computed value) input to the circuit MP is "0". Figure 15A is a timing chart of the circuit MP in this case.

[0285] The operation from time T1 to time T6 is similar to the operation from time T1 to time T6 in condition 1, so the explanation of the operation from time T1 to time T6 in condition 1 shall be taken into consideration.

[0286] After time T6, a low-level potential is input to the wiring X1L and a low-level potential is input to the wiring X2L as an input of a neuron signal (computation value) "0" to the circuit MP. This causes the transistors M3, M3r, M4, and M4r to be in an off state. In other words, this operation causes the circuits MC and MCr to be in a non-conductive state between the wirings OL and OLB.

[0287] Therefore, in the circuit MC, no current flows from the wiring OL to either the wiring VL or the wiring VLr. That is, the current I OLBdoes not change before and after time T6. Similarly, in the circuit MCr, no current flows from the wiring OLB to the other of the wiring VL and the wiring VLr. That is, the current I OL Also, there is no change before and after time T6.

[0288] In this condition, the weighting coefficient w is "0" and the neuron signal (computed value) input to the circuit MP is "0", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "0". The result of the product of the weighting coefficient and the neuron signal being "0" is that in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the above changes, which is consistent with the results of the circuit operation under conditions 1 and 4.

[0289] [Condition 8] In this condition, as an example, the operation of the circuit MP is considered under the condition 8 where the weight coefficient w is "+1" and the neuron signal (calculated value) input to the circuit MP is "0". Figure 15B is a timing chart of the circuit MP in this case.

[0290] The operation from time T1 to time T6 is similar to the operation from time T1 to time T6 in condition 2, so the explanation of the operation from time T1 to time T6 in condition 2 shall be referred to.

[0291] After time T6, a low-level potential is input to the wire X1L and a low-level potential is input to the wire X2L as an input of the neuron signal (computation value) "0" to the circuit MP. In other words, since this is the same as the operation after time T6 in condition 7, this operation causes the circuit MC to be in a non-conducting state between either the wire OL or OLB, and the circuit MCr to be in a non-conducting state between either the wire OL or the wire OLB. Therefore, no current flows from the wire OL or the wire OLB to either the wire VL or the wire VLr, so the current I output from the node outa of the wire OL OL , and the current I output from node outb of wiring OLBOLB do not change before and after time T6.

[0292] In this condition, the weighting coefficient w is set to "+1" and the neuron signal (computed value) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "0". The result of the product of the weighting coefficient and the neuron signal being "0" is that in the operation of the circuit MP, the current I OL and current I OLB corresponds to the case where each of the conditions does not change, which is consistent with the results of the circuit operation under conditions 1, 4, and 7.

[0293] [Condition 9] In this condition, as an example, the operation of the circuit MP is considered under condition 9, where the weight coefficient w is "-1" and the neuron signal (calculated value) input to the circuit MP is "0." Figure 15C is a timing chart of the circuit MP in this case.

[0294] The operation from time T1 to time T6 is similar to the operation from time T1 to time T6 in condition 3, so the explanation of the operation from time T1 to time T6 in condition 3 shall be referred to.

[0295] After time T6, a low-level potential is input to the wire X1L and a low-level potential is input to the wire X2L as an input of the neuron signal (computation value) "0" to the circuit MP. In other words, since this is the same as the operation after time T6 in condition 7, this operation causes the circuit MC to be in a non-conducting state between either the wire OL or the wire OLB, and the circuit MCr to be in a non-conducting state between either the wire OL or the wire OLB. Therefore, since no current flows from the wire OL or the wire OLB to either the wire VL or the wire VLr, the current I output from the node outa of the wire OL OL , and the current I output from node outb of wiring OLB OLB do not change before and after time T6.

[0296] In this condition, the weighting coefficient w is set to "-1" and the neuron signal (computed value) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the weighting coefficient and the neuron signal is "0". The result of the product of the weighting coefficient and the neuron signal being "0" is that in the operation of the circuit MP, the current I OL and current I OLB corresponds to the case where each of the conditions does not change, which is consistent with the results of the circuit operation under conditions 1, 4, 7, and 8.

[0297] The results of the operation examples under the above-mentioned conditions 1 to 9 are summarized in the table below. Note that in the table below, a high level potential is described as "high" and a low level potential is described as "low."

[0298] [Table 2]

[0299] Here, an example is shown in which one circuit MC and one circuit MCr are connected to the wiring OL and wiring OLB, respectively. In contrast, as shown in Figs. 2, 6, 7, and 8, when multiple circuits MC and multiple circuits MCr are connected to the wiring OL and wiring OLB, the currents output from each circuit MC and circuit MCr are added together based on Kirchhoff's current law. As a result, a sum operation is performed. In other words, a product operation is performed in the circuits MC and MCr, and a sum operation is performed by adding together the currents from the multiple circuits MC and MCr. As a result of the above, a product-sum operation is performed.

[0300] By the way, in the operation of circuit MP, by setting the weighting coefficients to only two values, "+1" and "-1", and performing calculations with neuron signals having only two values, "+1" and "-1", circuit MP can perform operations similar to an exclusive OR negation circuit (coincidence circuit).

[0301] In addition, by setting the weighting coefficients to only two values, "+1" and "0", and performing calculations with neuron signals to only two values, "+1" and "0", circuit MP can operate in the same way as a logical AND circuit.

[0302] In this operation example, the potentials held in the holding units HC and HCr of the circuits MC and MCr in the circuit MP are high level potentials or low level potentials, but the holding units HC and HCr may hold potentials indicating analog values. For example, when the weighting coefficient is a "positive analog value", a high level analog potential is held at the node nd1 of the holding unit HC, and a low level potential is held at the node nd1r of the holding unit HCr. When the weighting coefficient is a "negative analog value", for example, a low level potential is held at the node nd1 of the holding unit HC, and a high level analog potential is held at the node nd1r of the holding unit HCr. Then, the current I OL and current I OLB The magnitude of the current is in accordance with the analog potential. In addition, the holding of the potential indicating the analog value in the holding units HC and HCr is not limited to the operation example of the circuit MP in FIG. 9A, and may be performed in other circuits MP shown in this specification.

[0303] <Configuration example 2> Next, an example of a circuit configuration that can be applied to the circuit MP shown in FIG. 5C and FIG. 5D will be described.

[0304] The circuit MP shown in Figure 16A shows an example configuration of the circuit MP in Figure 5C, and differs from the circuit MP in Figure 9A in that the wiring IL and wiring ILB are combined into one, and that it has wiring W1L and wiring W2L as the wiring WL of Figure 9A.

[0305] In the circuit MP of Fig. 16A, the first terminal of the transistor M1 and the first terminal of the transistor M1r are electrically connected to the wiring IL. In addition, the gate of the transistor M1 is electrically connected to the wiring W1L, and the gate of the transistor M1r is electrically connected to the wiring W2L. Note that a description of the circuit MP of Fig. 16A and the circuit MP of Fig. 9A that have the same connection configuration will be omitted.

[0306] When setting a weighting factor in the circuit MP of FIG. 16A, first, the potentials supplied to the wiring W1L and the wiring W2L are changed to turn on the transistor M1 and turn off the transistor M1r, then a potential for holding is supplied from the wiring IL to the holding unit HC to turn off the transistor M1. After that, the potentials supplied to the wiring W1L and the wiring W2L are changed to turn off the transistor M1 and turn on the transistor M1r, then a potential for holding is supplied from the wiring IL to the holding unit HCr to turn off the transistor M1r. In this way, in the case of the circuit MP of FIG. 16A, potentials corresponding to the weighting factor can be held in the holding unit HC and the holding unit HCr by supplying potentials from the wiring IL to the holding unit HC and the holding unit HCr in sequence.

[0307] The circuit MP shown in FIG. 16B shows an example configuration of the circuit MP in FIG. 5D, and differs from the circuit MP in FIG. 9A in that the wiring IL and wiring OL are combined into a wiring IOL, and the wiring ILB and wiring OLB are combined into a wiring IOLB.

[0308] In the circuit MP of FIG. 16B, the first terminal of the transistor M1 is electrically connected to the wiring IOL, and the first terminal of the transistor M1r is electrically connected to the wiring IOLB. In addition, the second terminal of the transistor M3 is electrically connected to the wiring IOL, the second terminal of the transistor M4 is electrically connected to the wiring IOLB, the second terminal of the transistor M3r is electrically connected to the wiring IOLB, and the second terminal of the transistor M4r is electrically connected to the wiring IOL. Note that a description of the parts of the circuit MP of FIG. 16B that have the same connection configuration as the circuit MP of FIG. 9A will be omitted.

[0309] In the circuit MP of Figure 16B, the wiring IOL is electrically connected to the holding unit HC, the wiring IOLB is electrically connected to the holding unit HCr, and the gates of the transistors M1 and M1r are electrically connected to the wiring WL, so that, similarly to the circuit MP of Figure 9A, potentials corresponding to the weighting coefficients can be simultaneously written to the holding units HC and HCr.

[0310] <Configuration example 3> The circuit MP shown in FIG. 17 is different from the circuit MP in FIG. 9A in that it has not only a holding portion HC and a holding portion HCr but also a holding portion HCs and a holding portion HCsr.

[0311] A circuit MC included in the circuit MP of Fig. 17 has a transistor M1s, a transistor M2s, a transistor M5, a transistor M5s, and a capacitance element C1s in addition to the circuit elements included in the circuit MP of Fig. 9A. A circuit MCr included in the circuit MP of Fig. 17 has circuit elements similar to those of the circuit MC, and therefore has a transistor M1sr, a transistor M2sr, a transistor M5r, a transistor M5sr, and a capacitance element C1sr corresponding to the transistor M1s, the transistor M2s, the transistor M5, the transistor M5s, and the capacitance element C1s of the circuit MC, respectively.

[0312] In this specification and the like, unless otherwise specified, the transistor M5, the transistor M5s, the transistor M5r, and the transistor M5sr include a case where they ultimately operate in a linear region when they are in an on state, that is, the gate voltage, the source voltage, and the drain voltage of each of the above-mentioned transistors include a case where they are appropriately biased to a voltage within a range where they operate in a linear region.

[0313] Next, a description will be given of the configuration of the circuit MP in Fig. 17. Note that in the circuit MP in Fig. 17, parts that have the same configuration as the circuit MP in Fig. 9A will be omitted.

[0314] A gate of the transistor M1 is electrically connected to the wiring W1L. A first terminal of the transistor M5 is electrically connected to a second terminal of the transistor M2, a second terminal of the transistor M5 is electrically connected to a first terminal of the transistor M3 and a first terminal of the transistor M4, and a gate of the transistor M5 is electrically connected to the wiring S1L.

[0315] A first terminal of the transistor M1s is electrically connected to the wiring IL, a second terminal of the transistor M1s is electrically connected to a first terminal of the capacitor C1s and a gate of the transistor M2s, and the gate of the transistor M1s is electrically connected to the wiring W2L. A first terminal of the transistor M2s is electrically connected to a second terminal of the capacitor C1s and a wiring VLs, and a second terminal of the transistor M2s is electrically connected to a first terminal of the transistor M5s. A second terminal of the transistor M5s is electrically connected to a first terminal of the transistor M3 and a first terminal of the transistor M4, and the gate of the transistor M5s is electrically connected to the wiring S2L.

[0316] 17, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0317] The wiring VLs functions as a wiring that supplies a constant voltage, and the constant voltage can be VSS, which is a low-level potential, a low-level potential other than VSS, a ground potential, or the like. The constant voltage can also be VDD, which is a high-level potential. The constant voltage supplied by the wiring VLs can be different from or the same as the constant voltage supplied by the wiring VL. When the constant voltages supplied by the wiring VL and the wiring VLs are approximately equal, the wiring VLs can be the same wiring as the wiring VL.

[0318] The wiring VLsr functions as a wiring that supplies a constant voltage, and the constant voltage can be VSS, which is a low-level potential, a low-level potential other than VSS, a ground potential, or the like. The constant voltage can also be VDD, which is a high-level potential. The constant voltage supplied by the wiring VLsr can be different from or the same as the constant voltage supplied by the wiring VLr. When the constant voltages supplied by the wiring VLr and the wiring VLsr are approximately equal, the wiring VLsr can be the same wiring as the wiring VLr.

[0319] The constant voltages applied by the wiring VL, the wiring VLs, the wiring VLr, and the wiring VLsr may be different from each other or may be the same. The constant voltages applied by two or three wirings selected from the wiring VL, the wiring VLs, the wiring VLr, and the wiring VLsr may be the same.

[0320] The wiring S1L functions as a wiring that supplies a potential for turning on or off the transistor M5 and the transistor M5r, and the wiring S2L functions as a wiring that supplies a potential for turning on or off the transistor M5s and the transistor M5sr.

[0321] The circuit MP illustrated in FIGS. 5C and 5D can hold two weighting coefficients by applying the configuration illustrated in the circuit MP of FIG. 17. Specifically, the circuit MP of FIG. 17 can hold a potential corresponding to a first weighting coefficient in the holding unit HC of the circuit MC and the holding unit HCr of the circuit MCr, and can hold a potential corresponding to a second weighting coefficient in the holding unit HCs of the circuit MC and the holding unit HCsr of the circuit MC. The circuit MP of FIG. 17 can switch the weighting coefficient used in the calculation by potentials applied from the wirings S1L and S2L. For example, a weighting coefficient w1 is stored in the holding units HC and HCr included in the circuits MP[1,j] to MP[m,j] of the calculation circuit 110. (k-1) j (k) Or even w m (k-1) j (k)The weighting coefficient w1 is stored in each of the storage units HCs and HCsr included in the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 110. (k-1) h (k) Or even w m (k-1) h (k) (Here, h is an integer not less than 1 and not equal to j.) is held, and a signal z1 (k-1) ~z m (k-1) At this time, a high-level potential is applied to the wiring S1L to turn on the transistors M5 and M5r, and a low-level potential is applied to the wiring S2L to turn off the transistors M5s and M5sr. In this way, the circuits MP[1,j] to MP[m,j] in the arithmetic circuit 110 are adjusted to the weight coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) and signal z1 (k-1) ~z m (k-1) In addition, a low-level potential is applied to the wiring S1L to turn off the transistors M5 and M5r, and a high-level potential is applied to the wiring S2L to turn on the transistors M5s and M5sr. In this way, the circuits MP[1,j] to MP[m,j] in the arithmetic circuit 110 can calculate the sum of products of the weight coefficients w1 (k-1) h (k) Or even w m (k-1) h (k) and signal z1 (k-1) ~z m (k-1) It is possible to perform product-sum and activation function calculations with

[0322] As described above, by applying the circuit MP of Fig. 17 to the arithmetic circuit 110, two weight coefficients can be held, and the weight coefficients can be switched to perform calculations of product sums and activation functions. The arithmetic circuit 110 constituting the circuit MP of Fig. 17 is effective, for example, when the number of neurons in the k-th layer is greater than n, when calculations are performed in an intermediate layer different from the k-th layer, etc. In addition, in the circuit MP of Fig. 17, the circuit MC and the circuit MCr each have two holding units, but each of the circuit MC and the circuit MCr may have three or more holding units depending on the situation.

[0323] <Configuration Example 4> The circuit MP shown in FIG. 18A is a circuit that can be applied to the circuit MP of FIG. 5A, and differs from the circuit MP of FIG. 9A in that the holding unit HC and the holding unit HCr have load circuits LC and LCr instead of the capacitive elements C1 and C1r, respectively.

[0324] In circuit MC of circuit MP in Figure 18A, a first terminal of load circuit LC is electrically connected to a second terminal of transistor M1, a first terminal of transistor M3, and a first terminal of transistor M4, and a second terminal of load circuit LC is electrically connected to wiring VL.

[0325] 18A has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0326] The wiring VL and wiring VLr function as wirings for supplying a constant voltage VCNS. VCNS can be, for example, a ground potential (GND) or a low potential within a range that allows the load circuits LC and LCr to operate normally.

[0327] As an example, the load circuits LC and LCr are circuits that can change the resistance between the first terminal and the second terminal. By changing the resistance between the first terminal and the second terminal of the load circuits LC and LCr, the amount of current flowing between the first terminal and the second terminal of the load circuits LC and LCr can be changed.

[0328] Here, a method of changing the resistance value between the first terminal and the second terminal of the load circuit LC and the load circuit LCr in the circuit MP of FIG. 18A will be described. First, a low-level potential is input to each of the wiring X1L and the wiring X2L to turn off the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r. Next, a high-level potential is input to the wiring WL to turn on the transistors M1 and M1r, and the potential of the wiring IL (wiring ILB) is changed to set the resistance value between the first terminal and the second terminal of the load circuit LC (load circuit LCr). For example, there is a method of inputting a potential to the wiring IL (wiring ILB) for resetting the resistance value between the first terminal and the second terminal of the load circuit LC (load circuit LCr), and then inputting a potential to the wiring IL (wiring ILB) so that the resistance value between the first terminal and the second terminal of the load circuit LC (load circuit LCr) becomes a desired value. After the resistance value between the first terminal and the second terminal of the load circuit LC (load circuit LCr) is set to a desired value, a low-level potential is input to the wiring WL to turn off the transistor M1 and the transistor M1r.

[0329] The load circuit LC and the load circuit LCr may be, for example, a resistance change element VR as shown in Fig. 18B. The load circuit LC and the load circuit LCr may be, for example, a circuit VC including an MTJ element MR as shown in Fig. 18C. The load circuit LC and the load circuit LCr may be, for example, a resistance element including a phase change material used in a phase change memory (PCM) or the like (for convenience, referred to as a phase change memory PCM in this specification and the like) as shown in Fig. 18D.

[0330] In addition, the circuit MP using the load circuit LC and the load circuit LCr is not limited to the configuration shown in Fig. 18A, and the configuration of the circuit MP in Fig. 18A can be changed depending on the situation. As an example of a modification of the circuit MP in Fig. 18A, a circuit configuration can be adopted in which the wiring IL, the wiring ILB, the transistor M1, and the transistor M1r are not provided in the circuit MP in Fig. 18A. Fig. 19 is a circuit diagram showing this circuit configuration, which is one of the configuration examples of the circuit MP in Fig. 5D.

[0331] 19, the resistance value between the first and second terminals of the load circuit LC can be set by inputting a high-level potential to the wiring X1L and a low-level potential to the wiring X2L to turn on the transistor M3 and turn off the transistor M4, and applying a potential from the wiring IOL through the transistor M3 to the first terminal of the load circuit LC. At this time, a potential can be applied to the first terminal of the load circuit LCr from the wiring IOLB through the transistor M3r, so that the resistance value between the first and second terminals of the load circuit LCr can be set simultaneously with the load circuit LC.

[0332] The resistance value between the first and second terminals of the load circuit LC can also be set by inputting a low-level potential to the wiring X1L and a high-level potential to the wiring X2L to turn off the transistor M3 and turn on the transistor M4, and applying a potential from the wiring IOLB through the transistor M4 to the first terminal of the load circuit LC. At this time, a potential can be applied to the first terminal of the load circuit LCr from the wiring IOL through the transistor M4r, so that the resistance value between the first and second terminals of the load circuit LCr can be set simultaneously with the load circuit LC.

[0333] The resistance value between the first terminal and the second terminal of each of the load circuits LC and LCr shown in FIGS. 18A and 19 may have two values, three values ​​or more, or may be an analog value.

[0334] <Configuration Example 5> The circuit MP shown in FIG. 20A is a circuit that can be applied to the circuit MP of FIG. 5A, and differs from the circuit MP of FIG. 9A in that the holding unit HC and the holding unit HCr each have an inverter loop circuit configuration instead of the capacitive element C1 and the capacitive element C1r.

[0335] In the circuit MC of the circuit MP in FIG. 20A, the holding unit HC has an inverter circuit INV1 and an inverter circuit INV2. The input terminal of the inverter circuit INV1 is electrically connected to the output terminal of the inverter circuit INV2, the second terminal of the transistor M1, and the gate of the transistor M2. As in the description of FIG. 9A, the electrical connection point between the second terminal of the transistor M1, the gate of the transistor M2, the input terminal of the inverter circuit INV1, and the output terminal of the inverter circuit INV2 is called a node nd1. The node nd1 may be connected to the output terminal of the inverter circuit INV1 instead of the input terminal of the inverter circuit INV1.

[0336] 20A has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0337] The holding unit HC included in the circuit MC has an inverter loop formed by an inverter circuit INV1 and an inverter circuit INV2, and the holding unit HCr included in the circuit MCr has an inverter loop formed by an inverter circuit INV1r and an inverter circuit INV2r. In other words, the circuit MP in Fig. 20A can hold a potential corresponding to a weighting coefficient by the inverter loops of the holding unit HC and the holding unit HCr.

[0338] In the circuit MP of FIG. 20A, the inverter circuit INV1, the inverter circuit INV1r, the inverter circuit INV2, and the inverter circuit INV2r are illustrated, but at least one of the inverter circuits INV1, INV1r, INV2, and INV2r may be replaced with a logic circuit that receives an input signal and outputs an inverted signal of the input signal. The logic circuit may be, for example, a NAND circuit, a NOR circuit, an XOR circuit, or a combination of these. Specifically, when replacing the inverter circuit with a NAND circuit, the NAND circuit can function as an inverter circuit by inputting a high-level potential as a fixed potential to one of the two input terminals of the NAND circuit. Also, when replacing the inverter circuit with a NOR circuit, the NOR circuit can function as an inverter circuit by inputting a low-level potential as a fixed potential to one of the two input terminals of the NOR circuit. Also, when replacing the inverter circuit with an XOR circuit, the XOR circuit can function as an inverter circuit by inputting a high-level potential as a fixed potential to one of the two input terminals of the XOR circuit.

[0339] As described above, the inverter circuit described in this specification can be replaced with a logic circuit such as a NAND circuit, a NOR circuit, an XOR circuit, or a combination of these circuits. Therefore, in this specification, the term "inverter circuit" can be referred to as a "logic circuit."

[0340] The configuration of the circuit MP in Fig. 20A can be changed depending on the situation. An example of a change to the circuit MP in Fig. 20A is shown in Fig. 20B. The circuit MP in Fig. 20B has a configuration in which the holding unit HCr is removed from the circuit MCr of the circuit MP in Fig. 20A, and the holding unit HC of the circuit MC is electrically connected to the gate of the transistor M2r of the circuit MCr.

[0341] 20B, the electrical connection point between the output terminal of the inverter circuit INV1 and the input terminal of the inverter circuit INV2 is defined as a node nd2. That is, the potential of the node nd2 is input to the gate of the transistor M2r.

[0342] 20B, the circuit MCr does not include a holding unit HCr, and the potential provided to the gate of the transistor M2r is held by the holding unit HC of the circuit MC. In addition, since the holding unit HC has an inverter loop configuration consisting of the inverter circuit INV1 and the inverter circuit INV2, the node nd1 holds either a high level potential or a low level potential, and the node nd2 holds the other of the high level potential or the low level potential.

[0343] Due to the configuration of the inverter loop, the holding unit HC cannot hold the same potential at the nodes nd1 and nd2. Therefore, in the circuit MP of Fig. 20B, it is not possible to set a weighting factor represented by holding the same potential at the nodes nd1 and nd2. Specifically, in the above-mentioned operation example, since a low-level potential cannot be held at the gates of the transistors M2 and M2r, it is not possible to set a weighting factor of "0" in the circuit MP of Fig. 20B.

[0344] <Configuration Example 6> The circuit MP shown in FIG. 21A is a circuit that can be applied to the circuit MP of FIG. 5A, and differs from the circuit MP of FIG. 9A in that the holding unit HC and the holding unit HCr each have two transistors and two capacitive elements.

[0345] In the circuit MC of the circuit MP shown in FIG. 21A, the holding unit HC includes a transistor M1, a transistor M1s, a capacitance element C2, and a capacitance element C2s. The first terminal of the transistor M1 is electrically connected to the wiring IL, the second terminal of the transistor M1 is electrically connected to the first terminal of the capacitance element C2 and the gate of the transistor M6, and the gate of the transistor M1 is electrically connected to the wiring WL. The first terminal of the transistor M1s is electrically connected to the wiring IL, the second terminal of the transistor M1s is electrically connected to the first terminal of the capacitance element C2s and the gate of the transistor M7, and the gate of the transistor M1s is electrically connected to the wiring WL. As in the description of FIG. 9A, the electrical connection point between the second terminal of the transistor M1, the gate of the transistor M6, and the first terminal of the capacitance element C2s is called nd1, and the electrical connection point between the second terminal of the transistor M1s, the gate of the transistor M7, and the first terminal of the capacitance element C2s is called nd1s.

[0346] A second terminal of the capacitance element C2 is electrically connected to the wiring X1L, and a second terminal of the capacitance element C2s is electrically connected to the wiring X2L.

[0347] A first terminal of the transistor M6 is electrically connected to a first terminal of the transistor M7 and the wiring VL, a second terminal of the transistor M6 is electrically connected to the wiring OL, and a second terminal of the transistor M7 is electrically connected to the wiring OLB.

[0348] 21A has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0349] The holding unit HC included in the circuit MC has a function of holding a potential by the capacitive elements C2 and C2s. Specifically, a high-level potential is input to the wiring WL to turn on the transistors M1 and M1s, and then a predetermined potential is input to the wiring IL, so that the potential is written to the first terminals of the capacitive elements C2 and C2s. Then, a low-level potential is input to the wiring WL to turn off the transistors M1 and M1s, so that the potential can be held in the nodes nd1 and nd1s of the holding unit HC. When writing and holding a predetermined potential in the holding unit HC, it is preferable that the potentials of the wirings X1L and X2L are constant potentials, for example, and in particular, that the potentials are higher than the low-level potential and lower than the high-level potential. For convenience, the constant potential is called a reference potential.

[0350] Furthermore, in the circuit MP of FIG. 21A, since the wiring WL is electrically connected to each of the holding units HC and HCr, when a potential corresponding to a weighting coefficient is written and held in each of the holding units HC and HCr, a predetermined potential is written to the holding units HC and HCr simultaneously when the potential of the wiring WL is at a high level potential, and then the potential of the wiring WL is set to a low level potential to simultaneously turn off the transistors M1, M1s, M1r, and M1sr.

[0351] Here, the neuron signal input to the circuit MP is defined as follows: When a voltage higher than the reference potential (hereafter referred to as high-level potential) is applied to the wire X1L, and a voltage lower than the reference potential (hereafter referred to as low-level potential) is applied to the wire X2L, a neuron signal of "+1" is input to the circuit MP, when a low-level potential is applied to the wire X1L and a high-level potential is applied to the wire X2L, a neuron signal of "-1" is input to the circuit MP, and when a low-level potential is applied to both the wires X1L and X2L, a neuron signal of "0" is input to the circuit MP.

[0352] For example, when "+1" is input as a neuron signal to the circuit MP after the potentials corresponding to the weighting coefficients are held in the holding units HC and HCr, a high-level potential is input to the wiring X1L, so that the potentials of the nodes nd1 and nd1r are increased by the capacitive coupling of the capacitive elements C2 and C2r. As a result, the potentials of the gates of the transistors M6 and M6r are increased, so that the transistors M6 and M6r are turned on. Also, a low-level potential is input to the wiring X2L, so that the potentials of the nodes nd1s and nd1sr are decreased by the capacitive coupling of the capacitive elements C2s and C2sr. As a result, the potentials of the gates of the transistors M7 and M7r are decreased, so that the transistors M7 and M7r are turned off. In other words, when "+1" is input as a neuron signal to the circuit MP, the circuit MC and the wiring OL are brought into a conductive state, and the circuit MCr and the wiring OLB are brought into a conductive state.

[0353] Also, for example, when "-1" is input as a neuron signal to the circuit MP after the potentials corresponding to the weighting coefficients are held in the holding units HC and HCr, a low-level potential is input to the wiring X1L, so that the potentials of the nodes nd1 and nd1r are lowered by the capacitive coupling of the capacitive elements C2 and C2r. As a result, the potentials of the gates of the transistors M6 and M6r are lowered, so that the transistors M6 and M6r are turned off. Also, a high-level potential is input to the wiring X2L, so that the potentials of the nodes nd1s and nd1sr are higher by the capacitive coupling of the capacitive elements C2s and C2sr. As a result, the potentials of the gates of the transistors M7 and M7r are higher, so that the transistors M7 and M7r are turned on. In other words, when "-1" is input as a neuron signal to the circuit MP, the circuit MC and the wiring OLB are brought into a conductive state, and the circuit MCr and the wiring OL are brought into a conductive state.

[0354] For example, when "0" is input as a neuron signal to the circuit MP after the potentials corresponding to the weighting coefficients are held in the holding units HC and HCr, a low-level potential is input to the wiring X1L, so that the potentials of the nodes nd1 and nd1r are lowered by the capacitive coupling of the capacitive elements C2 and C2r. As a result, the potentials of the gates of the transistors M6 and M6r are lowered, so that the transistors M6 and M6r are turned off. As a low-level potential is input to the wiring X2L, the potentials of the nodes nd1s and nd1sr are lowered by the capacitive coupling of the capacitive elements C2s and C2sr. As a result, the potentials of the gates of the transistors M7 and M7r are lowered, so that the transistors M7 and M7r are turned off. In other words, when "0" is input as a neuron signal to the circuit MP, the circuits MC and MCr are non-conductive with the wirings OL and OLB.

[0355] Note that, as an example, the on-state of the transistor M6, the transistor M6r, the transistor M7, and the transistor M7r preferably operates in a saturation region. Therefore, it is preferable that the gate, source, and drain of each of the transistors M6, M6r, M7, and M7r are appropriately biased so that the transistors operate in a saturation region in the on-state. When the on-state of each of the transistors M6, M6r, M7, and M7r is operated in the saturation region, the gate-source potential increases, and the current flowing between the source-drain of the transistor increases. In other words, when the wiring X1L (wiring X2L) is at a high-level potential, the current flowing between the source-drain of the transistor M6 and the transistor M6r (the transistor M7 and the transistor M7r) is determined by the magnitude of the potential of the node nd1 and the node nd1r (the node nd1s and the node nd1sr). However, one embodiment of the present invention is not limited thereto.

[0356] The configuration of the circuit MP in Fig. 21A can be changed depending on the situation. An example of a change to the circuit MP in Fig. 21A is shown in Fig. 21B. The circuit MP in Fig. 21B has a configuration in which the back gates are removed from the transistors M6, M6r, M7, and M7r in Fig. 21A. Therefore, the transistors M6, M6r, M7, and M7r included in the circuit MP can be determined at the design stage without depending on the structure of the transistors.

[0357] For example, the transistor M6, the transistor M6r, the transistor M7, and the transistor M7r in Fig. 21B may be Si transistors containing single crystal silicon or non-single crystal silicon in an active layer. The transistor M6, the transistor M6r, the transistor M7, and the transistor M7r in Fig. 21B may be OS transistors containing an oxide semiconductor in an active layer. The transistor M6, the transistor M6r, the transistor M7, and the transistor M7r may be transistors containing an organic semiconductor, a compound semiconductor, or the like.

[0358] As described above, by applying the circuit MP of FIGS. 21A and 21B to the arithmetic circuit 110, it is possible to perform calculations of product sums and activation functions in the same way as the circuit MP of FIG. 9A.

[0359] <Configuration Example 7> In the configuration examples 1 to 6, a circuit MP was described that can calculate the product of the weighting coefficients held by the circuit MP, which have three values ​​of "+1", "-1", and "0", and the neuron signal corresponding to the potential input from the wiring X1L and the wiring X2L, which have three values ​​of "+1", "-1", and "0". In this configuration example, as an example, a circuit MP will be described that can calculate the product of the weighting coefficients, which have three values ​​of "+1", "-1", and "0", and the neuron signal (calculated value), which have two values ​​of "+1" and "0".

[0360] The circuit MP shown in Fig. 22A is a circuit obtained by removing the transistors M4 and M4r from the circuit MP in Fig. 9A. Since the transistors M4 and M4r are removed, the wiring X2L for inputting potentials to the gates of the transistors M4 and M4r is also removed in Fig. 22A. The wiring equivalent to the wiring X1L is indicated as wiring XL in Fig. 22A.

[0361] The weighting coefficient set in the circuit MP of FIG. 22A is “+1” when a high level potential is held at node nd1 of the holding unit HC and a low level potential is held at node nd1r of the holding unit HCr, “−1” when a low level potential is held at node nd1 of the holding unit HC and a high level potential is held at node nd1r of the holding unit HCr, and “0” when a low level potential is held at node nd1 of the holding unit HC and a low level potential is held at node nd1r of the holding unit HCr.

[0362] In addition, the neuron signal input to the circuit MP in FIG. 22A is “+1” when a high-level potential is applied to the wiring XL, and is “0” when a low-level potential is applied to the wiring XL.

[0363] For the operation of the circuit MP in FIG. 22A, the explanation of the operation example of the configuration example 1 should be referred to.

[0364] In the circuit MP of FIG. 22A, when the weighting coefficients and the input neuron signals are defined as described above, the current I output from the node outa of the wiring OL is calculated by inputting a neuron signal to the circuit MP for each weighting coefficient. OL and the current I output from node outb of wiring OLB OLB The presence or absence of change is as shown in the table below. Note that in the table below, high level potential is written as "high" and low level potential is written as "low."

[0365] [Table 3]

[0366] As shown in the above table, the circuit MP in FIG. 22A can calculate the product of three weighting coefficient values, "+1", "-1", and "0", and two neuron signals, "+1" and "0". Note that the weighting coefficient may be two-valued, or may have more than two values, instead of three values. For example, it may be two values, "+1" and "0", or two values, "+1" and "-1". Alternatively, the weighting coefficient may be an analog value or a multi-bit (multi-value) digital value.

[0367] In this operation example, the potentials held in the holding units HC and HCr of the circuits MC and MCr in the circuit MP are high level potential and low level potential, but the holding units HC and HCr may hold potentials indicating analog values. For example, when the weighting coefficient is a "positive analog value", a high level analog potential is held in the node nd1 of the holding unit HC, and a low level potential is held in the node nd1r of the holding unit HCr. When the weighting coefficient is a "negative analog value", for example, a low level potential is held in the node nd1 of the holding unit HC, and a high level analog potential is held in the node nd1r of the holding unit HCr. Then, the current I OL and current I OLB The magnitude of the current corresponds to the analog potential.

[0368] The circuit MP in FIG. 22A may have a configuration in which the wiring IL and the wiring ILB are combined into one and the wiring WL is divided into wirings W1L and W2L, similar to the circuit MP in FIG. 16A. Such a circuit configuration is shown in FIG. 22B. The circuit MP in FIG. 22B can be applied to the arithmetic circuit 120 in FIG. 6, as an example. Note that for the operation method of the circuit MP in FIG. 22B, the description of the operation method of the circuit MP in FIG. 16A should be referred to.

[0369] 22A may be configured such that the wiring XL is divided into wirings X1L and X2L. Such a circuit configuration is shown in FIG. 22C. If a high-level potential or a low-level potential is applied to each of the wirings X1L and X2L, there are four combinations of on and off states of the transistors M3 and M3r. If a high-level potential or a low-level potential is applied to the nodes nd1 and nd1r of the holding units HC and HCr, there are four combinations of potentials held at the nodes nd1 and nd1r.

[0370] Specifically, when a high-level potential is held at the node nd1 and a high-level potential is applied to the wiring X1L, the wiring OL and the wiring VL are electrically connected to each other, so that the amount of current I OL In addition, when a high-level potential is held at the node nd1r and a high-level potential is applied to the wiring X2L, the wiring OLB and the wiring VLr are electrically connected to each other, so that the amount of current I OLB In the circuit MP of FIG. 22C, a current I output from a node outa of a wiring OL is determined by a combination of potentials held at the nodes nd1 and nd1r and a combination of potentials applied by the wirings X1L and X2L. OL and the current I output from node outb of wiring OLB OLB The presence or absence of change is as shown in the table below. Note that in the table below, high level potential is written as "high" and low level potential is written as "low."

[0371] [Table 4]

[0372] Next, a circuit having a different configuration from the circuit MP of FIGS. 22A to 22C will be described.

[0373] The circuit MP shown in FIG. 23A is a circuit that calculates the product of three weighting coefficients, "+1", "-1", and "0", and two neuron signals, "+1" and "0", similar to the circuit MP in FIG. 22A, and does not include the transistors M1s, M1sr, M7, and M7r, nor the capacitance elements C2s and C2sr, as in the circuit MP in FIG. 21A. In addition, since the capacitance elements C2s and C2sr are omitted, the wiring X2L for inputting potentials to the second terminals of the capacitance elements C2s and C2sr is also omitted in FIG. 23A. In addition, the wiring equivalent to the wiring X1L is described as wiring XL in FIG. 23A.

[0374] For the operation of FIG. 23A, refer to the description of configuration example 6.

[0375] As in the circuit MP of FIG. 22A, by defining weighting coefficients and neuron signals for the circuit MP of FIG. 23A, the product of the weighting coefficients having three values ​​of "+1", "-1", and "0" and the neuron signals having two values ​​of "+1" and "0" can be calculated as shown in the above table. The weighting coefficients may have two values ​​or more than three values ​​instead of three values. For example, the weighting coefficients may have two values ​​of "+1" and "0", or two values ​​of "+1" and "-1". Alternatively, the weighting coefficients may be analog values ​​or multi-bit (multiple-valued) digital values. For example, the potentials held in the holding units HC and HCr of the circuit MC and circuit MCr of the circuit MP are high level potentials or low level potentials, but the holding units HC and HCr may hold potentials indicating analog values. For example, when the weighting coefficient is a "positive analog value", a high-level analog potential is held at the node nd1 of the holding unit HC, and a low-level potential is held at the node nd1r of the holding unit HCr. When the weighting coefficient is a "negative analog value", for example, a low-level potential is held at the node nd1 of the holding unit HC, and a high-level analog potential is held at the node nd1r of the holding unit HCr. Then, the current I OL and current I OLB The magnitude of the current corresponds to the analog potential.

[0376] The circuit MP in FIG. 23A may have a configuration in which the wiring IL and the wiring ILB are combined into one wiring, and the wiring WL is divided into wiring W1L and wiring W2L, similar to the circuit MP in FIG. 16A. Such a circuit configuration is shown in FIG. 23B. The circuit MP in FIG. 23B can be applied to the arithmetic circuit 120 in FIG. 6, as an example. Note that for the operation method of the circuit MP in FIG. 23B, the description of the operation method of the circuit MP in FIG. 16A should be referred to.

[0377] 23A may be configured to divide the wiring XL into wirings X1L and X2L, similarly to the circuit MP of FIG. 22C. Such a circuit configuration is shown in FIG. 23C. If a high-level potential or a low-level potential is applied to each of the wirings X1L and X2L, the on-state and off-state of each of the transistors M6 and M6r are combined in four ways. If a high-level potential or a low-level potential is held in the nodes nd1 and nd1r of the holding units HC and HCr, respectively, the potentials held in the nodes nd1 and nd1r are combined in four ways. Note that, for example, the potentials held in the holding units HC and HCr of the circuits MC and MCr of the circuit MP are set to a high-level potential or a low-level potential, but the holding units HC and HCr may hold potentials indicating analog values. For example, when the weighting coefficient is a "positive analog value", a high-level analog potential is held at the node nd1 of the holding unit HC, and a low-level potential is held at the node nd1r of the holding unit HCr. When the weighting coefficient is a "negative analog value", for example, a low-level potential is held at the node nd1 of the holding unit HC, and a high-level analog potential is held at the node nd1r of the holding unit HCr. Then, the current I OL and current I OLB The magnitude of the current corresponds to the analog potential.

[0378] In the circuit MP of FIG. 23C, the change in the current flowing through the wiring OL and the wiring OLB can be considered similarly to the circuit MP of FIG. 22C. Therefore, in the circuit MP of FIG. 23C, the current I output from the node outa of the wiring OL, which is determined by the combination of the potentials held at the nodes nd1 and nd1r and the combination of the potentials applied by the wirings X1L and X2L, OL and the current I output from node outb of wiring OLB OLB The presence or absence of change is as shown in the above table explained for the circuit MP in FIG. 22C.

[0379] <Configuration Example 8> The circuit MP shown in FIG. 24A is an example of a circuit that can be applied to the circuit MP of FIG. 5F.

[0380] The circuit MP in FIG. 24A includes a circuit MC, a circuit MCr, and a transistor MZ.

[0381] 24A has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0382] Moreover, the circuit MC has a holding unit HC and a transistor M8, and the circuit MCr has a holding unit HCr and a transistor M8r.

[0383] The holding unit HC included in the circuit MC of the circuit MP of Figure 24A can be configured in the same manner as the holding unit HC included in the circuit MC of the circuit MP of Figures 9A to 9C, 10A, 10B, 11A, 11B, 12A, and 12B, for example.

[0384] A first terminal of the transistor M8 is electrically connected to a first terminal of the transistor MZ, a gate of the transistor M8 is electrically connected to a second terminal of the transistor M1 and a first terminal of the capacitance element C1, and a second terminal of the transistor M8 is electrically connected to the wiring OL. A second terminal of the capacitance element C1 is electrically connected to the wiring CVL. A first terminal of the transistor M1 is electrically connected to the wiring IL.

[0385] A first terminal of the transistor M8r is electrically connected to a first terminal of the transistor MZ, a gate of the transistor M8r is electrically connected to a second terminal of the transistor M1r and a first terminal of the capacitance element C1r, and a second terminal of the transistor M8r is electrically connected to the wiring OLB. A second terminal of the capacitance element C1r is electrically connected to the wiring CVL. A first terminal of the transistor M1 is electrically connected to the wiring ILB.

[0386] The line CVL functions as, for example, a line that applies a constant voltage, which may be, for example, a high-level potential, a low-level potential, or a ground potential.

[0387] The holding unit HC and the holding unit HCr included in the circuit MP of Fig. 24A can hold a potential corresponding to the weighting coefficient, similar to the holding unit HC and the holding unit HCr included in the circuit MP shown in Fig. 9A etc. Specifically, for example, a predetermined potential may be applied to the wiring WL to turn on the transistor M1 and the transistor M1r, a potential may be supplied from the wiring IL to the first terminal of the capacitance element C1, and a potential may be supplied from the wiring ILB to the first terminal of the capacitance element C1r. After that, a predetermined potential may be applied to the wiring WL to turn off the transistor M1 and the transistor M1r.

[0388] Here, for example, the weighting coefficient set in the circuit MP of FIG. 24A is “+1” when a high level potential is held at node nd1 of the holding unit HC and a low level potential is held at node nd1r of the holding unit HCr, “−1” when a low level potential is held at node nd1 of the holding unit HC and a high level potential is held at node nd1r of the holding unit HCr, and “0” when a low level potential is held at node nd1 of the holding unit HC and a low level potential is held at node nd1r of the holding unit HCr.

[0389] The potentials of the gates of the transistors M8 and M8r are determined by holding potentials according to the weighting coefficients in the holding units HC and HCr, respectively. Here, the current flowing from the circuit MP to the wiring IL and / or the wiring ILB is determined by applying a potential according to the value of a neuron signal to the wiring XL. For example, when a high-level potential is applied to the wiring XL as the second data of "1", a constant voltage provided by the wiring VL is applied to the first terminal of the transistor M8 and the first terminal of the transistor M8r. At this time, when the potential of the gate of the transistor M8 is a high-level potential, a current flows between the first and second terminals of the transistor M8, and when the potential of the gate of the transistor M8 is a low-level potential, no current flows between the first and second terminals of the transistor M8. Similarly, when the gate potential of the transistor M8r is at a high level potential, a current flows between the first and second terminals of the transistor M8r, and when the gate potential of the transistor M8r is at a low level potential, no current flows between the first and second terminals of the transistor M8r. Also, for example, when a low level potential is applied to the line XL as the second data of "0", the constant voltage provided by the line VL is not applied to the first terminal of the transistor M8 and the first terminal of the transistor M8r, so that no current flows between the first and second terminals of the respective transistors.

[0390] In other words, to summarize the above, when the product of the weighting coefficient and the value of the neuron's signal is "+1", a certain current flows from the circuit MC to the wiring OL, and a certain current does not flow from the circuit MCr to the wiring OLB. Also, when the product of the weighting coefficient and the value of the neuron's signal is "-1", a certain current flows from the circuit MCr to the wiring OLB, and a certain current does not flow from the circuit MC to the wiring OL. Also, when the product of the weighting coefficient and the value of the neuron's signal is "0", a certain current does not flow from the circuit MC to the wiring OL, and a certain current does not flow from the circuit MCr to the wiring OLB.

[0391] 24A can calculate the product of three weighting coefficient values ​​of "+1", "-1", and "0" and two neuron signals (calculated values) of "+1" and "0", similar to the circuit MP described in configuration example 7. Also, the circuit MP in FIG. 24A may use analog values, multi-bit (multiple-value) digital values, etc. as weighting coefficients, similar to the circuit MP described in configuration example 7.

[0392] The circuit MP in FIG. 24A, which can be applied to an arithmetic circuit that is a semiconductor device of one embodiment of the present invention, may be modified as appropriate depending on the situation.

[0393] For example, when applying the circuit MP of FIG. 7 to the arithmetic circuit 130, the circuit MP of FIG. 24A may be changed to the circuit MP of FIG. 24B. The circuit MP of FIG. 24B is configured such that the wiring OL and the wiring IL in the circuit MP of FIG. 24A are combined into one wiring IOL, and the wiring OLB and the wiring ILB are combined into one wiring IOLB. The wiring XL shown in FIG. 24B corresponds to any one of the wirings XLS[1] to XLS[m] shown in FIG. 7, and the wiring WL shown in FIG. 24B corresponds to any one of the wirings WLS[1] to WLS[m] shown in FIG. 7.

[0394] Moreover, the circuit that can be applied to the circuit MP of FIG. 5A is not limited to the circuit MP of FIG. 24A.

[0395] For example, the circuit MP of Fig. 18A described in the configuration example 4 can be modified to a circuit applicable to the circuit MP of Fig. 5A. The circuit MP shown in Fig. 25A is a circuit applicable to the circuit MP of Fig. 5A, and has a holding unit HC including a load circuit LC and a holding unit HCr including a load circuit LCr, similar to Fig. 18A. For the operation of Fig. 25A, the explanation of the operation examples of the circuit MP of Fig. 24A and the circuit MP of Fig. 18A should be referred to.

[0396] 25A to the arithmetic circuit 130 in FIG. 7, the circuit MP in FIG. 25A may be changed to the circuit MP in FIG. 25B. The circuit MP in FIG. 25B is configured such that the wirings OL and IL are combined into a single wiring IOL, the wirings OLB and ILB are combined into a single wiring IOLB, and the transistors M1 and M1r are not provided. The wiring XL in FIG. 25B corresponds to any one of the wirings XLS[1] to XLS[m] in FIG. 7, and the wiring WL in FIG. 25B corresponds to any one of the wirings WLS[1] to WLS[m] in FIG. 7.

[0397] Also, for example, the circuit MP of FIG. 20A described in the configuration example 5 can be modified to a circuit applicable to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 26A is a circuit applicable to the circuit MP of FIG. 5A, and has a holding unit HC including the inverter circuit INV1 and the inverter circuit INV2, and a holding unit HCr including the inverter circuit INV1r and the inverter circuit INV2r, as in FIG. 20A. Note that the circuit MP of FIG. 26A does not include the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r. Note that the operation of FIG. 26A should be referred to the explanation of the operation examples of the circuit MP of FIG. 24A and the circuit MP of FIG. 20A.

[0398] Also, for example, the circuit MP of FIG. 20B described in the configuration example 5 can be modified to a circuit applicable to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 26B is a circuit applicable to the circuit MP of FIG. 5A, and has a holding unit HC including an inverter circuit INV1 and an inverter circuit INV2 as in FIG. 20B. Note that the circuit MP of FIG. 26B does not include the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r. Note that the operation of FIG. 26B should be referred to the explanation of the operation examples of the circuit MP of FIG. 24A and the circuit MP of FIG. 20B.

[0399] Also, for example, the circuit MP of FIG. 22A described in the configuration example 7 can be modified to a circuit applicable to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 27A is a circuit applicable to the circuit MP of FIG. 5A, and is a modified example of the circuit MP of FIG. 22A. The circuit MP of FIG. 22A is different from the circuit MP of FIG. 22A in that the second terminal of the capacitance element C1 is electrically connected to the wiring VL, the second terminal of the capacitance element C1r is electrically connected to the wiring VL, the first terminal of the transistor M2 and the first terminal of the transistor M2 are electrically connected to the first terminal of the transistor MZ, the transistor M3 and the transistor M3r are not provided, and the like. For the operation of FIG. 27A, the explanation of the operation examples of the circuit MP of FIG. 24A and the circuit MP of FIG. 22A should be referred to.

[0400] For example, when applying the circuit MP of FIG. 27A to the arithmetic circuit 120 of FIG. 6, the circuit MP of FIG. 27A may be changed to the circuit MP of FIG. 27B. The circuit MP of FIG. 27B is configured by combining the wiring IL and the wiring ILB of the circuit MP of FIG. 27A into a single wiring IL. The wiring XL shown in FIG. 27B corresponds to any one of the wirings XLS[1] to XLS[m] shown in FIG. 6, and the wiring WL shown in FIG. 27B corresponds to any one of the wirings WLS[1] to WLS[m] shown in FIG. 6.

[0401] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0402] (Embodiment 3) In this embodiment, a structural example of an OS transistor that can be used in the semiconductor device described in the above embodiment will be described.

[0403] <Example of semiconductor device configuration> The semiconductor device shown in Fig. 28 includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 30A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 30B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 30C is a cross-sectional view of the transistor 300 in the channel width direction.

[0404] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). Since the off-state current of the transistor 500 is small, the use of the transistor 500 for a semiconductor device, particularly for the transistors M1, M3, and M4 of the circuit MP included in the arithmetic circuit 110, enables written data to be held for a long period of time. In other words, the frequency of refresh operations is low or the refresh operations are not required, thereby reducing the power consumption of the semiconductor device.

[0405] The transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistor 300 and the transistor 500. Note that the capacitor 600 can be the capacitor C1, the capacitor C1r, or the like in the circuit MP.

[0406] The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. Note that the transistor 300 can be applied to, for example, the transistor in the above embodiment.

[0407] 30C, the upper surface and the side surface in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this manner, the effective channel width is increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 300.

[0408] The transistor 300 may be either a p-channel type or an n-channel type.

[0409] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0410] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0411] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0412] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0413] 28 is just an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the transistor 300 may have a similar structure to that of a transistor 500 including an oxide semiconductor, as shown in FIG 29. Details of the transistor 500 will be described later.

[0414] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300.

[0415] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0416] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0417] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 300 provided thereunder. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0418] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

[0419] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0420] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0421] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0422] A conductor 328, a conductor 330, and the like that connect to the capacitor 600 or the transistor 500 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as a plug or a wiring. In addition, a plurality of conductors that function as a plug or a wiring may be collectively given the same reference symbol. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, there are cases where a part of a conductor functions as a wiring and a case where a part of a conductor functions as a plug.

[0423] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0424] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 28 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0425] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0426] Note that, for example, tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, it is possible to suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0427] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 28, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0428] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0429] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 28, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0430] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0431] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 28, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0432] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0433] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0434] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen or hydrogen.

[0435] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0436] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0437] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0438] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0439] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0440] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0441] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistors 300 and 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0442] Above the insulator 516 is a transistor 500 .

[0443] As shown in Figures 30A and 30B, a transistor 500 has a conductor 503 arranged so as to be embedded in an insulator 514 and an insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therebetween overlapping with the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the formation surface of the oxide 530c, and a conductor 560 arranged on the formation surface of the insulator 550.

[0444] 30A and 30B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a, as shown in FIG. 30A and 30B. It is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550, as shown in FIG. 30A and 30B.

[0445] In the following, oxide 530a, oxide 530b, and oxide 530c may be collectively referred to as oxide 530.

[0446] In the transistor 500, a three-layer structure of oxides 530a, 530b, and 530c is shown in the region where a channel is formed and in the vicinity thereof, but the present invention is not limited thereto. For example, a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers may be provided. In addition, in the transistor 500, the conductor 560 is shown as having a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. In addition, the transistor 500 shown in FIG. 28 and FIG. 30A is an example, and the present invention is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

[0447] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0448] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. As a result, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0449] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made higher than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to when a negative potential is not applied.

[0450] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0451] The conductor 503 has a structure similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inside. Note that, although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer or a stacked structure of three or more layers.

[0452] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate through). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or the oxygen.

[0453] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and the conductivity from decreasing.

[0454] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 503b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium, titanium nitride, and the above-mentioned conductive material.

[0455] The insulators 520, 522, 524, and 550 function as a second gate insulating film.

[0456] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0457] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×1018 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more than 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

[0458] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O H→V O A reaction of "H+H" occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form HO, and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542 (conductor 542a and conductor 542b).

[0459] In addition, the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. In addition, the pressure of the microwave treatment may be set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, for example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0460] In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0461] In addition, by subjecting the oxide 530 to an oxygen supplying treatment, the oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OIn addition, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0462] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0463] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, so that oxygen contained in the oxide 530 does not diffuse toward the insulator 520. Furthermore, reaction of the conductor 503 with the insulator 524 or oxygen contained in the oxide 530 can be suppressed.

[0464] The insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0465] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0466] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0467] In addition, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable laminated structure with a high relative dielectric constant.

[0468] 30A and 30B, the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a three-layer stack structure, but the second gate insulating film may have a single layer, a two-layer, or a four or more layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may be a stack structure made of different materials.

[0469] In the transistor 500, it is preferable to use a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) may be used for the oxide 530. In particular, it is preferable that the In-M-Zn oxide applicable to the oxide 530 is CAAC-OS or CAC-OS described in the fourth embodiment. Alternatively, the oxide 530 may be In-Ga oxide or In-Zn oxide.

[0470] In addition, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. In order to reduce the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be reduced to reduce the defect state density. In this specification and the like, a low impurity concentration and a low defect state density are referred to as high purity intrinsic or substantially high purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0471] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which may cause oxygen vacancies in the metal oxide. In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen are bonded to form V O May form H. V O H functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. In addition, hydrogen in a metal oxide is easily mobile due to stress such as heat or an electric field, so if a metal oxide contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 OIt is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to compensate for the oxygen deficiency (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be obtained.

[0472] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for a metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in a metal oxide, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide, instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration".

[0473] Therefore, when a metal oxide is used for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0474] In addition, when a metal oxide is used for the oxide 530, the carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0475] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductor 542 (conductor 542a and conductor 542b) and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductor 542, resulting in the oxidation of the conductor 542. The oxidation of the conductor 542 is likely to result in a decrease in the conductivity of the conductor 542. The diffusion of oxygen in the oxide 530 into the conductor 542 can be rephrased as the conductor 542 absorbing the oxygen in the oxide 530.

[0476] Furthermore, oxygen in the oxide 530 may diffuse into the conductor 542 (conductor 542a and conductor 542b), forming insulating regions at and near the interface between the conductor 542a and the oxide 530b, and at and near the interface between the conductor 542b and the oxide 530b. Since the regions contain more oxygen than the conductor 542, the regions are presumed to have higher electrical resistance than the conductors 542a and 542b. In this case, the three-layer structure of the conductor 542, the regions, and the oxide 530b can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure, or a diode junction structure mainly based on the MIS structure.

[0477] It should be noted that the insulating region is not limited to being formed between the conductor 542 and the oxide 530b. For example, the insulating region may be formed between the conductor 542 and the oxide 530c, between the conductor 542 and the oxide 530b, and between the conductor 542 and the oxide 530c.

[0478] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0479] The oxide 530 has the oxide 530a below the oxide 530b, so that the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b can be suppressed. Also, the oxide 530 has the oxide 530c on the oxide 530b, so that the diffusion of impurities from structures formed above the oxide 530c to the oxide 530b can be suppressed.

[0480] The oxide 530 preferably has a laminated structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a. In addition, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0481] In addition, the energy of the conduction band minimum of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0482] Here, the energy level of the conduction band minimum changes gradually at the junction of the oxide 530a, the oxide 530b, and the oxide 530c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

[0483] Specifically, the oxides 530a and 530b, and the oxides 530b and 530c have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxides 530a and 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0484] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0485] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0486] 30, the conductor 542a and the conductor 542b are shown as a single-layer structure, but may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. Alternatively, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0487] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0488] 30A , regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0489] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0490] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0491] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0492] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later step. Note that the insulator 544 is not an essential component when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or when the conductivity does not decrease significantly even when oxygen is absorbed. It may be designed appropriately depending on the desired transistor characteristics.

[0493] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 580 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0494] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0495] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0496] By providing an insulator that releases oxygen when heated as the insulator 550 in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0497] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0498] The insulator 550 may have a laminated structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0499] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 30A and 30B, it may have a single-layer structure or a laminated structure of three or more layers.

[0500] The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). When the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0501] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium, titanium nitride, and the above conductive material.

[0502] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particu...

Claims

1. A semiconductor device having a first circuit and a second circuit, the first circuit includes first to fourth transistors and a first capacitor; the second circuit includes fifth to eighth transistors and a second capacitor; a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and a first terminal of the first capacitance element; one of a source and a drain of the second transistor is electrically connected to a second terminal of the first capacitance element; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor and one of the source and the drain of the fourth transistor; a gate of the third transistor is electrically connected to a first input wiring; a gate of the fourth transistor is electrically connected to a second input wiring; the other of the source and the drain of the third transistor is electrically connected to a first wiring; the other of the source and the drain of the fourth transistor is electrically connected to a second wiring; a gate of the sixth transistor is electrically connected to one of the source and the drain of the fifth transistor and a first terminal of the second capacitance element; one of a source and a drain of the sixth transistor is electrically connected to a second terminal of the second capacitance element; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor and one of the source and the drain of the eighth transistor; a gate of the seventh transistor is electrically connected to the first input wiring; a gate of the eighth transistor is electrically connected to the second input wiring; the other of the source and the drain of the seventh transistor is electrically connected to the second wiring; the other of the source and the drain of the eighth transistor is electrically connected to the first wiring; Semiconductor device.

2. A semiconductor device having a first circuit and a second circuit, the first circuit includes first to fourth transistors, a ninth transistor, and a first capacitor; the second circuit includes fifth to eighth transistors, a tenth transistor, and a second capacitor; a gate of the second transistor is electrically connected to one of the source and the drain of the first transistor, a gate of the ninth transistor, and a first terminal of the first capacitance element; one of a source and a drain of the second transistor is electrically connected to a second terminal of the first capacitance element and one of a source and a drain of the ninth transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; a gate of the third transistor is electrically connected to a first input wiring; a gate of the fourth transistor is electrically connected to a second input wiring; the other of the source and the drain of the third transistor is electrically connected to a first wiring; one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the ninth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a second wiring; a gate of the sixth transistor is electrically connected to one of the source and the drain of the fifth transistor, a gate of the tenth transistor, and a first terminal of the second capacitance element; one of a source and a drain of the sixth transistor is electrically connected to a second terminal of the second capacitance element and one of a source and a drain of the tenth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a gate of the seventh transistor is electrically connected to the first input wiring; a gate of the eighth transistor is electrically connected to the second input wiring; the other of the source and the drain of the seventh transistor is electrically connected to the second wiring; one of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the tenth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the first wiring; Semiconductor device.

3. In claim 1 or 2, the first circuit has a function of holding a first potential corresponding to first data at a gate of the second transistor; the second circuit has a function of holding a second potential corresponding to the first data at a gate of the sixth transistor; the first circuit has a function of outputting a current corresponding to the first potential to the first wiring, a function of outputting a current corresponding to the first potential to the second wiring, and a function of not outputting a current corresponding to the first potential to the first wiring and the second wiring; the second circuit has a function of outputting a current corresponding to the second potential to the second wiring, a function of outputting a current corresponding to the second potential to the first wiring, and a function of not outputting a current corresponding to the second potential to the first wiring and the second wiring. Semiconductor device.

4. A semiconductor device according to any one of claims 1 to 3, An electronic device that performs neural network calculations using the semiconductor device.

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