Wiring Board

Abstract

To provide a wiring board improved in quality.SOLUTION: A wiring board 100 of an embodiment includes: a core substrate 3 having a first surface 3a and a second surface 3b; a first laminate 1 comprising insulating layers 1a to 1d and conductor layers 11 to 14 on the first surface 3a; a second laminate 2 comprising insulating layers 2a to 2d and conductor layers 21 to 24 on the second surface 3b; and laminated conductor groups 4a, 4b including a plurality of via conductors penetrating through the insulating layers 1a to 1d or the insulating layers 2a to 2d, respectively, the laminated conductor groups penetrating through the first laminate 1 or the second laminate 2. The laminated conductor group 4b includes roughened conductor pads 44, 45 having surfaces which are covered with coating films to be roughened, the coating films improving adhesion between the insulating layers 2b to 2d and the conductor layers 21 to 23, and also includes a second via conductor 42 and a first via conductor 41 having a width greater than the width of the second via conductor 42, the first via being connected to the roughened conductor pad 45 on a core substrate 3 side.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses that, with respect to a printed wiring board, a chemical conversion coating is formed on the surface of a low-roughness or non-roughness metal wiring layer, and an insulating resin layer is formed on the metal wiring layer via this chemical conversion coating. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-172759 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a wiring board in which wiring layers and insulating layers are laminated on top of each other, such as the printed wiring board disclosed in Patent Document 1, the interface between the conductor layer and the via conductor that connects adjacent wiring layers via the insulating layer may not be able to withstand the stress applied to the wiring board and may peel off, which may result in deterioration of the quality of the printed wiring board. [Means for solving the problem]

[0005] The wiring board of the present invention includes a core substrate having a first surface and a second surface opposite to the first surface, the core substrate including inner-layer conductor layers formed on the first surface and the second surface, a first laminate formed on the first surface and composed of insulating layers and conductor layers alternately laminated, a second laminate formed on the second surface and composed of insulating layers and conductor layers alternately laminated, and a laminated conductor group including a plurality of via conductors penetrating the insulating layers constituting the first laminate or the second laminate, the laminated conductor group further including a roughened conductor pad having a roughened surface covered with a coating film that improves adhesion between the conductor layers constituting the first laminate or the second laminate and the insulating layers, the plurality of via conductors including a second via conductor and a first via conductor having a width larger than the width of the second via conductor and connected to the roughened conductor pad at an end face on the core substrate side.

[0006] According to an embodiment of the present invention, it may be possible to suppress deterioration in the quality of a wiring board caused by, for example, interfacial peeling between a conductor layer and a via conductor due to stress concentration in the wiring board. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a plan view showing an example of a laminated conductor group in one embodiment of the present invention. [Diagram 3] An enlarged view of part III in Fig. 1 . [Figure 4] 6 is a cross-sectional view showing another example of a via conductor in a laminated conductor group in the embodiment of the present invention. [Diagram 5] FIG. 11 is a cross-sectional view showing an example of a wiring board according to another embodiment of the present invention. [Figure 6] An enlarged view of part VI in Figure 5. [Figure 7A] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 7B]5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 7C] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 7D] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 7E] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 7F] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 7G] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. [Figure 7H] 5A to 5C are cross-sectional views showing an example of a manufacturing process of the wiring board according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] (First embodiment) A wiring board according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring board 100, which is an example of the wiring board of this embodiment, and FIG. 2 is a plan view (a plan view projected from below in FIG. 1) showing an example of a laminated conductor group 4b included in the wiring board 100. FIG. 3 shows an enlarged view of part III in FIG. 1, which is the periphery of the laminated conductor group 4b. Note that the wiring board 100 is merely an example of the wiring board of this embodiment. The number of each of the conductor layers and insulating layers included in the wiring board of the embodiment is not limited to the number of each of the conductor layers and insulating layers included in the wiring board 100 of FIG. 1.

[0009] As shown in FIG. 1, the wiring board 100 includes a core board 3 having two main surfaces (a first surface 3a and a second surface 3b opposite to the first surface 3a) facing each other in the thickness direction of the wiring board 100, a first laminate 1, and a second laminate 2. The core board 3 is a starting board when manufacturing the wiring board 100. That is, the first laminate 1 is formed on the first surface 3a of the core board 3, and the second laminate 2 is formed on the second surface 3b. The core board 3 includes an insulating layer 32 constituting the majority of the core board 3, and conductor layers (inner-layer conductor layers) 31 formed on each of the first surface 3a and the second surface 3b. The core board 3 further includes through-hole conductors 33 that penetrate the insulating layer 32 and connect the conductor layers 31 on both sides of the insulating layer 32.

[0010] In the description of the embodiment, the side of the wiring board 100 farther from the insulating layer 32 in the thickness direction is also referred to as the "upper side," "outer side," "upper side," or simply "upper," and the side closer to the insulating layer 32 is also referred to as the "lower side," "inner side," "lower side," or simply "lower." Furthermore, in each element included in the wiring board 100, the surface or end face facing the opposite side to the insulating layer 32 is also referred to as the "upper surface," and the surface or end face facing the insulating layer 32 is also referred to as the "lower surface" or "bottom surface."

[0011] The first laminate 1 and the second laminate 2 are each a laminate of insulating layers and conductor layers that are configured by alternately stacking insulating layers and conductor layers. In the wiring board 100, the first laminate 1 is formed by alternately stacking four insulating layers (insulating layers 1a-1d) and four conductor layers (conductor layers 11-14). Meanwhile, the second laminate 2 is formed by alternately stacking four insulating layers (insulating layers 2a-2d) and four conductor layers (conductor layers 21-24). The first laminate 1 and the second laminate 2 are build-up parts of the wiring board 100 that sandwich the core board 3.

[0012] A solder resist 6 is formed on the insulating layer 1d and the conductor layer 14. A solder resist 6 is also formed on the insulating layer 2d and the conductor layer 24. The solder resist 6 has an opening 6a that exposes a part of the conductor layer 14 or the conductor layer 24. The solder resist 6 is made of, for example, a photosensitive epoxy resin or a polyimide resin.

[0013] In each of the insulating layers 1a to 1d and the insulating layers 2a to 2d, a via conductor (first via conductor 41 or second via conductor 42) is formed, which penetrates each insulating layer and connects adjacent conductor layers via each insulating layer. In each of the insulating layers 1a to 1d and the insulating layers 2a to 2d, any number of any of the first via conductors 41 and the second via conductors 42 may be formed. In the wiring board 100 of the example of FIG. 1, the first via conductor 41 is formed in the insulating layer 2b, and the second via conductor 42 is formed in the other insulating layers (insulating layers 1a to 1d, 2a, 2c, and 2d). The first via conductor 41 and the second via conductor 42 have different sizes. The first via conductor 41 is a via conductor having a width larger than that of the second via conductor 42.

[0014] The insulating layers 1a to 1d, 2a to 2d, and 32 are formed of any insulating resin. Examples of the insulating resin include epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. In the example of FIG. 1, the insulating layer 32 includes a core material (reinforcing material) 32a formed of glass fiber, aramid fiber, or the like. Although not shown in FIG. 1, each insulating layer other than the insulating layer 32 may also include a core material made of glass fiber or the like. Each insulating layer may further include an inorganic filler (not shown) made of fine particles of silica (SiO2), alumina, mullite, or the like.

[0015] The conductor layers 11-14, 21-24, 31, the first and second via conductors 41, 42, and the through-hole conductor 33 may each be formed using any metal such as copper or nickel. In the example of FIG. 1, the conductor layer 31 includes a metal foil 31a, a metal film 31b, and a plating film 31c, which is, for example, an electrolytic plating film. The through-hole conductor 33 is formed integrally with the conductor layer 31 and is composed of the metal film 31b and the plating film 31c. Meanwhile, the conductor layers 11-14, 21-24, and the first and second via conductors 41, 42 are each composed of the metal film 10b and the plating film 10c, which is, for example, an electrolytic plating film. The metal film 31b and the metal film 10b are, for example, an electroless plating film or a sputtering film, and function as a power supply layer when the plating film 31c and the plating film 10c are formed by electrolytic plating, respectively. The first and second via conductors 41, 42 are formed integrally with the respective conductor layers which they connect to above.

[0016] Each of the conductor layers 11 to 14 and the conductor layers 21 to 24 includes a predetermined conductor pattern. In the example of Fig. 1, the conductor layer 22 includes a conductor pad 44, and each of the conductor layers 11 to 14, 21, 23, and 24 other than the conductor layer 22 includes a conductor pad 45. Each of the conductor layers 21 to 23 includes a wiring pattern 20.

[0017] The wiring board 100 further includes a laminated conductor group 4a and a laminated conductor group 4b, which are laminates of conductors constituted by stacked conductors. The laminated conductor group 4a penetrates the first laminate 1, and the laminated conductor group 4b penetrates the second laminate 2. The wiring board 100 in the example of FIG. 1 includes both the laminated conductor group 4a and the laminated conductor group 4b. However, the wiring board of the embodiment may include only one of the laminated conductor group penetrating the first laminate 1 and the laminated conductor group penetrating the second laminate 2. In addition, although the wiring board 100 includes a plurality of laminated conductor groups 4a and 4b, the wiring board of the embodiment may include at least one laminated conductor group.

[0018] In the wiring board 100, a part of the laminated conductor group 4a is laminated on the through-hole conductor 33 on the first surface 3a side of the core board 3, and a part of the laminated conductor group 4b is laminated on the through-hole conductor 33 on the second surface 3b side. That is, the wiring board 100 includes the laminated conductor group 4a, the through-hole conductor 33, and the laminated conductor group 4b, which are at least partially overlapped in a plan view. The wiring board 100 is linearly penetrated by the laminated conductor group 4a, the through-hole conductor 33, and the laminated conductor group 4b. Note that "plan view" refers to the wiring board of the embodiment viewed along a line of sight along its thickness direction.

[0019] As shown in Fig. 1, each of the laminated conductor groups 4a and 4b includes a plurality of laminated via conductors (first via conductors 41 and / or second via conductors 42). That is, the laminated conductor groups 4a and 4b are so-called stacked via conductors. Each of the plurality of via conductors penetrates one of the insulating layers 1a to 1d or one of the insulating layers 2a to 2d. The laminated conductor group 4a includes a plurality of second via conductors 42 as the plurality of via conductors, and all of the plurality of second via conductors 42 included in the laminated conductor group 4a overlap each other in a plan view. The plurality of second via conductors 42 included in the laminated conductor group 4a penetrates each of the insulating layers 1a to 1d.

[0020] The laminated conductor group 4b includes, as a plurality of via conductors, a plurality of second via conductors 42 and a first via conductor 41 having a width larger than that of the second via conductor 42. All of the second via conductors 42 and the first via conductors 41 included in the laminated conductor group 4b overlap each other in a planar view. The second via conductors 42 included in the laminated conductor group 4b penetrate each of the insulating layers 2a, 2c, and 2d, and the first via conductor 41 penetrates the insulating layer 2b.

[0021] Among the insulating layers 2a to 2d constituting the second laminate 2, the insulating layer 2b is the second closest to the core substrate 3 after the insulating layer 2a. In the example of FIG. 1, in addition to the first via conductor 41 included in the laminated conductor group 4b, one or more first via conductors 41 are formed in the insulating layer 2b to connect the conductor layer 21 and the conductor layer 22. All the via conductors that penetrate the insulating layer 2b have the same width. That is, all the via conductors formed in the insulating layer 2b are the first via conductors 41. It is considered that it is easy to form the via conductors in the insulating layer 2b.

[0022] The laminated conductor group 4a further includes a conductor pad 45 included in each of the conductor layers 11-14. That is, the laminated conductor group 4a is a laminate of a plurality of via conductors and a plurality of conductor pads, which are configured by second via conductors 42 penetrating each of the insulating layers 1a-1d and a plurality of conductor pads 45. Each conductor pad 45 is alternately stacked with each of the plurality of second via conductors 42 constituting the laminated conductor group 4a. The laminated conductor group 4a may include any number of conductor pads (conductor pads 44 and / or conductor pads 45) equal to or greater than two depending on the number of conductor layers constituting the first laminate 1.

[0023] 1 to 3, the laminated conductor group 4b further includes a conductor pad 44 included in the conductor layer 22, and a plurality of conductor pads 45 included in each of the conductor layers 21, 23, and 24. That is, the laminated conductor group 4b is a laminate of a plurality of via conductors and a plurality of conductor pads, which is composed of a first via conductor 41, three second via conductors 42, a conductor pad 44, and three conductor pads 45. The laminated conductor group 4b may include any number of conductor pads (conductor pads 44 and / or conductor pads 45) equal to or greater than two depending on the number of conductor layers constituting the second laminate 2.

[0024] In the example of FIG. 1, the first via conductor 41 included in the laminated conductor group 4b has the largest width among the via conductors included in the laminated conductor group 4b. The "width" of each via conductor (the first via conductor 41 and the second via conductor 42) included in each of the laminated conductor groups 4a and 4b is the longest distance between any two points on the periphery of each via conductor in a planar view. Each via conductor included in each of the laminated conductor groups 4a and 4b can have any planar shape. For example, when each via conductor has a circular planar shape, the width of each via conductor is the diameter of the planar shape of each via conductor.

[0025] In the laminated conductor group 4b of the wiring board 100 illustrated in Fig. 1, as illustrated in Fig. 2, the second via conductor 42 entirely overlaps with the first via conductor 41 in a plan view, and the second via conductor 42 entirely is included in the first via conductor 41 in a plan view. In the wiring board 100 illustrated in Fig. 1, both the first via conductor 41 and the second via conductor 42 have a tapered shape that tapers from the outside (upper side) toward the inside (lower side). As illustrated in Fig. 2, both the outer edge 42a of the upper surface and the outer edge 42b of the lower surface of the second via conductor 42 are located inside the outer edge 41a of the upper surface of the first via conductor 41, and are further located inside the outer edge 41b of the lower surface of the first via conductor 41.

[0026] In general, various stresses such as mechanical stress or thermal stress may be applied to a wiring board due to the action of an external force or changes in the ambient temperature. In a wiring board including so-called stack via conductors that penetrate the build-up portion (the first laminate 1 or the second laminate 2), such as the laminated conductor groups 4a and 4b of the wiring board 100, the stress due to the stress may be concentrated on the via conductors of a specific insulating layer due to, for example, differences in the copper remaining ratio of each conductor layer. In a via conductor that is subjected to stress concentration, peeling at the interface with the conductor layer to be connected or cracks may occur near the interface.

[0027] In contrast, in the present embodiment, as in the laminated conductor group 4b in the wiring board 100, at least one via conductor constituting the laminated conductor group penetrating the build-up portion (the first laminate 1 or the second laminate 2) has a width larger than the other via conductors. That is, the laminated conductor group (the laminated conductor group 4b in the wiring board 100) includes a via conductor (the first via conductor 41) having a width larger than the other via conductors (the second via conductor 42) in the laminated conductor group. In other words, the laminated conductor group includes a via conductor having a relatively large contact area with the conductor layer to be connected. Therefore, by providing a via conductor (the first via conductor 41) having a relatively large width at a location (layer) where stress is concentrated, it may be possible to prevent interfacial peeling or cracks between the via conductor and the conductor layer that may occur due to stress concentration at a specific location.

[0028] If all the via conductors constituting the laminated conductor group are large in width, it may hinder the high density of wiring in all conductor layers, and as a result, it may hinder the miniaturization of the wiring board. Therefore, in this embodiment, the connection conductor group includes a via conductor (first via conductor 41) having a relatively large width with excellent resistance to stress, and a via conductor (second via conductor 42) having a width smaller than that of the first via conductor. According to this embodiment, interfacial peeling and cracks between the via conductor and the insulating layer in the laminated conductor group are suppressed, and the high density of wiring and the miniaturization of the wiring board may be promoted.

[0029] In the wiring board 100 of the example of FIG. 1, a surface F1 on the first surface 3a side of the core substrate 3 in the wiring board 100 is a component mounting surface on which components (not shown) to be mounted on the wiring board 100 are mounted. That is, the first laminate 1 includes a component mounting surface. On the other hand, a surface F2 on the second surface 3b side of the core substrate 3 in the wiring board 100 may be a surface to be connected to, for example, a motherboard (not shown) of an electronic device in which the wiring board 100 is used. The second laminate 2 penetrated by the laminated conductor group 4b is laminated on the opposite side of the core substrate 3 to the component mounting surface. That is, the first via conductor 41 having a relatively large width is located on the second surface 3b side of the core substrate 3.

[0030] It is believed that stress is more likely to concentrate on the second laminate 2 laminated on the side opposite the component mounting surface than on the first laminate 1 located on the component mounting surface side. However, in the wiring board 100 of the example in Fig. 1, the first via conductor 41 having a relatively large width is located on the second surface 3b side of the core substrate, which is the side opposite the component mounting surface. Therefore, it is believed that interfacial peeling and cracks due to stress concentration that is thought to easily occur in the second laminate 2 are more likely to be suppressed.

[0031] 3, all of the via conductors included in the laminated conductor group 4b that are stacked farther from the core substrate 3 than the first via conductor 41 have a width equal to or smaller than that of the first via conductor 41. That is, all of the via conductors included in the laminated conductor group 4b and located outside the first via conductor 41 are second via conductors 42 that have a width smaller than that of the first via conductor 41. In other words, the first via conductor 41 is provided on the inner layer side of the two second via conductors 42 that penetrate the two insulating layers 2d and 2c located on the outer layer side in the second laminate 2, respectively.

[0032] In a wiring board having a core board such as the core board 3 of the wiring board 100, it is presumed that the stress is difficult to be alleviated in the insulating layer and the conductor layer on the inner layer side, which are thought to have a lower degree of freedom in terms of displacement and deformation than the outer layer side, and that stress is also easily applied from the outer layer side. Therefore, stress concentration may occur more easily on the inner layer side than on the outer layer side. In contrast, in the wiring board 100 of the example of Figs. 1 to 3, the first via conductor 41 having a relatively large width is provided on the inner layer side of the second via conductor 42 that penetrates the two insulating layers (insulating layer 2d and insulating layer 2c) on the outer layer side in the second laminate 2. Therefore, it is considered that defects such as interface peeling and cracks due to stress concentration that tend to occur on the inner layer side are easily suppressed.

[0033] In the example of FIG. 3, among the via conductors included in the laminated conductor group 4b, the first via conductor 41 is next closest to the core substrate 3 after the via conductor (second via conductor 42) that penetrates the insulating layer 2a. That is, among the via conductors included in the laminated conductor group 4b, the first via conductor 41 is the second closest to the core substrate 3. As described above, in a wiring substrate such as the wiring substrate 100, it is considered that stress concentration is more likely to occur on the inner layer side than on the outer layer side. However, at the interface between the conductor layer 31 of the core substrate 3 and the via conductor that penetrates the insulating layer 2a, it is presumed that substantial defects such as interfacial peeling and cracks are less likely to occur because the rigidity of the core substrate 3 itself is high. Therefore, substantial defects due to concentrated stress may be most likely to occur in the via conductor that penetrates the insulating layer 2b that is second closest to the core substrate 3 after the via conductor that penetrates the insulating layer 2a. In the example of Figure 3, the via conductor included in the laminated layer conductor group 4b that is second closest to the core substrate 3 is the first via conductor 41, which has a relatively large width, so that defects in the via conductor that is second closest to the core substrate 3 may be suppressed.

[0034] In this embodiment, the ratio of the width of the first via conductor 41 to the width of the second via conductor 42 is, for example, 2 times or more and 7 times or less. The width W1 of the first via conductor 41 at the interface (lower surface) with the inner conductor layer is, for example, 55 μm or more and 180 μm or less. The width W2 of the second via conductor 42 at the interface (lower surface) with the inner conductor layer is, for example, 5 μm or more and 60 μm or less. It is believed that when the first via conductor 41 having a width in such a numerical range is provided, the interfacial peeling and cracks between the via conductor and the conductor layer can be suppressed without excessively affecting the size of the wiring board 100.

[0035] With reference to FIG. 3, the conductor layers 21 to 24 including the conductor pads 44, 45 that constitute the laminated conductor group 4b will be further described.

[0036] Although omitted in FIG. 1, as shown in FIG. 3, the conductor layers 21-24 including the conductor pads 44, 45 constituting the laminated conductor group 4b and the conductor layer 31 are covered with a coating film 5. The coating film 5 is formed on the surface of each of the conductor layers 31 and 21-24, and is interposed between each of the conductor layers 31 and 21-24 and either the insulating layers 2a-2d or the solder resist 6 laminated on each of these conductor layers. The coating film 5 improves the adhesion between each of these conductor layers and each of the insulating layers or the solder resist 6. Therefore, it is considered that the insulating layers 2a-2d and the solder resist 6 are less likely to lift or peel off from the conductor layers 31 and 21-24, respectively.

[0037] Specifically, for example, in the conductor layers 21 to 23, the conductor pad 45 included in the conductor layer 21, the conductor pad 44 included in the conductor layer 22, the conductor pad 45 included in the conductor layer 23, and the wiring patterns 20 included in each of the conductor layers 21 to 23 are covered with the coating film 5. The wiring pattern 20 is entirely covered with the coating film 5. On the other hand, the conductor pads 44, 45 are partially covered with the coating film 5. The coating film 5 has openings on the conductor pads 44, 45, and the periphery of the openings covers the conductor pad 44 or the conductor pad 45. The coating film 5 also partially covers the surfaces of the insulating layers 2a to 2c and the insulating layer 32.

[0038] The coating film 5 is formed of a material that can bond with both organic materials such as resins constituting each insulating layer and solder resist 6, and inorganic materials such as metals constituting each conductor layer. The coating film 5 is formed of a material that contains both reactive groups that can chemically bond with organic materials and reactive groups that can chemically bond with inorganic materials. Therefore, the conductor patterns of each conductor layer covered by the coating film 5 and each insulating layer are adhered with sufficient strength. Examples of materials for the coating film 5 include silane coupling agents containing azole silane compounds such as triazole compounds. Note that the material for the coating film 5 is not limited to silane coupling agents as long as it can increase the adhesion strength between each conductor layer and each insulating layer or solder resist 6 compared to the case where each insulating layer or solder resist 6 is directly formed on each conductor layer.

[0039] In the conductor pads 44, 45 included in any of the conductor layers 21 to 23, the portions that are not covered by the coating film 5 and are exposed in the openings of the coating film 5 are covered by the first via conductor 41 or the second via conductor 42 and are connected to the first via conductor 41 or the second via conductor 42. Therefore, the metal such as copper constituting each conductor pad and the metal such as copper constituting each via conductor are in direct contact with each other without the intervention of an organic material such as a silane coupling agent constituting the coating film 5. Therefore, it is considered that a mechanically strong joint between the metals and with low electrical resistance is obtained at the interface between each conductor pad and each via conductor.

[0040] Although omitted in FIG. 1 referred to above, as shown in FIG. 3, the surface S1 and side surface facing outward of each of the conductor pads 44 and 45, and the surface S2 and side surface facing outward of each of the wiring patterns 20 may have irregularities. The height difference of the irregularities on the surface S2 and side surface of the wiring pattern 20 is smaller than the height difference of the irregularities on the surface S1 and side surface of the conductor pads 44 and 45, and the surface S2 and side surface of the wiring pattern 20 have a relatively low surface roughness (second surface roughness). The surface S2 and side surface of the wiring pattern 20 may not be roughened in a process that is intentionally provided for roughening the surface S2 and side surface of the wiring pattern 20. The irregularities on the surface S2 and side surface of the wiring pattern 20 may be caused by the irregularities on the surface of the resist during the formation of each conductor layer or the grain boundaries of the plating film.

[0041] Generally, in a wiring pattern having a highly rough surface, the transmission characteristics may be degraded due to an increase in substantial impedance caused by the skin effect in the transmission of high-frequency signals. In addition, in a fine wiring pattern having a surface of, for example, 10 μm / 10 μm (wiring width / wiring spacing) or less, if the surface is highly roughened, the desired dimensions may not be obtained after roughening for the designed wiring width and thickness. In contrast, in the example of Fig. 3, the surface S2 of the wiring pattern 20 has a relatively low surface roughness, at least a surface roughness lower than that of the surfaces S1 of the conductor pads 44 and 45, so it is considered that problems such as a deterioration in high-frequency transmission characteristics caused by high surface roughness are unlikely to occur.

[0042] On the other hand, between a conductor layer having a surface with a relatively low surface roughness and an insulating layer formed on the surface, the so-called anchor effect is relatively small, so peeling between the conductor layer and the insulating layer may easily occur. However, since the surface S2 of the wiring pattern 20 in the example of Fig. 3 is covered with the coating film 5, peeling between each wiring pattern 20 and each of the insulating layers 2b to 2d is considered to be unlikely to occur.

[0043] On the other hand, the surfaces S1 and side surfaces of the conductor pads 44, 45 have a surface roughness (first surface roughness) higher than the surface roughness (second surface roughness) of the surface S2 and side surfaces of the wiring pattern 20. The surfaces S1 and side surfaces of the conductor pads 44, 45 are roughened to have a first surface roughness higher than the second surface roughness. As described later, the surfaces S1 and side surfaces of the conductor pads 44, 45 are roughened by, for example, microetching.

[0044] Thus, in the example of FIG. 3, the conductor pads 44 and 45 included in the laminated conductor group 4b include conductor pads having a surface that is covered with the coating film 5 and roughened. "Conductor pads having a surface that is covered with the coating film 5 and roughened" are also called "roughened conductor pads". In the example of FIG. 3, the conductor pads 45 included in each of the conductor layers 21, 23, and 24, and the conductor pad 44 included in the conductor layer 22 are all roughened conductor pads (in the example of FIG. 3, the conductor pad connected to the second via conductor 42 in the conductor layer 31 is also a roughened conductor pad). Each of the conductor layers 21 to 23 including the roughened conductor pads includes a wiring pattern 20 covered with the coating film 5. The surface S1 and side surfaces of the roughened conductor pads (the conductor pad 44, and each of the conductor pads 45 included in the conductor layers 21 and 23) have a higher surface roughness than the surface S2 and side surfaces of the wiring pattern 20.

[0045] In the wiring board 100 of the example of FIG. 3, the surfaces S1 of the conductor pads 44, 45 are roughened to have a relatively high surface roughness (first surface roughness), so that peeling between the conductor pads 44, 45 and the insulating layers 2b-2d may be suppressed. Specifically, the unevenness of the surfaces S1 of the conductor pads, which have a relatively high surface roughness, prevents unintended liquid from penetrating into the interfaces between the conductor pads and the insulating layers. As a result, peeling between the conductor pads 44, 45 and the insulating layers 2b-2d, which may be caused by such liquid penetration, may be suppressed.

[0046] More specifically, in the manufacturing process of the wiring board 100, the inner walls of the through holes 46 provided in the insulating layers 2b-2d for forming the first via conductors 41 or the second via conductors 42 may be exposed to various processing solutions, plating solutions, and the like. These liquids may penetrate from the inner walls of the through holes 46 into the interfaces between the conductor pads 44, 45 and the insulating layers 2b-2d, respectively, causing peeling between each conductor pad and each insulating layer. However, in the example of Fig. 3, the intrusion of unintended liquids that may cause such peeling is prevented by the unevenness of the surfaces S1 of the conductor pads 44, 45, which have a relatively high first surface roughness.

[0047] Furthermore, in the example of FIG. 3, the unevenness of the surface S1 of each conductor pad may prevent quality deterioration due to dissolution of the coating film 5 formed on the surface S1 of each conductor pad. As described above, in the manufacturing process of the wiring board 100, the inner wall of the through hole 46 provided in the insulating layers 2b to 2d may be exposed to various liquids. When the liquid penetrates into the interface between the surface S1 of the conductor pads 44 and 45 and each of the insulating layers 2b to 2d, the penetrating liquid may dissolve the coating film 5 formed on the surface S1 of each conductor pad. In that case, the coating film 5 may dissolve into the through hole 46, causing a connection failure between each conductor pad and the first via conductor 41 or the second via conductor 42, or peeling may occur between each conductor pad and each insulating layer at the melted portion of the coating film 5. However, in this embodiment, the unevenness of the surface S1 of the conductor pads 44 and 45, which has a relatively high first surface roughness, prevents the intrusion of such an unintended liquid that may cause dissolution of the coating film 5.

[0048] As described above, in the example of FIG. 3, the wiring pattern 20 has good transmission characteristics and sufficient adhesion to each of the insulating layers 2b to 2d, and quality deterioration due to peeling between each of the conductor pads 44, 45 and each of the insulating layers 2b to 2d is suppressed.

[0049] Particularly in this embodiment, the first via conductor 41 is connected to the conductor pad 45 of the conductor layer 21, which is a conductor pad to be roughened, at the end surface on the core substrate 3 side. As described above, the first via conductor 41, which has a relatively large width, is preferably arranged at a location where stress is likely to concentrate in order to suppress interfacial peeling. Therefore, it is presumed that the conductor pad connected to the first via conductor 41 (for example, the conductor pad 45 of the conductor layer 21 in FIG. 3) is also likely to be affected by stress concentration. However, it is considered that peeling between the conductor pad 45 connected to the first via conductor 41 and the insulating layer 2b is suppressed by the unevenness of the surface S1 of the conductor pad 45, which is a conductor pad to be roughened, and the coating film 5 covering the surface S1. As described above, in this embodiment, it is considered that peeling between the via conductor and the conductor layer at the stress concentration location is suppressed by the relatively large contact area between the first via conductor 41 and each conductor layer. And, it is considered that peeling between the conductor pad and the insulating layer at the stress concentration location is suppressed by the roughened surface S1 of the conductor pad to be roughened and the coating film 5 covering the surface S1.

[0050] In order to achieve both good high-frequency transmission characteristics in the wiring pattern 20 and reliable prevention of liquid penetration into the interfaces between the conductor pads 44, 45 and the insulating layers 2b to 2d, it is preferable that the difference between the first surface roughness and the second surface roughness is large. For example, the first surface roughness is 100% or more higher than the second surface roughness. In that case, it is considered that good transmission characteristics for high-frequency signals of the order of several GHz can be obtained in the wiring pattern 20 while almost reliably preventing liquid penetration into the interfaces between the conductor pads 44, 45 and the insulating layers 2b to 2d. The first surface roughness may be 1200% or less of the second surface roughness. The roughening process of the surfaces S1 of the conductor pads 44, 45 does not require excessive time, and it is also considered that damage to the insulating layers 2a to 2d during the roughening process is small. The first surface roughness is, for example, 0.3 μm or more and 0.6 μm or less in arithmetic mean roughness (Ra). The second surface roughness is, for example, 0.05 μm or more and 0.15 μm or less in arithmetic mean roughness (Ra).

[0051] 3, the portions of the surface S1 of the conductor pads 44, 45 that are covered by the first via conductor 41 or the second via conductor 42 have a third surface roughness that is lower than the surface roughness (first surface roughness) of the portions of the surface S1 that are covered by the coating film 5. The third surface roughness may be higher than the second surface roughness or lower than the second surface roughness.

[0052] In the wiring board 100 of Figs. 1 to 3, each of the via conductors constituting the laminated conductor groups 4a and 4b has a tapered shape tapering from the outside to the inside. When comparing the widths of the via conductors, if each via conductor has a tapered shape, the widths of the upper surfaces (outer end faces) or the lower surfaces (inner end faces, end faces on the core substrate 3 side in the example of Fig. 1) of the compared via conductors are compared. In addition, the laminated conductor group in this embodiment exemplified by the laminated conductor groups 4a and 4b in Fig. 1 may be composed of a plurality of via conductors having tapered shapes with different gradients. An example of this point is shown in Fig. 4.

[0053] FIG. 4 shows a part of a laminated conductor group 400, which is another example of a laminated conductor group penetrating the second laminate 2 in FIG. 1. A part of the laminated conductor group 400 is constituted by a laminate of a via conductor 401 penetrating the insulating layer 201 and a via conductor 402 penetrating the insulating layer 202. The via conductor 402 has a tapered shape with a gentler gradient than the via conductor 401. Comparing the width W3 of the lower surface 401a of the via conductor 401 with the width W4 of the upper surface 402b of the via conductor 402, the width W4 of the upper surface 402b of the via conductor 402 is larger. However, the width W3 of the lower surface 401a of the via conductor 401 is larger than the width W5 of the lower surface 402a of the via conductor 402. Therefore, in the laminated conductor group 400 of the example of FIG. 4, the via conductor 401 is the first via conductor, and the via conductor 402 is the second via conductor.

[0054] In addition, when comparing the widths of the via conductors, if the result of comparing the widths of the upper surfaces is different from the result of comparing the widths of the lower surfaces, the size relationship of the widths of the via conductors is determined based on the result of comparing the widths of the lower surfaces. The reason is that peeling or cracks are more likely to occur at the interface with the lower conductor layer than the upper surface that is continuous with the upper conductor layer. Therefore, in the example of FIG. 4, even if the slope of the side surface of the via conductor 402 is more gentle and the width of the upper surface 402b of the via conductor 402 is larger than the width of the upper surface 401b of the via conductor 401, the via conductor 401 is the first via conductor as long as the width of the lower surface 401a of the via conductor 401 is larger than the width of the lower surface 402a of the via conductor 402.

[0055] Second embodiment A wiring board of the second embodiment will be described with reference to Figures 5 and 6. Figure 5 shows a cross-sectional view of a wiring board 200, which is an example of the wiring board of the present embodiment, and Figure 6 shows an enlarged view of a portion VI in Figure 5, which is a peripheral portion of a laminated conductor group 4d. In Figures 5 and 6, components similar to those shown in Figures 1 and 3 are given the same reference numerals as those in Figures 1 and 3, and repeated description will be omitted as appropriate.

[0056] 5, the wiring board 200 includes a core board 3, a first laminate 1 formed on a first surface 3a of the core board 3, and a second laminate 2 formed on a second surface 3b of the core board, similar to the wiring board 100 of FIG. 1. The wiring board 200 includes a laminated conductor group 4c (first laminated conductor group) penetrating the first laminate 1, similar to the laminated conductor group 4a of the wiring board 100 of FIG. 1. The wiring board 200 further includes a laminated conductor group 4d (second laminated conductor group) penetrating the second laminate 2, similar to the laminated conductor group 4b of the wiring board 100 of FIG. 1. The laminated conductor group 4c includes a plurality of via conductors (first via conductors 41 and second via conductors 42) penetrating the insulating layers 1a to 1d constituting the first laminate 1, respectively. The laminated conductor group 4d includes a plurality of via conductors (a first via conductor 41, a second via conductor 42, and a third via conductor 43) that penetrate the insulating layers 2a to 2d that constitute the second laminate 2, respectively.

[0057] 1, the laminated conductor group 4c includes a plurality of second via conductors 42 and a first via conductor 41 having a width greater than that of the second via conductor 42. The first via conductor 41 penetrates the insulating layer 1b, which is the second closest to the core substrate 3 after the insulating layer 1a, among the insulating layers 1a to 1d constituting the first laminate 1. The first via conductor 41 constituting the laminated conductor group 4c is the via conductor second closest to the core substrate 3 among the plurality of via conductors constituting the laminated conductor group 4c.

[0058] On the other hand, like the laminated conductor group 4b of the wiring board 100 in Fig. 1, the laminated conductor group 4d also includes a plurality of second via conductors 42 and a first via conductor 41 having a width larger than that of the second via conductor 42. Like the first via conductor 41 in Fig. 1, the first via conductor 41 constituting the laminated conductor group 4d in the wiring board 200 is also the second closest via conductor to the core substrate 3 among the plurality of via conductors constituting the laminated conductor group 4d.

[0059] As described above, in this embodiment, both the laminated conductor group 4c penetrating the first laminate 1 and the laminated conductor group 4d penetrating the second laminate 2 include the first via conductors 41 having a relatively large width. On both sides of the core substrate 3, peeling or cracks at the interfaces between the via conductors and the conductor layers due to stress concentration may be suppressed.

[0060] The wiring board 200 of the present embodiment further includes a laminated conductor group 4e that penetrates the second laminate 2 in the same manner as the laminated conductor group 4d. The laminated conductor group 4e includes a plurality of via conductors (first via conductors 41 and second via conductors 42) that penetrate the insulating layers 2a to 2d that constitute the second laminate 2, respectively. The laminated conductor group 4e includes two first via conductors 41 having a width greater than the width of the second via conductor 42. The laminated conductor group included in the wiring board of the embodiment may include a plurality of first via conductors 41 having a relatively large width, like the laminated conductor group 4e. Interfacial peeling and cracks between the via conductors and the conductor layer may be further suppressed.

[0061] 5, in addition to the first via conductor 41, second via conductors 42 are also formed in insulating layers 1b, 2b, and 2c, which are respectively penetrated by first via conductors 41. In the wiring board of the embodiment, second via conductors 42 having a width smaller than that of first via conductors 41 may be formed together with first via conductors 41 in the insulating layer in which first via conductors 41 are formed. It is considered that the increase in size of wiring board 200 is suppressed compared to the case in which all via conductors formed in a specific insulating layer are formed as first via conductors 41 having a relatively large width.

[0062] As shown in FIG. 5 and FIG. 6, the laminated conductor group 4d includes a third via conductor 43 in addition to the first via conductor 41 and the second via conductor 42. The third via conductor 43 has a width larger than that of the second via conductor 42 and smaller than that of the first via conductor 41. The third via conductor 43 is located between the first via conductor 41 and the second via conductor 42. That is, the third via conductor 43 is provided on the outer layer side of the first via conductor 41 and on the inner layer side of the second via conductor 42. As described above, in a wiring board having a core board, it is considered that stress concentration is more likely to occur on the inner layer side than on the outer layer side. Therefore, when the third via conductor 43 is located between the first via conductor 41 and the second via conductor 42, the resistance to stress that increases toward the inner layer side may be increased toward the inner layer side. In addition, compared to a case in which only the first via conductor 41 and the second via conductor 42 are provided, the increase in size of the wiring board 200 may be suppressed.

[0063] 6, in the laminated conductor group 4d, the surface S1 and side surfaces of the conductor pads 44, 45 constituting the laminated conductor group 4d are also roughened to have a surface roughness higher than the surface roughness of the surface S2 of the wiring pattern 20. Moreover, the wiring patterns 20 and the conductor pads 44, 45 formed on the conductor layers 21-23 are covered with a coating film 5. In the example of FIG. 6, the first via conductor 41 is connected to the conductor pad 45, which is a surface-roughened conductor pad, on the end face on the core substrate 3 side.

[0064] Next, a method for manufacturing the wiring board of the embodiment will be described with reference to FIGS. 7A to 7H using wiring board 100 of FIG. 1 as an example.

[0065] As shown in Fig. 7A, a core substrate 3 is formed. For example, a starting substrate (e.g., a double-sided copper-clad laminate) is prepared, which includes an insulating layer that will become the insulating layer 32 of the core substrate 3 and metal foils 31a laminated on both surfaces of the insulating layer. Then, a conductor layer 31 having a desired conductor pattern and through-hole conductors 33 are formed by forming through holes and patterning using a subtractive method following panel plating.

[0066] 7B, insulating layer 1a and insulating layer 2a are formed respectively on a first surface 3a and a second surface 3b of core substrate 3. For example, a film-like epoxy resin is laminated on core substrate 3 and heated and pressurized to form insulating layer 1a and insulating layer 2a, respectively.

[0067] Further, the conductor layer 11 and the conductor layer 21 are formed. The second via conductor 42 is formed in the insulating layer 1a and the insulating layer 2a, respectively. The conductor layer 11, the conductor layer 21, and the second via conductor 42 are formed, for example, by a semi-additive method. That is, the through hole 46 is formed in the insulating layer 1a and the insulating layer 2a, and the metal film 10b is formed in the through hole 46 and on the surface of the insulating layer 1a and the insulating layer 2a, for example, by electroless plating. A plating resist (not shown) having an appropriate opening is provided on the metal film 10b, and the plating film 10c is formed in the opening of the plating resist by electrolytic plating. As a result, the conductor layer 11, the conductor layer 21, and the second via conductor 42 are formed, respectively.

[0068] As shown in FIG. 7C, the area of ​​the surface of the conductor layer 21 that is not in contact with the insulating layer 2a is roughened. FIG. 7C shows the state of the surface of the conductor layer 21 after roughening treatment in the VIIC part of FIG. 7B. Although not shown, the surface of the conductor layer 11 can also be roughened in the same manner as the surface of the conductor layer 21. In roughening the surface of the conductor layer 21, the exposed surface of the wiring pattern 20 is not roughened, but the exposed surface of the conductor pad 45 is roughened. Therefore, as shown in FIG. 7C, a resist film R1 is provided to cover the exposed surface other than the surface of the conductor pad 45. The roughening of the exposed surface of the conductor layer 21 is performed, for example, by a surface oxidation treatment such as blackening treatment or a microetching treatment. The exposed surface of the conductor pad 45 is roughened so as to have a surface roughness higher than the surface roughness of at least the unroughened surface of the wiring pattern 20.

[0069] As shown in FIG. 7D, a coating film 5 is provided on the exposed surface of the conductor layer 21. FIG. 7D shows a state after the coating film 5 is formed for the same part as FIG. 7C. The coating film 5 is formed by immersing the conductor layer 21 in a liquid containing a material that can bond with both organic and inorganic materials, such as a silane coupling agent, or by spraying such a liquid. After the formation of the conductor layer 31 shown in FIG. 7A, the surface of the conductor layer 31 is roughened in a manner similar to the roughening of the exposed surface of the conductor layer 21 shown in FIG. 7C, and the coating film 5 is provided in a manner similar to the formation of the coating film 5 shown in FIG. 7D. After the formation of each of the conductor layers 22 to 24 described later, the surface of each conductor layer is roughened and the coating film 5 is formed in the same manner.

[0070] As shown in Figures 7E and 7F, insulating layers 1b and 2b are formed. Figure 7F shows an enlarged view of the VIIF portion in Figure 7E. Insulating layers 1b and 2b are formed, for example, by laminating film-like epoxy resins and applying heat and pressure, similar to insulating layers 1a and 2a. Through holes 46 are formed in insulating layers 1b and 2b, for example, by irradiating carbon dioxide laser light. Through holes 46 having a width larger than that of insulating layer 2a are formed in insulating layer 2b.

[0071] As shown in Fig. 7F, a part of the coating film 5 formed on the surface S1 of the conductor pad 45 is removed by forming the through hole 46. Although not shown, when a coating film 5 is formed on the surface of the conductor pad 45 included in the conductor layer 11 shown in Fig. 7E, a part of the coating film 5 is removed in the same manner as the coating film 5 on the conductor pad 45 shown in Fig. 7F. Note that the unevenness of the surface S1 of the conductor pad 45, which is roughened to a relatively high surface roughness, prevents the dissolving solution of the coating film 5 from penetrating into the interface between the conductor pad 45 and the insulating layer 2b when removing the coating film 5.

[0072] After the through-holes 46 are formed, a desmear process is performed as necessary. The unevenness of the roughened surface S1 of the conductive pads 45 prevents the processing liquid for the desmear process from penetrating into the interface between the conductive pads 45 and the insulating layer 2b.

[0073] As shown in FIG. 7G, a conductor layer 12 is formed on an insulating layer 1b, and a second via conductor 42 penetrating the insulating layer 1b is formed. A conductor layer 22 is formed on an insulating layer 2b. With the formation of the conductor layer 22, a first via conductor 41 having a width larger than that of the second via conductor 42 penetrating the insulating layer 2a is formed in the insulating layer 2b. The first via conductor 41 penetrates the insulating layer 2b and connects the conductor layer 21 and the conductor layer 22. The conductor layer 12 and the conductor layer 22, and the second via conductor 42 and the first via conductor 41 penetrating the insulating layer 1b and the insulating layer 2b, respectively, are formed by, for example, a method similar to the method of forming the second via conductor 42 penetrating the conductor layer 11 and the insulating layer 1a described above. For example, a semi-additive method is used.

[0074] As shown in FIG. 7H, the insulating layer 1c and the insulating layer 2c are further formed, the conductor layer 13 and the conductor layer 23 are formed, and the second via conductor 42 penetrating the insulating layer 1c and the insulating layer 2c is formed. Furthermore, the insulating layer 1d and the insulating layer 2d are formed, the conductor layer 14 and the conductor layer 24 are formed, and the second via conductor 42 penetrating the insulating layer 1d and the insulating layer 2d is formed. Each of these insulating layers is formed by the same method as the above-mentioned insulating layer 1a, and the second via conductor 42 penetrating each insulating layer can be formed by the same method as the above-mentioned insulating layer 1a. Furthermore, each conductor layer can be formed by the same method as the above-mentioned conductor layer 11. As a result, the first laminate 1 is formed on the first surface 3a of the core substrate 3, and the second laminate 2 is formed on the second surface 3b. Furthermore, a laminated conductor group 4a penetrating the first laminate 1 is formed, and a laminated conductor group 4b penetrating the second laminate 2 is formed.

[0075] In the example of Fig. 7H in which the wiring board 100 is manufactured, a solder resist 6 having an opening 6a is formed. The solder resist 6 and the opening 6a are formed by forming a resin layer containing, for example, a photosensitive epoxy resin or polyimide resin, and exposing and developing the resin layer using a mask having an appropriate opening pattern. Through the above steps, the wiring board 100 of the example of Fig. 1 is completed.

[0076] When the wiring board 200 of the second embodiment is manufactured, openings 46 having appropriate widths according to the first via conductor 41, the second via conductor 42, and the third via conductor 43 to be formed are formed in the insulating layers 1a to 1d and the insulating layers 2a to 2d.

[0077] The wiring board of the embodiment is not limited to those having the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. As described above, the wiring board of the embodiment may include any number of conductor layers and insulating layers. The first via conductor 41 may be present in any layer on the laminated structure of the wiring board. Only a part of the conductor pads constituting the laminated conductor group may be covered with the coating film 5. The adhesion between the conductor pads not covered with the coating film 5 and the insulating layer may be ensured by the anchor effect of the roughened surface. The first to third via conductors 41 to 43 may not have a tapered shape as in the example of FIG. 1. The laminated conductor group may be formed only on one of the first laminate 1 and the second laminate 2. The through-hole conductor 33 and the laminated conductor groups 4a and 4b may not overlap in a plan view. In addition, the first surface 3a side of the core substrate 3 may not include a component mounting surface. [Explanation of symbols]

[0078] 100, 200 Wiring board 1 First laminate 11~14 Conductor layers 1a~1d Insulating layer 2 Second laminate 20 Wiring Pattern 21~24 Conductor layers 2a~2d Insulating layer 3 Core Board 3a 1st page 3b 2nd side 31 Conductor layer (inner layer conductor layer) 4a, 4b, 4e Laminated conductor group 4c Laminated conductor group (first laminated conductor group) 4d Laminated conductor group (second laminated conductor group) 41 First via conductor 42 Second via conductor 43 Third via conductor 44, 45 Contact pad 5 Coating film S1 Contact pad surface S2 Surface of wiring pattern

Claims

1. a core substrate having a first surface and a second surface opposite to the first surface, the core substrate including an inner-layer conductor layer formed on each of the first surface and the second surface; a first laminate formed on the first surface and composed of insulating layers and conductor layers alternately laminated; a second laminate formed on the second surface and composed of insulating layers and conductor layers alternately laminated; a laminated conductor group including a plurality of via conductors penetrating the insulating layers constituting the first laminate or the second laminate, the laminated conductor group penetrating the first laminate or the second laminate; A wiring board comprising: The laminated conductor group further includes a roughened conductor pad having a roughened surface covered with a coating film that improves adhesion between the conductor layer and the insulating layer constituting the first laminate or the second laminate, the plurality of via conductors include a second via conductor and a first via conductor connected to the roughened conductor pad at an end surface on the core substrate side; The width of the first via conductor at the end face is greater than the width of the second via conductor at the end face facing the core substrate.

2. 2. The wiring board according to claim 1, a conductor layer constituting the first laminate or the second laminate and including the roughened conductor pad connected to the end surface of the first via conductor further includes a wiring pattern covered with the coating film; The surface of the roughened conductor pad has a higher surface roughness than the surface of the wiring pattern.

3. A wiring board as described in claim 1, wherein all of the via conductors among the plurality of via conductors included in the laminated conductor group that are laminated farther from the core substrate than the first via conductor have a width at their end faces facing the core substrate that is less than or equal to the width of the first via conductor at the end face.

4. 4. The wiring board according to claim 3, the laminated conductor group further includes, as the plurality of via conductors, a third via conductor having a width at an end surface facing the core substrate that is larger than a width at the end surface of the second via conductor and smaller than a width at the end surface of the first via conductor, The third via conductor is located between the first via conductor and the second via conductor.

5. 2. The wiring board according to claim 1, wherein the first via conductor is a via conductor that is second closest to the core substrate among the plurality of via conductors included in the laminated conductor group.

6. 2. The wiring board according to claim 1, a surface of the wiring board on the first surface side of the core substrate is a component mounting surface on which components to be mounted on the wiring board are mounted, The first via conductor included in the laminated conductor group is located on the second surface side of the core substrate.

7. 2. The wiring board according to claim 1, The wiring board includes, as the laminated conductor group, a first laminated conductor group penetrating the first laminate and a second laminated conductor group penetrating the second laminate, Both the first laminated conductor group and the second laminated conductor group include the first via conductors.

8. 2. The wiring board according to claim 1, wherein a width of the first via conductor at the end face is not less than two times but not more than seven times a width of the second via conductor at the end face.

9. 2. The wiring board according to claim 1, wherein the laminated conductor group includes a plurality of the first via conductors.

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