Method for using ultra-thin ruthenium metal hardmask for etch profile control

Abstract

A method for processing a substrate, in one example a microelectronic workpiece, is disclosed, the method including forming a multi-layer metal hard mask (MHM) layer, wherein at least one underlayer of the multi-layer MHM is composed of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed on one or more underlying layers on the substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be at least partially etched using the patterned ALD Ru MHM layer as a mask to protect portions of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

Description

[Technical field]

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 878,900, entitled "Method and System For Developer Drain Monitoring," filed July 26, 2019, U.S. Provisional Patent Application No. 62 / 880,256, entitled "Method For Using Ultra Thin Ruthenium Metal Hard Mask For Etching Profile Control," filed July 30, 2019, and U.S. Nonprovisional Patent Application No. 16 / 582,297, entitled "Method For Using Ultra Thin Ruthenium Metal Hard Mask For Etching Profile Control," filed September 25, 2019, the disclosures of which are expressly incorporated herein by reference in their entireties. [Background technology]

[0002] The present disclosure relates to processing of substrates, such as microelectronic workpieces. In particular, the present disclosure provides a method for patterning a substrate. In one embodiment, the method may be for processing a semiconductor substrate.

[0003] The formation of devices in microelectronic workpieces typically involves a series of manufacturing techniques involving the formation, patterning, and removal of many layers of material on a substrate. To meet the physical and electrical specifications of current and next generation devices, process flows are reducing the dimensions of features while maintaining structural integrity for the various patterning processes.

[0004] In some devices formed on microelectronic workpieces, vias are formed in one or more layers to reach conductive interconnects formed by patterned conductive layers. The critical dimension (CD) for this via formation, for example using back-end-of-line (BEOL) etching processes, typically needs to be precisely controlled for the electronic device to function properly. If the via CD is smaller than the target via CD, it will be difficult to fill the via with metal or conductive material during the metallization process step. Furthermore, the resistance of the metal interconnects formed in these small vias will increase due to the smaller cross-sectional area of ​​the metal, which affects the electrical properties. If the via CD is larger than the target via CD, a short circuit may occur between two adjacent metal interconnects after metallization, which may lead to failure of the electronic device.

[0005] To facilitate the formation of vias in patterned structures of microelectronic workpieces, previous process solutions have used metal hardmask (MHM) layers and hardmask (HM) layers as patterned masks that cover portions of underlying layers that should not be etched. For example, titanium nitride (TiN) has been used as the material for the MHM layer because it is more resistant to etching compared to typical materials used for HM layers, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), or other similar materials. In these conventional process solutions, the MHM layer is formed on top of the HM layer to better control the via CD during the etching process that forms the patterned structures (e.g., BEOL etching to form dual damascene structures). However, the TiN MHM layer is still exposed to etching during the etching process that opens into the HM layer for the formation of the patterned structures, including via formation. This undesired etching of the TiN MHM layer can result in the via CD being larger than the target via CD, which can result in reduced local critical dimension uniformity (LCDU).

[0006] Conventional solutions typically use TiN formed on a SiN HM layer as the MHM layer. Conventional solutions may also include an additional HM layer on the TiN. However, when the TiN MHM layer is opened in a via opening step to allow vias to also be opened in the underlying SiN HM layer, the typical chemistry used in this etch (e.g., an etch chemistry including chlorine (Cl2) and argon (Ar)) will also etch the underlying SiN HM layer and form gouging in the underlying SiN HM layer, as shown in Figures 1A-1B (Prior Art). Furthermore, the level of gouging typically varies at different locations across the substrate due to variations in the etch process, such as variations in reactive ion etching (RIE) lag. Higher density patterns typically have lower levels of gouging, and lower density patterns typically have higher levels of gouging. Different levels of gouging result in different via CDs after the etch process used to etch underlying layers, such as the etch process for the underlying HM layer, ultra-low dielectric constant (ULK) layer, barrier low-k (Blok) layer, and / or other layers, ultimately resulting in the final via CDs of contact vias to underlying conductive layers, such as metal (M) layers, being significantly different from one another.

[0007] Referring now to FIG. 1A (PRIOR ART), one embodiment 100 of multiple layers formed on a microelectronic workpiece is shown, including a TiN layer 104 as an MHM layer and a SiN layer 106 as an HM layer. An oxide layer 102 (e.g., SiO2) is formed and patterned on the TiN layer 104 to act as an additional HM as part of the MHM opening process. Other layers below these layers 102 / 104 / 106 include a dielectric layer 108, such as a ULK layer, a Blok layer 110, and an additional dielectric layer 112. A conductive region 114, such as a metal (M) conductive region, is formed in the dielectric layer 112. FIG. 1B (PRIOR ART) is an exemplary embodiment 120 after a portion of the TiN MHM layer 104 has been removed using an etching process to open a via in the TiN MHM layer 104 vertically above the conductive region 114. This via in the TiN MHM layer 104 extends down to the SiN layer 106. However, the etching process for forming this via, as described above, can leave gouges 122 in the underlying SiN layer 106 that cause the SiN layer 106 to be thinner than other vias formed across the substrate of the microelectronic workpiece. Furthermore, the amount of gouges can vary between different vias due to variations in the etching process, such as variations in RIE lag.

[0008] Another problem with this use of TiN as a MHM material in conventional solutions is that the TiN MHM layer is often eroded during subsequent etching process steps to the underlying layers, such as etching the underlying HM, ULK, Blok, and / or other underlayer layers. As described herein, the chemistries used to open these layers also tend to etch the TiN MHM layer. For example, as shown in Figures 2A-2C, lateral etching can occur in the TiN MHM layer during such underlayer etching, and the top of the TiN MHM layer can also be consumed. This undesirable etching can cause the via CD to be larger than the target CD value. The undesirable larger CD value can cause shorts to the metal (M) contacts and / or cause the via profile in the underlayer (such as the ULK layer) to be more distorted. Furthermore, TiN residue will typically result from this lateral etching of the TiN MHM layer during the via and trench etch steps, and this residue can adversely affect the yield associated with the via opening process and the resulting electronic devices formed on the microelectronic workpiece.

[0009] Turning now to Figure 2A (PRIOR ART), one embodiment 200 of layers formed on a microelectronic workpiece is shown. Similar to Figures 1A-1B (PRIOR ART), the layers include a dielectric layer 102, a TiN layer 104 as a MHM layer formed on a SiN layer 106 acting as a HM layer. Other layers include a dielectric layer 108 such as a ULK layer, a Blok layer 110, and a dielectric layer 112. In addition, on the structure shown in Figure 1B (PRIOR ART), an OPL (organic planarization layer) layer 146 is formed as a protective and planarization layer, and a silicon anti-reflective coating (SiARC) layer 144 and a photoresist (PR) layer 142 are formed and patterned on the OPL layer 146.

[0010] 2B (PRIOR ART) shows an example embodiment 220 after an etching process has been used to open a via in OPL layer 146 vertically above conductive region 114 down to SiN layer 106. This via formation exposes gouge 122 in the underlying SiN layer 106.

[0011] 2C (PRIOR ART) is an exemplary embodiment 240 after a further etching process has been used to remove the SiN layer 106 in the vias formed over the conductive regions 114. The TiN layer 104 used as the MHM layer is often eroded as part of this further etching process. This erosion 184 in the TiN MHM layer 104, and similar erosion 182 in the oxide layer 102, results in a larger than desired target critical dimension (CD) 188 for the via. Additionally, the gouging 122 in the SiN layer 106 will also result in gouging 186 in the dielectric layer 112. Additionally, the different levels of gouging 122 in the SiN layer 106 for different vias across the substrate will result in different levels of gouging 186 in the dielectric layer 112 for those different vias. Ultimately, CD variations and gouging variations can result in undesirable variations in the CD of the vias that are subsequently formed all the way to the conductive regions 114, and these undesirable variations can lead to defects and performance problems in the final electronic devices formed in the fabricated microelectronic workpiece.

[0012] It would be desirable to provide an improved patterning process. Summary of the Invention [Means for solving the problem]

[0013] Described herein are embodiments that use additional materials for a metal hard mask (MHM) layer to provide better control of critical dimensions (CDs) in the formation of patterned structures, including via formation in underlying layers, such as an underlying patterned conductive layer. The additional material is provided as a ruthenium (Ru) layer, such as a Ru MHM layer, realized using Ru and / or using Ru-containing materials with similar properties to Ru for the process steps described herein. Additionally, other metals or metal-containing materials with similar properties to Ru for the process steps described herein may also be used. In one embodiment, a Ru MHM layer may be disposed below a TiN MHM layer and utilized as a patterned mask layer to protect portions of the underlying layer during an etching process for the manufacture of microelectronic workpieces, such as during an etching process to form vias through the underlying layer. The addition of a Ru MHM layer below the TiN MHM layer provides better control of the etch profile of the final structure and eliminates RIE lag, since Ru has a high etch resistance to TiN etching, and also has a higher etch resistance than TiN for many other BEOL etch recipes. Thus, an MHM composed at least in part of an underlayer of Ru provides an improved substrate processing flow. Ru may be a thin Ru layer since Ru exhibits high etch resistance to other etches. Thus, the benefits discussed above can be obtained without the need to add thick process layers that may further complicate patterning objectives. In one embodiment, the Ru layer may be a layer deposited by atomic layer deposition (ALD). In some embodiments, the Ru layer need only be 2-5 nm thick. Different or additional features, variations, materials, and embodiments may also be implemented, and related systems and methods may also be utilized.

[0014] In one embodiment, a method of processing a microelectronic workpiece is disclosed that includes forming a multi-layer MHM layer, where at least one underlayer of the multi-layer MHM is composed of Ru. The Ru MHM layer can be an ALD Ru MHM layer formed on one or more underlying layers on a substrate. The ALD Ru MHM layer can be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers can be at least partially etched using the patterned ALD Ru MHM layer as a mask to protect a portion of the one or more underlying layers.

[0015] In one embodiment of the technology disclosed herein, a method for processing a substrate is provided. The method may include forming a multi-layer hardmask stack including at least a first metal hardmask layer and a second metal hardmask layer underlying the first metal hardmask layer, the second metal hardmask layer being a ruthenium metal hardmask layer including ruthenium, and the formed multi-layer hardmask stack overlies one or more underlying layers on a substrate. The method further includes etching the multi-layer hardmask stack to provide a patterned ruthenium metal hardmask layer to expose a portion of the one or more underlying layers, and etching the exposed portion of the one or more underlying layers using the patterned ruthenium metal hardmask layer as a mask to protect the unexposed portion of the one or more underlying layers.

[0016] In one particular embodiment of the method, the ruthenium metal hardmask layer is a material that includes 95% or more ruthenium (Ru). In another embodiment, the ruthenium metal hardmask layer is a material that includes 70% or more ruthenium. In another embodiment, the ruthenium metal hardmask layer is formed by atomic layer deposition and has a thickness of 20 nm or less. In another embodiment of the method, the ruthenium metal hardmask layer has a thickness of 10 nm or less. In another embodiment of the method, the method further includes etching the ruthenium metal hardmask layer with a plasma etching process using a plasma that includes oxygen. In some embodiments, etching the one or more underlying layers includes forming a via. In one embodiment of the method, the one or more underlying layers include a dielectric hardmask layer. In one embodiment, the ruthenium metal hardmask layer is formed on a dielectric hardmask layer. In another embodiment, the first metal hardmask layer is a titanium nitride layer. In another embodiment, the hardmask layer includes at least one of SiN, SiO2, or SiON.

[0017] In one alternative embodiment of the method described above, the ruthenium metal hardmask layer is formed by atomic layer deposition and has a thickness of 20 nm or less, and the etching of the multi-layer hardmask includes a first etching process that etches the first metal hardmask layer and a second etching process that etches the ruthenium metal hardmask layer, and unlike the first and second etching processes, no additional patterned layer is formed on the multi-layer hardmask between performing the first etching process and performing the second etching process. In a second alternative embodiment of the method described above, the ruthenium metal hardmask layer is formed by atomic layer deposition and has a thickness of 20 nm or less, and the etching of the multi-layer hardmask includes a first etching process that etches the first metal hardmask layer and a second etching process that etches the ruthenium metal hardmask layer, and unlike the first and second etching processes, no additional patterned layer is formed on the multi-layer hardmask after performing the first etching process but before performing the second etching process.

[0018] A more complete understanding of the present invention and its advantages can be obtained by reference to the following description in conjunction with the accompanying drawings, in which like reference numerals indicate like features, and in which: It should be noted, however, that the accompanying drawings depict only exemplary embodiments of the disclosed concepts and therefore should not be considered as limiting the scope, as the disclosed concepts may be applied to other equally effective embodiments. [Brief description of the drawings]

[0019] [Figure 1] 1A-1B illustrate an exemplary embodiment of a conventional process flow in which an opening is formed in an MHM layer to an HM layer. [Diagram 2] 2A-2C (PRIOR ART) provide an exemplary embodiment of a conventional process flow for forming vias in an MHM layer and an underlying layer of an HM layer, where lateral erosion of the MHM layer occurs. [Diagram 3]3A-3C provide an exemplary embodiment of a process flow in which a multi-layer MHM is utilized, where ruthenium or a material containing ruthenium is used as the bottom MHM while forming an opening in the multi-layer MHM to an underlying HM layer. [Figure 4] 4A-4C provide an exemplary embodiment of a process flow that may be performed after the process flow of FIGS. 3A-3C. [Diagram 5] 5A-5D provide an exemplary embodiment of a process flow that may be performed after the process flow of FIGS. 3A-3B. [Figure 6] 1 illustrates an exemplary method utilizing the techniques described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Described herein are embodiments that use additional materials for the MHM layer to better control the critical CD in forming patterned structures, including via formation into underlying layers, such as an underlying patterned conductive layer. The additional material is provided as a Ru layer, such as a Ru MHM layer, realized using Ru and / or using Ru-containing materials with similar properties to Ru for the process steps described herein. Additionally, other metals or metal-containing materials with similar properties to Ru for the process steps described herein can also be used. In one embodiment, a Ru MHM layer can be placed under a TiN MHM layer and utilized as a patterned mask layer to protect a portion of the underlying layer during the etching process. In one embodiment, the etching process is used to form vias through underlying layers for the fabrication of microelectronic workpieces. The addition of a Ru MHM layer under a TiN MHM layer can provide better control of the etch profile of the final structure and eliminate RIE lag, since Ru has a high etch resistance to TiN etching, and also has a higher etch resistance than TiN for other BEOL etch recipes. Therefore, the profile of the pattern being etched can be better controlled and the effects of gouging the HM layer can be countered.

[0021] Thus, a multi-layer MHM composed at least in part of an underlayer of Ru provides improved substrate processing flow. Ru may be a thin Ru layer since Ru exhibits high etch resistance to other etches. Thus, the above benefits can be obtained without the need to add thick process layers that may further complicate patterning objectives. In one embodiment, the Ru layer may be a layer deposited by atomic layer deposition (ALD). In some embodiments, the Ru layer need only be 2-5 nm thick. Different or additional features, variations, materials, and embodiments may also be implemented, and related systems and methods may also be utilized.

[0022] In one embodiment, a method of processing a microelectronic workpiece is disclosed that includes forming a multi-layer MHM layer, where at least one underlayer of the multi-layer MHM is composed of Ru. The Ru MHM layer can be an ALD Ru MHM layer formed on one or more underlayers on a substrate. The ALD Ru MHM layer can be etched to provide a patterned ALD Ru MHM layer. The one or more underlayers may then be at least partially etched using the patterned ALD Ru MHM layer as a mask to protect a portion of the one or more underlayers.

[0023] 3A-5D show exemplary process flows illustrating the use of the concepts described herein. As one of ordinary skill in the art will appreciate, it will be understood that these process flows are merely exemplary and that the concepts described herein may be utilized in many other process flows.

[0024] Thus, for example, as shown, in one embodiment, to better control via CD in an underlying layer (e.g., an ultra-low dielectric constant (ULK) layer), an embodiment disclosed herein introduces Ru as an underlying layer for an MHM layer, where the Ru layer is deposited on one or more underlying layers of a substrate. In one embodiment, the underlying layer can be a conventional hard mask layer including SiN, SiO2, SiON, combinations thereof, and / or similar materials. The Ru MHM layer can be realized using Ru and / or using Ru-containing materials that have similar properties as Ru with respect to the process steps described herein. Typical MHM etches used to etch MHM layers, such as TiN, can have high etch selectivity to Ru-containing layers. Furthermore, etches used to etch the Ru MHM layer can have high etch selectivity (compared to conventional MHM etch processes) to underlying layers of the Ru layer because Ru is less sensitive to typical etch chemistries (e.g., Cl2, N2, Ar, and C) used for etching typical TiN layers, HM layers, and layers underlying the HM layers. x F yThe Ru MHM layer is not etched or is hardly etched by the ULK and Blok layers, for example. For example, other typical layers below the HM layer include the ULK and Blok layers. Ru is typically effectively etched using, for example, oxygen (O2)-based chemistries to form RuO4. Other gases that may be added to the etch include N2, Cl2, and / or Ar. Thus, Ru will not be eroded during standard etching processes, such as standard BEOL etching processes, and the Ru MHM layer will maintain its original profile and thickness. The lack of such erosion with the Ru MHM layer allows for better control of CD when forming patterned structures such as vias.

[0025] Moreover, due to the high etch selectivity, the thickness of the Ru layer underlying the MHM layer (e.g., underlying a TiN MHM layer) can be very thin. In one embodiment, the Ru-containing layer can be 20 nm or less. In another embodiment, the Ru-containing layer can be 10 nm or less. In yet another embodiment, the Ru-containing layer can be 2-5 nm. Because the Ru layer can achieve the desired objectives described herein at such thin thickness levels, the impact of adding the Ru layer on other process variables in the process flow can be minimized.

[0026] The Ru MHM layer technology described herein can be applied to current etch processes, such as typical BEOL process integration flows. The disclosed embodiments also effectively address via CD distortion and RIE lag issues experienced when combined deposition-etch solutions are used instead of etch-only solutions. The Ru MHM layer can be removed ex-situ by wet cleaning or by surface etching and cleaning. Furthermore, the Ru layer can also be removed in-situ in the same etch chamber used for via formation using Ru etch chemistry. Furthermore, due to the thin nature of the Ru layer, the Ru layer can be easily removed by chemical mechanical planarization (CMP) processes.

[0027] In contrast to conventional solutions, the embodiments described herein that use a Ru MHM layer underlying the MHM layer provide important advantages over conventional MHM solutions. First, the top MHM layer (e.g., a TiN MHM layer) can be effectively etched without gouging the Ru MHM layer due to the selective nature of TiN etching with respect to Ru-containing layers. The Ru MHM layer can then be effectively etched with O2-based chemistries that may have higher selectivity to typical hard mask layers (e.g., hard mask layers using SiN, SiO2, SiON, or similar materials) with respect to the HM layer, so that the etching process step used to open a via in the Ru MHM layer can better stop at the underlying HM layer without gouging the underlying HM layer. Thus, very little, if any, gouging occurs into the HM layer, and the RIE lag problem experienced in conventional solutions when performing the etching step can be more effectively suppressed. Additionally, the high etch resistance of the Ru MHM layer allows the Ru MHM layer to not be attacked during subsequent etching steps on additional underlying layers (e.g., the ULK layer, the Blok layer, and / or other underlying layers). For example, the Ru MHM layer will not be attacked by (1) typical HM etches such as fluorocarbon-based etches (e.g., carbon tetrafluoride and argon etches), (2) typical low-k dielectric layer etches and Blok etches (e.g., CHxFy / N2 / Ar etches), and (2) certain ashing steps such as those used in N2 / H2 or CO2 ashing processes.

[0028] Thus, as realized in the disclosed embodiments, Ru provides an advantageous material to use as an additional layer underneath a typical MHM layer to maintain the via CD at a desired or target parameter. The yield of the via opening process will also be more stable since no Ru impurities are generated in the via during the via formation and trench etching processes.

[0029] Advantages of the disclosed embodiments using a Ru MHM layer include, but are not limited to: (1) effectively eliminating RIE lag (e.g., little or no gouging of the Ru layer by TiN etching and little or no gouging of the HM layer, which may include SiN, SiO2, SiON, or other similar materials), (2) better control of via CD (e.g., no erosion of the Ru MHM layer during via and trench etch steps), and (3) helping to ensure the yield of the via opening process (e.g., no Ru residue is generated during the via formation and trench etch steps).

[0030] In one disclosed embodiment, the Ru layer is formed as an additional MHM layer: (1) below an upper MHM layer (e.g., a TiN layer) and (2) above an HM layer, e.g., a SiN HM layer. In one embodiment, the Ru layer is formed using one or more deposition steps. The Ru layer may be formed by any of a wide variety of deposition processes, including chemical vapor deposition, plasma deposition, etc., as are known in the art. In a preferred embodiment, the thin Ru layer may be formed utilizing atomic layer deposition techniques, also known in the art.

[0031] With reference to Figures 3A-3C, 4A-4C, and 5A-5D, process steps for the formation of vias are shown, where a Ru MHM layer is used under the top MHM layer to protect the underlying layers and improve CD control. As shown in Figures 3A-3C, 4A-4D, and 5A-5D, alternative process flows are disclosed. However, these process flows are merely examples of process flows that may incorporate the techniques disclosed herein, and other flows may be utilized. In a first exemplary embodiment, the process flow includes the process steps shown in Figures 3A, 3B, 3C, 4A, 4B, and 4C. A second exemplary embodiment incorporates the steps shown in Figures 3A, 3B, 5A, 5B, 5C, and 5D.

[0032] As shown in FIG. 3A, one embodiment 300 of multiple layers formed on a microelectronic workpiece is shown, including a Ru layer 301 as an additional MHM layer formed under an upper MHM layer (e.g., an upper TiN layer 104) and over an underlying HM layer (e.g., an underlying SiN layer 106). The multiple layers also include a dielectric layer 108, such as an ultra-low dielectric (k) layer, a Blok layer 110, and a dielectric layer 112. A conductive region 114, such as a metal (M) conductive region, is formed in the dielectric layer 112. An oxide layer 102 is formed and patterned as a hard mask layer over the metal hard mask layer (TiN layer 104 and Ru layer 302) as part of a patterning process, for example, using known lithography techniques. Thus, compared to the prior art as seen in FIG. 1, the embodiment 300 of FIG. 3A includes a thin additional MHM layer (in this case, Ru layer 301) under another MHM layer.

[0033] 3B is an example embodiment 320 after an etching process has been used to remove a portion of the TiN layer 104 above the conductive region 114 to open a via in the TiN layer 104. As shown in FIG. 3B, due to the etch resistance of the Ru layer 301, etching of the top MHM layer (TiN layer 104) can be accomplished without gouging the Ru layer 301. Thus, unlike conventional solutions, this via formation through the TiN layer 104 does not result in a gouged region because the TiN etch is highly selective to the Ru MHM layer that is underneath the TiN. Also, across multiple vias, the gouging in region 304 remains at the same level regardless of the width of the region.

[0034] After processing of FIG. 3B, alternative process flows may be followed. In a first process flow (FIGS. 3C, 4A, 4B, and 4C), the Ru layer 301 may be etched as shown in FIG. 3C. Thus, in this process flow, the Ru layer 301 is etched before additional subsequent process layers are formed on the structure shown in FIG. 3C. As described herein, in one embodiment, the etch of the Ru layer 301 may be a plasma etch using an O2-based chemistry. Because the O2 chemistry has high selectivity to the underlying HM layer (e.g., SiN layer 106), the Ru layer 301 may be etched without etching the underlying HM layer, as shown in FIG. 3C (as opposed to the process flow as described above in prior art FIG. 1B).

[0035] Turning now to FIG. 4A, an embodiment 400 of a plurality of layers formed on a microelectronic workpiece is shown, including additional layers formed subsequently above the process steps of the embodiment 340 of FIG. 3C. As shown in FIG. 4A, an OPL layer 146 is formed as a planarization and protective layer on the structure of FIG. 3C. Additionally, a SiARC layer 144 and a PR layer 142 are formed and patterned on the OPL layer 146. The additional layers in FIG. 4A are shown by way of example only, and other stacking and patterning techniques may be utilized. One alternative process is, for example, stacking of an OPL, a SiON, a bottom antireflective coating (BARC), and a PR layer.

[0036] FIG. 4B is an exemplary embodiment 420 after an etching process has been used to open a via in the OPL layer 146 above the conductive region 114 down to the SiN layer 106. As shown in FIG. 4B, this via formation exposes region 304 to the underlying SiN layer 106. However, it will be understood that the OPL layer may also etch the upper HM layer, in which case the OPL etch will stop on the TiN layer 104. In yet another alternative embodiment, the OPL etch may also etch (in whole or in part) the combination of the oxide layer 102 and the TiN layer 104, stopping at the Ru layer 301. Next, FIG. 4C is an exemplary embodiment 440 after a further etching process has been used to remove the SiN layer 106. In contrast to conventional solutions, the Ru layer 301 is not eroded as part of this further etching process. While there is still erosion 182 in the oxide layer 102 and even the TiN layer 104, the lack of erosion in the Ru layer 301 provides improved control of the critical dimension (CD) 404 for the vias formed through the SiN layer 106. Furthermore, gouging 402, if present (in the underlying dielectric layer 108 by etching the SiN layer 106), can be better controlled (or eliminated) and limited to the desired critical dimension, and further, any gouging 402 will be more consistent for various vias across a substrate for a microelectronic workpiece. This consistency results in consistent CD for vias subsequently formed all the way through to the conductive regions 114, thereby improving the performance of the final electronic devices formed in the fabricated microelectronic workpiece.

[0037] As mentioned above, an alternative process flow may be performed after the process step of FIG. 3B. Specifically, the process flow may proceed from the step of FIG. 3B to the steps of FIG. 5A-FIG. 5D. In this alternative process flow, an additional layer may be formed on the Ru layer 301 before the Ru layer 301 is etched. Thus, as shown in the embodiment 500 of FIG. 5A, after the processing of FIG. 3B, an OPL layer 146 is formed on the structure as a planarization and protection layer. Furthermore, a SiARC layer 144 and a PR layer 142 are formed and patterned on the OPL layer 146.

[0038] FIG. 5B is an exemplary embodiment 520 after an etching process has been used to open a via in the OPL layer 146 above the conductive region 114 down to the Ru layer 301. This via formation exposes region 304 to the underlying Ru layer 301 and the HM layer (oxide layer 102 in this embodiment) above the TiN layer 104. However, it will be understood that the OPL layer may also etch the top HM layer, in which case the OPL etch will stop on the TiN layer 104. In yet another alternative embodiment, the OPL etch may also etch (in whole or in part) the combination of the oxide layer 102 and the TiN layer 104, stopping at the Ru layer 301. Then, as shown in embodiment 540 of FIG. 5C, the Ru layer 301 may be etched in region 304 using, for example, an etch that etches Ru but is selective to the underlying hard mask layer. In the example shown, the Ru etch may be an oxygen-based plasma etch. This exposes region 304 to the underlying SiN layer 106. 5D is an exemplary embodiment 560 after a further etching process is used to remove the SiN layer 106. In contrast to conventional solutions, the Ru layer 301 is not eroded as part of this further etching process. Although there may still be erosion 182 in the oxide layer 102 and even the TiN layer 104, the lack of erosion in the Ru layer 301 improves the control of the critical dimension (CD) 404 for the vias formed through the SiN layer 106. Furthermore, gouging 402, if present (in the underlying dielectric layer 108 due to etching of the SiN layer 106), can be better controlled (or eliminated) and limited to the desired critical dimension, and further, any gouging 402 will be consistent for various vias across the substrate for the microelectronic workpiece. This consistency results in consistent CD for vias subsequently formed down to the conductive regions 114, thereby improving the performance of the final electronic devices formed in the fabricated microelectronic workpiece.

[0039] Thus, as described above, a masking layer can be used to open and expose portions of the multi-layer HM and MHM structure. In one embodiment, the MHM is comprised of at least two layers, an upper MHM layer and a Ru layer. In another embodiment, the multi-layer HM and MHM structure may include an upper hard mask and a lower HM between which a multi-layer MHM structure is formed, at least one of the multi-layer MHM layers being a Ru layer underlying another MHM layer. The Ru layer may be etched, for example, by O2 plasma, as shown in Figures 3C and 5C, without gouging into the lower HM layer. Additional layers may be deposited after etching the Ru to form a pattern in the Ru MHM layer using one or more etching process steps. These layers may include an OPL layer, a SiARC layer, and a PR layer, which are deposited, for example, by spin-on coating, on the HM and MHM layers. However, it will be understood that other different layers may be utilized on top of the HM and MHM depending on the particular process flow incorporating the concepts described herein.

[0040] In contrast to prior art solutions, the use of a Ru MHM layer protects the underlying HM layer from gouging. Additionally, the etching characteristics of the Ru etch allow the Ru layer to be etched without gouging the underlying HM layer. Additionally, the lack of erosion of the Ru layer during the etching of the various layers below it allows the Ru MHM layer to maintain its desired via CD without erosion, as also shown in Figures 4A-4C and 5A-5D. This lack of erosion of the Ru MHM layer allows for more precise control of the via CD and other advantages described herein.

[0041] After processing the substrate through the process steps of FIG. 4C or FIG. 5D, an additional etch may be performed to open vias to the conductive regions 114. For example, the dielectric layer 108 (in one embodiment, the ULK layer) may be opened to form vias to an underlying layer such as the Blok layer 110. Finally, the via formation may be completed by etching the Blok layer 110 (either in combination with the etching of the dielectric layer 108 or as a separate additional process step). For example, the underlying Blok layer may also be fully opened during the etching of the SiN HM and ULK layers. Alternatively, an additional Blok etch step may be used to open vias completely through the Blok layer to the underlying patterned conductive layer (e.g., metal layer). The intervening layers (e.g., OPL) may then be removed (using an ashing step in one example) to expose the HM and MHM layers.

[0042] In an exemplary embodiment, once via formation is complete, for example where the via lands on a metal (M) layer or other conductive layer, a post-etch treatment (PET) may be used to remove residue from the bottom and sidewalls of the via. After the PET step, the remaining portions of the HM and MHM layers may be removed by either ex-situ or in-situ methods using a variety of known wet etching, dry etching, or CMP techniques, either alone or in combination. Techniques utilizing a thin Ru layer (e.g., an ALD Ru layer) are particularly beneficial for subsequent removal of the Ru layer. For example, a thin Ru layer may be removed by a CMP process, but removing a thicker Ru layer using a CMP process may not be as effective. Plasma etching of the thin Ru layer may also be more easily accomplished due to the thin nature of the disclosed Ru layer.

[0043] The microelectronic workpiece may also be processed sequentially to subsequently fill the formed vias with metal. Thus, one or more metallization process steps may be used to fill the vias with the metal. Other variations may also be implemented.

[0044] With respect to the Ru MHM layer, the layer can be made from Ru or from a Ru-containing material. In one exemplary embodiment, the Ru MHM layer is a material that contains 95% or more Ru. In another exemplary embodiment, the Ru MHM layer is a material that contains 70 percent or more Ru. Thus, it will be understood that it is possible to utilize a ruthenium layer that contains other materials as the Ru layer, so long as the layer can be used as an etch stop for overlying layers and can be suitably removed without gouging the underlying layers, as described herein.

[0045] Additionally, as discussed above, the etching technique for etching the MHM layer overlying the Ru layer may have a high selectivity to the Ru layer. For example, a Cl2 / Ar etch utilized to etch a TiN MHM layer overlying a Ru layer may have a selectivity to Ru such that the TiN etch rate is in one embodiment at least 5 times as high as the Ru etch rate, and in another embodiment at least 10 times as high. Additionally, the etch used to etch the Ru MHM layer for the embodiments described herein preferably has a selectivity to the next underlying layer of at least 10 or more. Thus, for a selected etch chemistry and process, the etch rate for the Ru MHM layer will be at least 10 times or more than the etch rate of the next underlying layer. As an example, the etch rate of the Ru MHM layer is at least 10 times or more than the etch rate of the HM layer (e.g., SiN, SiO2, or SiON) that is adjacent and underlying the Ru MHM layer. In other embodiments, the Ru MHM layer has a selectivity to the next underlying layer of at least 5 or more over one or more underlying layers. As a further example, a SiN HM layer is used as the next adjacent underlayer and an O2 etch chemistry is used. Other variations may also be implemented.

[0046] It should be noted that one or more deposition processes can be used to form the material layers described herein. For example, one or more depositions can be performed using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputter deposition, and / or other deposition processes. In plasma deposition processes, a precursor gas mixture, including but not limited to, hydrocarbons, fluorohydrocarbons, or nitrogen-containing hydrocarbons, can be used in combination with one or more dilution gases (e.g., argon, nitrogen, etc.) at various pressure, power, flow, and temperature conditions. Thus, for example, a Ru layer can be formed by any of a wide variety of techniques that can be utilized to form ruthenium. For example, an atomic layer deposition process, a sputtering process, a chemical vapor deposition process, and / or a plasma deposition process may be utilized. In one example, a ruthenium layer is formed by use of an atomic layer deposition process that utilizes a ruthenium-containing precursor or derivatives thereof. It will be understood that the techniques described herein are not limited to a particular technique for forming a ruthenium layer, and other processes may be utilized.

[0047] As previously mentioned, in one embodiment, the Ru layer may be deposited by an ALD process. In a preferred embodiment, the Ru layer may be an ALD layer less than 20 nm thick, or more preferably less than 10 nm thick, in one embodiment, 2-5 nm thick. However, it will be understood that the concepts described herein may be utilized with other Ru formation techniques. In this manner, a relatively thin Ru MHM layer is provided, as compared to the thicknesses of other MHM and HM layers. For example, when used with the Ru layer thicknesses described above, an exemplary HM layer thickness may be in the range of, for example, about 20-30 nm, and other MHM layers (e.g., TiN layer 104) may be in the range of, for example, about 20-30 nm.

[0048] The lithography process for the PR layer may be performed using optical lithography, extreme ultra-violet (EUV) lithography, and / or other lithography processes. The etching process may be performed using a plasma etching process, a discharge etching process, and / or other desired etching process. For example, the plasma etching process may be performed using a plasma containing fluorocarbon, oxygen, nitrogen, hydrogen, argon, and / or other gases. In addition, the operating variables of the process steps may be controlled to ensure that the CD target parameters of the vias are achieved during the via formation. The operating variables may include, for example, the chamber temperature, the chamber pressure, the flow rate of the gases, the frequency and / or power applied to the electrode assembly in generating the plasma, and / or other operating variables for the process steps. Variations may also be implemented while still utilizing the techniques described herein.

[0049] The techniques disclosed herein may be utilized during the processing of a wide variety of substrates. The substrate may be any substrate for which patterning of the substrate is desired. For example, in one embodiment, the substrate may be a semiconductor substrate having one or more semiconductor processing layers formed thereon, all of which together may constitute the substrate. Thus, in one embodiment, the substrate may be a semiconductor substrate that has been subjected to multiple semiconductor processing steps resulting in a wide variety of structures and layers, all of which are known in the substrate processing art and which may be considered part of the substrate. For example, in one embodiment, the substrate may be a semiconductor wafer having one or more semiconductor processing layers formed thereon. The concepts disclosed herein may be utilized at any stage of the substrate process flow, for example, any of the numerous photolithography steps that may be utilized to form a completed substrate.

[0050] Figure 6 illustrates an exemplary methodology that uses the processing techniques described herein. It will be understood that the embodiment of Figure 6 is merely exemplary, and that additional methods may utilize the techniques described herein. Additionally, additional processing steps may be added to the methodology illustrated in Figure 6, as the steps described are not intended to be exclusive. Moreover, the order of steps is not limited to the order illustrated in the drawings, as different orders may occur and / or various steps may be combined or performed simultaneously.

[0051] 6 illustrates an exemplary method of processing a substrate. The method includes forming 605 a multi-layer metal hardmask comprising at least a first metal hardmask layer and a second metal hardmask layer underlying the first metal hardmask layer, the second metal hardmask layer being a ruthenium metal hardmask layer comprising ruthenium, the formed multi-layer metal hardmask overlying one or more underlying layers on the substrate. The method further includes 610 etching the multi-layer metal hardmask to provide a patterned ruthenium metal hardmask layer. The method further includes 615 etching the one or more underlying layers using the patterned ruthenium metal hardmask layer as a mask to protect a portion of the one or more underlying layers.

[0052] Further modifications and alternative embodiments of the present invention will become apparent to those skilled in the art in view of the description herein. Therefore, the description herein should be interpreted as illustrative only and for the purpose of teaching those skilled in the art how to practice the present invention. It should be understood that the forms and methods of the present invention shown and described herein should be interpreted as presently preferred embodiments. Equivalent techniques may be used in place of those illustrated and described herein, and certain features of the present invention may be utilized independently of the use of other features, all of which will become apparent to those skilled in the art after having the benefit of the description herein of the present invention.

Claims

1. 1. A method of processing a substrate, the method comprising: forming a multi-layer hardmask stack including at least a first metal hardmask layer and a second metal hardmask layer underlying the first metal hardmask layer, the second metal hardmask layer being a ruthenium metal hardmask layer comprising ruthenium, the formed multi-layer hardmask stack overlying one or more underlying layers on the substrate; Etching the multi-layer hardmask stack to provide a patterned ruthenium metal hardmask layer to expose a portion of the one or more underlying layers; etching the exposed portions of the one or more underlying layers using the patterned ruthenium metal hardmask layer as a mask to protect unexposed portions of the one or more underlying layers; Including, 11. The method of claim 10, wherein the etching of the multi-layer hardmask stack includes a first etching process that etches the first metal hardmask layer and a second etching process that etches the ruthenium metal hardmask layer, and wherein the first etching process and the second etching process are distinct such that no additional patterned layer is formed on the multi-layer hardmask stack between performing the first etching process and performing the second etching process.

2. A method for processing a substrate, the method comprising: forming a multi-layer hardmask stack including at least a first metal hardmask layer and a second metal hardmask layer underlying the first metal hardmask layer, the second metal hardmask layer being a ruthenium metal hardmask layer comprising ruthenium, the formed multi-layer hardmask stack overlying one or more underlying layers on the substrate; Etching the multi-layer hardmask stack to provide a patterned ruthenium metal hardmask layer to expose a portion of the one or more underlying layers; etching the exposed portions of the one or more underlying layers using the patterned ruthenium metal hardmask layer as a mask to protect unexposed portions of the one or more underlying layers; Including, 11. The method of claim 10, wherein the etching of the multi-layer hardmask stack includes a first etching process that etches the first metal hardmask layer and a second etching process that etches the ruthenium metal hardmask layer, the first etching process and the second etching process being different such that after performing the first etching process and before performing the second etching process, an additional patterned layer is formed on the multi-layer hardmask stack.

3. The ruthenium metal hard mask layer is a material containing 95% or more ruthenium. The method according to claim 1 or 2.

4. 3. The method of claim 1 or 2, wherein the ruthenium metal hardmask layer is a material containing 70 percent or more ruthenium.

5. 5. The method of claim 4, wherein the ruthenium metal hardmask layer is formed by atomic layer deposition and has a thickness of 20 nm or less.

6. The ruthenium metal hard mask layer has a thickness of 10 nm or less. The method according to claim 5.

7. The ruthenium metal hard mask layer has a thickness of 20 nm or less. The method according to claim 1 or 2.

8. The method of claim 7 , wherein the one or more underlying layers comprises a dielectric hardmask layer.

9. 7. The method of claim 6, further comprising etching the ruthenium metal hardmask layer with a plasma etch process using a plasma comprising oxygen.

10. said etching of said one or more underlying layers includes forming vias. The method according to claim 1 or 2.

11. The ruthenium metal hard mask layer has a thickness of 10 nm or less. The method according to claim 1 or 2.

12. the one or more underlying layers include a dielectric hardmask layer, the ruthenium metal hardmask layer being formed on the dielectric hardmask layer by utilizing an atomic layer deposition process, the method further comprising etching the ruthenium metal hardmask layer using a plasma etching process using a plasma comprising oxygen. The method of claim 11.

13. The method of claim 1 or 2, wherein the one or more underlying layers comprises a dielectric hardmask layer.

14. the ruthenium metal hardmask layer is formed over the dielectric hardmask layer; The method of claim 13.

15. 3. The method of claim 1 or 2, wherein the first metal hardmask layer is a titanium nitride layer.

16. 14. The method of claim 13, wherein the dielectric hardmask layer comprises at least one of SiN, SiO2, or SiON.

17. the second etching process comprises an oxygen-based plasma etch; The method according to claim 1 or 2.

18. said etching of said one or more underlying layers includes forming vias.

20. The method of claim 17.

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