Photoelectric conversion device, imaging system, and mobile object

Abstract

To reduce the circuit area of a photoelectric conversion device and the power consumption on photon counting.SOLUTION: The photoelectric conversion device has a plurality of pixels, each of the pixels including a first avalanche photodiode and a second avalanche photodiode whose photosensitive areas are different from each other. The first avalanche photodiode is connected between a first waveform shaping circuit and a first switch. The second avalanche photodiode is connected between a second waveform shaping circuit and a second switch. An inverter circuit is provided between a control node of the first switch and a control node of the second switch.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device, an imaging system, and a moving object. [Background technology]

[0002] In recent years, semiconductor devices capable of detecting weak light at the single photon level are expected to be applied in a wide range of fields. In particular, so-called photon counting, which counts the luminance of input light, which has traditionally been treated as a continuous value, as a discrete value called the number of photons, has attracted attention.

[0003] An example of a photodetector element that realizes photon counting in a semiconductor device is the avalanche photodiode (hereinafter, also referred to as "APD"). The APD can amplify the amount of signal charge excited by photons by several to a million times by using the avalanche multiplication phenomenon that occurs due to a strong electric field induced in the pn junction of a semiconductor. By utilizing the high gain of this avalanche multiplication phenomenon, the APD can greatly amplify a weak light signal, improve the signal-to-noise ratio relative to the readout noise generated in the readout circuit, and realize a luminance resolution at the single photon level.

[0004] Patent Document 1 describes an imaging device having a plurality of pixels as an example of a semiconductor device, each of the plurality of pixels having a plurality of single photon avalanche diodes (SPADs). Patent Document 1 describes a method for improving the degree of freedom in setting a photoelectric conversion gain by changing the number of avalanche diodes set to an active state among the avalanche diodes of each pixel according to the brightness of a subject. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-157387 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in Patent Document 1, it is necessary to independently control the avalanche diodes of each pixel, which causes problems such as a large circuit area due to the required signal lines, and an increase in the number of signal lines and the total number of counts in the counter, which causes problems such as a large power consumption required for photon counting.

[0007] The present invention has been made in view of the above problems, and has an object to reduce the circuit area and power consumption of a photoelectric conversion device using an avalanche diode. [Means for solving the problem]

[0008] One aspect of the present invention is a photoelectric conversion device having a plurality of pixels, each of which includes a first avalanche photodiode and a second avalanche photodiode having light-receiving surface areas different from each other, wherein the first avalanche photodiode is connected between a first waveform shaping circuit and a first switch, the second avalanche photodiode is connected between a second waveform shaping circuit and a second switch, and an inverter circuit is provided between a control node of the first switch and a control node of the second switch.

[0009] Another aspect of the present invention is a photoelectric conversion device having a plurality of pixels, each of the plurality of pixels including a first avalanche photodiode and a second avalanche photodiode having a different light receiving surface area, the device further comprising a control unit that, when a reverse bias voltage equal to or greater than a breakdown voltage is applied to one of the first avalanche photodiode and the second avalanche photodiode, does not apply a reverse bias voltage equal to or greater than a breakdown voltage to the other of the first avalanche photodiode and the second avalanche photodiode, In some of the plurality of pixels, a reverse bias voltage equal to or greater than a breakdown voltage is applied to the first avalanche photodiode, and in other pixels, a reverse bias voltage equal to or greater than a breakdown voltage is applied to the second avalanche photodiode. Effect of the Invention

[0010] According to the present invention, it is possible to reduce the circuit area and power consumption for photon counting of a photoelectric conversion device using an avalanche photodiode. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic diagram of a photoelectric conversion device according to a first embodiment. [Diagram 2] 2 is a configuration example of a pixel circuit of the photoelectric conversion device according to the first embodiment. [Diagram 3] 1A and 1B are a schematic plan view and a schematic cross-sectional view showing a configuration example of an APD of a pixel of a photoelectric conversion device according to a first embodiment. [Figure 4] 1 is a graph showing an example of current-voltage characteristics of an APD. [Diagram 5] 1 is a graph showing the relationship between the number of incident photons and the number of counted photons. [Figure 6] 2 is a plan view showing a configuration example of an APD of a pixel of the photoelectric conversion device according to the first embodiment. FIG. [Figure 7] 13 is a configuration example of a pixel circuit of a photoelectric conversion device according to a second embodiment. [Figure 8] FIG. 11 is a schematic diagram of a photoelectric conversion device according to a third embodiment. [Figure 9] 13 is a configuration example of a pixel circuit of a photoelectric conversion device according to a third embodiment. [Figure 10] 13 is a configuration example of a pixel circuit of a photoelectric conversion device according to a third embodiment. [Figure 11] 1 is a block diagram showing a schematic configuration of an imaging system according to an embodiment. [Figure 12] 1 is a diagram illustrating an example of the configuration of an imaging system and a moving object according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG.

[0013] Fig. 1 is a schematic diagram of a photoelectric conversion device according to an embodiment, and Fig. 2 is a configuration example of a pixel circuit of the photoelectric conversion device according to an embodiment. Fig. 3 is a plan view and a cross-sectional view showing a schematic configuration example of an APD of a pixel of the photoelectric conversion device according to an embodiment. Fig. 4 is a graph showing an example of the current-voltage characteristic of an APD, and Fig. 5 is a graph showing the relationship between the number of incident photons and the number of counted photons according to an embodiment. Fig. 6 is a configuration example of a pixel circuit of the photoelectric conversion device according to an embodiment.

[0014] (Overall configuration of photoelectric conversion device) The photoelectric conversion device 1000 according to this embodiment includes a pixel region 100, a vertical scanning circuit 20, a column readout circuit 30, a horizontal scanning circuit 40, a control circuit 50, and a signal processing circuit 60, as shown in FIG.

[0015] The pixel region 100 is provided with a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. A control signal line 14 is arranged in each row of the pixel array of the pixel region 100, extending in the row direction (horizontal direction in FIG. 1). The control signal line 14 is connected to each of the pixels 12 arranged in the row direction, and serves as a common signal line for these pixels 12. In addition, a vertical output line 16 is arranged in each column of the pixel array of the pixel region 100, extending in the column direction (vertical direction in FIG. 1). The vertical output line 16 is connected to each of the pixels 12 arranged in the column direction, and serves as a common signal line for these pixels 12. Although one vertical output line is depicted in FIG. 1, a plurality of vertical output lines may be connected according to the number of bits of the output signal.

[0016] The number of pixels 12 constituting the pixel region 100 is not particularly limited. For example, the pixel region 100 may be constituted by several thousand rows and several thousand columns of pixels 12 as in a general digital camera, or may be constituted by a plurality of pixels 12 arranged in one row or one column. Alternatively, the pixel region 100 may be constituted by one pixel 12.

[0017] The control signal lines 14 of each row are connected to a vertical scanning circuit 20. The vertical scanning circuit 20 is a circuit section that supplies control signals to the pixels 12 via the control signal lines 14, for driving readout circuits in the pixels 12 when reading out pixel signals from the pixels 12.

[0018] One end of the vertical output line 16 of each column is connected to a column readout circuit 30. Pixel signals read out from the pixels 12 are input to the column readout circuit 30 via the vertical output line 16. The column readout circuit 30 may include a memory that holds the pixel signals read out from the pixels 12.

[0019] The horizontal scanning circuit 40 is a circuit section that supplies control signals to the column readout circuit 30 for sequentially transferring pixel signals held in the column readout circuit 30 to the signal processing circuit 60 for each column. The control circuit 50 is a circuit section that supplies control signals that control the operations and timings of the vertical scanning circuit 20, the column readout circuit 30 and the horizontal scanning circuit 40. The signal processing circuit 60 processes the pixel signals.

[0020] (Pixel configuration) The configuration and connection relationship of the pixel 12 according to this embodiment will be described. Fig. 2 is a block diagram or an equivalent circuit diagram showing a schematic configuration of the pixel 12. As shown in Fig. 2, each pixel 12 includes a photoelectric conversion unit 140, a counter circuit 120, a counter circuit 121, a selection circuit 130, an inverter circuit 154, and an inverter circuit 155.

[0021] The photoelectric conversion unit 140 includes an avalanche photodiode 143 (hereinafter, also referred to as "APD") and an APD 144. The anodes of the APD 143 and the APD 144 are connected to a power supply that supplies a voltage VL. The cathode of the APD 143 is connected to a P-type MOS transistor 141 and an input terminal of an inverter circuit 145, and the cathode of the APD 144 is connected to a P-type MOS transistor 142 and an input terminal of an inverter circuit 146. The P-type MOS transistor 141 and the P-type MOS transistor 142 are connected to a power supply that supplies a voltage VH that is higher in potential than the voltage VL. The gate of the NMOS transistor 152 is connected to the output of the inverter circuit 154. The NMOS transistor 152 is further connected to a ground potential that is a reference voltage source and to the cathode of the APD 143. The gate of the NMOS transistor 153 is connected to the output of the inverter circuit 155. The NMOS transistor 153 is further connected to a ground potential and the cathode of the APD 144.

[0022] The output terminals of the inverter circuit 145 and the inverter circuit 146 are output nodes of the photoelectric conversion unit 140. The output terminals of the inverter circuit 145 and the inverter circuit 146 are connected to the counter circuit 120 and the counter circuit 121, respectively. A part of the output of the counter circuit 120 is input to the inverter circuit 155 via the wiring 156, and the output of the inverter circuit 155 is input to the inverter circuit 154. The outputs of the counter circuit 120 and the counter circuit 121 are connected to the vertical output line 16 via the selection circuit 130.

[0023] Note that "connection" is not limited to the case where each element is directly connected. In this specification, when "connection" is used, unless otherwise specified, other elements or members such as resistors and capacitors may be provided between the electrical paths connecting each element that is the subject of the "connection". In other words, as long as the electrical paths of each element are connected, it is included in the category of "connection".

[0024] (Functions of each element of a pixel) The function of each element of a pixel will now be described.

[0025] The photoelectric conversion unit 140 photoelectrically converts light incident on the APD 143 and APD 144, and the generated charges cause avalanche multiplication. To achieve this, a voltage exceeding a reverse breakdown voltage is applied to each of the APD 143 and APD 144. Since a quenching resistor, which will be described later, is connected to each of the APD 143 and APD 144, the voltages of the cathodes of the APD 143 and APD 144 change due to the occurrence of avalanche multiplication.

[0026] 2, APD 143 has a larger area of ​​the light receiving surface of the photoelectric conversion unit than APD 144, and is more sensitive to light. When a microlens for guiding incident light to the light receiving unit is provided on the photoelectric conversion unit, one microlens is disposed so as to cover both APD 143 and APD 144. Therefore, when one microlens is projected onto the light receiving surface, the projection of the microlens at least partially overlaps with the light receiving surfaces of APD 143 and APD 144.

[0027] The P-type MOS transistors 141 and 142 function as quenching resistors when the APD is operated in Geiger mode. Due to the presence of these resistors, the voltages of the cathodes of APD 143 and APD 144 change temporarily due to the occurrence of avalanche multiplication, and then return to the original voltage (typically, voltage VH). This is because an appropriate impedance is generated between the power supply node and the cathode. In this way, by connecting the quenching resistors, the voltage can change a number of times corresponding to the number of incident photons.

[0028] Inverter circuits 145 and 146 determine whether the signals output from APD 143 and APD 144 exceed a threshold value, and output a signal in which the magnitude relationship of the input signal with respect to the threshold value is inverted. The input terminal of inverter circuit 145 is connected to the cathode of APD 143, and the input terminal of inverter circuit 146 is connected to the cathode of APD 144, so that the outputs of inverter circuits 145 and 146 are pulse waves in which the voltage changes at the cathodes of each APD are shaped. In other words, the inverter circuits function as a waveform shaping circuit that shapes the continuous signals output from the APDs into pulses and outputs them.

[0029] As mentioned above, a voltage change occurs at the cathode of the APD every time a photon is incident. Therefore, a number of pulse waves corresponding to the number of incident photons are output from each inverter circuit. As a result, photon counting becomes possible.

[0030] The counter circuits 120 and 121 count the number of photons incident on the APD by counting the number of pulses output from the inverter circuit. For example, a 3-bit counter circuit can obtain count values ​​up to the third power of 2 in decimal notation, for example, from 0 to 7. When the count value reaches the maximum value of the counter circuit, the counter overflows and it is not possible to obtain a count value equal to or greater than the maximum value of the counter circuit. Since the counter circuit restarts counting from the initial value or an indefinite value, the obtained count value does not match the actual number of input photons. Also, when the counter circuit is reset, it starts counting again from the initial value.

[0031] The selection circuit 130 is connected to the vertical scanning circuit 20 via the control signal line 14, and receives a control signal supplied from the control circuit 50 to select reading out the count value of the counter circuit 120 or the counter circuit 121 to the vertical output line 16. The selected signal is output to the vertical output line 16 as the signal of the pixel from which the signal is to be read out among the multiple pixels 12 in the pixel area 100.

[0032] Inverter circuit 155 is connected to counter circuit 120 via wiring 156, and a part of the count value of counter circuit 120 is input to inverter circuit 155. The output terminal of inverter circuit 155 is further connected to the input terminal of inverter circuit 154. Since the inverter circuit outputs a signal that is an inversion of the input signal, the output of inverter circuit 154 and the output of inverter circuit 155 have an exclusive signal relationship. The output of inverter circuit 154 is input to the gate of NMOS transistor 152, and the output of inverter circuit 155 is input to the gate of NMOS transistor 153.

[0033] NMOS transistor 152 functions as a switch that determines whether or not a reverse bias voltage is applied to APD 143 based on the output of inverter circuit 154. Similarly, NMOS transistor 153 functions as a switch that determines whether or not a reverse bias is applied to APD 144 based on the output of inverter circuit 155. Since the output of inverter circuit 154 and the output of inverter circuit 155 have an exclusive signal relationship, the on / off of NMOS transistor 152 and the on / off of NMOS transistor 153 also have an exclusive relationship.

[0034] The control signal line 14 includes a reset signal line RES and a selection signal line SEL. The reset signal line RES is connected to the counter circuits 120 and 121 of the pixels 12 in the corresponding row, and supplies a reset signal that resets the counts of the counter circuits. The selection signal line SEL is connected to the selection circuit 130 of the pixels 12 in the corresponding row, and supplies the selection circuit 130 with a signal that controls the reading of signals from each pixel to a vertical output line.

[0035] (Avalanche photodiode configuration) The structures of the APD 143 and the APD 144 will be described with reference to FIG. 3. In one example, the photoelectric conversion device according to this embodiment can be configured by bonding a first substrate on which the APD 143 and the APD 144 are provided and a second substrate on which other components are provided. The other components may include peripheral circuits such as the vertical scanning circuit 20, the column readout circuit 30, the horizontal scanning circuit 40, the control circuit 50, and the signal processing circuit 60, in addition to the components of the pixel 12 other than the APD 143 and the APD 144. FIG. 3(b) is a schematic cross-sectional view of the substrate on which the APD is provided, taken along the line TT' of FIG. 3(a) out of these two substrates. Note that the photoelectric conversion device according to this embodiment is not limited to the configuration shown in FIG. 3(b), and may be a pixel having a stacked structure in which, for example, a part of the pixel 12 is provided on the first substrate and the other part is provided on the second substrate.

[0036] The APD 143 and the APD 144 of each pixel 12 are both formed on a semiconductor substrate 210. The semiconductor substrate 210 is, for example, an n-type silicon substrate. The semiconductor substrate 210 includes a first surface 212 and a second surface 214 opposed to the first surface 212. For example, the first surface 212 is a front surface of the semiconductor substrate 210, and the second surface 214 is a rear surface of the semiconductor substrate 210.

[0037] An n-type semiconductor region 224 is provided in the semiconductor substrate 210. The n-type semiconductor region 224 is divided into regions corresponding to one pixel 12 by a separation portion made of the p-type semiconductor region 220. The p-type semiconductor region 220 is disposed so as to surround each n-type semiconductor region 224 in a planar view. The second surface 214 side of the p-type semiconductor region 220 is in contact with a p-type semiconductor region 222 provided in contact with the second surface 214 of the semiconductor substrate 210.

[0038] Of the p-type semiconductor region and n-type semiconductor region constituting APD 143 and APD 144 included in one pixel 12, the n-type semiconductor region is surrounded by p-type semiconductor region 220 and p-type semiconductor region 222. The n-type semiconductor region includes one of n-type semiconductor regions 224 separated by p-type semiconductor region 220, and n-type semiconductor regions 226 and 228 arranged in that n-type semiconductor region 224.

[0039] Although an example is shown here in which the n-type semiconductor region 224 in which the multiple APDs of each pixel 12 are arranged is isolated by pn junction isolation, it may be isolated by other element isolation methods such as the STI (Shallow Trench Isolation) method, the DTI (Deep Trench Isolation) method, and the LOCOS (LOCal Oxidation of Silicon) method.

[0040] Each n-type semiconductor region 224 defined by the p-type semiconductor region 220 as a separation portion constitutes a plurality of APDs 143 and APDs 144 included in one pixel 12. The white portions separating the APDs 143 and APDs 144 disposed in the n-type semiconductor region 224 shown in Fig. 3(a) correspond to the p-type semiconductor region 230 in Fig. 3(b).

[0041] In the APD143, the region of the n-type semiconductor region 224 adjacent to the p-type semiconductor regions 220 and 222 serves as a cathode, and the p-type semiconductor regions 220 and 222 in contact with the n-type semiconductor region 224 serve as an anode. The n-type semiconductor region 226 is a part of the cathode of the APD143. In the APD144, the center of the n-type semiconductor region 224 serves as a cathode, and the p-type semiconductor regions 220 and 222 serve as an anode. The n-type semiconductor region 228 is a part of the cathode of the APD144. The n-type semiconductor region 226 and the n-type semiconductor region 228 are disposed in contact with the first surface 212 of the semiconductor substrate 210. The APD143 and the APD144 are separated from elements outside the pixel 12 by the p-type semiconductor region 220. The APD143 and the APD144 include the p-type semiconductor regions 220 and 222 as a common anode. In contrast, the cathode of APD 143 and the cathode of APD 144 are electrically separated by p-type semiconductor region 230. P-type semiconductor region 230 is disposed in contact with first surface 212 of semiconductor substrate 210 between n-type semiconductor region 228 and n-type semiconductor region 226 of adjacent APDs.

[0042] An insulating film 234 is provided on the first surface 212 of the semiconductor substrate 210 on which the APD is provided. A wiring 238 connected to the p-type semiconductor region 220 via a contact plug 236 is provided on the insulating film 234. Furthermore, a wiring 242 connected to the n-type semiconductor region 226 via a contact plug 240 and a wiring 243 connected to the n-type semiconductor region 228 via a contact plug 241 are provided.

[0043] A voltage VL is supplied to the p-type semiconductor region 220, which is the anode, via a wiring 238 and a contact plug 236. The n-type semiconductor region 226, which is the cathode, is connected to the inverter circuit 145 shown in FIG. 2 via a contact plug 240 and a wiring 242. The n-type semiconductor region 228 is connected to the inverter circuit 146 via a contact plug 241 and a wiring 243.

[0044] Taking APD143 as an example, since a reverse bias is applied between p-type semiconductor region 220 and n-type semiconductor region 226, a depletion layer is formed at the PN junction surface between p-type semiconductor regions 220 and 222 and n-type semiconductor region 224. When light is incident on second surface 214 of p-type semiconductor region 222, electron-hole pairs are generated in the semiconductor region of the incident portion. The generated electrons are accelerated by the electric field directed from p-type semiconductor region 222 to n-type semiconductor region 226, causing avalanche multiplication.

[0045] Here, the impurity concentration of the n-type semiconductor region 226 is higher than the impurity concentration of the n-type semiconductor region 224. Furthermore, a potential barrier is formed around the n-type semiconductor region 226 by the p-type semiconductor region 230, so that the charges generated by avalanche multiplication are collected in the n-type semiconductor region 226 corresponding to the generation position.

[0046] Avalanche multiplication also occurs in the APD 144, and the generated charges are collected in the n-type semiconductor region 228. By making the concentration of the n-type semiconductor regions 226, 228 sufficiently high, potential valleys are formed in stages from the PN junction where avalanche multiplication occurs, and charges can be collected in the n-type semiconductor regions 226, 228.

[0047] The impurity concentration of the p-type semiconductor regions 220 and 222 is higher than that of the p-type semiconductor region 230, and an electric field sufficient to cause avalanche multiplication is formed between the p-type semiconductor region 220 and the n-type semiconductor region 224. It is also possible to use a p-type silicon substrate as the semiconductor substrate 210, and to use a p-type semiconductor region 224a having a lower impurity concentration than the p-type semiconductor regions 220 and 222 as the n-type semiconductor region 224 in FIG. 3. In this case, avalanche multiplication occurs due to the electric field formed between the p-type semiconductor region 224a and the n-type semiconductor region 226. In this way, by replacing the semiconductor region 224 with the p-type semiconductor region 224a having a lower impurity concentration than the p-type semiconductor region 220, the electric field strength can be increased, and as a result, avalanche multiplication can be performed at a lower voltage. In such a configuration, providing a guard region that prevents avalanche multiplication from concentrating at the end of the n-type semiconductor region 226 is effective in reducing noise.

[0048] In the pixel configuration example shown in FIG. 3, among the APDs included in one pixel 12, a small-area, low-sensitivity APD 143 is arranged in the center, and a large-area, high-sensitivity APD 144 is arranged on the periphery, but the pixel configuration example is not limited to this.

[0049] As another configuration example, it is possible to utilize the light collection efficiency of a microlens arranged on a pixel. For example, when the area of ​​the APDs included in one pixel 12 is the same, the APD arranged under the center of the microlens can be used for high sensitivity and the APD arranged under the outer periphery of the microlens can be used for low sensitivity, and the same effect can be obtained.

[0050] (APD operation) Next, the operation of the APD in the Geiger mode will be described.

[0051] As an example of voltages VH and VL operating in Geiger mode for APD 143 and APD 144, it is assumed that the APD has a current-voltage characteristic as shown in Fig. 4. The reverse breakdown voltage (hereinafter also simply referred to as the breakdown voltage) of the APD shown in Fig. 4 is between -50V and -53.3V. That is, even if a reverse bias of up to about -50V is applied to this APD, avalanche multiplication does not occur, but if a reverse bias greater than that, that is equal to or greater than the breakdown voltage, is applied, avalanche multiplication occurs. Furthermore, if a reverse bias of about -53.3V or more is applied, the APD operates in what is called Geiger mode, in which the gain of avalanche multiplication is very high.

[0052] In this embodiment, the APD is used as a single photon avalanche diode (SPAD) operating in Geiger mode. Therefore, for example, −50 V is applied as a voltage VL to the anode of the APD, and for example, +3.3 V is applied as a voltage VH to the P-type MOS transistor. As a result, a reverse bias of about 53.3 V is applied to each of the APD 143 and APD 144.

[0053] The gates of the P-type MOS transistors 141 and 142 serving as quenching resistors are usually applied with the same voltage as that applied to the sources. This allows the P-type MOS transistors 141 and 142 to operate as resistor elements whose resistance value is determined by the dimensions of the transistors. It is also possible to set the voltage applied to the gates of the P-type MOS transistors 141 and 142 lower than the voltage applied to the sources, and use them as resistor elements with a higher resistance value. The gate voltages of the P-type MOS transistors 141 and 142 can be appropriately set so as to obtain a desired quenching resistance.

[0054] A reverse bias voltage of 53.3 V, which is the potential difference between voltages VH and VL, is applied to the APD. This reverse bias voltage is higher than the breakdown voltage and is sufficient to cause avalanche multiplication. However, in the absence of seed carriers, avalanche multiplication does not occur and no current flows through the APD.

[0055] In this state, when photons are incident on the second surface 214 side of the semiconductor substrate 210, the photons are absorbed in the n-type semiconductor region 224, generating electron-hole pairs. Of these, the holes are ejected via the p-type semiconductor regions 220, 222, and 230. Meanwhile, the electrons are accelerated by the electric field of the n-type semiconductor region 226 or the n-type semiconductor region 228, causing avalanche multiplication, and the APD operates in the Geiger mode.

[0056] Focusing on the behavior of carriers, when avalanche multiplication occurs and a large current flows through the APD, the potential of the node on the cathode side of the APD drops and avalanche multiplication stops. The carriers at the node on the cathode side are discharged via the P-type MOS transistors 141 and 142 connected as loads, and the node on the cathode side returns to the initial voltage (quenching operation).

[0057] In this way, the potential of the cathode of the APD changes from a carrier standby state to a state in which a large current flows in Geiger mode and the voltage drops as a result of the incidence of photons, and then returns to the carrier standby state again. This voltage waveform is shaped by inverter circuits 145 and 146 to generate a signal pulse that starts at the arrival time of one photon. By counting the number of these signal pulses, so-called photon counting can be performed.

[0058] (Pile-up phenomenon) In such photon counting, when the number of incident photons is small, high linearity can be obtained between the number of incident photons on APD 143 and APD 144 and the count numbers of counter circuits 120 and 121.

[0059] However, when the number of incident photons is large, first, the number of photons counted by the counter circuit 120 may become smaller than the number of photons that actually entered. This is because when the light is extremely strong and the number of incident photons is extremely large, the counter circuit 120 cannot count the photons, and the number of photon counts may become nearly zero.

[0060] On the other hand, since the APD 144 has a lower sensitivity than the APD 143 as described above, even when strong light is incident such that the counter circuit 120 cannot count photons, the counter circuit 121 can count photons accurately.

[0061] The reason why such a phenomenon occurs will be explained below. When the number of incident photons is relatively small, the probability that the timings at which photons are detected within the APDs overlap in time is very low for both APD 143 and APD 144. After the signal pulse rises in inverter circuits 145 and 146, the pulse falls before the next photon arrives, so that it is possible to output a number of signal pulses corresponding to the number of photons incident on the APD.

[0062] On the other hand, when the number of incident photons is large, the probability that photons will be incident on the APD 143 again after the signal pulse rises in the inverter circuit 145 and before it falls is high. The incidence of new photons increases the avalanche current, and as a result, the voltage of the cathode of the APD 143, that is, the input node of the inverter circuit 145, becomes difficult to return. Therefore, a pile-up phenomenon occurs in which multiple signal pulses are connected, and newly incident photons may not be counted. Furthermore, when the number of incident photons is extremely large, the output of the inverter circuit remains at a high level and does not change. As a result, the counter circuit 120 cannot count the signal pulses, and the accuracy of the photon count decreases.

[0063] In this way, in photon counting, the frequency of detectable photon arrival (=light intensity) is determined by the period from when one photon is detected until the next photon can be detected (called the "dead time"). The length of the dead time varies depending on the impedance of the quenching resistors (P-type MOS transistors 141 and 142) and the parasitic capacitance of the cathodes of APDs 143 and 144.

[0064] In order to realize a photoelectric conversion device with ultra-high sensitivity that can detect photons even in very dark conditions such as moonlight or starlight, it is conceivable to provide a relatively large sized pixel 12. However, in a photoelectric conversion device configured in this way, in bright conditions such as under daylight, the frequency of photon detection becomes too high, even if the amount of light is reduced by an aperture mechanism, and the photon counting accuracy decreases.

[0065] (Expanded dynamic range) In this embodiment, APD 144 has a smaller area and lower sensitivity than APD 143. Therefore, in a situation where relatively weak light is incident, the APD 144 shows a smaller count number than the count number 443 of APD 143. Even in a state where relatively strong light is incident and a decrease in the count number corresponding to APD 143 occurs, the photon count number of APD 144 continues to increase linearly with the number of incident photons as long as the frequency of photons incident on APD 144 does not overlap with the dead time.

[0066] Therefore, when the number of incident photons is small and the outputs of both APD 144 and APD 143 can maintain linearity, photodetection with high sensitivity is performed by APD 143. On the other hand, when the number of incident photons is large and the linearity of the output of APD 143 may decrease, photodetection can be performed by APD 144, which can maintain the linearity of the output. By using different APDs for photodetection depending on the light intensity in this way, it is possible to expand the dynamic range of the entire pixel.

[0067] However, in order to count photons with each of the multiple APDs in a pixel in order to select the APD for light detection depending on the light intensity, a circuit for controlling the operation of each APD is required, which increases the circuit area and power consumption.

[0068] (Example of operation) The method for solving the problem according to this embodiment will be described below.

[0069] In this embodiment, for example, it is assumed that the sensitivity ratio between the APD 143 and the APD 144 is n times. For the same amount of light in the region A, the count number corresponding to the APD 143 is n times the count number corresponding to the APD 144.

[0070] 5 is a graph showing the relationship between the number of incident photons and the number of counted photons according to the embodiment. The horizontal axis shows the number of incident photons per unit time and unit area, and the vertical axis shows the number of photon counts in the counter circuit. Plot 443 in FIG. 5 shows the number of photon counts corresponding to APD 143 in FIG. 2, and plot 444 in FIG. 5 shows the number of photon counts corresponding to APD 144. As shown in FIG. 5, when the number of incident photons is small (region A), APD 143 can accurately count the number of photons in the counter circuit 120. Since APD 144 stops counting in region A, plot 444, which is the number of photon counts, does not increase in region A.

[0071] 2 is multiplied by n and a threshold value a is added to the result. This plot shows the relationship between the number of incident photons per unit time and unit area after image processing and the number of photon counts after arithmetic processing in this embodiment.

[0072] When light is incident on APD 143 and APD 144, avalanche multiplication occurs in each APD, and the output of APD 143 is shaped into a pulse wave by inverter circuit 145, and the output of APD 144 is shaped into a pulse wave by inverter circuit 146. The pulse wave output from inverter circuit 145 is input to counter circuit 120, and the pulse wave output from inverter circuit 146 is input to counter circuit 121. As a result, counter circuit 120 counts the total number of photons detected by APD 143, and counter circuit 121 counts the total number of photons detected by APD 144.

[0073] A part of the output of the counter circuit 120 is input to a wiring 156, which is connected to an input terminal of an inverter circuit 155. The output terminal of the inverter circuit 155 is further connected to an input terminal of an inverter circuit 154.

[0074] The inverter circuits 155 and 154 ensure that the signal input to the gate of the NMOS transistor 152 and the signal input to the gate of the NMOS transistor 153 have mutually exclusive signal values.

[0075] For example, in this embodiment, when the number of incident photons is small and the output of the counter circuit 120 is at Lo level, the input level of the inverter circuit 155 is also at Lo level. Therefore, the output of the inverter circuit 155 and the gate voltage of the NMOS transistor 153 are at Hi level, and the NMOS transistor 153 is in the ON state. On the other hand, the output of the inverter circuit 154 and the gate voltage of the NMOS transistor 152 are at Lo level, and the NMOS transistor 152 is in the OFF state.

[0076] Since the NMOS transistor 153 is connected to the ground potential, when the NMOS transistor 153 is turned on, the potential of the cathode (node ​​N) of the APD 144 becomes 0V, and the reverse bias voltage applied to the APD 144 becomes a voltage equal to or lower than the breakdown voltage. In this state, even if electrons are generated by the incidence of photons, the electrons are discharged via the P-type MOS transistor 142 without causing avalanche multiplication. Since the current due to the elementary charge is very small and the voltage drop by the P-type MOS transistor 142 is very small, the threshold of the inverter circuit 146 is not exceeded and a signal pulse is not output. In other words, the NMOS transistor 153 functions as a switch that stops the avalanche multiplication of the APD 144.

[0077] On the other hand, since the gate level of the NMOS transistor 152 is Lo, the NMOS transistor 152 is turned off. As described above, the APD 143 operates in the Geiger mode and performs photon counting.

[0078] When the output of counter circuit 120 reaches a predetermined value a, the level of wiring 156 changes from Lo to Hi. The gate voltage of NMOS transistor 153 connected to the output of inverter circuit 155 becomes Lo level, and NMOS transistor 153 is turned off. On the other hand, the gate voltage of NMOS transistor 152 connected to the output of inverter circuit 154 becomes Hi level, and NMOS transistor 152 is turned on.

[0079] In other words, when the output of the counter circuit 120 reaches a predetermined value a, the avalanche multiplication of the APD 143 stops, and the count number 443 becomes constant when the photon count number reaches a. Meanwhile, the APD 144 starts operating in the Geiger mode, and the count number 444 starts to be counted.

[0080] When the count number 443 does not exceed the threshold a (when the amount of incident light is within the range of region A), only the APD 143 undergoes avalanche multiplication. During this time, the APD 144 does not undergo avalanche multiplication, and photon counting is not performed. On the other hand, when the count number 443 exceeds the threshold a (when the amount of incident light is within the range of region B), the avalanche multiplication of the APD 143 stops, and photon counting is not performed. Only the APD 144 undergoes avalanche multiplication, and photon counting is performed. In this way, when an inverter circuit is used, multiple APDs can be operated exclusively with fewer signal lines, and an increase in the circuit area can be prevented. In addition, the number of counters operating at one time is reduced compared to when counters according to the number of APDs are operated in parallel in each pixel, making it possible to reduce power consumption.

[0081] In this embodiment, the pulse signal input to the selection circuit 130 in each of the regions A and B is only a signal corresponding to either the APD 143 or the APD 144 .

[0082] The outputs of the counter circuit 120 and the counter circuit 121 are input to the selection circuit 130, and the output of the selection circuit 130 is read out to the vertical output line 16 by a control signal supplied from the SEL. The read out count numbers 443 and 444 are subjected to arithmetic processing by the signal processing circuit 60. Specifically, when the count number 443 is equal to or less than the threshold a (when the amount of incident light is within the range of region A), the count number 443 is used as the number of photons. When the count number 443 is equal to or greater than a (when the amount of incident light is within the range of region B), when the count number 444 is x, nx+a is used as the number of photons, and the linearity of the photon count number is maintained by this arithmetic processing.

[0083] Here, the threshold value a is, for example, the maximum value that the counter circuit 120 can count. However, any value can be used for the threshold value a within the range that the counter circuit 120 can count. In addition, it is preferable that the value by which the count number 444 is multiplied is a value according to the sensitivity ratio between the APD 143 and the APD 144. However, an exact sensitivity ratio does not have to be used, and a calculation such as adding a constant instead of multiplication may be performed.

[0084] In this operation example, APD 143 is connected to operate first in Geiger mode, but APD 144 may be connected to operate first. The dynamic range can also be expanded by operating APD 144 first, and then switching the operating APD to APD 143 after a certain time has elapsed depending on the number of photon counts of APD 144. In this case, it is also desirable that only one APD operates at a time, either APD 143 or APD 144, and that only one counter circuit operates.

[0085] Fig. 6 is a plan view showing a schematic configuration example of an APD of a pixel of a photoelectric conversion device according to an embodiment. 610 in Fig. 6 is an APD, and n-type semiconductor regions, which are the cathodes of each APD 610, are separated from each other on a semiconductor substrate. In Fig. 6, the cathodes of eight APDs are electrically connected using wiring 642, and eight APDs 610 are connected to form one APD equivalent to the APD 143 in Fig. 3.

[0086] In other words, the n-type semiconductor region 226 formed like a ring surrounding APD 144 in FIG. 3 is divided into eight, and the eight n-type semiconductor regions 226 are isolated from one another by isolation sections made of p-type semiconductor regions or by other element isolation methods, which is the example configuration shown in FIG.

[0087] In this manner, a plurality of APDs may be connected to form a relatively highly sensitive photodiode.

[0088] Moreover, the APDs shown in FIGS. 3 and 6 are both examples, and the structure of an APD applicable to the present invention is not limited to that shown in either FIG. 3 or FIG. 6, both in plan view and in cross section.

[0089] [Second embodiment] This embodiment will be described with reference to Fig. 7. In this embodiment, the number of counter circuits in each pixel is made smaller than the number of APDs, thereby making it possible to reduce the power consumption related to photon counting while miniaturizing the pixel.

[0090] FIG. 7 is a configuration example of a pixel circuit of a photoelectric conversion device according to an embodiment.

[0091] 7. Since the same reference numerals as those in FIG. 2 are used for the respective numbers in FIG. 7, the explanation thereof will be omitted, and the following mainly explains the parts that are different from the first embodiment.

[0092] 7, the pixel 12 in FIG. 7 includes a photoelectric conversion unit 140, a counter circuit 120, a selection circuit 130, a selection circuit 150, a saturation detection circuit 151, an inverter circuit 154, and an inverter circuit 155.

[0093] When the level of the terminal S is Lo, the selection circuit 150 outputs the input of the 0 terminal from the OUT terminal, and when the terminal S is Hi, the selection circuit 150 outputs the input of the 1 terminal from the OUT terminal.

[0094] An output of the high-sensitivity APD 143 is connected to a terminal 0 of the selection circuit 150 via an inverter circuit 145, and an output of the low-sensitivity APD 144 is connected to a terminal 1 of the selection circuit 150 via an inverter circuit 146. The output of the selection circuit 150 is input to a counter circuit 120. A saturation detection circuit 151 is connected to a terminal S of the selection circuit, and the output of the saturation detection circuit 151 switches from Lo to Hi when the count value of the counter circuit 120 input to the saturation detection circuit 151 exceeds a certain threshold value.

[0095] The saturation detection circuit 151 holds the levels of the Lo signal and Hi signal that are part of the output of the counter circuit 120. The saturation detection circuit 151 is connected to the selection circuit 130, and the held signal levels are read out to the vertical output line 16 together with the count result.

[0096] As mentioned above, the dynamic range is expanded by using APDs with different light sensitivities. However, if multiple APDs are used to count photons, and a corresponding number of counter circuits are arranged for each APD, this limits the area of ​​the pixel and the flexibility of the configuration.

[0097] The method for solving the problem according to this embodiment will be described below.

[0098] A graph showing the relationship between the number of incident photons per unit time and unit area and the number of counted photons in this embodiment is similar to that in Fig. 5. In Fig. 5, the horizontal axis shows the number of incident photons per unit time and unit area, and the vertical axis shows the number of photons counted in the counter circuit. Plot 443 in Fig. 5 shows the number of photon counts corresponding to APD 143 in Fig. 7. Plot 444 shows the number of photon counts corresponding to APD 144 in Fig. 7. Plot 445 is a plot of the relationship between the number of incident photons per unit time and unit area after image processing and the number of photon counts after arithmetic processing in this embodiment.

[0099] In this embodiment as well, for example, the sensitivity ratio between the APD 143 and the APD 144 is assumed to be n times, and the count number corresponding to the APD 143 is assumed to be n times the count number corresponding to the APD 144 in a situation where the same amount of light is incident.

[0100] First, consider the case where the number of incident photons is small (region A). The output of terminal 0 of selection circuit 150 is input to counter circuit 120, and a part of the output of counter circuit 120 is input as Lo level to inverter circuit 155. The output of inverter circuit 155 and the gate voltage of NMOS transistor 153 become Hi level, and NMOS transistor 153 is turned on. On the other hand, the output of inverter circuit 154 and the gate voltage of NMOS transistor 152 become Lo level, and NMOS transistor 152 is turned off.

[0101] Since the source of the NMOS transistor 153 is connected to the ground potential, when the NMOS transistor 153 is turned on, the potential of the cathode (node ​​N) of the APD 144 becomes 0V, and the reverse bias voltage applied to the APD 144 becomes a voltage equal to or lower than the breakdown voltage. In this state, even if electrons are generated by the incidence of photons, the electrons are discharged via the P-type MOS transistor 142 without causing avalanche multiplication. Since the current due to the elementary charge is very small and the voltage drop by the P-type MOS transistor 142 is very small, the threshold of the inverter circuit 146 is not exceeded and a signal pulse is not output. In other words, the NMOS transistor 153 functions as a switch that stops the avalanche multiplication of the APD 144.

[0102] On the other hand, since the gate level of the NMOS transistor 152 is Lo, the NMOS transistor 152 is turned off. As described above, the APD 143 operates in the Geiger mode and performs photon counting.

[0103] When the output of counter circuit 120 reaches a predetermined value a, the level of wiring 156 changes from Lo to Hi. The gate voltage of NMOS transistor 153 connected to the output of inverter circuit 155 becomes Lo level, and NMOS transistor 153 is turned off. On the other hand, the gate voltage of NMOS transistor 152 connected to the output of inverter circuit 154 becomes Hi level, and NMOS transistor 152 is turned on.

[0104] In other words, when the output of the counter circuit 120 reaches a predetermined value a, the avalanche multiplication of the APD 143 stops, and the count number 443 becomes constant at the point when the photon count number reaches a. Meanwhile, the APD 144 starts operating in Geiger mode, and the count number 444 starts to increase.

[0105] Furthermore, the input to the S terminal of the selection circuit 150 becomes Hi, and the selection circuit 150 outputs the input to its 1 terminal.

[0106] In this way, when the number of incident photons is small and photon counting while maintaining linearity is possible with the light-sensitive APD 143 (region A), only the APD 143 operates in Geiger mode. When the amount of incident photons is large and pile-up occurs in the APD 143 (region B), only the APD 144 operates in Geiger mode.

[0107] Since the signal input to the counter circuit corresponds to either the APD 143 or the APD 144, photon counting is possible with one counter circuit for two APDs.

[0108] In this way, by changing the counting process using the magnitude relationship between the threshold value detected by the saturation detection circuit 151 and the count value, it is possible to obtain a seamless linear signal after arithmetic processing as shown in FIG.

[0109] In this embodiment, the number of counter circuits in each pixel can be made smaller than that of the APD, so it is possible to make the pixels smaller and to make the pitch narrower than in the photoelectric conversion device shown in the first embodiment. Also, since the number of counters in the counter circuit can be reduced as in the first embodiment, it is possible to reduce power consumption.

[0110] The reduction in the number of counters will be described in detail below.

[0111] First, consider the case where photon counting is performed using only the APD 143. For example, if you want to obtain a count value of 2 to the power of 16 in decimal notation using a 16-bit counter, you need to count 65,536 times, and power will be consumed for the number of counts.

[0112] In contrast, in this embodiment, a case where photon counting is performed by switching between APD143 and APD144 is considered. For example, the sensitivity ratio n between APD143 and APD144 is 16, and the threshold a is 4096. The signal of APD143 is counted until the photon count reaches the threshold, and when the photon count exceeds the threshold, the photon count is set to a value obtained by multiplying the count of APD144 by 16 and adding 4096. In this case, the number of counts corresponding to the signal of APD144 until the photon count reaches 65536 is 65336 / 16=4096, and the total number of counts until the count reaches 65536 is 4096+4096=8192. In other words, the total number of counts can be reduced, enabling reduction in power consumption.

[0113] In this case, in the range where the signal from APD 144 is used, the resolution is reduced to 1 / n compared to when the signal from APD 143 is used. However, since there is a sufficient amount of light in this range, the effect of optical shot noise is large, and the impact of the reduction in resolution is negligible.

[0114] Furthermore, in this embodiment, there is no need to output the signals of both APD 143 and APD 144 from the photoelectric conversion unit 140, and the only signals that need to be read by the signal processing circuit 60 are the count result of the counter circuit 120 and the saturation signal, making it possible to speed up readout.

[0115] In this operation example, the selection circuit 150 first selects the output of APD 143 and connects it to the counter circuit 120, but it may also connect APD 144 first. The dynamic range can also be expanded by connecting APD 144 first and switching the output after a certain time has passed depending on the number of photon counts of APD 144. In this case, too, only one of APD 143 and APD 144 operates at a time, and only one counter circuit operates.

[0116] [Third embodiment] This embodiment will be described with reference to Figures 8 and 9. In this embodiment, a photoelectric conversion unit used for light detection is set for each pixel, thereby making it possible to reduce power consumption related to photon counting.

[0117] Fig. 8 is a schematic diagram of a photoelectric conversion device according to an embodiment, and Fig. 9 is a configuration example of a pixel circuit of the photoelectric conversion device according to an embodiment. Explanation of parts that overlap with the first and second embodiments will be omitted, and mainly parts that differ from the first and second embodiments will be explained.

[0118] (Overall configuration of photoelectric conversion device) As shown in FIG. 8, the photoelectric conversion device 1000 according to this embodiment has a pixel region 100, a dynamic range control circuit 10, a vertical scanning circuit 20, a column readout circuit 30, a horizontal scanning circuit 40, a control circuit 50, and a signal processing circuit 60.

[0119] The pixel region 100 includes a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns, and a dynamic range control unit 201. A control signal line 14 is arranged in each row of the pixel array of the pixel region 100, extending in the row direction (horizontal direction in FIG. 1). The control signal line 14 is connected to the pixels 12 arranged in the row direction and the dynamic range control unit 201, respectively, and forms a signal line common to these pixels 12 and the dynamic range control unit 201. Furthermore, a vertical output line 16 is arranged in each column of the pixel array of the pixel region 100, extending in the column direction (vertical direction in FIG. 1). The vertical output line 16 is connected to the pixels 12 arranged in the column direction, respectively, and forms a signal line common to these pixels 12. Furthermore, a control signal line 17 is arranged in each column of the pixel array of the pixel region 100, extending in the column direction (vertical direction in FIG. 1).

[0120] The control signal lines 14 of each row are connected to a vertical scanning circuit 20. The vertical scanning circuit 20 is a circuit section that supplies control signals to the pixels 12 via the control signal lines 14, for driving readout circuits in the pixels 12 when reading out pixel signals from the pixels 12.

[0121] The control signal line 15 of each row is connected to a vertical scanning circuit 20. The vertical scanning circuit 20 supplies a control signal to a dynamic range control unit 201 via the control signal line 15.

[0122] One end of the vertical output line 16 of each column is connected to a column readout circuit 30. Pixel signals read out from the pixels 12 are input to the column readout circuit 30 via the vertical output line 16. The column readout circuit 30 may include a memory that holds the pixel signals read out from the pixels 12.

[0123] One end of the control signal line 17 of each column is connected to the dynamic range control circuit 10. The dynamic range control circuit 10 is a circuit section that supplies a dynamic range control signal to a dynamic range control section 201 via the control signal line 17.

[0124] The horizontal scanning circuit 40 is a circuit section that supplies control signals to the column readout circuit 30 for sequentially transferring pixel signals held in the column readout circuit 30 to the signal processing circuit 60 for each column. The control circuit 50 is a circuit section that supplies control signals that control the operations and timings of the vertical scanning circuit 20, the column readout circuit 30 and the horizontal scanning circuit 40. The signal processing circuit 60 processes the pixel signals.

[0125] (Pixel configuration) The configuration and connection relationship between the pixel 12 and the dynamic range control unit 201 according to this embodiment will be described. Fig. 9 is a block diagram or an equivalent circuit diagram showing a schematic configuration of the pixel 12 and the dynamic range control unit 201. Each pixel 12 includes a photoelectric conversion unit 140, a counter circuit 120, a selection circuit 130, a selection circuit 150, an inverter circuit 154, and an inverter circuit 155, as shown in Fig. 2.

[0126] The photoelectric conversion unit 140 includes an APD 143 and an APD 144. The anodes of the APD 143 and the APD 144 are connected to a power supply that supplies a voltage VL. The cathode of the APD 143 is connected in series to a P-type MOS transistor 141 and an input terminal of an inverter circuit 145, and the cathode of the APD 144 is connected in series to a P-type MOS transistor 142 and an input terminal of an inverter circuit 146. The P-type MOS transistor 141 and the P-type MOS transistor 142 are connected to a power supply that supplies a voltage VH having a higher potential than the voltage VL. The gate of the NMOS transistor 152 is connected to the output of the inverter circuit 154. The NMOS transistor 152 is further connected in series to a ground potential and the anode of the APD 143. The gate of the NMOS transistor 153 is connected to the output of the inverter circuit 155. That is, the photoelectric conversion unit 140 has an inverter circuit 154 between the control node of the NMOS transistor 152 and the control node of the NMOS transistor 153. The NMOS transistor 153 is further connected in series with the ground potential and the anode of the APD 144 .

[0127] The output of the inverter circuit 155 is connected to the gate of the NMOS transistor 153 and the input of the inverter circuit 154, and the output of the inverter circuit 154 is connected to the gate of the NMOS transistor 152. The input terminal of the inverter circuit 155 is connected to the dynamic range control unit 201 via the PD selection line PDSEL.

[0128] The output terminals of the inverter circuit 145 and the inverter circuit 146 are the output node of the photoelectric conversion unit 140. The output terminals of the inverter circuit 145 and the inverter circuit 146 are connected to the selection circuit 150.

[0129] The output of the selection circuit 150 is input to the counter circuit 120 , and the output of the counter circuit 120 is connected to the vertical output line 16 via the selection circuit 130 .

[0130] Selection circuit 150 outputs the input of terminal 0 from the OUT terminal when the level of terminal S is Lo, and outputs the input of terminal 1 from the OUT terminal when terminal S is Hi. An output of high-sensitivity APD 143 is connected to terminal 0 of selection circuit 150 via inverter circuit 145, and an output of low-sensitivity APD 144 is connected to terminal 1 of selection circuit 150 via inverter circuit 146. The output of selection circuit 150 is input to counter circuit 120. In addition, an output of inverter circuit 154 is connected to terminal S of the selection circuit, and the output of inverter circuit 154 switches between Lo and Hi depending on the output signal of dynamic range control unit 201 input to inverter circuit 155.

[0131] A control signal is input to the dynamic range control section 201 via a control signal line 15 (DrangeSEL_V), and the output of the dynamic range control circuit 10 is input to the dynamic range control section 201 via a control signal line 17 (DrangeSEL_H).

[0132] As mentioned above, the dynamic range is expanded by using APDs with different light sensitivities. However, in order to count photons with each of the multiple APDs in a pixel in order to use different APDs for light detection depending on the light intensity, a circuit is required to control the operation of each APD, which increases the circuit area and power consumption.

[0133] (Example of operation) The method for solving the problem according to this embodiment will be described below.

[0134] In this embodiment, the APD used for light detection in each pixel is determined by the dynamic range control signal output from the dynamic range control circuit 10.

[0135] First, consider the case where APD 143 is used for photodetection. In this case, the output of dynamic range control unit 201 is Lo. The output of inverter circuit 155 and the input of NMOS transistor 153 are Hi. On the other hand, the output of inverter circuit 154 and the input of NMOS transistor 152 are Lo. The output Lo of inverter circuit 154 is also input to the S terminal of selection circuit 150. When the level of terminal S is Lo, selection circuit 150 outputs the input of terminal 0, i.e., the output of inverter circuit 154, from the OUT terminal.

[0136] When the gate voltage of the NMOS transistor 153 becomes Hi level, the NMOS transistor 153 is turned on. On the other hand, the output of the inverter circuit 154 and the gate voltage of the NMOS transistor 152 become Lo level, and the NMOS transistor 152 is turned off.

[0137] Since the NMOS transistor 153 is connected to the ground potential, when the NMOS transistor 153 is turned on, the potential of the cathode of the APD 144 becomes 0V, and the reverse bias voltage applied to the APD 144 becomes a voltage equal to or lower than the breakdown voltage. In this state, even if electrons are generated by the incidence of photons, the electrons are discharged via the P-type MOS transistor 142 without causing avalanche multiplication. Since the current due to the elementary charge is very small and the voltage drop by the P-type MOS transistor 142 is very small, the threshold of the inverter circuit 146 is not exceeded and a signal pulse is not output. In other words, the NMOS transistor 153 functions as a switch that stops the avalanche multiplication of the APD 144.

[0138] On the other hand, since the gate level of the NMOS transistor 152 is Lo, the NMOS transistor 152 is in an off state. As described above, the APD 143 operates in the Geiger mode and performs photon counting. The output of the APD 143 is shaped into a pulse wave by the inverter circuit 145, and the pulse wave output from the inverter circuit 145 is input to the counter circuit 120 via terminal 0 of the selection circuit 150. The counter circuit 120 counts the total number of photons detected by the APD 143.

[0139] In this way, when APD143 is used for light detection, only APD143 undergoes avalanche multiplication. During this time, APD144 does not undergo avalanche multiplication, and photon counting is not performed. On the other hand, when APD144 is used for light detection, avalanche multiplication of APD143 stops, and photon counting is not performed. Only APD144 undergoes avalanche multiplication and photon counting is performed. In this way, by using an inverter circuit, it is possible to have a configuration in which one APD operates while the other APD does not operate, without significantly increasing the circuit area. Furthermore, compared to the case where large and small APDs and counters corresponding to the APDs are operated in each pixel, the number of APDs operating at one time is reduced, making it possible to reduce power consumption.

[0140] In this embodiment, the case where all the pixels on the pixel region 100 have the structure of pixel 12 has been described, but only some of the pixels may have the structure of pixel 12. In this case as well, the effect of reducing the circuit area and power consumption can be obtained according to the proportion of pixels having the structure of pixel 12.

[0141] In addition, in this embodiment, the NMOS transistors 152 and 153 are used as switches to stop avalanche multiplication, but for example, P-type MOS transistors 141 and 142 may be used as similar switches as shown in Fig. 10. In such a configuration, multiple APDs can be operated exclusively without the NMOS transistors 152 and 153, making it possible to further reduce the circuit area.

[0142] In the explanation so far, each pixel has inverter circuits 154, 155. In such a configuration, it is possible to select the APD to be used for each pixel. However, the present invention can also be applied to a configuration in which an inverter circuit is shared by multiple pixels. In this case, the APD to be selected is fixed according to the connection state of elements between the pixels sharing the inverter circuit, but the total number of required circuits can be reduced, making it possible to further reduce the circuit area and power consumption.

[0143] When implementing this embodiment, different APDs may be used depending on the location, such as using different APDs at the center and outer edge of the pixel array, or only one of APD 143 and APD 144 may be used to detect light across the entire pixel array.

[0144] As in the former case, by using different APDs depending on the location in the pixel array, it is expected that the dynamic range will be expanded and shading will be reduced. More specifically, it is conceivable to use APD143, which has a large pixel area, at the outer edge of the pixel array where shading is likely to occur, and to use APD144 at the center of the pixel array where there is little high-angle light, or to selectively use APD143 and APD144.

[0145] Furthermore, when only one APD is used for the entire pixel array, as in the latter case, the in-plane uniformity of sensitivity can be improved.

[0146] Note that which APD is used for each pixel may be determined by, for example, a mode selection by the user, or may be determined based on an output signal from an AE sensor that is provided to obtain luminance information. A configuration may also be adopted in which the APD to be used by each pixel in the next frame is selected based on a pixel signal captured in a certain frame.

[0147] [Fourth embodiment] The photoelectric conversion system according to this embodiment will be described with reference to Fig. 11. Fig. 11 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0148] The photoelectric conversion devices described in the first to third embodiments are applicable to various photoelectric conversion systems. Examples of the applicable photoelectric conversion systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion systems. FIG. 11 illustrates a block diagram of a digital still camera as an example of these.

[0149] 11 includes an image pickup device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the image pickup device 1004. The system further includes an aperture 1003 that varies the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device according to any one of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0150] The photoelectric conversion system also has a signal processing unit 1007 which is an image generating unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compression as necessary to output image data. The signal processing unit 1007 may be formed on the semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004.

[0151] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data on the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system, or may be removable.

[0152] The photoelectric conversion system further includes an overall control / calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0153] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004, and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0154] In this way, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0155] [Fifth embodiment] The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 12. Fig. 12 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0156] FIG. 12(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an image capture device 310. The image capture device 310 is the photoelectric conversion device (image capture device) described in any of the above embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the image capture device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0157] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0158] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 12(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0159] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0160] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0161] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0162] In this embodiment, two types of APDs, one for high sensitivity and one for low sensitivity, are used, but for example, three or more types of APDs may be used, with one of them operating in Geiger mode. By increasing the number of APD types, a wider dynamic range can be achieved.

[0163] In the above embodiment, the multiple APDs of one pixel are arranged in one n-type semiconductor region 224, but each APD may be arranged in a separate n-type semiconductor region 224. Arranging each APD in a separate n-type semiconductor region 224 is expected to improve the degree of freedom in arrangement on the substrate.

[0164] Furthermore, the photoelectric conversion systems shown in the above fourth and fifth embodiments are examples of photoelectric conversion systems to which a photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 11 and 12.

[0165] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0166] 100 Photoelectric conversion device 143, 144 Avalanche photodiodes 120, 121 Counter circuit

Claims

1. A photoelectric conversion device having a plurality of pixels, each of the plurality of pixels including a first avalanche photodiode and a second avalanche photodiode having light receiving surfaces different in area from each other, the first avalanche photodiode is connected between a first waveform shaping circuit and a first switch, and the second avalanche photodiode is connected between a second waveform shaping circuit and a second switch; a first switch connected to a first node and a second switch connected to a second node;

2. 2. The photoelectric conversion device according to claim 1, further comprising a control unit that controls the first switch and the second switch so as to be in either an on state or an off state.

3. 3. The photoelectric conversion device according to claim 2, wherein the inverter circuit is connected between the first switch and the control unit.

4. When the first switch is in an off state, a reverse bias voltage equal to or higher than a breakdown voltage is applied to the first avalanche photodiode, 4. The photoelectric conversion device according to claim 1, wherein a reverse bias voltage equal to or greater than a breakdown voltage is not applied to the first avalanche photodiode when the first switch is in an on state.

5. 5. The photoelectric conversion device according to claim 1, wherein the first switch is connected in series between the first avalanche photodiode and a reference voltage source.

6. the first switch and the second switch are either in an on state or an off state, 6. The photoelectric conversion device according to claim 1, wherein a state taken by the first switch and a state taken by the second switch are different from each other.

7. 7. The photoelectric conversion device according to claim 1, wherein each of the plurality of pixels includes the inverter circuit.

8. 7. The photoelectric conversion device according to claim 1, wherein some of the pixels included in the plurality of pixels are connected to a common inverter circuit.

9. 9. The photoelectric conversion device according to claim 1, further comprising a counter circuit that counts a first signal based on the charge generated in the first avalanche photodiode and a second signal based on the charge generated in the second avalanche photodiode.

10. the first signal and the second signal are each a pulse signal corresponding to a change in voltage caused by the occurrence of avalanche multiplication, 10. The photoelectric conversion device according to claim 9, wherein the count number output from the counter circuit changes in response to at least one of a change in the first signal and a change in the second signal.

11. The photoelectric conversion device according to claim 9 or 10, characterized in that the first or second avalanche photodiode to which a reverse bias voltage equal to or greater than a breakdown voltage is applied is different when a count number including either the first signal or the second signal is greater than a threshold value and when the count number is smaller than the threshold value.

12. 12. The photoelectric conversion device according to claim 11, further comprising a control circuit that stops application of a reverse bias voltage equal to or greater than a breakdown voltage to the first avalanche photodiode when the count number reaches the threshold value.

13. 13. The photoelectric conversion device according to claim 11, further comprising a control circuit that starts applying a reverse bias voltage equal to or greater than a breakdown voltage to the second avalanche photodiode when the count number reaches the threshold value.

14. 14. The photoelectric conversion device according to claim 1, further comprising a microlens, and in the pixel, the first avalanche photodiode and the second avalanche photodiode are arranged under the same microlens.

15. 15. The photoelectric conversion device according to claim 14, wherein the first avalanche photodiode is an avalanche photodiode arranged under a center portion of the microlens, and the second avalanche photodiode is an avalanche photodiode arranged under an outer periphery of the microlens.

16. A photoelectric conversion device having a plurality of pixels, each of the plurality of pixels including a first avalanche photodiode and a second avalanche photodiode having light receiving surfaces different in area from each other, a control unit that, when a reverse bias voltage equal to or greater than a breakdown voltage is applied to one of the first avalanche photodiode and the second avalanche photodiode, does not apply a reverse bias voltage equal to or greater than a breakdown voltage to the other of the first avalanche photodiode and the second avalanche photodiode; a reverse bias voltage equal to or greater than a breakdown voltage is applied to the first avalanche photodiode in some of the plurality of pixels, and a reverse bias voltage equal to or greater than a breakdown voltage is applied to the second avalanche photodiode in other pixels.

17. The photoelectric conversion device according to any one of claims 1 to 16, a processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

18. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 16, A moving body comprising: a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

Images