Photovoltaic cell and its manufacturing method, photovoltaic module

Abstract

To disclose a photovoltaic battery, a manufacturing method of the same, and a photovoltaic module.SOLUTION: A manufacturing method of a photovoltaic battery comprise the steps of: providing a silicon wafer; forming a tunnel oxide layer at the silicon wafer, and forming a P-type amorphous silicon layer at the tunnel oxide layer; forming an N-type dopant at the P-type amorphous silicon layer; performing processing to the N-type dopant, and converting the P-type amorphous silicon layer to an amorphous silicon layer in which a P-type amorphous silicon and an N-type amorphous silicon are alternately arranged; removing and the N-type dopant and forming a protection layer; performing processing to the protection layer and the amorphous silicon layer, and forming a trench and a projection; processing the silicon wafer and increasing a depth of the trench; removing the protection layer; and performing processing to a first surface of the silicon wafer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The embodiments of the present invention relate to the photovoltaic technology field, and in particular to a photovoltaic cell and its manufacturing method, and a photovoltaic module. [Background technology]

[0002] Photovoltaic cells, also known as solar cells, are devices that convert light energy into electrical energy using the photovoltaic effect. There are many types of photovoltaic cells, which can be divided into several types: single crystal silicon cells, polycrystalline silicon cells, amorphous silicon cells, and compound cells. In 1975, Purdue University in the United States proposed the Interdigitated Back Contact Solar Cell, abbreviated as IBC cell. In the manufacturing process of IBC cells, the local diffusion process of phosphorus and boron requires doping the silicon wafer substrate, which causes a certain amount of recombination and the selective transport performance of the doped carriers is not ideal. In addition, the manufacturing process of conventional IBC cells is complicated, and they cannot be combined with the manufacturing line of conventional crystalline silicon cells, making large-scale mass production difficult.

[0003] Therefore, it is necessary to provide a method for producing photovoltaic cells by using an N-type dopant to convert P-type polycrystalline silicon to N-type polycrystalline silicon, improving the selective transport performance of the doped carriers, simplifying and improving the manufacturing process of photovoltaic cells, and enabling them to be combined with conventional crystalline silicon cell manufacturing lines and realize large-scale mass production. Summary of the Invention [Means for solving the problem]

[0004] In view of the above, an embodiment of the present invention provides a method for manufacturing a photovoltaic cell, the method for manufacturing a photovoltaic cell includes: providing a silicon wafer; forming a tunnel oxide layer on a first surface of the silicon wafer, forming a P-type amorphous silicon layer on the tunnel oxide layer; forming an N-type dopant at a spaced apart position on a side of the P-type amorphous silicon layer away from the silicon wafer, the N-type dopant including phosphorus atoms; and performing a laser treatment on the N-type dopant to mix some of the phosphorus atoms in the N-type dopant into a portion of the P-type amorphous silicon layer in contact with the N-type dopant, thereby forming a P-type amorphous silicon layer. converting the layer into an amorphous silicon layer in which P-type amorphous silicon and N-type amorphous silicon are alternately arranged; removing remaining portions of the N-type dopant on a surface of the amorphous silicon layer and forming a protective layer on a surface of the amorphous silicon layer; performing a laser treatment on the protective layer and the amorphous silicon layer to form trenches and protrusions; treating the silicon wafer, in which a depth of the trench increases during the process of treating the silicon wafer; removing the protective layer; and performing a high temperature treatment on the silicon wafer to convert the amorphous silicon layer into a polycrystalline silicon layer.

[0005] Optionally, after performing a laser treatment on the N-type dopant, the content of phosphorus atoms in the P-type amorphous silicon layer in contact with the N-type dopant is greater than the content of boron atoms.

[0006] Optionally, the silicon wafer has a second side opposite the first side, and the method includes forming a textured structure on the second side of the silicon wafer upon further processing of the silicon wafer.

[0007] To select, the silicon wafer is subjected to a high temperature treatment to convert the amorphous silicon layer into a polycrystalline silicon layer, and then simultaneously forming a passivation layer on a first side and a second side of the silicon wafer; forming an electrode on the first surface of the silicon wafer.

[0008] Optionally, the N-type dopant is a phosphorus-containing silicon glass or a phosphorus-containing wax, where the concentration of phosphorus atoms in the phosphorus-containing silicon glass is 1×10 21 atoms / cm 3 The mass fraction of phosphorus atoms in the phosphorus-containing wax is 0.2% to 2%.

[0009] Optionally, removing remaining portions of the N-type dopant on the surface of the amorphous silicon layer includes using a trough-type apparatus to remove the N-type dopant with a mixture of potassium hydroxide and diethylene glycol butyl ether, where the concentration of potassium hydroxide is in the range of 0.1%-0.5% and the concentration of diethylene glycol butyl ether is in the range of 0.1%-0.3%.

[0010] To be selected, the doping concentration range of boron atoms in the P-type amorphous silicon layer is 3.0×10 19 atoms / cm 3 ~3.0×10 20 atoms / cm 3 It is.

[0011] Optionally, after further processing, the depth of the trench is greater than the combined thickness of the polysilicon layer and the tunnel oxide layer.

[0012] Optionally, a trough type apparatus is utilized to further treat the silicon wafers with potassium hydroxide, an additive, and deionized water, where the potassium hydroxide concentration ranges from 1% to 1.5% and the additive concentration ranges from 0.5% to 1%.

[0013] Optionally, removing the protective layer includes using a trough-type apparatus to remove the protective layer with a hydrogen fluoride solution, where the concentration of hydrogen fluoride ranges from 10% to 20%.

[0014] Optionally, during high temperature treatment, the high temperature range is 850°C to 950°C.

[0015] In accordance with an embodiment of the present invention, there is further provided a photovoltaic cell, the photovoltaic cell comprising a photovoltaic cell manufactured by the method for manufacturing a photovoltaic cell described above.

[0016] In an embodiment of the present invention, there is further provided a photovoltaic module, which includes the photovoltaic cell described above. Effect of the Invention

[0017] Compared with the prior art, the photovoltaic cell and its manufacturing method, and photovoltaic module provided in the embodiments of the present invention achieve at least the following beneficial effects:

[0018] The embodiment of the present invention provides a photovoltaic cell and its manufacturing method, and a photovoltaic module. The manufacturing method of the photovoltaic cell simplifies and improves the manufacturing process of the photovoltaic cell, and uses an N-type dopant to convert P-type polycrystalline silicon into N-type polycrystalline silicon, improving the selective transport performance of the doped carriers, so that the photovoltaic cell can be produced on a large scale in combination with the conventional crystalline silicon cell production line, and the photoelectric conversion efficiency of the photovoltaic cell can be greatly improved.

[0019] Of course, any product embodying an embodiment of the present invention need not specifically achieve all of the technical advantages discussed above simultaneously.

[0020] Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the invention, taken in conjunction with the accompanying drawings, in which: FIG. [Brief description of the drawings]

[0021] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. [Figure 1] FIG. 1 is a flow chart of a method for manufacturing a photovoltaic cell according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a flow chart of one alternative embodiment of a photovoltaic cell according to an embodiment of the present invention. [Diagram 3] FIG. 3 is a diagram showing the atomic structure of a P-type amorphous silicon layer and an N-type dopant before laser treatment of the N-type dopant provided in an embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing the atomic structure of an amorphous silicon layer and an N-type dopant after laser treatment of the N-type dopant provided in an embodiment of the present invention. [Diagram 5] FIG. 5 is a flow chart of another method for manufacturing a photovoltaic cell according to the present invention. [Figure 6] FIG. 6 is a flow chart of another alternative embodiment of a photovoltaic cell according to the present invention. [Figure 7] FIG. 7 is a diagram showing the structure of a photovoltaic cell according to the present invention. [Figure 8] FIG. 8 is a diagram showing the structure of a photovoltaic module according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, each exemplary embodiment of the present invention will be described in detail with reference to the drawings. Note that, unless otherwise specified, the arrangements, formulas, and numerical values ​​corresponding to the components and steps described in these embodiments do not limit the scope of the present invention.

[0023] The following description of at least one illustrative embodiment is merely exemplary in nature and is not intended to be in any way limiting of the invention and its application or uses.

[0024] Techniques, methods and devices that are well known to those skilled in the art may not be described in detail, but where appropriate, said techniques, methods and devices shall be considered part of the description.

[0025] In all examples shown and discussed herein, any specific numerical values ​​should be construed as merely illustrative and not limiting, and therefore other examples of the illustrative embodiments may have different numerical values.

[0026] It should be noted that like symbols and letters indicate like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further considered in the next drawing.

[0027] 1 to 4, Fig. 1 is a flow chart of a method for manufacturing a photovoltaic cell according to an embodiment of the present invention, Fig. 2 is a flow chart of one optional embodiment of the photovoltaic cell according to the present invention, Fig. 3 is a diagram showing the atomic structure of a P-type amorphous silicon layer and an N-type dopant before laser processing of the N-type dopant provided in the present invention, and Fig. 4 is a diagram showing the atomic structure of an amorphous silicon layer and an N-type dopant after laser processing of the N-type dopant 30 provided in the present invention. In this embodiment, a method for manufacturing a photovoltaic cell is provided, and the method for manufacturing the photovoltaic cell includes the following steps:

[0028] S1: Provide silicon wafer 00.

[0029] Specifically, as shown in FIG. 2(a), the silicon wafer 00 is an N-type single crystal silicon, and its resistivity is 1 ohm·cm to 10 ohm·cm. The thickness range of the silicon wafer 00 is 80 μm to 180 μm. If the thickness of the silicon wafer 00 is less than 80 μm, the chip rate in the manufacturing process will be high and the yield will be low. If the thickness of the silicon wafer 00 is more than 180 μm, the resistance and cost of the silicon wafer 00 will be increased. Therefore, by setting the thickness range of the silicon wafer 00 to 80 μm to 180 μm, it is possible to avoid the chip rate in the manufacturing process being high and the yield being low, and to avoid the increase in the electrical resistance and cost of the silicon wafer 00. The thickness of the silicon wafer 00 may be 80 μm, 100 μm, 120 μm, 140 μm, 160 μm or 180 μm for selection.

[0030] The length range of silicon wafer 00 is 156mm to 220mm. If the length of silicon wafer 00 is less than 156mm, the production capacity is low and the cost is high, and if the length of silicon wafer 00 is more than 220mm, the fragmentation rate is high and the difficulty of process uniformity is high. Therefore, by setting the length range of silicon wafer 00 to 156mm to 220mm, it is possible to avoid not only low production capacity and high cost, but also high fragmentation rate and high difficulty of process uniformity. The length of silicon wafer 00 may be 156mm, 170mm, 185mm, 200mm, 210mm or 220mm as a choice.

[0031] Incidentally, the silicon wafer 00 at this time is a clean silicon wafer 00 from which impurities such as organic surface films, impurity ions, and metal contaminants have already been removed, and the cleaning method therefor utilizes existing technology, so a description thereof will be omitted here.

[0032] S2: A tunnel oxide layer 10 is formed on the first surface 01 of the silicon wafer 00, and a P-type amorphous silicon layer 20 is formed on the tunnel oxide layer 10.

[0033] Specifically, as shown in FIG. 2(a), the first surface 01 of the silicon wafer 00 is the surface of the silicon wafer 00 that is not exposed to sunlight (i.e., the back surface), and the materials of the tunnel oxide layer 10 and the P-type amorphous silicon layer 20 are both SiO x , AlO x , SiON x It is one of the following.

[0034] The tunnel oxide layer 10 is used for passivation of the rear surface of the photovoltaic cell, which can provide excellent surface passivation and selective collection of carriers, thereby improving the conversion efficiency of the photovoltaic cell.

[0035] The thickness range of the tunnel oxide layer 10 is 1 nm to 1.5 nm. If the thickness of the tunnel oxide layer 10 is less than 1 nm, the tunnel oxide layer 10 is too thin, which affects the passivation effect of the photovoltaic cell. If the thickness of the tunnel oxide layer 10 is more than 1.5 nm, the tunnel oxide layer 10 is too thick, which affects the tunnel effect of the carriers. Therefore, by setting the thickness range of the tunnel oxide layer 10 to 1 nm to 1.5 nm, it is possible to not only avoid affecting the passivation effect of the photovoltaic cell, but also to avoid affecting the tunnel effect of the carriers. The thickness of the tunnel oxide layer 10 may be 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm or 1.5 nm as desired.

[0036] The method for manufacturing the tunnel oxide layer 10 is a method for forming the tunnel oxide layer 10 by thermal oxidation using a low pressure chemical vapor deposition (LPCVD) apparatus, and the process parameters include a temperature range of 550°C to 650°C, an oxygen flow rate range of 20sccm to 40sccm, a time range of 400s to 600s, and a gas pressure in the furnace tube of 500,000mTorr to 800,000mTorr (i.e., 66500Pa to 106400Pa). It should be noted that if the temperature is less than 550°C, the tunnel oxide layer 10 will be too thin, and if the temperature exceeds 650°C, the formation rate of the tunnel oxide layer 10 will be too fast and difficult to control. If the oxygen flow rate is less than 20sccm, the formation rate of the tunnel oxide layer 10 will be slow and non-uniform, and if the oxygen flow rate exceeds 40sccm, it will not contribute much to the formation of the tunnel oxide layer 10, resulting in a waste of costs. If the time is less than 400s, the tunnel oxide layer 10 is too thin, which affects the passivation effect of the photovoltaic cell, if the time is more than 600s, the tunnel oxide layer 10 is too thick, which affects the tunnel effect of carriers, if the gas pressure in the furnace tube is lower than 500,000mTorr, the pressure is too low, which slows down the formation rate of the tunnel oxide layer 10, if the gas pressure in the furnace tube is more than 800,000mTorr, the pressure is too high, which affects the mean free path of oxygen atoms, which leads to poor uniformity of the tunnel oxide layer 10.

[0037] The P-type amorphous silicon layer 20 serves as a field passivation layer, forming band bending on the surface of the silicon wafer 00, realizing selective transport of carriers, and reducing recombination loss.

[0038] The thickness range of the P-type amorphous silicon layer 20 is 60nm to 300nm. If the thickness of the P-type amorphous silicon layer 20 is less than 60nm, the doping difficulty of the P-type amorphous silicon is high and the metallization matching difficulty is also high. If the thickness of the P-type amorphous silicon layer 20 is more than 300nm, the light absorption situation of the P-type amorphous silicon becomes serious. Therefore, by setting the thickness range of the P-type amorphous silicon layer 20 to 60nm to 300nm, not only can the doping difficulty of the P-type amorphous silicon and the metallization matching difficulty be avoided, but also the light absorption of the P-type amorphous silicon can be avoided from becoming serious. The thickness of the P-type amorphous silicon layer 20 can be selected to be 60nm, 110nm, 160nm, 210nm, 260nm or 300nm.

[0039] The P-type amorphous silicon layer 20 is manufactured as follows: A low pressure chemical vapor deposition (LPCVD) system is used to deposit the amorphous silicon layer, with process parameters including monosilane (SiH4) gas flowing into both the furnace tail and the furnace throat, gas flow rate range of the furnace tail is 1,500sccm to 2,000sccm, gas flow rate range of the furnace throat is 100sccm to 200sccm, temperature range is 590°C to 610°C, and gas pressure range is 100mtorr to 500mtorr (i.e., 13.3Pa to 66.5Pa). It should be noted that if the gas flow rate of the furnace tail is less than 1,500sccm, the amorphous silicon at the furnace tail will be thin and the furnace will be thick. Step 1: if the gas flow rate of the tail exceeds 2,000 sccm, the amorphous silicon at the furnace tail becomes thicker; if the gas flow rate of the furnace throat is less than 100 sccm, the amorphous silicon at the furnace throat becomes thinner; if the gas flow rate of the furnace throat is more than 200 sccm, the amorphous silicon at the furnace throat becomes thicker; if the temperature is less than 590°C, the amorphous silicon layer 20 becomes thinner; if the temperature is more than 610°C, the amorphous silicon layer becomes thicker; if the gas pressure is less than 100 mtorr, the amorphous silicon layer becomes thinner; if the gas pressure is more than 500 mtorr, the amorphous silicon layer becomes thicker and the uniformity becomes poor; and step 2, ex-situ doping the amorphous silicon layer with boron using a diffusion device.

[0040] S3: N-type dopants 30 are formed at intervals on the side of the P-type amorphous silicon layer 20 away from the silicon wafer 00, and the N-type dopants include phosphorus atoms.

[0041] Specifically, as shown in FIG. 2(a), forming N-type dopants 30 at intervals on the side of the P-type amorphous silicon layer 20 away from the silicon wafer 00, Step 1: printing an N-type dopant 30 on a side of the P-type amorphous silicon layer 20 away from the silicon wafer 00 using a printer and a stencil; Step 2: using a chain drying oven to dry the N-type dopant 30, the process parameters of which include a drying temperature range of 150°C to 250°C and a drying time range of 1 to 3 minutes, and it should be noted that when the drying temperature is less than 150°C, the drying effect is normal, and when the drying temperature is more than 250°C, the N-type dopant 30 is easy to fall off, and when the drying time is less than 1 minute, the drying effect is normal, and when the drying time is more than 3 minutes, the N-type dopant 30 is easy to fall off.

[0042] The thickness of the N-type dopant 30 is in the range of 1 μm to 50 μm. If the thickness of the N-type dopant 30 is less than 1 μm, the doping source will be insufficient, and if the thickness of the N-type dopant 30 is more than 50 μm, the drying effect will be poor and the material will be wasted. Therefore, by setting the thickness of the N-type dopant 30 to 1 μm to 50 μm, it is possible to not only avoid the shortage of the doping source, but also to avoid the deterioration of the drying effect and the waste of the material. The thickness of the N-type dopant 30 may be 1 μm, 15 μm, 30 μm, 45 μm or 50 μm as desired.

[0043] S4: A laser treatment is performed on the N-type dopant 30 to mix some of the phosphorus atoms in the N-type dopant 30 into the portion of the P-type amorphous silicon layer 20 that contacts the N-type dopant 30, thereby converting the P-type amorphous silicon layer 20 into an amorphous silicon layer 40 in which P-type amorphous silicon 41 and N-type amorphous silicon 42 are arranged alternately.

[0044] Specifically, as shown in FIG. 2(b) and FIG. 3-FIG. 4, the method of performing laser processing on the N-type dopant 30 is to irradiate the N-type dopant 30 with a nanosecond laser device, and the process parameters include a laser wavelength range of 300 nm-1,000 nm, a laser line width range of 50 μm-120 μm, a laser energy range of 5 W-20 W, and an overlapping area range of adjacent spots of 10%-30%. It should be noted that if the laser wavelength is less than 300 nm, the light source action depth is shallow, which affects the doping effect, and if the laser wavelength is more than 1,000 nm, it affects the doping effect and at the same time, the laser causes great damage. If the laser line width is less than 50 μm, the production capacity of the laser is too small, and if the laser line width is more than 120 μm, the uniformity of the energy distribution of the spot is poor. If the laser energy is less than 5 W, the doping concentration of the phosphorus atoms will be insufficient, and if the laser energy exceeds 20 W, there will be significant damage to the N-type dopant 30 and the P-type amorphous silicon layer 20. If the overlapping area of ​​adjacent spots is less than 10%, the doping concentration of the phosphorus atoms at the spot intersection will be insufficient, and if the overlapping area of ​​adjacent spots exceeds 30%, there will be significant damage to the N-type dopant 30 at the energy intersection.

[0045] S5: The N-type dopant 30 is removed and a protective layer 50 is formed on the side of the amorphous silicon layer 40 away from the silicon wafer 00.

[0046] Specifically, as shown in FIG. 2(c), first, the remaining portion of the N-type dopant 30 on the surface of the amorphous silicon layer is removed, and then, a protective layer 50 is formed on the side of the amorphous silicon layer 40 away from the silicon wafer 00, and the material of the protective layer 50 is SiO x , SiON x , SiN x The protective layer 50 serves to protect the non-open areas of the amorphous silicon layer 40.

[0047] The thickness of the protective layer 50 is 2 nm or more. If the thickness of the protective layer 50 is less than 2 nm, the protective effect of the protective layer 50 decreases.

[0048] The method of forming the protective layer 50 is to first install an ozone (chemical formula O3) generator and a heating device at the feed end of the chain type device to generate a thin protective layer 50, and then thicken the protective layer 50 with a hydrogen peroxide solution (called hydrogen peroxide water) at the end of the trough type device. Here, the heating temperature range of the heating device is 60°C to 80°C. If the heating temperature is less than 60°C, the thickness of the protective layer 50 will be thin. If the heating temperature exceeds 80°C, the requirements for the device are high, increasing the difficulty of the process. The concentration range of the hydrogen peroxide solution is 1% to 2%. If the concentration of the hydrogen peroxide solution is less than 1%, the thickness of the protective layer 50 will be thin. If the concentration of the hydrogen peroxide solution is more than 2%, the hydrogen peroxide solution will volatilize quickly, wasting costs. The temperature of the trough type device is 80°C, and the time is 120s.

[0049] S6: A laser process is performed on the protective layer 50 and the amorphous silicon layer 40 to form a trench 61 and a protrusion 62.

[0050] Specifically, as shown in FIG. 2(d), a picosecond laser device is used to irradiate the protective layer 50 and the amorphous silicon layer 40 to form alternating trenches 61 and protrusions 62, and the process parameters include a laser wavelength range of 300 nm to 1,000 nm, a laser spot size range of 50 μm to 120 μm, a laser energy range of 2 W to 15 W, and an overlapping area range of adjacent spots of 10% to 30%. It should be noted that if the laser wavelength is less than 300 nm, the light source action depth is shallow, which affects the doping effect, and if the laser wavelength is more than 1,000 nm, the doping effect is affected and the laser causes great damage. If the laser spot is less than 50 μm, the production capacity of the laser is too low, and if the laser spot is more than 120 μm, the protective layer 50 cannot be removed uniformly. If the laser energy is less than 2 W, the protective layer 50 cannot be removed uniformly, and if the laser energy exceeds 15 W, the laser causes significant damage to the protective layer 50 and the amorphous silicon layer 40. If the overlapping area of ​​adjacent spots is less than 10%, the protective layer 50 cannot be removed uniformly, and if the overlapping area of ​​adjacent spots exceeds 30%, the laser causes significant damage to the protective layer 50 and the amorphous silicon layer 40.

[0051] The width of the protrusion 62 perpendicular to the laser irradiation direction (i.e., the distance between adjacent trenches 61) is 100 μm to 500 μm. If the width of the protrusion 62 perpendicular to the laser irradiation direction is less than 100 μm, the difficulty of metallization alignment is large, and if the width of the protrusion 62 perpendicular to the laser irradiation direction exceeds 500 μm, the carrier absorption is affected. Therefore, by setting the width of the protrusion 62 perpendicular to the laser irradiation direction to 100 μm to 500 μm, not only the difficulty of metallization alignment can be reduced, but also the influence on the carrier absorption can be avoided. The width of the protrusion 62 perpendicular to the laser irradiation direction may be 100 μm, 200 μm, 300 μm, 400 μm, or 500 μm as a selectable width.

[0052] The width of the trench 61 perpendicular to the laser irradiation direction (i.e., the distance between adjacent protrusions 62) is 100 to 300 μm. If the width of the trench 61 perpendicular to the laser irradiation direction is less than 1 μm, there is a risk of electric leakage, and if the width of the trench 61 perpendicular to the laser irradiation direction exceeds 50 μm, it affects the absorption of carriers. Therefore, by setting the width of the trench 61 perpendicular to the laser irradiation direction to 100 to 300 μm, not only the risk of electric leakage can be avoided, but also the influence on the absorption of carriers can be avoided. The width of the trench 61 perpendicular to the laser irradiation direction may be 100 μm, 150 μm, 200 μm, 250 μm, or 300 μm as a selectable width.

[0053] S7: The silicon wafer 00 is processed, and in the course of further processing the silicon wafer 00, the depth of the trenches 61 increases.

[0054] Specifically, as shown in FIG. 2(e), the method for processing the first surface 01 of the silicon wafer 00 is to etch the silicon wafer 00 in a trough-type device, and the process parameters include a chemical temperature range of 80°C to 85°C and an immersion time range of 200s to 500s. It should be noted that if the chemical temperature is lower than 80°C, the etching speed is slow, and if the chemical temperature is higher than 85°C, the etching speed is too fast. If the immersion time is less than 200s, the depth of the trench after etching is insufficient, and if the immersion time is more than 500s, the depth of the trench after etching is almost unchanged, resulting in damage to the protective layer 50 and the amorphous silicon layer 40 in the area not irradiated by the laser.

[0055] The reason why the depth of trench 61 after processing first surface 01 of silicon wafer 00 is required to be greater than the depth of trench 61 after laser processing protective layer 50 and amorphous silicon layer 40 is that trench 61 separates P-type amorphous silicon 41 and N-type amorphous silicon 42, forming a gap at the connection point between the two, thereby improving the performance of the photovoltaic cell, such as the current and open circuit voltage.

[0056] S8: The protective layer 50 is removed (as shown in FIG. 2(f), this step will be described in the following examples and will not be described here).

[0057] S9: The silicon wafer 00 is subjected to a high temperature treatment to convert the amorphous silicon layer 40 into a polycrystalline silicon layer 70.

[0058] Specifically, as shown in (g) of FIG. 2, the method of high-temperature processing of the first surface 01 of the silicon wafer 00 is to convert the amorphous silicon layer 40 into a polycrystalline silicon layer 70 using a tube furnace high-temperature device, and the process parameters include a temperature range of 850°C to 950°C, an internal tube pressure range of 100 mtorr to 800 mtorr, and a flow rate ratio of nitrogen gas (N2) and oxygen gas (O2) in the mixed gas of nitrogen gas and oxygen gas being introduced of 1:1 to 5:1.

[0059] Here, if the temperature is lower than 850°C, the conversion rate from the amorphous silicon layer 40 to the polycrystalline silicon layer 70 is low, and if the temperature is higher than 950°C, the interface state density of the polycrystalline silicon layer 70 increases. If the pressure inside the tube is lower than 100 mtorr, annealing during the high-temperature treatment process is insufficient, and if the pressure inside the tube is higher than 800 mtorr, the uniformity of the resulting polycrystalline silicon layer 70 is poor. If the gas flow ratio of nitrogen gas to oxygen gas is lower than 1:1, the consumption of oxygen gas is high, and if the gas flow ratio of nitrogen gas to oxygen gas is higher than 5:1, annealing during the high-temperature treatment process is insufficient.

[0060] As an emitter layer, the polysilicon layer 70 can further enhance the transport of photo-generated carriers and improve the performance of the photovoltaic cell, such as backing factor, short circuit current and open circuit voltage.

[0061] The method for manufacturing a photovoltaic cell provided in this embodiment has at least the following beneficial effects compared with the prior art.

[0062] In this embodiment, the manufacturing process of a photovoltaic cell is simplified and improved, and the P-type polycrystalline silicon is converted into N-type polycrystalline silicon using an N-type dopant, and the selective transport performance of the carriers formed by doping is improved. This type of photovoltaic cell can be produced on a large scale in combination with a conventional crystalline silicon cell production line, and a manufacturing method of a photovoltaic cell is provided, which can greatly improve the photoelectric conversion efficiency of the photovoltaic cell.

[0063] In one optional embodiment, as shown in FIGS. 3-4, after performing laser treatment on the N-type dopant 30, the content of phosphorus atoms 31 in the P-type amorphous silicon layer 20 in contact with the N-type dopant 30 is greater than the content of boron atoms 21.

[0064] Specifically, the doping concentration of phosphorus atoms 31 is 2×10 20 atoms / cm 3 The doping concentration of phosphorus atoms 31 is required to be 2×10 or more. 20 atoms / cm 3 If it is lower, not only will the contact resistance be affected, but the field passivation effect will also be reduced.

[0065] Generally, the doping concentration and curve are monitored using a 4-point probe sheet resistance meter and a diffusion concentration meter / junction depth meter (abbreviated as ECV meter), and the minority carrier lifetime passivation monitoring method further contributes to confirming the doping effect.

[0066] In one optional embodiment, Fig. 5 is a flowchart of another method for manufacturing a photovoltaic cell provided by the present invention, and Fig. 6 is a flowchart of another optional embodiment of a photovoltaic cell provided by the present invention. As shown in Figs. 5 and 6, a process is performed on a first surface 01 of a silicon wafer 00, and at the same time, a process is performed on a second surface 02 of the silicon wafer 00, so that a texture structure is formed on the second surface 02 of the silicon wafer 00 (not shown).

[0067] Specifically, by performing a texturing process on the second surface 02 (front surface) of the silicon wafer 00, the number of light rays absorbed by the silicon wafer can be increased, and the photoelectric conversion efficiency of the photovoltaic cell can be improved. Here, the texture structure is generally a pyramid, and the size of the shape is usually in the range of 1 μm to 3 μm, and the height is usually in the range of 0.5 μm to 2 μm. Specifically, if the size of the shape is larger than 3 μm or the height is smaller than 0.5 μm, both of these will result in a decrease in the surface reflectance of the silicon wafer 00, and if the size of the shape is smaller than 1 μm or the height is higher than 2 μm, both of these will result in poor surface passivation of the silicon wafer 00.

[0068] In one alternative embodiment, as shown in FIGS. 5 and 6, a high-temperature treatment is performed on the first surface 01 of the silicon wafer 00 to convert the amorphous silicon layer 40 into a polycrystalline silicon layer 70, and then: forming a passivation layer 80 simultaneously on a first surface 01 and a second surface 02 of the silicon wafer 00; forming an electrode 90 on the first surface 01 of the silicon wafer 00.

[0069] Specifically, the method for preparing a photovoltaic cell provided in this embodiment further includes the following steps:

[0070] S10: A passivation layer 80 is formed simultaneously on the first surface 01 and the second surface 02 of the silicon wafer 00.

[0071] The passivation layer 80 may be two or three layers, with two layers being preferred in this embodiment.

[0072] The passivation layer 80 includes a first passivation layer 81 and a third passivation layer 83 located on the first side 01 of the silicon wafer 00, and a second passivation layer 82 and a fourth passivation layer 84 located on the second side 02 of the silicon wafer 00, where the first passivation layer 81 and the second passivation layer 82 are both film layers close to the silicon wafer 00, and the third passivation layer 83 and the fourth passivation layer 84 are both film layers away from the silicon wafer 00.

[0073] As shown in FIG. 6(h), the material of the first passivation layer 81 and the second passivation layer 82 is SiO x or AlO x , whose role is to reduce the recombination rate in photovoltaic cells, improve the minority carrier lifetime, and increase the efficiency of photovoltaic cells.

[0074] The thickness range of the first passivation layer 81 and the second passivation layer 82 is 5 nm to 20 nm. If the thickness of the first passivation layer 81 and the second passivation layer 82 is less than 5 nm, the passivation effect of the photovoltaic cell is poor, and if the thickness of the first passivation layer 81 and the second passivation layer 82 exceeds 20 nm, the paste used in manufacturing the electrode 90 later is difficult to be baked, and the contact effect between the electrode and the silicon wafer 00 is poor. Therefore, by setting the thickness range of the first passivation layer 81 and the second passivation layer 82 to 5 nm to 20 nm, not only can the passivation effect of the photovoltaic cell be prevented from being deteriorated, but also the contact effect between the electrode and the silicon wafer 00 can be prevented from being deteriorated. The thickness of the first passivation layer 81 and the second passivation layer 82 may be 5 nm, 10 nm, 15 nm or 20 nm as desired.

[0075] The manufacturing method of the first passivation layer 81 and the second passivation layer 82 can be divided into the following two methods.

[0076] Method 1: This is the same as the method for forming the protective layer 50 in S5, and therefore the description thereof will be omitted here.

[0077] Method 2: Using a high-temperature tube furnace, a mixed gas of nitrogen gas (N2) and oxygen gas (O2) is introduced to oxidize the silicon wafer 00, and the process parameters include a nitrogen gas to oxygen gas flow ratio range of 1:1 to 5:1, a temperature range of 650°C to 750°C, and a time range of 10 min to 20 min. If the nitrogen gas to oxygen gas flow ratio is less than 1:1, the proportion of oxygen gas will be low, which will lead to the first passivation layer 81 and the second passivation layer 82 being thin and not dense. If the nitrogen gas to oxygen gas flow ratio is less than 5:1, the proportion of oxygen gas will be low, which will lead to the first passivation layer 81 and the second passivation layer 82 being thin and not dense. If the temperature is lower than 650°C, the first passivation layer 81 and the second passivation layer 82 will be thin and not dense; if the temperature is higher than 750°C, it will not contribute much to the passivation effect and will increase the cost; if the time is less than 10 minutes, the first passivation layer 81 and the second passivation layer 82 will be thin and not dense; if the time is more than 20 minutes, the first passivation layer 81 and the second passivation layer 82 will be thick and will affect the efficiency of the battery cell.

[0078] As shown in FIG. 6(i), the material of the third passivation layer 83 and the fourth passivation layer 84 is SiN x , SiN x and SiON x and SiO x Mixture of SiN x and SiON x A mixture of SiN x and SiO x The role of the anti-reflection layer is to increase the light absorption amount of the silicon wafer 00 and improve the photoelectric conversion efficiency.

[0079] The thickness range of the third passivation layer 83 is 75nm-85nm, and the thickness range of the fourth passivation layer 84 is 70nm-80nm. If the thickness of the third passivation layer 83 is less than 75nm and the thickness of the fourth passivation layer 84 is less than 70nm, the optimal anti-reflection and transmission increase effect cannot be achieved. If the thickness of the third passivation layer 83 exceeds 85nm and the thickness of the fourth passivation layer 84 exceeds 80nm, the required process time is long, the efficiency is low, and the material is wasted and the cost is increased. Therefore, by setting the thickness range of the third passivation layer 83 to 75nm-85nm and the thickness range of the fourth passivation layer 84 to 70nm-80nm, it is possible to not only ensure the optimal anti-reflection and transmission increase effect, but also to avoid problems such as the required process time being long, the efficiency being low, the material being wasted and the cost being increased. Optionally, the third passivation layer 83 may have a thickness of 75 nm, 77 nm, 79 nm, 81 nm, 83 nm or 85 nm, and the fourth passivation layer 84 may have a thickness of 70 nm, 72 nm, 74 nm, 76 nm, 78 nm or 80 nm.

[0080] The manufacturing method of the third passivation layer 83 and the fourth passivation layer 84 is both plasma enhanced chemical vapor deposition, and the process parameters of the third passivation layer 83 and the fourth passivation layer 84 are the same except for the temperature, and the other parameters include a gas flow ratio range of 1:10 to 3:10 for the mixed gas of monosilane (SiH4) and ammonia (NH3), and a pressure range of 1,000 mtorr to 2,000 mtorr. If the gas flow ratio is less than 1:10, the refractive index of the generated passivation layer is low and the passivation effect is poor, and if the gas flow ratio is more than 3:10, the refractive index of the passivation layer is high and the contact effect is poor. If the pressure is less than 1,000 mtorr, the coating speed is slow, and if the pressure is more than 2,000 mtorr, the uniformity of the generated film layer is poor.

[0081] The temperature range for manufacturing the third passivation layer 83 is 500°C to 570°C. If the temperature for manufacturing the third passivation layer 83 is less than 500°C, the coating speed will be slow, and if the temperature for manufacturing the third passivation layer 83 exceeds 570°C, the uniformity of the generated film layer will be poor.

[0082] The temperature range for manufacturing the fourth passivation layer 84 is 460°C to 500°C. If the temperature for manufacturing the fourth passivation layer 84 is less than 460°C, the coating speed will be slow, and if the temperature for manufacturing the fourth passivation layer 84 is more than 500°C, the uniformity of the generated film layer will be poor.

[0083] In addition, the manufacturing method of the passivation layer 80 includes, in addition to the above-mentioned method, atomic layer deposition (abbreviated as ALD), reactive sputtering, magnetron sputtering (a type of physical vapor deposition PVD), etc., which can form the film layer described in this embodiment, but is not limited to these.

[0084] S11: An electrode 90 is formed on the first surface 01 of the silicon wafer 00.

[0085] As shown in FIG. 6(j), the electrode 90 can be formed on the first surface 01 of the silicon wafer 00 using a conventional silk screen printing method and a conventional paste. As an option, the electrode 90 in contact with the P-type amorphous silicon 41 is preferably a silver-aluminum paste, in which the proportion of the silver (Ag) component ranges from 80% to 90%, the proportion of the aluminum (Al) component ranges from 1% to 3%, and the width of the electrode 90 ranges from 20 μm to 40 μm. The electrode 90 in contact with the N-type amorphous silicon 42 is preferably a silver paste, in which the proportion of the silver (Ag) component ranges from 82% to 92%, and the width of the electrode 90 ranges from 20 μm to 40 μm. The silver-aluminum paste and the silver paste corrode the passivation layer 80 during the high-temperature sintering process, and form a good ohmic contact with the polycrystalline silicon layer 70 on the back surface of the silicon wafer 00.

[0086] Alternatively, the electrodes 90 may be made of aluminum paste, silver-clad copper, or the like.

[0087] In addition, the method for producing the electrode 90 includes, in addition to the above-mentioned method, a metal vapor deposition method and an electroplating method capable of forming the electrode 90 described in this embodiment, but is not limited to these.

[0088] The width range of the electrode 90 perpendicular to the laser irradiation direction is 10 μm to 80 μm. If the width of the electrode 90 perpendicular to the laser irradiation direction is less than 10 μm, it affects the transport of carriers and increases the difficulty of the process, and if the width of the electrode 90 perpendicular to the laser irradiation direction exceeds 80 μm, the cost increases. Therefore, by setting the width range of the electrode 90 perpendicular to the laser irradiation direction to 10 μm to 80 μm, it is possible to avoid not only the increase in the difficulty of the process due to the influence on the transport of carriers, but also the increase in the cost. The width of the electrode 90 perpendicular to the laser irradiation direction may be 10 μm, 25 μm, 40 μm, 65 μm, or 80 μm as a selectable range.

[0089] The depth range of the electrode 90 penetrating into the polycrystalline silicon layer 70 is 10 nm to 100 nm. If the electrode 90 penetrates into the polycrystalline silicon layer 70 to a depth less than 10 nm, the contact resistance will be deteriorated, and if the electrode 90 penetrates into the polycrystalline silicon layer 70 to a depth greater than 100 nm, the passivation effect will be affected. Therefore, by setting the depth range of the electrode 90 penetrating into the polycrystalline silicon layer 70 to 10 nm to 100 nm, not only the deterioration of the contact resistance can be avoided, but also the influence on the passivation effect can be avoided. The depth of the electrode 90 penetrating into the polycrystalline silicon layer 70 may be 10 nm, 30 nm, 50 nm, 70 nm, or 100 nm as desired.

[0090] In one alternative embodiment, the N-type dopant 30 is a phosphorus-containing silicon glass or a phosphorus-containing wax, where the concentration of phosphorus atoms 31 in the phosphorus-containing silicon glass is 1×10 21 atoms / cm 3That is, the mass fraction of phosphorus atoms 31 in the phosphorus-containing wax is 0.2% to 2%.

[0091] Specifically, the phosphorus atom 31 concentration in phosphorus-containing silicon glass is 1×10 21 atoms / cm 3 or more, or if the mass fraction of phosphorus atoms 31 in the phosphorus-containing wax is not 0.2% to 2%, the doping concentration of phosphorus atoms 31 in the P-type amorphous silicon layer 20 will be low, and will not contribute to the conversion of P-type amorphous silicon 41 in the P-type amorphous silicon layer 20 to N-type amorphous silicon 42, and will not be able to eliminate the voltage saturation effect under high light concentration conditions or reduce the series resistance of the photovoltaic cell. 21 atoms / cm 3 or more, or by setting the mass fraction of phosphorus atoms 31 in the phosphorus-containing wax to 0.2% to 2%, it contributes to converting the P-type amorphous silicon 41 in the P-type amorphous silicon layer 20 into N-type amorphous silicon 42, and also eliminates the voltage saturation effect under high light concentration conditions, and reduces the series resistance of the photovoltaic cell. 21 atoms / cm 3 , 2×10 21 atoms / cm 3 , 3×10 21 atoms / cm 3 , 4×10 21 atoms / cm 3 or 5×10 21 atoms / cm 3 and the mass fraction of phosphorus atoms 31 in the phosphorus-containing wax may be 0.2%, 0.6%, 1%, 1.5% or 2%.

[0092] In one alternative embodiment, removing the N-type dopant 30 includes using a trough-type apparatus to remove the N-type dopant 30 with a mixture of potassium hydroxide and diethylene glycol butyl ether, where the concentration range of potassium hydroxide is 0.1%-0.5% and the concentration range of diethylene glycol butyl ether is 0.1%-0.3%.

[0093] Specifically, the N-type dopant 30 is used to convert the P-type amorphous silicon layer 20 into an amorphous silicon layer 40 in which P-type amorphous silicon 41 and N-type amorphous silicon 42 are alternately arranged, instead of the structure of the photovoltaic cell, and the N-type dopant 30 needs to be removed after use. The method of removing the N-type dopant 30 includes adopting a trough-type apparatus, and in the case of the trough-type apparatus, it needs to be controlled at room temperature conditions (generally 25°C), and the time is 60s. The N-type dopant 30 is removed by a mixture of potassium hydroxide and diethylene glycol butyl ether, where the concentration range of potassium hydroxide is 0.1% to 0.5%, and the concentration range of diethylene glycol butyl ether is 0.1% to 0.3%. If the concentration of potassium hydroxide is less than 0.1%, the N-type dopant 30 cannot be completely removed, which will affect the manufacture of the subsequent photovoltaic cell film layers, and ultimately affect the structure and power generation efficiency of the entire photovoltaic cell. If the concentration of potassium hydroxide is more than 0.5%, the etching rate is fast and difficult to control, and the amorphous silicon layer 40 is easily damaged, which affects the structure and power generation efficiency of the photovoltaic cell. If the concentration of diethylene glycol butyl ether is less than 0.1%, the N-type dopant 30 cannot be completely removed, which affects the manufacture of the subsequent photovoltaic cell film layer, and ultimately affects the structure and power generation efficiency of the entire photovoltaic cell. If the concentration of diethylene glycol butyl ether is more than 0.3%, it does not have much effect on the etching rate, but is prone to material waste. Therefore, by setting the concentration range of potassium hydroxide to 0.1%-0.5% and the concentration range of diethylene glycol butyl ether to 0.1%-0.3%, it is possible to completely remove the N-type dopant 30 and ensure that the manufacture of the subsequent photovoltaic cell film layer and the structure and power generation efficiency of the photovoltaic cell are not affected, and the etching rate can be controlled and material waste can be avoided. Optionally, the concentration of potassium hydroxide may be 0.1%, 0.2%, 0.3%, 0.4% or 0.5% and the concentration of diethylene glycol butyl ether may be 0.1%, 0.15%, 0.2%, 0.25% or 0.3%.

[0094] In one alternative embodiment, the doping concentration range of boron atoms 21 in the P-type amorphous silicon layer 20 is 3.0×10 19 atoms / cm 3 ~3.0×10 20 atoms / cm 3 It is.

[0095] Specifically, the doping concentration of boron atoms 21 in the P-type amorphous silicon layer 20 is 3.0×10 19 atoms / cm 3 If the doping concentration of the boron atoms 21 in the P-type amorphous silicon layer 20 is less than 3.0×10, the contact between the electrode 90 and the P-type amorphous silicon and the field passivation effect will be deteriorated. 20 atoms / cm 3 If the doping concentration exceeds 3.0×10, it will be costly and time-consuming. Therefore, the doping concentration range of the boron atoms 21 in the P-type amorphous silicon layer 20 is set to 3.0×10 19 atoms / cm 3 ~3.0×10 20 atoms / cm 3 By setting the doping concentration of boron atoms 21 in the P-type amorphous silicon layer 20, the contact between the electrode 90 and the P-type amorphous silicon and the field passivation effect are not affected, and the cost and time are not wasted. 19 atoms / cm 3 , 1.5×10 20 atoms / cm 3 , 3.0×10 20 atoms / cm 3 may be also possible.

[0096] In one optional embodiment, as shown in (d)-(e) of FIG. 2, after processing the first surface 01 of the silicon wafer 00, the depth of the trench 61 is greater than the total thickness of the polysilicon layer 70 and the tunnel oxide layer 10.

[0097] Specifically, after processing the first surface 01 of the silicon wafer 00, the depth of the trench 61 is greater than the total thickness of the polycrystalline silicon layer 70 and the tunnel oxide layer 10, which is equivalent to the trench 61 penetrating into the silicon wafer 00. This allows the P-type amorphous silicon 41 and the N-type amorphous silicon 42 to be completely cut off from each other, thereby preventing leakage current.

[0098] Here, the depth range of the trench 61 into the silicon wafer 00 is 0.2 μm to 2 μm. If the depth of the trench 61 into the silicon wafer 00 is less than 0.2 μm, the trench 61 cannot exert a good insulating effect and there is a risk of electric leakage, and if the depth of the trench 61 into the silicon wafer 00 exceeds 2 μm, the passivation effect is affected. Therefore, by setting the depth range of the trench 61 into the silicon wafer 00 to 0.2 μm to 2 μm, the trench 61 can exert a good insulating effect and avoid the risk of electric leakage, as well as avoid affecting the passivation effect. The depth of the trench 61 into the silicon wafer 00 may be 0.2 μm, 0.6 μm, 1 μm, 1.4 μm, 1.8 μm, or 2 μm as desired.

[0099] In one optional embodiment, as shown in FIG. 5 , treating the first side 01 of the silicon wafer 00 and simultaneously treating the second side 02 of the silicon wafer 00 includes utilizing a trough-type apparatus to simultaneously treat the first side 01 and the second side 02 of the silicon wafer 00 with potassium hydroxide, an additive, and deionized water, where the concentration range of the potassium hydroxide is 1%-1.5% and the concentration range of the additive is 0.5%-1%.

[0100] Specifically, if the concentration of potassium hydroxide is less than 1%, the reaction rate is too slow and time is wasted. If the concentration of potassium hydroxide is more than 1.5%, the reaction rate is too fast and the process is difficult to control. Therefore, by setting the concentration range of potassium hydroxide to 1%-1.5%, it is possible to avoid the reaction rate being too slow and time is wasted, and also to avoid the reaction rate being too fast and difficult to control. For selection, the concentration of potassium hydroxide may be 1%, 1.1%, 1.2%, 1.3%, 1.4% or 1.5%.

[0101] The main components of the additive include water, isopropyl alcohol (IPA), sodium hydroxide (NaOH), weak acid salt and surfactant. If the concentration of the additive is less than 0.5%, the reaction rate is too fast and the process is difficult to control. If the concentration of the additive is more than 1%, the reaction rate is too slow and time is wasted. Therefore, by setting the concentration range of the additive to 0.5%-1%, it is possible to avoid the reaction rate being too fast and difficult to control the process, and also to avoid the reaction rate being too slow and time is wasted. For selection, the concentration of the additive may be 0.5%, 0.6%, 0.7%, 0.8%, 0.9% or 1%.

[0102] In one optional embodiment, as shown in (e)-f) of FIG. 2, removing the protective layer 50 includes utilizing a trough-type apparatus to remove the protective layer 50 with a hydrogen fluoride solution, where the concentration range of hydrogen fluoride is 10%-20%.

[0103] Specifically, if the hydrogen fluoride concentration is less than 10%, the protective layer 50 cannot be completely removed and the removal time is too long. If the hydrogen fluoride concentration is more than 20%, material waste will occur. Therefore, by setting the hydrogen fluoride concentration range to 10% to 20%, the protective layer 50 cannot be completely removed and the removal time is too long, and material waste can be avoided. The hydrogen fluoride concentration may be 10%, 12%, 14%, 16%, 18% or 20% as a selection.

[0104] In one alternative embodiment, when a high temperature treatment is performed on the first surface 01 of the silicon wafer 00, the temperature range of the high temperature treatment is 850°C to 950°C.

[0105] Specifically, if the temperature of the high-temperature treatment is lower than 850°C, the conversion rate from the amorphous silicon layer 40 to the polycrystalline silicon layer 70 is low. If the temperature of the high-temperature treatment is higher than 950°C, the interface state density of the polycrystalline silicon layer 70 increases. Therefore, by setting the temperature range of the high-temperature treatment to 850°C to 950°C, the conversion rate from the amorphous silicon layer 40 to the polycrystalline silicon layer 70 can be ensured and the interface state density of the polycrystalline silicon layer 70 can be prevented from increasing. The high-temperature temperature may be 850°C, 870°C, 890°C, 910°C, 930°C, or 950°C as desired.

[0106] In one alternative embodiment, Fig. 7 is a diagram showing the structure of a photovoltaic cell provided in an embodiment of the present invention. As shown in Fig. 7, the photovoltaic cell 100 includes a photovoltaic cell manufactured by any of the above-mentioned photovoltaic cell manufacturing methods.

[0107] Specifically, along a direction perpendicular to the light irradiation direction, the photovoltaic cell 100 includes a trench region 130, and a first electrode region 110 and a second electrode region 120 located on either side of the trench region 130, respectively. Along the light irradiation direction, the trench region 130 sequentially includes a fourth passivation layer 84, a second passivation layer 82, a silicon wafer 00, a first passivation layer 81, and a third passivation layer 83; the first electrode region 110 sequentially includes a fourth passivation layer 84, a second passivation layer 82, a silicon wafer 00, a tunnel oxide layer 10, an N-type polycrystalline silicon 72, a first passivation layer 81, a third passivation layer 83, and an electrode 90; and the second electrode region 120 sequentially includes a fourth passivation layer 84, a second passivation layer 82, a silicon wafer 00, a tunnel oxide layer 10, a P-type polycrystalline silicon 71, a first passivation layer 81, a third passivation layer 83, and an electrode 90.

[0108] In one alternative embodiment, Fig. 8 is a diagram showing the structure of a photovoltaic module provided in the present invention. As shown in Fig. 8, the photovoltaic module 200 includes a photovoltaic cell 100 manufactured by any of the above-mentioned photovoltaic cell manufacturing methods.

[0109] Specifically, the photovoltaic module 200 provided in this embodiment includes a laminated member 210 and a photovoltaic module frame 220 that is wrapped around the laminated member 210, and the laminated member 210 includes, in order along the light irradiation direction, a front plate 211, a first sealing adhesive film 212, at least one set of cell strings 213, a second sealing adhesive film 214, and a back plate 215. Here, the cell string 213 includes a photovoltaic cell 100 manufactured by any of the above-mentioned photovoltaic cell manufacturing methods, and the rest of the structure is conventional, so a description thereof will be omitted here.

[0110] As can be seen from the above embodiments, the photovoltaic cell and its manufacturing method, and the photovoltaic module provided in the embodiments of the present invention achieve at least the following beneficial effects:

[0111] The present invention provides a photovoltaic cell and its manufacturing method, and a photovoltaic module. The manufacturing method of the photovoltaic cell simplifies and improves the manufacturing process of the photovoltaic cell, and uses N-type dopant to convert P-type polycrystalline silicon into N-type polycrystalline silicon, improving the selective transport performance of the doped carriers, so that this kind of photovoltaic cell can be produced on a large scale in combination with the traditional crystalline silicon cell production line, and the photoelectric conversion efficiency of the photovoltaic cell can be greatly improved.

[0112] Although several specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Those skilled in the art should understand that the above examples can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is limited by the claims.

Claims

1. Providing a silicon wafer; forming a tunnel oxide layer on a first surface of the silicon wafer and forming a P-type amorphous silicon layer on the tunnel oxide layer; forming an N-type dopant at a distance from the silicon wafer on the P-type amorphous silicon layer, the N-type dopant including phosphorus atoms and having a thickness in the range of 1 μm to 50 μm; performing a laser treatment on the N-type dopant to mix some phosphorus atoms in the N-type dopant into a portion of the P-type amorphous silicon layer that is in contact with the N-type dopant, thereby converting the P-type amorphous silicon layer into an amorphous silicon layer in which P-type amorphous silicon and N-type amorphous silicon are arranged alternately; removing remaining portions of the N-type dopant at a surface of the amorphous silicon layer and forming a protective layer on the surface of the amorphous silicon layer; performing a laser process on the protective layer and the amorphous silicon layer to form a trench and a protrusion, the protrusion having a width perpendicular to the laser irradiation direction ranging from 100 μm to 500 μm, and the trench having a width perpendicular to the laser irradiation direction ranging from 100 μm to 300 μm; During the process of processing the silicon wafer and further processing the silicon wafer, the depth of the trench increases, and the range of the depth of the trench into the silicon wafer is 0.2 μm to 2 μm; removing the protective layer; and performing a high temperature treatment on the silicon wafer to convert the amorphous silicon layer into a polycrystalline silicon layer. A method for producing a photovoltaic cell comprising the steps of:

2. After performing a laser treatment on the N-type dopant, the content of phosphorus atoms in the P-type amorphous silicon layer in contact with the N-type dopant is greater than the content of boron atoms.

2. The method for producing a photovoltaic cell according to claim 1 .

3. the silicon wafer having a second side opposite the first side, the method including forming a textured structure on the second side of the silicon wafer upon further processing the silicon wafer. A method for producing a photovoltaic cell according to claim 1.

4. The silicon wafer is subjected to a high-temperature treatment to convert the amorphous silicon layer into a polycrystalline silicon layer, and then forming a passivation layer simultaneously on the first side and the second side of the silicon wafer; forming an electrode on the first surface of the silicon wafer; A method for producing a photovoltaic cell according to claim 1.

5. The N-type dopant is a phosphorus-containing silicon glass or a phosphorus-containing wax, and the concentration of phosphorus atoms in the phosphorus-containing silicon glass is 1×10 ２１ atoms / cm ３ or more, and the mass fraction of phosphorus atoms in the phosphorus-containing wax is 0.2% to 2%; 3. The method for producing a photovoltaic cell according to claim 2.

6. The removing of the N-type dopant includes removing the N-type dopant with a mixture of potassium hydroxide and diethylene glycol butyl ether using a trough type device, where the concentration of potassium hydroxide is in the range of 0.1% to 0.5%, and the concentration of diethylene glycol butyl ether is in the range of 0.1% to 0.3%; A method for producing a photovoltaic cell according to claim 1.

7. The doping concentration range of boron atoms in the P-type amorphous silicon layer is 3.0×10 １９ atoms / cm ３ ~3.0 x 10 ２０ atoms / cm ３ That is, A method for producing a photovoltaic cell according to claim 1.

8. After further processing of the silicon wafer, the depth of the trench is greater than the total thickness of the polysilicon layer and the tunnel oxide layer. A method for producing a photovoltaic cell according to claim 1.

9. Further processing the silicon wafers using a trough-type apparatus with potassium hydroxide, an additive, and deionized water, wherein the potassium hydroxide concentration ranges from 1% to 1.5% and the additive concentration ranges from 0.5% to 1%; 4. The method for producing a photovoltaic cell according to claim 3.

10. Removing the protective layer includes removing the protective layer with a hydrogen fluoride solution using a trough-type device, where the concentration range of hydrogen fluoride is 10% to 20%; A method for producing a photovoltaic cell according to claim 1.

11. In the process of performing high temperature treatment, the high temperature range is 850°C to 950°C; A method for producing a photovoltaic cell according to claim 1.

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