Method for manufacturing a composite structure comprising a thin layer made of monocrystalline SiC on a carrier substrate made of SiC

Abstract

The present invention relates to a method for manufacturing a composite structure comprising a thin layer made of single-crystal SiC arranged on a carrier substrate made of SiC, the method comprising the steps of: a) providing a donor substrate made of single-crystal SiC; b) forming an embedded brittle plane in the donor substrate; c) n consecutive steps for forming a plurality of crystalline carrier layers, the n crystalline carrier layers being arranged successively one after the other on the front surface of the donor substrate to form the carrier substrate, the individual formation steps including a step of performing direct liquid injection chemical vapor deposition to form a carrier layer formed by an amorphous SiC matrix, and a step of performing a crystallization heat treatment on the carrier layer to form the crystalline carrier layer; and d) a step of separating along the embedded brittle plane to form a composite structure comprising the thin layer on the carrier substrate and the remainder of the donor substrate.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor materials for microelectronic components. In particular, the present invention relates to a method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide on a carrier substrate made of silicon carbide. [Background technology]

[0002] Interest in silicon carbide (SiC) has grown significantly in recent years due to the increased ability of this semiconducting material to process energy. SiC is being used more and more extensively to manufacture innovative power devices that meet the needs of rising sectors in electronics, especially electric vehicles.

[0003] Power devices and integrated power supply systems based on monocrystalline silicon carbide can manage much higher power densities and can do so with smaller active zone dimensions compared to conventional power devices and integrated power supply systems made of silicon. To further limit the dimensions of power devices on SiC, it is advantageous to manufacture vertical components instead of lateral ones. To do so, the SiC structure must allow vertical electrical conduction between electrodes arranged on the front and back sides of the SiC structure.

[0004] However, single-crystal SiC substrates intended for the microelectronics industry are still expensive and difficult to supply in large sizes. It is therefore advantageous to use thin layer transfer solutions to manufacture composite structures, typically comprising a thin layer of single-crystal SiC, on a less expensive carrier substrate. One well-known thin layer transfer solution is the Smart Cut™ process, based on the implantation of light ions and on assembly by direct bonding. Such a process makes it possible to manufacture composite structures, for example comprising a thin layer made of single-crystal SiC (c-SiC), taken from a c-SiC donor substrate in direct contact with a carrier substrate made of polycrystalline SiC (p-SiC), and allows vertical electrical conduction. However, achieving high-quality direct bonding by molecular adhesion between two substrates made of c-SiC and p-SiC remains difficult due to the complex control of the surface state and roughness of said substrates.

[0005] Various methods derived from this process are also known from the prior art. For example, F. Mu et al. (ECS Transactions, 86(5), 3-21, 2018) have realized direct bonding after activating the surfaces to be assembled by bombardment with argon (SAB: "Surface Activation Bonding"), such a treatment prior to bonding creates a very high density of side bonds that promotes the formation of covalent bonds at the assembly interface and thus high bonding energy. However, this method has the drawback of creating an amorphous layer on the surface of the monocrystalline SiC donor substrate, which negatively affects the vertical electrical conduction between the thin layer made of c-SiC and the carrier substrate made of p-SiC.

[0006] Solutions have been proposed to solve this problem, notably in EP 3168862, which involve the implantation of dopant species into the amorphous layer in order to restore its electrical properties. The main drawback of this approach is its complexity and therefore its cost.

[0007] Also known is US Patent No. 8,436,363, which describes a method for manufacturing a composite structure comprising a thin layer made of c-SiC, arranged on a metal carrier substrate, the thermal expansion coefficient of the composite structure matching that of the thin layer. forming a buried brittle plane in a c-SiC donor substrate, defining a thin layer between the buried brittle plane and a front surface of the donor substrate; depositing a layer of metal, for example tungsten or molybdenum, on the front surface of the donor substrate to form a carrier substrate having a sufficient thickness to act as a stiffener; Separation along the embedded brittle plane in order to form, on the one hand, a composite structure comprising a metal carrier substrate and a thin layer made of c-SiC, and, on the other hand, the remaining part of the donor substrate made of c-SiC. Includes.

[0008] However, such a manufacturing method is not compatible when the material forming the carrier substrate is p-SiC and requires deposition at temperatures above 1200° C. (the usual temperature for manufacturing p-SiC). In particular, at these high temperatures, the growth kinetics of the cavities present in the embedded brittle planes is faster than that of the p-SiC layer, and the thickness required for the reinforcement effect is not reached until the appearance of blisters associated with the deformation of the layer vertically aligned with the cavities.

[0009] Regardless of the layer transfer technique used, additional problems arise in providing composite structures with thin c-SiC layers of very high quality, in particular those free of extended defects (or having a very low density of defects), which cause an impact on the performance quality and reliability of power devices intended to be manufactured on said thin layers. Summary of the Invention

[0010] The present invention relates to an alternative solution to the prior art solutions and is aimed at overcoming completely or partially the above mentioned drawbacks.The present invention relates in particular to a method for manufacturing a composite structure comprising a high quality thin layer made of c-SiC on a lower quality carrier substrate made of SiC.

[0011] The present invention relates to a method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising the steps of: a) providing a donor substrate made of single crystal silicon carbide; b) ion implanting light species into the donor substrate to form a buried brittle plane, the buried brittle plane defining a thin layer between the buried brittle plane and a free surface of the donor substrate; c) a number of successive n steps for forming a plurality of crystalline carrier layers, n being 2 or more, the n crystalline carrier layers being successively disposed on a front surface of the donor substrate to form a carrier substrate, each of the forming steps being: applying direct liquid injection chemical vapor deposition at a temperature less than 900° C. to form a carrier layer, the carrier layer being at least partially formed by an amorphous SiC matrix and having a thickness of 200 microns or less; subjecting the carrier layer to a crystallization heat treatment at a temperature of 1000° C. or less to form a crystalline carrier layer; and d) forming, on the one hand, a composite structure comprising a thin layer on a carrier substrate and, on the other hand, a separation along the embedded brittle plane in order to form the remaining part of the donor substrate; Includes.

[0012] According to other advantageous non-limiting features of the present invention taken alone or in any technically attainable combination, The method comprises a step e) of subjecting the composite structure to mechanical and / or chemical treatment(s), in which the treatment(s) is / are applied to the free side of the carrier substrate, to the back side of the composite structure and / or to the free side of the lamina, to the front side of the composite structure, Step e) comprises simultaneously mechanochemically polishing the front and back surfaces of the composite structure; Between steps c) and d), the free side of the carrier substrate is subjected to chemical etching, mechanical grinding and / or mechanochemical polishing, the thickness of each deposited carrier layer is less than 100 microns, or even less than 50 microns, or even less than 10 microns; The deposition of step c) is carried out at a temperature between 100° C. and 800° C., preferably between 200° C. and 600° C., The deposition of step c) is carried out at a pressure between 1 Torr and 500 Torr; the precursors used during the deposition of step c) are selected from polysilylethylene and disilabutane, Step c) comprises n successive steps for forming a plurality of crystalline carrier layers, n being between 3 and several tens; Step a) comprises a step a') of providing an initial substrate made of monocrystalline silicon carbide, and a step a'') of epitaxially growing a monocrystalline silicon carbide donor layer on the initial substrate to form a donor substrate, the donor layer having a density of crystal defects lower than a density of crystal defects of the initial substrate, Step a') comprises forming a single crystal conversion layer on the initial substrate to convert basal plane dislocation defects of the initial substrate into threading edge dislocation defects; the epitaxial growth step a″) is carried out at a temperature higher than 1200° C., preferably between 1500° C. and 1650° C., the separating step d) is carried out at a temperature equal to or greater than the temperature of the crystallization heat treatment of step c), The method includes recovering the remaining portion of the donor substrate for reuse as an initial substrate or as a donor substrate.

[0013] Other features and advantages of the present invention will become apparent from the following detailed description of the invention, which proceeds with reference to the accompanying drawings. [Brief description of the drawings]

[0014] [Figure 1] 1 shows a composite structure manufactured according to a manufacturing method according to the present invention; [Figure 2a] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2b] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2c(i)] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2c(ii)] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2c(iii)] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2c(iv)] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2c(v)] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2c(vi)] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2d] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2e] 1 illustrates steps of a manufacturing method according to the invention; [Figure 2f] 1 illustrates steps of a manufacturing method according to the invention; [Figure 3a] 1 illustrates steps of a manufacturing method according to the invention; [Figure 3b] 1 illustrates steps of a manufacturing method according to the invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] In the description, the same reference numerals of the figures may be used for elements of the same type. The figures are schematic and not to scale for ease of reading. In particular, the thickness of layers along the z-axis is not to scale relative to the lateral dimensions along the x- and y-axes, nor are the relative thicknesses of layers with respect to each other to scale in the figures.

[0016] The invention relates to a method for manufacturing a composite structure 1 (FIG. 1) comprising a thin layer 10 made of monocrystalline silicon carbide arranged on a carrier substrate 20 made of silicon carbide. The carrier substrate 20 is advantageously polycrystalline (polycrystalline SiC is referred to using "p-SiC").

[0017] The method first comprises step a) of providing a donor substrate 111 made of monocrystalline silicon carbide. Throughout the remainder of the description, "c-SiC" is used to refer to monocrystalline silicon carbide.

[0018] The donor substrate 111 is preferably in the form of a wafer with a diameter of 100 mm, 150 mm or 200 mm, or even 300 mm or even 450 mm, and a typical thickness between 300 and 800 microns. The donor substrate 111 has a front surface 11a and a back surface 11b. The surface roughness of the front surface 11a is advantageously selected to be less than 1 nm Ra (average roughness) as measured by atomic force microscopy (AFM) over a 20 micron by 20 micron scan.

[0019] According to an advantageous embodiment, step a) comprises a step a') of providing an initial substrate 11 made of monocrystalline silicon carbide. The method then comprises a step a'') of epitaxially growing a monocrystalline silicon carbide donor layer 110 on the initial substrate 11 to form a donor substrate 111 (Figure 2a). The epitaxial growth step is performed such that the donor layer 110 has a crystal defect density less than the crystal defect density of the initial substrate 11.

[0020] For example, the initial substrate 11 made of c-SiC may be of 4H or 6H polytype, with an offcut angle of less than 4.0°±0.5° relative to the <11-20> crystal axis and a threading dislocation (micropipe) density of 5 / cm 2 Below that, even 1 / cm 2 For doping N (nitrogen) type, the initial substrate 11 preferably has a resistivity between 0.015 and 0.030 ohm cm. Of course, the dopant may be a dopant other than nitrogen and the doping may optionally be P-type doping. A low density, typically 3000 / cm 2 An initial substrate 11 can be chosen that has basal plane dislocation (BPD) defects of less than 1500 / cm 2 c-SiC substrates having a BPD density of about 1000 nm are reasonably available, which may facilitate the supply of c-SiC substrates.

[0021] It is advantageous for the donor layer 110, from which the c-SiC thin layer 10 of the composite structure 1 is to be formed as a result of the method of the invention, to have an excellent crystal quality in order to meet the specifications required for the vertical components intended to be manufactured on said thin layer 10. This is due to the presence of various types of extended defects in the layer or substrate made of c-SiC. These extended defects can affect the performance quality and reliability of the components. In particular, for bipolar components, defects of the BPD type are fatal, since Shockley stacking faults (or SSFs) are extended from dislocations when energy is available to recombine electron-hole pairs. The extension of SSF stacking faults inside the active area of ​​the component leads to an increase in the pass-state resistance of the component.

[0022] Therefore, 1 / cm 2 The c-SiC donor layer 110 is fabricated to have the following BP defect density:

[0023] For that purpose, the epitaxial growth step a'') is carried out at a temperature higher than 1200° C., preferably between 1500° C. and 1650° C. The precursors used are silane (SiH4), propane (C3H8) or ethylene (C2H4) and the carrier gas may be hydrogen with or without argon.

[0024] The donor layer 110 with a low content of BPD defects is obtained by supporting the conversion of BPD defects present in the initial substrate 11 into threading edge dislocations (TEDs).

[0025] According to a particular embodiment, step a″) comprises the formation of a monocrystalline conversion layer 13, preferably made of c-SiC, in order to maximize the conversion of BPD defects of the initial substrate 11 into TED defects (FIG. 3a). For that purpose, it is advantageous to choose a small cleavage angle close to 4° for the initial c-SiC substrate 11, to achieve a high growth rate (typically higher than 5 μm / h), to have a high in situ etching carried out before the epitaxial growth, and finally to choose growth conditions for the monocrystalline conversion layer 13 with a C / Si ratio in the precursor stream close to 1.

[0026] Epitaxial growth of a donor layer 110 on said conversion layer 13 can then be carried out (FIG. 3b). According to this particular embodiment, 2 Below that, even 0.1 / cm 2 It is also possible to obtain a c-SiC donor layer 110 with a BPD defect density of less than 1000 nm. Furthermore, as a result of the method according to the invention, the probability of bipolar degradation (probability of holes arriving below the BPD / TED conversion point) is negligible (less than 0.1%) and the monocrystalline conversion layer 13 is not intended to be transferred to the composite structure 1. Prior art aimed at reducing the bipolar degradation involves the incorporation of a recombination layer (1 E 18at / cm 3 This layer has a thickness of 10 μm and a thickness of 5 E 18 / cm 3 In exchange for a concentration exceeding 0.1%, the probability of holes being present can be reduced to 0.1% relative to the basic structure not including this recombination layer. Since the monocrystalline conversion layer 13 is not transferred in the present invention, the probability of holes reaching the nucleation point of bipolar degradation (BPD-TED conversion point or any BPD point) is at least less than 0.1%, and even close to 0%.

[0027] It is noted that a conventional cleaning or etching sequence of the initial substrate 11 aimed at removing all or part of any particulate, metallic or organic contaminants or native oxide layer potentially present on the front surface 11a of the initial substrate 11 can be carried out prior to and / or subsequent to the epitaxial growth step a'').

[0028] Alternatively, the donor substrate 111 can be formed only from an initial substrate 11 having a low defect density, which is compatible with the specifications of the upcoming thin layer 10, which is then obtained from the donor substrate 111 in subsequent steps of the method described below.

[0029] The manufacturing method according to the invention also comprises a step b) of ion implanting light species into the donor substrate 111 (and in particular into the donor layer 110, if present) to a predetermined depth representing the desired thickness of the thin layer 10. It should be noted that this depth is always kept below the thickness of the donor layer 110, if present. This implantation produces a buried brittle plane 12 in the donor substrate 111, which delimits the thin layer 10 between said buried brittle plane 12 and the free surface 11a of said donor substrate 111 (Figure 2b).

[0030] The light species implanted are preferably hydrogen, helium or a co-implantation of these two species. As is well known with reference to the Smart-Cut™ process, these light species form microcavities distributed at approximately a predefined depth in a thin layer parallel to the free surface 11a of the donor substrate 111, i.e. parallel to the plane (x,y) of the drawing. This thin layer is referred to for simplicity as the buried brittle plane 12.

[0031] The energy for implanting the light species is selected to reach a predetermined depth in the donor substrate 111 .

[0032] Typically, hydrogen ions are injected at energies between 10 keV and 250 keV for 5 min to define a thin layer 10 having a thickness of about 100-1500 nm. E 16 / cm 2 and 1 E 17 / cm 2 The implantation is carried out at a dose between 0.01 and 0.1.

[0033] It should be noted that prior to the ion implantation step, a protective layer can be deposited on the free surface of the donor substrate 111. This protective layer can consist of a material such as silicon oxide or silicon nitride, for example.

[0034] The method according to the present invention then includes a number of successive n steps for forming a plurality of crystalline carrier layers 20'', where n is 2 or more. The number of successive forming steps may be three or more, and typically ranges up to several tens of steps.

[0035] A number of n crystalline carrier layers 20″ are arranged successively on the free surface 11a of the donor substrate 111 to form the carrier substrate 20. In other words, a first crystalline carrier layer 20″ is in direct contact with the front surface 11a of the donor substrate 111, then a second crystalline carrier layer 20″ is in contact with the first carrier layer 20″, and so on for the n crystalline carrier layers 20″ (FIGS. 2c(i)-(vi)).

[0036] The individual forming steps include direct liquid injection chemical vapor deposition (DLI-CVD) followed by a crystallization heat treatment for the deposited layer 20'.

[0037] The DLI-CVD deposition is carried out at a temperature below 900° C., preferably between 100° C. and 800° C., between 100° C. and 700° C., and more advantageously between 200° C. and 600° C. The pressure of the deposition chamber is defined to be between 1 and 500 Torr.

[0038] DLI-CVD deposition techniques can provide good yields between delivered materials (precursors) and achieved deposition thicknesses without the need for the use of chlorided precursors, which limits cost and environmental constraints.

[0039] DLI-CVD deposition preferably includes a disilabutane or polysilylethylene precursor, said precursor being pure or diluted. Optionally, other precursors such as methyltrichlorosilane, ethylenetrichlorosilane, dichloromethylvinylsilane, tetraethylsilane, tetramethylsilane, diethylmethylsilane, bistrimethylsilylmethane or hexamethyldisilane can be used.

[0040] The DLI-CVD deposition technique is described in a paper by Guilhaume Boisselier (2013, "Depot chimique en phase vapour de carburetors de chrome, de silicium et d'hafnium assiste par injection liquide pulsee [Pulsed liquid injection-chemical vapour deposition of chromium, silicon and hafnium carbides]") for the application of depositing ceramic coatings on components, e.g. components of steel or alloy metals, thereby protecting them during extremely high temperature treatments.

[0041] The applicant has developed a DLI-CVD deposition for forming a carrier layer 20' deposited on a c-SiC donor substrate 111 in order to obtain a composite structure 1 intended for a completely different application, namely as a result of the manufacturing method, in the field of microelectronics.

[0042] The deposited carrier layer 20' forms a SiC matrix that includes amorphous SiC and reaction by-products formed from carbon chains originating from the precursors used during deposition. Additionally, the SiC matrix may optionally include crystalline SiC particles.

[0043] Typically, the carrier layer 20' has a thickness of 200 microns or less, 100 microns or less, 50 microns or less, 10 microns or less, or even a few microns or less. It is noted that DLI-CVD techniques can have deposition rates of 10 microns / hour or more, even greater than 50 microns / hour, or even greater than 100 microns / hour.

[0044] The thickness of each of the deposited carrier layers 20' can be exactly the same, but this is not necessary. According to one option, the thickness of the n successively deposited carrier layers 20' is gradually increased, which can limit the detrimental effects of differences in the thermal expansion coefficients of the layers present in the structure, the thinner carrier layers 20' deposited at the beginning being less constrained in the structure than the thicker layers (especially during the crystallization heat treatment following the deposition) and can change their thermal expansion coefficient towards a gentler coefficient, which is more favorable for the subsequent deposition of the thicker carrier layers 20'.

[0045] According to another option, the thickness of the n successively deposited carrier layers 20' is gradually reduced, which can have the advantage of gradually reducing the size of cracks generated during a crystallization heat treatment of the deposited layers 20', which process will be explained in detail later in this description.

[0046] It is noted that step c) is advantageously aimed at defining a non-insulating interface between the donor substrate 111 and the carrier substrate 20. In other words, step c) is carried out in such a way that in the final composite structure 1, the interface between the donor substrate 111 and the first carrier substrate 20 is electrically conductive, the aim being to achieve a dielectric constant of less than 1 milliohm cm 2The aim is to obtain a specific interface resistance which is preferably less than 100 nm. To guarantee the electrical conductivity of the interface, it is advantageous to carry out the removal of the native oxide present on the free surface 11a of the donor substrate 111 by HF (hydrofluoric acid) deoxidation, by wet or dry route. Alternatively, it is advantageous to carry out an overdoping of at least a few nanometers of the first deposited of the first carrier layer 20' by introducing dopant species during the DLI-CVD deposition. It is generally noted that dopant species can be introduced (in different doses) during the n depositions of step c) according to the targeted doping level and electrical conductivity for the carrier substrate 20.

[0047] It may also be advantageous to subject the donor substrate 111 to a cleaning sequence prior to deoxidation and / or prior to the formation of the first carrier layer 20' in order to remove all or part of any particulate, metallic or organic contaminants potentially present on the free surface of the donor substrate 111.

[0048] After DLI-CVD deposition, step c) comprises subjecting the carrier layer 20' to a crystallization heat treatment at a temperature below 1000° C. to form a crystalline carrier layer 20″. The temperature of the heat treatment may be, for example, 950° C. or 900° C. or 800° C.

[0049] The annealing atmosphere may include gases such as argon, nitrogen, hydrogen, helium or mixtures of these gases, among others. Such annealing has the effect of removing hydrogen from the carrier layer 20' and of causing crystallization of the SiC matrix in the form of polycrystalline SiC.

[0050] The crystallization heat treatment can be carried out using conventional furnaces for processing multiple structures simultaneously (batch annealing), where the typical duration of the treatment is between a few minutes and a few hours.

[0051] The crystallization heat treatment can alternatively be carried out in a rapid thermal processing (RTP) furnace. Typical annealing times are between a few seconds and a few minutes.

[0052] Finally, one can also envisage carrying out a crystallization heat treatment in situ in the DLI deposition chamber for a typical period of time on the order of a few minutes.

[0053] The relatively thin thickness of the deposited carrier layer 20' allows for rapid crystallization, which prevents the thermal budget of the crystallization heat treatment from causing overgrowth of voids in the buried brittle plane 12 of the donor substrate 111. For example, a 10 micron thick carrier layer 20' may be subjected to a crystallization heat treatment at 800° C. for 10 minutes, which is insufficient to overcome the critical density and size of voids present in the buried brittle plane 12 of the donor substrate 111 (causing voids to form or spontaneously separate along the buried brittle plane 12).

[0054] It is important to note that crystallization of the individual carrier layers 20' often leads to cracks 2 in the crystalline carrier layer 20'', which affect the mechanical and electrical qualities of the crystalline carrier layer 20''. That is why the method according to the invention envisages successive steps for forming the crystalline carrier layer 20''.

[0055] As can be seen in Fig. 2c(i), a first carrier layer 20' is deposited on the donor substrate 111 during a first DLI-CVD deposition. This stack is then subjected to a first crystallization heat treatment, resulting in the conversion of the first carrier layer 20' into a first crystalline carrier layer 20'' in the form of poly-SiC and the appearance of cracks 2 in said crystalline layer 20'' (Fig. 2c(ii)).

[0056] A second DLI-CVD deposition is then performed on the free surface (FIG. 2c(iii)) of the first crystalline carrier layer 20″ and in particular on the cracks 2, thus giving a second superficial carrier layer 20′ and also the cracks 2′ filled with the same material as said second layer 20′ (at least partially amorphous SiC matrix). This stack is subjected to a second crystallization heat treatment, resulting in the conversion of the second carrier layer 20′ into a second crystalline carrier layer 20″ in the form of p-SiC and the appearance of cracks 2 in said second crystalline layer 20″ (FIG. 2c(iv)). The SiC matrix present in the cracks 2″ of the first crystalline carrier layer 20″ can also crystallize in the form of p-SiC and heal the initial superficial cracks 2 of said first layer 20″.

[0057] A third DLI-CVD deposition can then be performed on the free surface (FIG. 2c(v)) of the second crystalline carrier layer 20″ and especially on the appearing cracks 2, thus giving a third carrier layer 20′ and also the cracks 2′ filled with the same material as said third layer 20′. This stack is subjected to a third crystallization heat treatment, resulting in the conversion of the third carrier layer 20′ into a third crystalline carrier layer 20″ in the form of p-SiC and the appearance of cracks 2 in said third crystalline layer 20″ (FIG. 2c(vi)). The SiC matrix present in the cracks 2″ of the second crystalline carrier layer 20″ can also crystallize in the form of p-SiC and heal the initial cracks 2 of said second layer.

[0058] It should be noted that the n DLI-CVD depositions, as well as the n crystallization annealing operations, can be performed at different temperatures.

[0059] The method comprises at least two successive steps for forming a crystalline carrier layer 20″. By way of example, Fig. 2c(i)-(vi) show three of them, but it is entirely conceivable to carry out between two and ten, or even several tens of successive deposition and crystallization steps until a carrier substrate 20 formed by a superposition of crystalline carrier layers 20″ is obtained.

[0060] The deposition and crystallization annealing parameters of step c) are such that the carrier substrate 20: have good electrical conductivity, i.e. less than 0.03 ohm cm, or even less than 0.01 ohm cm, High thermal conductivity, i.e. 150W.m -1 .K -1 or more, even 200W.m -1 .K -1 and has a thermal conductivity of at least and a coefficient of thermal expansion close to that of the thin layer 10, i.e. typically 3.8 at room temperature. E -6 / K and 4.2 E -6 / K It is determined as follows.

[0061] To obtain these properties, the following targeted structural features are preferred for the carrier substrate 20: polycrystalline structure, 3C SiC type grains, 111 orientation, average size in the main plane of the substrate between 1 and 50 μm, N-type doping for a final resistivity of less than 0.03 ohm cm, or even less than 0.01 ohm cm.

[0062] As a result of step c), the carrier substrate 20 has a sufficient thickness to carry out the subsequent separating step d) and advantageously has the desired thickness for the composite structure 1. The thickness of the carrier substrate 20 can thus be 10 microns or more, 50 microns or more, or even 100 microns or more.

[0063] The stack 211 obtained by step c) comprises a carrier substrate 20 arranged on the donor substrate 111 .

[0064] The method according to the invention then comprises a step d) of separation along the embedded brittle plane 12 in order to form, on the one hand, the composite structure 1 and, on the other hand, the remaining part 111' of the donor substrate (FIG. 2d).

[0065] According to an advantageous embodiment, the separation step d) is carried out by subjecting the stack 211 to a heat treatment at a separation temperature equal to or higher than the deposition temperature and the crystallization temperature of step c). In particular, the microcavities present in the buried brittle plane 12 follow a growth kinetics until a breaking wave is generated that propagates over the entire extent of the buried brittle plane 12, resulting in a separation between the composite structure 1 and the remainder of the initial substrate 111'. In practice, the temperature may be between 950°C and 1200°C, preferably between 1000°C and 1200°C, as a function of the implantation conditions of step b).

[0066] According to an alternative embodiment, the separating step d) is performed by applying a mechanical stress to the stack 211, optionally preceded by a heat treatment to embrittle the embedded brittle plane 12. The stress can for example be applied by inserting a tool (for example a laser blade) close to the embedded brittle plane 12. By way of example, the separating stress may be of the order of a few gigapascals, preferably more than 2 GPa.

[0067] According to another embodiment, a separation step d) can be performed during the last (n-th) crystallization anneal of step c). In such a case, it can be envisaged to optionally perform at least one (n+1)-th DLI-CVD deposition after separation in order to further thicken the carrier substrate 20 and at least one (n+1)-th crystallization anneal in order to form p-SiC.

[0068] After step d), a composite structure 1 is obtained comprising a thin layer 10 made of monocrystalline silicon carbide arranged on a carrier substrate 20 made of polycrystalline silicon carbide.

[0069] As can be seen, as a result of the separation step d), the free surface 10a of the thin layer 10 of the composite structure 1 has a surface roughness of between 5 nm RMS and 100 nm RMS (measured with an atomic force microscope (AFM) with a scan of 20 microns x 20 microns).

[0070] Step e) of subjecting the composite structure 1 to (one or more) mechanical and / or chemical treatments can therefore be envisaged for smoothing the free surface 10a of the thin layer 10 and for modifying the thickness uniformity of the composite structure 1 (Figure 2e).

[0071] Step e) may comprise a mechanochemical polishing (MCP) of the free surface 10a of the thin layer 10, typically removing around 50 nm to 1000 nm of material to obtain a final roughness of less than 0.5 nm RMS (with an AFM field of view of 20x20 μm), even less than 0.3 nm. Step e) may also comprise a chemical or plasma treatment (cleaning or etching) to further improve the quality of the free surface 10a of the thin layer 10, for example cleaning of SC1 / SC2 type (standard cleaning 1, standard cleaning 2) and / or HF (hydrofluoric acid), and / or N2, Ar, CF4, etc. plasma.

[0072] Furthermore, step e) may include mechanochemical polishing (MCP) and / or chemical (etching or cleaning) and / or mechanical (grinding) treatment of the back surface 20b of the carrier substrate 20, which may remove all or part of the residual cracks 2. Such treatment may also improve the thickness uniformity of the carrier substrate 20 and may also improve the roughness of the back surface 20b of the carrier substrate 20. For the production of vertical components, where at least one metal electrode will be present on the back surface 20b of the composite substrate 1, a roughness of less than 0.5 nm RMS (measured by atomic force microscope (AFM) in a field of view of 20 microns x 20 microns) is desired.

[0073] It should be noted that these treatments applied to the back surface 20b of the carrier substrate 20 can also be optionally carried out just before the separation step d), i.e. before the front surface 10a of the composite structure 1 is stripped bare, thereby making it possible to limit contamination of the front surface 10a, especially during contamination or limiting processes such as chemical etching or mechanical grinding.

[0074] Polishing or grinding of the edges of the composite structure 1 may also be carried out during this step e) in order to make the shape of the circular profile of the composite structure 1 and the shape of the cutting edge waste compatible with the requirements of the microelectronic manufacturing process.

[0075] According to an advantageous embodiment, the mechanochemical treatment step e) comprises simultaneous polishing (MCP) of the front surface 10a and the back surface 20b of the composite structure 1 in order to smooth the structure 1 and improve the thickness uniformity of said structure 1. The polishing parameters may be different between the front surface and the back surface, and the smoothing of c-SiC and p-SiC surfaces usually requires different consumables. If the carrier substrate 20 is made of p-SiC, the mechanical component of polishing is preferred, especially for the back surface 20b, in order to limit the preferential attack of grain boundaries by the chemical component of polishing. As an example, the polishing parameters such as rotation speed (polishing head and plate), pressure, concentration and physical properties of the abrasive (i.e. diamond nanoparticle size between about 10 nm and 1 μm) can be modified to enhance the effect of the mechanical component.

[0076] Optionally, step e) is followed by a step e') of heat treatment at a temperature between 1000° C. and 1800° C. for about one hour and up to several hours. The purpose of this step is to stabilize the composite structure 1 by repairing structural or surface defects still present in and / or on the thin layer 10 and, if appropriate, by evolving the crystalline structure of the carrier substrate 20, so that the structure 1 is compatible with the subsequent high-temperature heat treatments necessary for the manufacture of components on the thin layer 10. Such a heat treatment can also have the advantage of restoring good electrical conductivity at the deposition interfaces of the layers forming the carrier substrate 20.

[0077] The method according to the invention can include a second step f) of epitaxially growing an additional layer 10' of monocrystalline silicon carbide on the thin layer 10 of the composite structure 1 (FIG. 2f). Such a step applies when a relatively thick working layer 100 is required to manufacture a component, typically a working layer 100 with a thickness of about 5 microns to 50 microns.

[0078] In order to limit the stresses induced by the composite structure 1 in the working layer 100 (corresponding to the combination of the thin layer 10 and the additional layer 10'), it is possible to choose to limit the temperature applied during this step f).

[0079] Finally, the manufacturing method may include a step of reclaiming the remaining part 111' of the donor substrate for reuse as the initial substrate 11 or as the donor substrate 111. Such a reclaiming step is based on one or more treatments of the face 110' (FIG. 2d) by mechanochemical polishing of the surface or edges and / or by mechanical grinding and / or by wet or dry chemical etching.

[0080] The thickness of the donor layer 110 formed in step a'') is preferably defined such that the remaining portion 111' of the donor substrate 111 can be reused as the donor substrate 111 at least two times.

[0081] If conversion layer 13 is present, care must be taken to keep said layer intact, i.e. it is preferred to always maintain a portion of donor layer 10 on top of the remaining portion 111' of the donor substrate. Thus, if that portion of donor layer 10 is insufficient for producing composite structure 1, only the step of epitaxially growing donor layer 10 is required, without the preceding step of growing conversion layer 13.

[0082] (Example) According to a non-limiting embodiment example, the initial substrate 11 provided in step a') of the manufacturing method is a wafer made of c-SiC of the 4H polytype, oriented at 4.0°±0.5° relative to the <11-20> axis, with a diameter of 150 mm and a thickness of 350 μm.

[0083] Prior to the epitaxial growth step a″) of the c-SiC donor layer 110, the initial substrate 11 is subjected to a conventional RCA cleaning sequence (Standard Clean 1 + Standard Clean 2) using Caro's acid (a mixture of sulfuric acid and hydrogen peroxide) followed by HF (hydrofluoric acid).

[0084] The growth is carried out in an epitaxy chamber at a temperature of 1650° C. using precursors such as silane (SiH4) and propane (C3H8) or ethylene (C2H4) to produce a c-SiC donor layer 110 with a thickness of 30 microns (growth rate: 10 microns / h). The donor layer has a thickness of 1 / cm 2 The BPD defect density is about

[0085] The energy was 150 keV, and the entire free surface of the donor layer 110 was 6 E 16H+ / cm 2 Thus, a buried brittle plane 12 is created at a depth of about 800 nm in the initial substrate 11.

[0086] To remove potential contaminants from the free surface of the donor layer 110, a RCA+Caro's acid cleaning sequence is performed on the donor substrate 111.

[0087] A first DLI-CVD deposition is performed on the donor layer 110 using a disilabutane (DSB) precursor at a temperature of 650° C., at a pressure of 50 Torr, for 80 minutes, such that the first carrier layer 20′ has a thickness of 140 microns. Under these conditions, the carrier layer 20′ forms an amorphous SiC matrix containing reaction by-products derived from the deposition precursors.

[0088] The stack 211 is then subjected to a first crystallization annealing operation under a neutral atmosphere of nitrogen or argon at 800° C. for less than 15 minutes. Due to the crystallization of the first p-SiC carrier layer 20′, cracks 2 appear.

[0089] A second DLI-CVD deposition is performed on the first crystalline carrier layer 20'' under the same conditions as the first deposition, such that the thickness of the second carrier layer 20' is 140 microns. This deposition also allows filling of surface cracks in the first crystalline carrier layer 20''. The second carrier layer 20' also forms an at least partially amorphous SiC matrix.

[0090] A second crystallization annealing operation similar to the first annealing operation is then performed. The first crystalline carrier layer 20'' can be repaired by crystallization of the SiC matrix deposited in the cracks 2''. The second crystalline carrier layer 20'' is also formed from p-SiC, in which second layer 20'' the cracks 2 appear.

[0091] A third DLI-CVD deposition is performed on the second crystalline carrier layer 20'', followed by a third crystallization annealing operation identical to the preceding crystallization annealing operation.

[0092] Finally, a fourth DLI-CVD deposition is performed on the third crystalline carrier layer 20'', followed by a fourth crystallization annealing operation, also identical to the preceding crystallization annealing operation.

[0093] It should be remembered that the various deposition and crystallization annealing operations may be entirely carried out under different conditions.

[0094] A fourth crystalline carrier layer 20'' is formed from p-SiC, and the crack 2 appears in this fourth layer 20''.

[0095] The carrier substrate 20 formed by the superposition of four crystalline carrier layers 20'' has a thickness of approximately 560 microns.

[0096] The stack formed by the donor substrate 111 and the carrier substrate 20 is then subjected to an anneal at 1000° C. for 50 minutes. During said annealing, separation is performed at the level of the embedded brittle plane 12. As a result of this separation step d), the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the remaining part 111′ of the donor substrate.

[0097] Grinding of the backside of the carrier substrate 20 is performed to remove the zone containing the residual cracks 2. For this purpose, a thickness of about 100 to 200 microns is removed from the backside of the carrier substrate 20.

[0098] Next, one or more mechanochemical polishing operations are performed to restore the surface roughness of the thin layer 10 and the back surface of the carrier substrate 20, followed by a conventional cleaning sequence.

[0099] Of course, the invention is not limited to the embodiments and examples described, and implementation variations can be made thereto without departing from the scope of the invention as defined by the claims.

Claims

1. A method for manufacturing a composite structure (1) comprising a thin layer (10) made of monocrystalline silicon carbide arranged on a carrier substrate (20) made of silicon carbide, comprising: a) providing a donor substrate (111) made of single crystal silicon carbide; b) ion implantation of light species into the donor substrate (111) to form a buried brittle plane (12), the buried brittle plane (12) defining the thin layer (10) between the buried brittle plane (12) and a free surface of the donor substrate (111); c) successive n steps for forming a plurality of crystalline carrier layers (20″), n being 2 or more, said n crystalline carrier layers (20″) being disposed successively one after the other on the front surface of said donor substrate (111) to form said carrier substrate (20), each forming step comprising: applying direct liquid injection chemical vapor deposition at a temperature of less than 900° C. to form a carrier layer (20′), said carrier layer (20′) being at least partially formed by an amorphous SiC matrix and having a thickness of less than 200 microns; subjecting the carrier layer (20') to a crystallization heat treatment at a temperature of less than or equal to 1000°C to form a crystalline carrier layer (20''); and d) forming, on the one hand, a composite structure (1) comprising said thin layer (10) on said carrier substrate (20) and, on the other hand, a separation along said embedded brittle plane (12) in order to form the remaining part (111') of said donor substrate (111); The method includes:

2. 2. The method according to claim 1, further comprising the step e) of subjecting the composite structure (1) to (one or more) mechanical and / or chemical treatments, wherein the mechanical and / or chemical treatments are applied to the free side of the carrier substrate (20), to the back side of the composite structure (1) and / or to the free side of the thin layer (10), to the front side of the composite structure (1).

3. The method of claim 2, wherein step e) comprises simultaneously mechanochemically polishing the front and back faces of the composite structure (1).

4. Method according to any one of the preceding claims, wherein between steps c) and d) the free face of the carrier substrate (20) is subjected to chemical etching, mechanical grinding and / or mechanochemical polishing.

5. Method according to any one of the preceding claims, wherein the thickness of each deposited carrier layer (20') is less than or equal to 100 microns.

6. Method according to any one of the preceding claims, wherein the deposition of step c) is carried out at a temperature between 100°C and 800°C.

7. The method of any one of claims 1 to 6, wherein the deposition of step c) is carried out at a pressure between 1 and 500 Torr.

8. A method according to any one of the preceding claims, wherein the precursors used during the deposition of step c) are selected from polysilylethylene and disilabutane.

9. The method of any one of claims 1 to 8, wherein step c) comprises n successive steps for forming a plurality of crystalline carrier layers (20''), n being 3 or greater.

10. Step a) is a') providing an initial substrate (11) made of monocrystalline silicon carbide; a'') epitaxially growing a monocrystalline silicon carbide donor layer (110) on said initial substrate (11) to form a donor substrate (111), said donor layer (110) having a density of crystal defects lower than the density of crystal defects of said initial substrate (11); The method according to any one of claims 1 to 9, comprising:

11. 11. The method of claim 10, wherein step a′) comprises forming a monocrystalline conversion layer (13) on the initial substrate (11) in order to convert basal plane dislocation defects of the initial substrate (11) into threading edge dislocation defects.

12. Method according to any one of the preceding claims, wherein said step a'') is carried out at a temperature higher than 1200°C, preferably between 1500°C and 1650°C.

13. The method according to any one of the preceding claims, wherein the separating step d) is carried out at a temperature equal to or greater than the temperature of the crystallization heat treatment of step c).

14. The method according to any one of the preceding claims, comprising a step of reclaiming the remaining part (111') of the donor substrate (111) for reuse as an initial substrate or as a donor substrate.

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