Method for creating an equivalent circuit model of a multi-terminal capacitor, program for creating an equivalent circuit model, storage medium storing the program for creating an equivalent circuit model, simulation method, and simulation device

Abstract

The present invention derives an equivalent circuit model of a multi-terminal capacitor with three or more terminals. Provided is a method for creating an equivalent circuit model of a multi-terminal capacitor in which external electrode terminals of positive polarity and negative polarity are arranged in a staggered manner, the method comprising: a step of measuring an S parameter of the multi-terminal capacitor; a step of deriving an overall impedance of the multi-terminal capacitor on the basis of the measured value of the S parameter; a step of creating an equivalent circuit model of two terminals from the derived overall impedance; a step of deriving an equivalent circuit model of a unit cell from the created equivalent circuit model of two terminals; a step of combining an equivalent circuit model of a parasitic component comprising capacitive and inductive circuit elements with the derived equivalent circuit model of a unit cell to create a topology of a three-dimensional lattice shape; and a step of setting terminals of the multi-terminal capacitor to nodes of the created topology of the three-dimensional lattice.

Description

[Technical field]

[0001] The present disclosure relates to an equivalent circuit model creating method for a multi-terminal capacitor, an equivalent circuit model creating program, a storage medium storing an equivalent circuit model creating program, a simulation method, and a simulation device. [Background technology]

[0002] A method for deriving an equivalent circuit model of a capacitor is disclosed in Patent Document 1. The method disclosed in Patent Document 1 targets a two-terminal capacitor. In other words, the method disclosed in Patent Document 1 is premised on deriving an equivalent circuit model for a two-terminal capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-259482 A Summary of the Invention [Problem to be solved by the invention]

[0004] The method disclosed in Patent Document 1 cannot derive an equivalent circuit model for a capacitor having more than two terminals, i.e., three or more terminals.

[0005] The present invention has been made in view of the above, and an object of the present invention is to provide an equivalent circuit model creating method, an equivalent circuit model creating program, a storage medium storing the equivalent circuit model creating program, a simulation method, and a simulation apparatus, which are capable of deriving an equivalent circuit model of a multi-terminal capacitor having three or more terminals. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, a method for creating an equivalent circuit model of a multi-terminal capacitor according to an embodiment of the present disclosure is a method for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which positive external electrode terminals and negative external electrode terminals are arranged in a staggered manner so that adjacent terminals have different polarities, the method including: a first step of measuring S-parameters of the multi-terminal capacitor; a second step of deriving an impedance of the entire multi-terminal capacitor based on measured values ​​of the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining an equivalent circuit model of a parasitic component based on capacitive and inductive circuit elements with the equivalent circuit model of the unit cell derived in the fourth step to create a three-dimensional lattice-like topology; and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the three-dimensional lattice topology created in the fifth step.

[0007] In order to solve the above-mentioned problems and achieve the object, an equivalent circuit model creation program according to an embodiment of the present disclosure is an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which positive external electrode terminals and negative external electrode terminals are arranged in a staggered pattern so that adjacent terminals have different polarities, the equivalent circuit model creation program causing a computer to execute the following steps: a first step of measuring S-parameters of the multi-terminal capacitor; a second step of deriving an impedance of the entire multi-terminal capacitor based on measured values ​​of the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining an equivalent circuit model of a parasitic component based on capacitive and inductive circuit elements with the equivalent circuit model of the unit cell derived in the fourth step to create a three-dimensional lattice-like topology; and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the three-dimensional lattice topology created in the fifth step.

[0008] In order to solve the above-mentioned problems and achieve the object, a storage medium according to an embodiment of the present disclosure is a storage medium storing an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which positive external electrode terminals and negative external electrode terminals are arranged in a staggered pattern so that adjacent terminals have different polarities, the storage medium storing the equivalent circuit model creation program for causing a computer to execute the following steps: a first step of measuring S-parameters of the multi-terminal capacitor; a second step of deriving an impedance of the entire multi-terminal capacitor based on measured values ​​of the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining an equivalent circuit model of a parasitic component based on capacitive and inductive circuit elements with the equivalent circuit model of the unit cell derived in the fourth step to create a three-dimensional lattice-like topology; and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the three-dimensional lattice topology created in the fifth step.

[0009] In order to solve the above-mentioned problems and achieve the objective, a simulation method according to one aspect of the present disclosure utilizes an equivalent circuit model of a multi-terminal capacitor created using the above-mentioned equivalent circuit model creation method to calculate characteristics of the multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor.

[0010] In order to solve the above-mentioned problems and achieve the objective, a simulation device according to an embodiment of the present disclosure uses an equivalent circuit model of a multi-terminal capacitor created using the above-mentioned equivalent circuit model creation method to calculate characteristics of the multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor. Effect of the Invention

[0011] According to the present disclosure, it is possible to derive an equivalent circuit model of a capacitor having three or more terminals. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a flowchart showing an example of a method for creating an equivalent circuit model of a multi-terminal capacitor according to the present disclosure. [Diagram 2] FIG. 2 is a plan view showing a configuration example of a multi-terminal capacitor. [Diagram 3] FIG. 3 is a cross-sectional view of a portion of FIG. [Figure 4] FIG. 4 is a cross-sectional view of a portion of FIG. [Diagram 5] FIG. 5 is a diagram showing the internal structure of a multi-terminal capacitor. [Figure 6] FIG. 6 is a diagram for explaining a method for measuring the S parameters of a multi-terminal capacitor. [Figure 7] FIG. 7 is a cross-sectional view of a portion of FIG. [Figure 8] FIG. 8 is a cross-sectional view of a portion of FIG. [Figure 9] FIG. 9 is a diagram showing an equivalent circuit of a substrate including a multi-terminal capacitor. [Figure 10] FIG. 10 is a diagram showing the basic form of an equivalent circuit. [Figure 11] FIG. 11 is a diagram showing an equivalent circuit for fitting the low frequency range. [Figure 12] FIG. 12 is a diagram showing an equivalent circuit for fitting the entire frequency band including the low frequency range. [Figure 13] FIG. 13 is a table showing the values ​​of each element included in each of the circuits shown in FIGS. [Figure 14] FIG. 14 is a diagram showing an example of a change in impedance with respect to frequency. [Figure 15] FIG. 15 is a diagram showing an example of a change in equivalent series resistance with respect to frequency. [Figure 16]FIG. 16 is a flowchart showing an example of the fitting process. [Figure 17] FIG. 17 is a diagram showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance. [Figure 18] FIG. 18 is a diagram showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance. [Figure 19] FIG. 19 is a diagram showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance. [Figure 20] FIG. 20 is a diagram showing an example of a unit cell. [Figure 21] FIG. 21 is a diagram showing an image of the overall impedance. [Figure 22] FIG. 22 is a diagram showing an example of an arrangement of unit cells corresponding to the overall impedance. [Figure 23] FIG. 23 is a diagram for explaining weighting coefficients according to placement locations. [Figure 24] FIG. 24 is a table explaining the weighting coefficients of each symbol. [Diagram 25] FIG. 25 is a table illustrating the number of elements corresponding to each symbol. [Figure 26] FIG. 26 is a diagram for explaining the definition of the expansion coefficient. [Figure 27] FIG. 27 is a table illustrating an example of the weighting coefficient of each symbol. [Figure 28] FIG. 28 is a diagram showing the relationship between the expansion coefficient and the weighting coefficient. [Figure 29] FIG. 29 is a table showing the relationship between the expansion coefficient and the weighting coefficient. [Diagram 30] FIG. 30 is a diagram for explaining the elements that constitute the impedance of a unit cell. [Diagram 31] FIG. 31 is a diagram showing an example of a model of a unit cell. [Diagram 32] FIG. 32 is a diagram showing a one-dimensional model corresponding to the impedance of FIG. [Diagram 33]FIG. 33 is a diagram showing a two-dimensional model corresponding to the one-dimensional model of FIG. [Diagram 34] FIG. 34 is a diagram showing a two-dimensional model in which the two-dimensional model shown in FIG. 33 is simply expressed. [Diagram 35] FIG. 35 is a diagram showing a three-dimensional model obtained by combining the two-dimensional models shown in FIG. 34 in simplified notation. [Diagram 36] FIG. 36 is a diagram showing an example of a three-dimensional model obtained by combining the two-dimensional models shown in FIG. 34 in simplified notation. [Figure 37] FIG. 37 is a diagram showing an example of a three-dimensional model having 12 terminals in 3 rows and 4 columns. [Figure 38] FIG. 38 is a diagram showing an example of a three-dimensional model having 12 terminals in 3 rows and 4 columns. [Figure 39] FIG. 39 is a diagram showing an example of a three-dimensional model having 12 terminals in 3 rows and 4 columns. [Diagram 40] FIG. 40 is a diagram showing an example of a three-dimensional model having 12 terminals in 3 rows and 4 columns. [Diagram 41] FIG. 41 is a diagram for explaining the procedure for converting a three-dimensional model into a circuit diagram symbol. [Diagram 42] FIG. 42 is a diagram for explaining the procedure for converting a three-dimensional model into a circuit diagram symbol. [Diagram 43] FIG. 43 is a diagram for explaining the procedure for converting a three-dimensional model into a circuit diagram symbol. [Diagram 44] FIG. 44 is a diagram showing an example of a three-dimensional model with a terminal arrangement of 3 rows and 3 columns. [Diagram 45] FIG. 45 is a diagram showing an example of a part model expressed using the symbols shown in FIG. [Diagram 46] FIG. 46 is a diagram showing a multi-terminal capacitor having terminals arranged in 3 rows and 5 columns. [Figure 47] FIG. 47 is a diagram showing an equivalent circuit of a substrate including a multi-terminal capacitor, which has been described with reference to FIG. [Figure 48] FIG. 48 is a diagram showing an example of a simulation result of S parameters. [Figure 49]FIG. 49 is a diagram for explaining an example of a simulation in the time domain. [Figure 50] FIG. 50 is a diagram showing changes in the current value of the current source in FIG. [Figure 51] FIG. 51 is a diagram showing an example of a change in the load voltage. [Figure 52] FIG. 52 is a diagram illustrating an example of the configuration of a simulation device according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In the following description of each embodiment, the same or equivalent components as those in other embodiments are given the same reference numerals, and their description will be simplified or omitted. The present invention is not limited to each embodiment. In addition, the components of each embodiment include those that are replaceable and easy for a person skilled in the art, or those that are substantially the same. The configurations described below can be appropriately combined. In addition, the configurations can be omitted, replaced, or modified within the scope of the gist of the invention.

[0014] Fig. 1 is a flowchart showing an example of a method for creating an equivalent circuit model of a multi-terminal capacitor according to the present disclosure. As shown in Fig. 1, first, a multi-terminal capacitor is mounted on a board, and S parameters of the multi-terminal capacitor are measured (step ST1). For example, a jig on which a capacitor is mounted is prepared, and the S parameters are measured using the jig.

[0015] Next, the impedance of the entire multi-terminal capacitor is calculated based on the S-parameters measured in step ST1 (step ST2). Furthermore, a two-terminal equivalent circuit model is created from the entire impedance calculated in step ST2 (step ST3). At this time, the two-terminal equivalent circuit model is created by a fitting process. The fitting process will be described later.

[0016] An equivalent circuit model of a unit cell is derived from the two-terminal equivalent circuit model created in step ST3 (step ST4). At this time, the equivalent circuit model of the unit cell is derived from the two-terminal equivalent circuit model based on the periodic structure.

[0017] Next, a three-dimensional lattice topology is created by combining the equivalent circuit model of the unit cell derived in step ST4 with an equivalent circuit model of the parasitic components due to capacitive and inductive circuit elements (step ST5).Then, terminals of a multi-terminal capacitor are set at the nodes of the three-dimensional lattice created in step ST5 (step ST6).

[0018] (Example of multi-terminal capacitor configuration) 2 to 5 are diagrams showing configuration examples of a multi-terminal capacitor. Fig. 2 is a plan view showing a configuration example of a multi-terminal capacitor. Fig. 3 is a diagram showing a cross section of A1-A1 part in Fig. 2. Fig. 4 is a diagram showing a cross section of A2-A2 part in Fig. 2.

[0019] For ease of explanation, the mutually orthogonal X-axis, Y-axis, and Z-axis directions are defined here. The direction from terminal T1 toward terminal T2 is defined as the X-axis direction. The direction from terminal T1 toward terminal T4 is defined as the Y-axis direction. The depth direction of substrate 10 is defined as the Z-axis direction.

[0020] As shown in FIG. 2, the multi-terminal capacitor 1 of this example is formed on a substrate 10. The multi-terminal capacitor 1 of this example has nine terminals T1 to T9. In FIG. 2, the terminals T2, T4, T6, and T8 are positive terminals connected to the positive electrode as described later. Also, the terminals T1, T3, T5, T7, and T9 are negative terminals connected to the negative electrode as described later. In the multi-terminal capacitor 1 of this example, the polarities of the terminals adjacent to each other in the X-axis direction are different, and the polarities of the terminals adjacent to each other in the Y-axis direction are different. For example, when focusing on the terminal T1 which is a negative terminal, the terminal T2 adjacent to the terminal T1 in the X-axis direction is a positive terminal, and the terminal T4 adjacent to the terminal T1 in the Y-axis direction is a positive terminal. Also, when focusing on the terminal T4 which is a positive terminal, the terminal T5 adjacent to the terminal T4 in the X-axis direction is a negative terminal, and the terminals T1 and T7 adjacent to the terminal T4 in the Y-axis direction are negative terminals. Furthermore, when focusing on terminal T5, which is a negative terminal, terminals T4 and T6 adjacent to terminal T5 in the X-axis direction are positive terminals, and terminals T2 and T8 adjacent to terminal T5 in the Y-axis direction are positive terminals. In this way, the polarities of terminals adjacent to terminal T5 in the X-axis direction are different, and the polarities of terminals adjacent to terminal T5 in the Y-axis direction are different, and the positive and negative terminals are arranged alternately, i.e., in a staggered pattern, in the X-axis and Y-axis directions.

[0021] Fig. 3 is a diagram showing a cross section of A1-A1 part in Fig. 2. Referring to Fig. 3, the terminal T1 is electrically connected to the negative electrodes NE1 and NE2 inside the substrate 10 by a via hole VH1 inside the substrate 10. The terminal T2 is electrically connected to the positive electrodes PE1 and PE2 inside the substrate 10 by a via hole VH2 inside the substrate 10. The terminal T3 is electrically connected to the negative electrodes NE1 and NE2 inside the substrate 10 by a via hole VH3 inside the substrate 10.

[0022] Fig. 4 is a diagram showing a cross section of part A2-A2 in Fig. 2. Referring to Fig. 4, a negative electrode NE1, a positive electrode PE1, a negative electrode NE2, and a positive electrode PE2 are laminated inside the substrate 10. The positive electrode PE1 is insulated from the negative electrodes NE1 and NE2. The positive electrode PE2 is insulated from the negative electrodes NE1 and NE2.

[0023] FIG. 5 is a diagram showing the internal structure of the multi-terminal capacitor 1. In FIG. 5, the surface layer of the substrate 10 is separated from the internal negative electrode NE1 to show the internal structure of the multi-terminal capacitor 1. Also, in FIG. 5, a part of the multi-terminal capacitor 1 is cut away to show the internal structure. In FIG. 5, the diameter of the holes is exaggerated. Also, in FIG. 5, the diameter of each of the terminals T1 to T5, T7 to T9 is the same as the diameter of the via holes VH1 and VH2, but in reality, the diameters are different as shown in FIG. 2 and FIG. 3.

[0024] As shown in FIG. 5, the terminal T1 is electrically connected to the negative electrode NE1 through a via hole VH1. The terminal T1 is electrically connected to the negative electrode NE2 through a via hole VH1. Similarly, the terminals T5 and T9 are electrically connected to the negative electrode NE1 and the negative electrode NE2. The terminal T2 is connected to the positive electrode PE and the positive electrode PE2 through a via hole VH2. Similarly, the other terminals are electrically connected to the positive electrode PE1 and the positive electrode PE2, or the negative electrodes NE1 and NE2. The negative electrode NE1 and the positive electrode PE1 face each other through an insulating layer (not shown). The positive electrode PE1 and the negative electrode NE2 face each other through an insulating layer (not shown). The negative electrode NE2 and the positive electrode PE2 face each other through an insulating layer (not shown). The opposing electrodes can realize a desired capacitance.

[0025] 2 to 5 are examples of multi-terminal capacitors using multilayer ceramic capacitors, in which positive and negative electrodes are arranged in a staggered pattern. As long as the multi-terminal capacitor has positive and negative electrodes arranged in a staggered pattern, it may be a silicon capacitor or the like.

[0026] (S-parameter measurement) Fig. 6 is a diagram for explaining a method for measuring S parameters of a multi-terminal capacitor. Fig. 6 is a diagram showing a jig for measuring S parameters. Fig. 7 is a diagram showing a cross section taken along the B1-B1 portion in Fig. 6. Fig. 8 is a diagram showing a cross section taken along the B2-B2 portion in Fig. 6.

[0027] 6, a substrate 10a is provided on a jig 11. The substrate 10a is a substrate for evaluating the multi-terminal capacitor 1. The multi-terminal capacitor 1 is mounted on the substrate 10a.

[0028] The multi-terminal capacitor 1 has nine terminals T1 to T9. The terminals T2, T4, T6, and T8 are positive electrode terminals electrically connected to a positive electrode PE inside the substrate 10a. The terminals T1, T3, T5, T7, and T9 are negative electrode terminals electrically connected to a negative electrode NE inside the substrate 10a.

[0029] For example, as shown in FIG. 7, the terminal T1 is electrically connected to the negative electrode NE inside the substrate 10a by a via hole VH1. The terminal T1 is not connected to the positive electrode PE inside the substrate 10a. The terminal T2 is electrically connected to the positive electrode PE inside the substrate 10a by a via hole VH2. The terminal T3 is electrically connected to the negative electrode NE inside the substrate 10a by a via hole VH3. The terminal T3 is not connected to the positive electrode PE inside the substrate 10a. In this way, the polarities of the terminals adjacent to each other in the X-axis direction are different, and the polarities of the terminals adjacent to each other in the Y-axis direction are different, and the positive electrode terminals and the negative electrode terminals are alternately arranged, i.e., in a staggered pattern, in the X-axis and Y-axis directions.

[0030] The substrate 10a has ports PO1 and PO2. The port PO1 is provided on one side of the multi-terminal capacitor 1 in the Y-axis direction, and the port PO2 is provided on the other side. The port PO1 has a positive electrode PO11 and a negative electrode PO12. The port PO2 has a positive electrode PO21 and a negative electrode PO22.

[0031] When measuring the S-parameters, a resistor RA is electrically connected between the positive pole PO11 and the negative pole PO12 of the port PO1. Similarly, a resistor RB is electrically connected between the positive pole PO21 and the negative pole PO22 of the port PO2. The resistors RA and RB are, for example, 50Ω chip resistors.

[0032] As shown in FIG. 8, the positive electrode PO11 of the port PO1 is electrically connected to the positive electrode PE inside the substrate 10a by a via hole VP1. The negative electrode PO12 of the port PO1 is electrically connected to the negative electrode NE inside the substrate 10a by a via hole VN1. The negative electrode PO12 is not connected to the positive electrode PE inside the substrate 10a. Similar to the port PO1, the positive electrode PO21 of the port PO2 is electrically connected to the positive electrode PE inside the substrate 10a, and the negative electrode PO22 of the port PO2 is electrically connected to the negative electrode NE inside the substrate 10a.

[0033] FIG. 9 is a diagram showing an equivalent circuit of the substrate 10a including the multi-terminal capacitor 1. As shown in FIG. 9, the positive electrode PO11 of the port PO1 is electrically connected to the positive electrode PE. The positive electrode PO21 of the port PO2 is electrically connected to the positive electrode PE. The negative electrode PO12 of the port PO1 is electrically connected to the negative electrode NE. The negative electrode PO22 of the port PO2 is electrically connected to the negative electrode NE. The terminals T1, T3, T5, T7 and T9 are negative terminals and are electrically connected to the negative electrode NE. The terminals T2, T4, T6 and T8 are positive terminals and are electrically connected to the positive electrode PE.

[0034] In the equivalent circuit shown in Figure 9, S-parameters are measured according to the shunt-through method. In this case, for example, a network analyzer is used to measure the S-parameters. S-parameters (Scattering parameters), also called scattering matrices or scattering parameters, are parameters that express the transmitted and reflected power characteristics of a circuit network.

[0035] Based on the S-parameter measurement results, the impedance Z of the entire circuit is calculated. total Find the value of impedance Z total The value of is derived using the following formula (1). Z total =(Z0 / 2)×{S 21 / (1-S 21 )} …(1)

[0036] In addition, Z0 in the above formula (1) is the characteristic impedance. S 21is the power gain when the impedance of the source and load is Z0.

[0037] (Fitting process) Next, the fitting process will be described. The fitting process is carried out by calculating the impedance Z total The fitting process is a process for deriving an equivalent circuit that corresponds to the measured value. The fitting process is a process for matching the simulation value with the measured value. Specifically, in order to match the impedance simulation value by the SPICE (Simulation Program with Integrated Circuit Emphasis) model with the measured value, an equivalent circuit is derived by combining resistive elements, inductive elements, and capacitive elements.

[0038] Figures 10 to 12 show the impedance Z of the entire circuit. total FIG. 10 is a diagram showing an example of an equivalent circuit for the value of . FIG. 10 is a diagram showing a basic form of an equivalent circuit. The equivalent circuit shown in FIG. 10 includes resistive elements R1 and R3, a capacitive element C1, and an inductive element L2. The capacitive element C1, the inductive element L2, and the resistive element R3 are connected in series. The resistive element R1 is connected in parallel to the capacitive element C1. The resistive element R1 is an insulation resistor.

[0039] Fig. 11 is a diagram showing an equivalent circuit for fitting a low frequency range. The equivalent circuit shown in Fig. 11 includes resistive elements R1, R3 to R6, capacitive elements C1, C4 to C6, and an inductive element L2. The capacitive element C1, the inductive element L2, and the resistive elements R3, R4, R5, and R6 are connected in series. The resistive element R1 is connected in parallel to the capacitive element C1, the capacitive element C4 to the resistive element R4, the capacitive element C5 to the resistive element R5, and the capacitive element C6 to the resistive element R6. The resistive element R1 is an insulation resistor.

[0040] Fig. 12 is a diagram showing an equivalent circuit for fitting the entire frequency band including the low frequency band. The equivalent circuit shown in Fig. 12 includes resistive elements R1, R3 to R8, capacitive elements C1, C4 to C6, and inductive elements L2, L7, and L8. The capacitive element C1, the inductive element L2, and the resistive elements R3, R4, R5, R6, R7, and R8 are connected in series. The resistive element R1 is connected in parallel to the capacitive element C1, the capacitive element C4 to the resistive element R4, the capacitive element C5 to the resistive element R5, the capacitive element C6 to the resistive element R6, the inductive element L7 to the resistive element R7, and the inductive element L8 to the resistive element R8. The resistive element R1 is an insulation resistor.

[0041] FIG. 13 is a table showing the values ​​of each element included in the circuits shown in FIGS. 10 to 12. That is, the table in FIG. 13 shows examples of the capacitance value [F] of each capacitive element C, the inductance value [H] of each inductive element L, and the resistance value [Ω] of each resistive element R. The numbers 1 to 8 in the "No." column in the leftmost column in the table, and the codes combined with the capacitive element C, the inductive element L, or the resistive element R correspond to the codes of the elements included in the circuits shown in FIGS. 10 to 12. For example, the capacitance value of the capacitive element C1 is 8.455×10 -8 [F], the inductance value of the inductive element L2 is 1.005×10 -11 [H], the resistance value of resistor element R1 is 1.000×10 8 [Ω], the resistance value of resistor element R3 is 9.780×10 -3 The values ​​of the other elements are as shown in the table in FIG.

[0042] Fig. 14 is a diagram showing an example of change in impedance with respect to frequency. In Fig. 14, the horizontal axis is frequency [Hz], and the vertical axis is impedance [Ω]. For example, as shown in Figs. 10 to 12, by combining a capacitance element C, an inductance element L, and a resistance element R, it is possible to make the simulation value SM1 of the impedance by the SPICE model coincide with the measured value ME1. That is, an equivalent circuit is created by connecting the capacitance element C, the inductance element L, and the resistance element R so that the simulation value SM1 of the SPICE model coincides with the measured value ME1.

[0043] FIG. 15 is a diagram showing an example of the change in equivalent series resistance (ESR) with respect to frequency. In FIG. 15, the horizontal axis is frequency [Hz], and the vertical axis is equivalent series resistance [Ω]. For example, as shown in FIG. 10 to FIG. 12, by combining a capacitance element C, an inductance element L, and a resistance element R, it is possible to make the simulation value SM2 of the equivalent series resistance by the SPICE model coincide with the measured value ME2. That is, an equivalent circuit is created by connecting the capacitance element C, the inductance element L, and the resistance element R so that the simulation value SM2 of the SPICE model coincides with the measured value ME2.

[0044] Fig. 16 is a flowchart showing an example of fitting processing. In Fig. 16, first, a circuit model to which a resistive element, an inductive element, or a capacitive element is added is created (step ST31). Then, a simulation is performed using the circuit model to which a resistive element, an inductive element, or a capacitive element is added (step ST32).

[0045] Next, it is determined whether or not a simulation value based on a circuit model to which a resistive element, an inductive element, or a capacitive element is added matches the measured value (step ST33). If the simulation value matches the measured value as a result of the determination in step ST33 (Yes in step ST33), the circuit model corresponding to the simulation value is set as an equivalent circuit model corresponding to the measured value of the impedance value of the entire circuit (step ST34).

[0046] On the other hand, if the result of the judgment in step ST33 is that the simulation value does not match the measured value (No in step ST33), the process returns to step ST31, and a new circuit model is created by further adding a resistive element, an inductive element, or a capacitive element. A simulation is performed using the new circuit model (step ST32), and it is judged whether the simulation value using the circuit model matches the measured value (step ST33). The above process is repeated until the simulation value using the circuit model matches the measured value. By repeating the above process, the simulation value gradually approaches the measured value, and it is possible to finally make the simulation value match the measured value. The simulation value that matches the measured value is set as an equivalent circuit model. By performing a fitting process using basic circuit elements, i.e., resistive elements, inductive elements, and capacitive elements, it is possible to provide an equivalent circuit model (e.g., a SPICE netlist) that can be used in a general-purpose circuit simulator.

[0047] (Determining whether it matches or not) In step ST33 of FIG. 16, whether or not the simulation value matches the measured value may be determined, for example, as follows. That is, the measured value is not constant, but has a range of variation as shown in FIG. 14 and FIG. 15. When the entire simulation value is included in the range of variation of this measured value, it can be determined that the simulation value matches the measured value. That is, as shown in FIG. 14, the measured impedance value ME1 has a range of variation, and when the entire simulation value SM1 is included in the range of variation of the measured value ME1, it can be determined that the simulation value matches the measured value. Also, as shown in FIG. 15, the measured equivalent series resistance (ESR) value ME2 has a range of variation, and when the entire simulation value SM2 is included in the range of variation of the measured value ME2, it can be determined that the simulation value matches the measured value.

[0048] Also, a frequency range may be divided, and if the simulation value is included in the range of change of the measurement value within that frequency range, it may be determined that the simulation value matches the measurement value. For example, if the frequency band to be used is known in advance, a frequency range may be divided, and it may be determined whether or not the simulation value matches the measurement value within that frequency range.

[0049] 17 to 19 are diagrams showing examples of measured values ​​and simulated values ​​for impedance and equivalent series resistance (ESR). In FIG. 17 to FIG. 19, the horizontal axis is frequency [Hz], and the vertical axis is impedance [Ω]. By sequentially adding and combining elements as in the circuits shown in FIG. 10 to FIG. 12, a process is performed in which the simulation value SM1 is made to match the impedance measurement value ME1 and the simulation value SM2 is made to match the equivalent series resistance (ESR) measurement value ME2, i.e., a fitting process. At this time, by sequentially combining elements from the low frequency band to the high frequency band, the waveforms of the simulation values ​​SM1 and SM2 are made to match the measurement values ​​ME1 and ME2.

[0050] Figure 17 corresponds to the equivalent circuit in Figure 10. The equivalent circuit in Figure 10 uses one resistive element for the equivalent series resistance and one inductive element for the equivalent series inductance. Since the equivalent series resistance has a small number of elements, it has flat characteristics that do not have frequency dependency, as shown in Figure 17.

[0051] Figure 18 corresponds to the equivalent circuit in Figure 11. The equivalent circuit in Figure 11 is an equivalent circuit in which three CR parallel circuits are added in series to the equivalent circuit in Figure 10. As shown in Figure 18, the frequency characteristics of the equivalent series resistance in the low range are reflected.

[0052] Figure 19 corresponds to the equivalent circuit in Figure 12. The equivalent circuit in Figure 12 is an equivalent circuit in which two LR parallel circuits are added in series to the equivalent circuit in Figure 11. As shown in Figure 19, the frequency characteristics of the impedance and equivalent series resistance in a frequency range higher than the self-resonant frequency are reflected.

[0053] In other words, the accuracy of matching the simulation values ​​with the measured values ​​is higher in the case of FIG. 18, in which the equivalent circuit of FIG. 11 is added, than in the case of FIG. 17, in which the equivalent circuit of FIG. 10 is added. The accuracy of matching the simulation values ​​with the measured values ​​is higher in the case of FIG. 19, in which the equivalent circuit of FIG. 12 is added, than in the case of FIG. 18, in which the equivalent circuit of FIG. 11 is added. As described above, by adding resistive elements, inductive elements, and capacitive elements, the accuracy of matching the simulation values ​​with the measured values ​​can be improved.

[0054] As described above, a unit cell shown in FIG. 20 can be obtained by fitting the measured values ​​to the simulation values. FIG. 20 is a diagram showing an example of a unit cell. The unit cell shown in FIG. 20 includes resistive elements R1, R3 to R9, capacitive elements C1, C4, C5, C7, C8, and inductive elements L2, L7 to L10. The capacitive element C1, the inductive element L2, and the resistive elements R3, R4, R5, R6, R7, R8, and R9 are connected in series. The resistive element R1 is connected to the capacitive element C1, the capacitive element C4 is connected to the resistive element R4, the capacitive element C5 is connected to the resistive element R5, the inductive element L7 is connected to the resistive element R6, the inductive element L8 is connected to the resistive element R7, the capacitive element C7 and the inductive element L9 are connected to the resistive element R8, and the capacitive element C8 and the inductive element L10 are connected to the resistive element R9 in parallel. The resistive element R1 is an insulation resistor.

[0055] (Unit cell array) Figure 21 shows the overall impedance Z total FIG. 22 shows an image of the overall impedance Z total FIG. 13 is a diagram showing an example of an arrangement of unit cells corresponding to

[0056] In Figure 21, the overall impedance Z total One terminal is positive (+) and the other terminal is negative (-). Next, the total impedance Z total is converted to an array of m rows and n columns (m and n are natural numbers). In this example, when the array is m rows and n columns, the impedance Z unit Let us consider the total impedance Z totalis defined as the impedance Z of the unit cell. unit is defined by the following equation (2). Z unit =K Z total …(2)

[0057] Using the above formula, the impedance of a unit cell is derived from the overall impedance based on the periodic structure of the array. For example, as shown in FIG. 22, when the array is 3×3, m=3 and n=3, so the number of unit cells K=2·3·3-3-3=12. Therefore, as shown in FIG. 22, 12 unit cells are arranged in a matrix, that is, connected in series and in parallel. In this example, a weighting coefficient is set according to the location of the impedance between each terminal, that is, the location of the unit cell in the matrix. Then, each impedance value is multiplied by the weighting coefficient.

[0058] FIG. 23 is a diagram for explaining weighting coefficients according to the placement location. FIG. 23 shows a state in which unit cells are arranged in a lattice shape with m rows and n columns. In FIG. 23, a symbol with the number "1" in a rectangle indicates impedance Z1. Impedance Z1 is an element placed inside the lattice. In other words, impedance Z1 is placed in a location other than the outer periphery of the lattice. Impedance Z1 is a factor of the overall impedance Z total is multiplied by a weighting coefficient K1.

[0059] In FIG. 23, the symbol with the number "2" in the rectangle indicates impedance Z2. Impedance Z2 is an element arranged at the end of the outer periphery excluding the corners of the lattice. Impedance Z2 is the overall impedance Z total is multiplied by weighting coefficient K2.

[0060] In FIG. 23, the symbol with the number "3" in the rectangle indicates impedance Z3. Impedance Z3 is an element arranged at the corner of the outer periphery of the lattice. Impedance Z3 is the overall impedance Z total is multiplied by weighting coefficient K3.

[0061] Here, examples of weighting coefficients K1, K2, and K3 will be described with reference to Fig. 24. Fig. 24 is a table explaining the weighting coefficients of each symbol. As shown in Fig. 24, the weighting coefficients K1, K2, and K3 are defined by the following equations (3) to (5). K1 = 2mn…(3) K2 = 4mn / 3…(4) K3=8mn / 7…(5) However, in the formulas (3) to (5), m ≧ 3 and n ≧ 3. By setting such weighting coefficients, the overall impedance Z total is calculated as the sum of the reciprocals of the impedances Z1, Z2, and Z3 of each element. This means that it can be calculated as the sum of the admittances.

[0062] Fig. 25 is a table for explaining the number of elements corresponding to each symbol. As shown in Fig. 25, if the number of elements corresponding to the symbol with the number "1" in the rectangle is N1, the number of elements corresponding to the symbol with the number "2" in the rectangle is N2, and the number of elements corresponding to the symbol with the number "3" in the rectangle is N3, the numbers N1, N2, and N3 are expressed by the following formulas (6) to (8). N1 = 2mn-3m-3n+4…(6) N2 = 2m + 2n - 12 … (7) N3=8…(8)

[0063] The identity satisfied by numbers N1, N2, and N3 is equation (9). (1 / 2)·N1+(3 / 4)·N2+7 / 8·N3=mn…(9)

[0064] The relationship between the numbers N1, N2, and N3 can be expressed using weighting coefficients as shown in equation (10). (N1 / K1)+(N2 / K2)+(N3 / K3)=1…(10)

[0065] Overall impedance Z total The identity that is satisfied is shown in equation (11). (N1 / Z1)+(N2 / Z2)+(N3 / Z3)=1 / Ztotal …(11)

[0066] In addition, the overall impedance Z total To divide it into 12 unit cells connected in a matrix, the resistance and induction values ​​should be multiplied by 6 (K=6), and the capacitance should be multiplied by 1 / 6 (K=6). That is, the resistance value R unit is expressed by the following equation (12), the induction value L of the unit cell unit is expressed by the following equation (13), and the capacitance value of the unit cell C unit is expressed as follows: R unit =K R total …(12) L unit =K L total …(13) C unit =C total / K …(14)

[0067] In formula (12), R total is the resistance value of the resistor element before it is divided into unit cells. In equation (13), L total is the inductance value of the inductive element before it is divided into unit cells. In equation (14), C total is the capacitance value of the capacitive element before being divided into unit cells.

[0068] In other words, to divide it into K unit cells connected in a matrix, the resistance and induction values ​​are multiplied by K, and the capacitance value is multiplied by 1 / K. In this way, the value of each element is multiplied by K or 1 / K and then distributed to the unit cells.

[0069] By determining the values ​​of each element as shown in the above equations (12) to (14), the impedance obtained by combining all the elements is the original impedance Z total become.

[0070] Here, formulas (12) to (14) are for the case where there is no weighting and the weighting coefficients are equal. If weighting coefficients K1, K2, and K3 are applied instead of being equal, then according to the definitions of formulas (3) to (5), K1 = 18, K2 = 12, and K3 = 72 / 7. The resistance value R of the unit cell reflecting the weighting coefficients is unit1 , R unit2 , R unit3 , induction value L unit1 , L unit2 , L unit3 , capacitance value C unit1 , C unit2 , C unit3 When calculating, the following formula is applied instead of formula (12), formula (13), and formula (14).

[0071] For the weighting coefficient K1, equations (12.1) to (14.1) are applied. R unit1 =K1 R total …(12.1) L unit1 =K1 L total …(13.1) C unit1 =C total / K1…(14.1)

[0072] For the weighting coefficient K2, equations (12.2) to (14.2) are applied. R unit2 =K2 R total …(12.2) L unit2 =K2 L total …(13.2) C unit2 =C total / K2…(14.2)

[0073] For the weighting coefficient K3, equations (12.3) to (14.3) are applied. R unit3 =K3 R total …(12.3) L unit3 =K3 L total …(13.3) C unit3 =C total / K3…(14.3)

[0074] That is, to divide it into K unit cells connected in a matrix, the resistance and induction values ​​are multiplied by K1, K2, and K3, and the capacitance values ​​are multiplied by 1 / K1, 1 / K2, and 1 / K3. In this way, the value of each element is multiplied by K1, K2, and K3 or 1 / K1, 1 / K2, and 1 / K3, and then allocated to the unit cells.

[0075] By setting the weighting coefficients as described above, it is possible to perform correct weighting for any m-row, n-column array. That is, even if the array is changed, it is possible to perform correct weighting for the impedance Z1 of the elements arranged inside the lattice, the impedance Z2 of the elements arranged on the outer periphery excluding the corners of the lattice, and the impedance Z3 of the elements arranged at the corners of the lattice.

[0076] Incidentally, the above is based on the premise that the unit cells arranged in m rows and n columns have the same size. That is, it is based on the premise that the regions having the same area in plan view are arranged in m rows and n columns, and the electrodes inside the substrate are evenly divided. In reality, the areas may not be the same in plan view, and it is preferable to set the weighting coefficient taking such a case into consideration. For example, a portion corresponding to an electrode arranged on the periphery may extend outward. Since the parasitic capacitance of this extended portion is large, it is preferable to take this into consideration. In this way, when the electrodes inside the substrate are not evenly divided, a more accurate simulation can be performed by changing the weighting coefficient. That is, when the unit cells are arranged on the periphery of the matrix, and there is an extended portion of the electrode corresponding to the unit cell, the weighting coefficient is set taking the extended portion into consideration.

[0077] Therefore, in this disclosure, an expansion coefficient δ is defined and applied to the expansion portion of the electrode corresponding to the unit cells arranged on the periphery. Figure 26 is a diagram explaining the definition of the expansion coefficient δ. The expansion coefficient δ is the ratio of the portion of the internal electrode that is formed by protruding outside the arrangement of the unit cells.

[0078] As shown in FIG. 26, unit cells Cu are arranged in m rows and n columns on the substrate 1c. Each unit cell Cu is provided with a terminal T. An internal electrode region 1ce of the substrate 1c is formed to extend outside the m rows and n columns of the unit cell Cu. If the vertical and horizontal width CL1 of the unit cell is "1", the internal electrode region 1ce is "m+2δ" with respect to "m" and "n+2δ" with respect to "n", and the extension width in the vertical and horizontal directions is 2δ. In this example, since the width CL1 of the unit cell is "1", the extension coefficient δ / 1=δ. As a result, the extension width outside the arrangement of the unit cells becomes the extension coefficient δ.

[0079] (ratio of width to length of unit cell) In this example, when considering the extended portion, the effective number of unit cells is set to (m+2δ)(n+2δ) instead of mn. In this case, the numbers of elements (N1, N2, N3) satisfy the following identity (15). (1 / 2)N1+pN2+qN3=(m+2δ)(n+2δ)…(15)

[0080] Of the weighting coefficients K1 to K3, the weighting coefficients K2 and K3 are changed according to the external dimensions of the internal electrodes. Examples of the weighting coefficients K1, K2, and K3 will be described. FIG. 27 is a table for explaining examples of the weighting coefficients of each symbol. As shown in FIG. 27, the weighting coefficients K1, K2, and K3 are defined by the following equations (3), (4a), and (5a). K1 = 2mn…(3) K2 = mn / p…(4a) K3=mn / q…(5a) However, in formulas (3), (4a), and (5a), m≧3 and n≧3. In equation (4a), the value p is given by the following equation (16): p = (3 / 4) + δ … (16) In equation (5a), the value q is given by the following equation (17): q=(7 / 8)+(3δ / 2)+(δ 2 / 2)…(17)

[0081] In addition, if the expansion coefficient δ=0 in equations (16) and (17), equation (4a) coincides with equation (4), and equation (5a) coincides with equation (5).

[0082] Fig. 28 is a diagram showing the relationship between the expansion coefficient and the weighting coefficient. In Fig. 28, the horizontal axis represents the expansion coefficient δ, and the vertical axis represents the ratio of the weighting coefficient to the number mn of unit cells. In Fig. 28, the solid line represents the change in the ratio of the weighting coefficient K1 to the number mn of unit cells. The dashed line represents the change in the ratio of the weighting coefficient K2 to the number mn of unit cells. The dashed line represents the change in the ratio of the weighting coefficient K3 to the number mn of unit cells.

[0083] Fig. 29 is a table showing the relationship between the expansion coefficient and the weighting coefficient. Fig. 29 shows examples of the ratios K1 / mn, K2 / mn, and K3 / mn of the weighting coefficients K1, K2, and K3 to the number of parts arranged in m rows and n columns when the expansion coefficient δ=0 or when the expansion coefficient δ=0.4. Note that K2 / mn=1 / p and K3 / mn=1 / q.

[0084] In this example, when the expansion coefficient δ=0, the ratio K1 / mn is 2, the ratio K2 / mn is approximately 1.333, and the ratio K3 / mn is approximately 1.142. When the expansion coefficient δ=0.4, the ratio K1 / mn is 2, the ratio K2 / mn is approximately 0.869, and the ratio K3 / mn is approximately 0.643. Considering the case where the external dimensions of the internal electrodes change as a degree of design freedom, that is, the case where the expansion coefficient changes, the weighting coefficient is practically set within the range shown in FIG.

[0085] FIG. 30 is a diagram for explaining the components that constitute the impedance of a unit cell. The impedance Z unit In this example, the parasitic components of the wiring on the mounting board are not taken into consideration. Therefore, in this example, the impedance Z unit the impedance of the first element Z u1 and the impedance of the second element Z u2 In other words, the impedance Z unit is the impedance Zu1 and the second element, the impedance Z u2 The second element, impedance Z u2 corresponds to the parasitic component of the wiring on the mounting board. By considering the second element, it is possible to obtain simulation results that take into account the parasitic components of the actual board wiring. Note that the impedance Z u2 In this example, it consists of an inductive element and two resistive elements connected in series, with another inductive element connected in parallel to one of the resistive elements.

[0086] In the following explanations, the impedance Z of the unit cell is unit is represented by a thick solid line, and the impedance of the first element Z u1 is represented by a double line, and the impedance of the second element Z u2 is represented by a triple line.

[0087] 31 to 36 are diagrams for explaining the process of creating a three-dimensional model from a unit cell. FIG. 31 is a diagram showing an example of a unit cell model. In the unit cell model M shown in FIG. 31, the impedance Z unit One end of the positive electrode TP and the other end of the negative electrode TN. In Fig. 31, the negative electrode TN is represented by a double circle. This is the same in the subsequent figures.

[0088] Figure 32 shows the impedance Z unit FIG. 32 shows a one-dimensional model 1M corresponding to the impedance Z u1 and impedance Z u2 The first element, impedance Z, is connected in series to the other side of node S. u1 and on the other side is the second element, the impedance Z u2 Impedance Z u1 One end of the impedance is the node S and the other end is the positive electrode TP. u2 One end of is the node S and the other end is the negative electrode TN. In this example, the impedance Z u1is a capacitive circuit element, and impedance Z u2 is an inductive circuit element.

[0089] FIG. 33 is a diagram showing a two-dimensional model 2M corresponding to the one-dimensional model 1M in FIG. u1 is divided into two, and the impedance Z u2 In this case, as shown in Figure 33, a 2Z u1 is connected, and between the node S and the negative electrode TN, "2Z u2 " is connected between the other node S and the positive electrode TP. u2 " is connected, and "2Z u1 " is connected. In this way, the state in which twice the original impedance value is connected to both sides of node S is the two-dimensional model.

[0090] The two-dimensional model 2M shown in Figure 33 is a series-connected "2Z u1 " and "2Z u2 " are connected in parallel. Therefore, the combined impedance between the positive electrode TP and the negative electrode TN is equal to the impedance of the one-dimensional model 1M in FIG.

[0091] FIG. 34 is a diagram showing a two-dimensional model 2Ma that is a simplified representation of the two-dimensional model 2M shown in FIG. u1 " is indicated by double lines, and "2Z" in FIG. u2 " is shown by a thick solid line (shaded solid line).

[0092] Fig. 35 is a diagram showing a three-dimensional model 3M obtained by combining two-dimensional models 2Ma shown in Fig. 34 in a simplified manner. The three-dimensional model 3M shown in Fig. 35 is a three-dimensional model constructed by combining the two-dimensional models shown in Fig. 34 in a three-dimensional lattice shape. A multi-terminal three-dimensional model can be created by arbitrarily combining the two-dimensional models shown in Fig. 34.

[0093] Fig. 36 is a diagram showing an example of a three-dimensional model obtained by combining two-dimensional models 2Ma shown in Fig. 34 in a simplified notation. The three-dimensional model 3Ma shown in Fig. 36 is a three-dimensional model having nine terminals in three rows and three columns. By combining the two-dimensional models 2Ma shown in Fig. 34, a three-dimensional model having more terminals can be created.

[0094] 36, if we assume that the positive poles are at the same potential and the negative poles are at the same potential, then by combining the two nodes S into one, the three-dimensional model can be folded back into a two-dimensional model. In other words, the two-dimensional model can be converted into a three-dimensional model, and conversely, the three-dimensional model can be converted back into a two-dimensional model.

[0095] 37 to 40 are diagrams showing an example of a three-dimensional model having 12 terminals in three rows and four columns. The impedances Z1, Z2, and Z3 of the unit cell of the two-dimensional model are combined according to the symbols with the numbers "1", "2", and "3" in each rectangle shown in FIG. 37. In that case, as shown in FIG. 38, seven impedances Z1, two impedances Z2, and eight impedances Z3 are required. The three-dimensional model shown in FIG. 39 is obtained by combining the impedances Z1, Z2, and Z3 shown in FIG. 38. In the three-dimensional model shown in FIG. 39, the number N1 of impedances Z1 is "7", the number N2 of impedances Z2 is "2", and the number N3 of impedances Z3 is "8", as shown in FIG. 40.

[0096] Overall impedance Z total The identity that is satisfied is the above-mentioned equation (11). In other words, the reciprocal of the total impedance is the sum of the reciprocals of each of the impedances Z1, Z2, and Z3.

[0097] In addition, as for the three-dimensional model shown in Figure 39, if we assume that the positive electrodes are at the same potential and the negative electrodes are at the same potential, the three-dimensional model can be folded and converted into a two-dimensional model by combining the two nodes S into one.

[0098] (Schematic Symbol) Next, a procedure for converting into circuit diagram symbols will be described. Fig. 41 to Fig. 43 are diagrams for explaining a procedure for converting a three-dimensional model into circuit diagram symbols. Referring to Fig. 41, cells constituting the three-dimensional model can be classified into cells Ca arranged inside, cells Cb arranged at ends other than the corners, and cells Cc arranged at the corners.

[0099] Referring to Figure 42, the impedance Z of the equivalent circuit model in the table u1 , impedance Z u2 In contrast, the internal cell Ca has eight terminals for connecting with adjacent cells. Cell Ca has an impedance of 2Z u2 " and impedance "Z u1 ". The cell Ca also has a terminal T for connection to an external terminal.

[0100] Cell Cb, which is located at the end other than the corner, has six terminals for connecting with adjacent cells. Cell Cb has an impedance of (4 / 3)Z u2 " and impedance "2Z u2 " and impedance "Z u1 ". Cell Cb also has a terminal T for connection to an external terminal.

[0101] The cell Cc located at the corner has four terminals for connecting with the adjacent cells. The cell Cc has an impedance of (4 / 3)Z u2 " and impedance "(2 / 3)Z u2 " and impedance "Z u1 ". The cell Cc also has a terminal T for connection to an external terminal.

[0102] (Example of symbols) The equivalent circuit model of a multi-terminal capacitor can be represented by symbols. Figure 43 is a table showing examples of symbols that represent the equivalent circuit model of a multi-terminal capacitor.

[0103] Figure 43 shows symbols for cells of two types of poles, positive pole P and negative pole N. Item (a) in Figure 43 is a symbol for an interior cell of the array, i.e. a non-corner and non-end cell. Item (b) in Figure 43 is a symbol for an end cell, not a corner. Item (c) in Figure 43 is a symbol for a corner cell.

[0104] In FIG. 43, the symbol of the positive electrode P is composed of a white rectangle RE0, a rectangle RE1 arranged in the upper right of the rectangle RE0, a line segment H1 extending from the rectangle RE1 to the lower left of the rectangle RE0, a black rectangle TS arranged outside the rectangle RE0, and a line segment TSS connecting the rectangle RE0 and the rectangle TS. The black rectangle TS indicates a terminal connected to an adjacent cell. In item (a) of FIG. 43, the rectangle TS is eight, indicating that the cell has eight terminals. In item (b) of FIG. 43, the rectangle TS is six, indicating that the cell has six terminals. In item (c) of FIG. 43, the rectangle TS is four, indicating that the cell has four terminals.

[0105] In FIG. 43, the symbol of the negative electrode N is composed of a white rectangle RE0, a rectangle RE2 arranged in the lower left of the rectangle RE0, a line segment H2 extending from the rectangle RE2 toward the upper right of the rectangle RE0, a black rectangle TS arranged outside the rectangle RE0, and a line segment TSS connecting the rectangle RE0 and the rectangle TS. The black rectangle TS indicates a terminal connected to an adjacent cell. In item (a) of FIG. 43, the rectangle TS is eight, indicating that it has eight terminals. In item (b) of FIG. 43, the rectangle TS is six, indicating that it has six terminals. In item (c) of FIG. 43, the rectangle TS is four, indicating that it has four terminals.

[0106] FIG. 43 shows an example of setting symbols divided into lattice-shaped areas, and other symbols may be used.

[0107] Fig. 44 is a diagram showing an example of a three-dimensional model with a terminal arrangement of 3 rows and 3 columns. In the three-dimensional model shown in Fig. 44, impedances Z provided between each terminal T are represented by rectangles.

[0108] Fig. 45 is a diagram showing an example of a part model expressed using the symbols shown in Fig. 43. Fig. 45 shows a part model expressed using the symbols shown in Fig. 43 for the three-dimensional model in Fig. 44. The three-dimensional model in Fig. 44 and the part model in Fig. 45 are equivalent. Therefore, by expressing the part model using the symbols shown in Fig. 43, the three-dimensional model in Fig. 44 can be converted into the part model in Fig. 45.

[0109] As described with reference to Figs. 43 to 45, by setting symbols corresponding to elements constituting a multi-terminal capacitor, editing of a circuit diagram in a circuit simulator, such as changing the terminal arrangement, becomes easy. For example, it is easy to change from a multi-terminal capacitor 1a with a terminal arrangement of 3 rows and 3 columns shown in Fig. 45 to a multi-terminal capacitor 1b with a terminal arrangement of 3 rows and 5 columns shown in Fig. 46. Fig. 46 is a diagram showing a multi-terminal capacitor with a terminal arrangement of 3 rows and 5 columns. The multi-terminal capacitor 1b shown in Fig. 46 has 15 terminals T1 to T15. In this example, the impedance of the symbol corresponding to the terminal T4 is evenly distributed to the symbol of the terminal T10 and the symbol of the terminal T13, the impedance of the symbol corresponding to the terminal T5 is evenly distributed to the symbol of the terminal T11 and the symbol of the terminal T14, and the impedance of the symbol corresponding to the terminal T6 is evenly distributed to the symbol of the terminal T12 and the symbol of the terminal T15. In this way, it is possible to change from the multi-terminal capacitor 1a with a terminal arrangement of 3 rows and 3 columns to the multi-terminal capacitor 1b with a terminal arrangement of 3 rows and 5 columns.

[0110] FIG. 47 is a diagram showing an equivalent circuit of the substrate 10a including the multi-terminal capacitor 1 described with reference to FIG. 6. In FIG. 47, the multi-terminal capacitor 1a is expressed by the symbols described with reference to FIG. 43. In the multi-terminal capacitor 1a of FIG. 47, the terminals T2, T5, T7, and T9 corresponding to the four symbols corresponding to the positive pole are electrically connected to the positive pole PO11 of the port PO1 and the positive pole PO21 of the port PO2. The terminals T1, T3, T4, T6, and T8 corresponding to the five symbols corresponding to the negative pole are electrically connected to a reference potential, for example, a ground. A resistor RA is electrically connected between the positive pole PO11 and the negative pole PO12. A resistor RB is electrically connected between the positive pole PO21 and the negative pole PO22. By connecting as in FIG. 47, an S parameter for impedance evaluation based on the shunt-through method can be obtained for the multi-terminal capacitor 1a.

[0111] Fig. 48 is a diagram showing an example of a simulation result of S parameters. In Fig. 48, the horizontal axis indicates frequency [Hz], and the vertical axis indicates S parameter values ​​[dB]. Fig. 48 shows S11 and S21 among the S parameters. S11 is a value obtained by dividing the power reflected from port PO1 by the power incident on port PO1. S21 is a power gain when the impedance of the power supply and the load is set to 50Ω.

[0112] (Example of application of multi-terminal capacitor) FIG. 49 is a diagram for explaining an example of a simulation in the time domain. In this example, power is supplied from a DC power supply 20 to a load 30 via a substrate 10. A voltage Vdc of the DC power supply 20 is applied to the load 30 via the substrate 10. In this example, a current source Idc is provided that is connected in parallel to the load 30. The connections of the resistive element and the inductive element, and the connections of the resistive element, the inductive element and the capacitive element in FIG. 49 are equivalent circuits of the substrate 10. The load 30 is, for example, a semiconductor chip such as a controller or a processor.

[0113] Fig. 50 is a diagram showing changes in the current value of the current source Idc in Fig. 49. In Fig. 50, the horizontal axis represents the rise time Ti of the current value, and the vertical axis represents the amplitude Ai.

[0114] Fig. 51 is a diagram showing an example of changes in load voltage. In Fig. 51, the horizontal axis is time [ns] and the vertical axis is voltage [V]. The dashed line in Fig. 51 shows voltage V0 when multi-terminal capacitor 1a is not provided. The solid line in Fig. 51 shows voltage V1 when multi-terminal capacitor 1a is provided.

[0115] 49 to 51, the operation of the load 30 may cause the current value of the current source Idc to increase or the load voltage to drop. For example, as shown in FIG. 51, the load voltage may drop and then change to rise. Even in such a case, the fluctuation in the load voltage can be reduced or suppressed by charging and discharging the multi-terminal capacitor 1a provided on the substrate 10. As shown in FIG. 51, the voltage V1 when the multi-terminal capacitor 1a is provided fluctuates less than the voltage V0 when the multi-terminal capacitor 1a is not provided.

[0116] (Simulation device) Fig. 52 is a diagram showing a configuration example of a simulation device of the present disclosure. The simulation device 100 shown in Fig. 52 is a simulation device equipped with a program for calculating the characteristics of a multi-terminal capacitor or the characteristics of a circuit to which a multi-terminal capacitor is connected. In Fig. 52, the simulation device includes an input unit 101, a calculation unit 102, an output unit 103, a storage unit 104, and a storage unit 105.

[0117] Data such as conditions for setting an equivalent circuit model is input through the input unit 101. The input unit 101 includes, for example, a keyboard and a mouse.

[0118] The calculation unit 102 executes a program based on the data input by the input unit 101. The calculation unit 102 includes, for example, a CPU (Central Processing Unit).

[0119] The output unit 103 displays the calculation results from the calculation unit 102, the waveforms of characteristics from a simulator, etc. The output unit 103 is realized by, for example, a display device.

[0120] The storage unit 104 stores data of an equivalent circuit model. The data of the equivalent circuit model stored in the storage unit 104 is, for example, data of a multi-terminal capacitor 1a shown in FIG. 27 or data of a multi-terminal capacitor 1b shown in FIG. 28. The storage unit 105 stores a program for executing a simulator. The simulator stored in the storage unit 105 calculates the characteristics of a multi-terminal capacitor or the characteristics of a circuit to which a multi-terminal capacitor is connected. The storage units 104 and 105 may be realized by a magnetic disk device or a semiconductor memory.

[0121] 52, data input from an input unit 101 and data of an equivalent circuit model are stored in a storage unit 104. A calculation unit 102 executes a program stored in a storage unit 105 to start a simulator. The calculation unit 102 performs calculations using the simulator. An output unit 103 outputs the waveform of characteristics obtained as a result of the calculations of the calculation unit 102 in a format such as a graph display.

[0122] The simulation device shown in FIG. 52 is provided with a program for calculating the characteristics of a multi-terminal capacitor or the characteristics of a circuit to which a multi-terminal capacitor is connected. By using a simulation device provided with data and a program of an equivalent circuit model capable of calculating the characteristics of a multi-terminal capacitor, it is possible to efficiently and accurately design a circuit for an electronic device using a multi-terminal capacitor. This provides an efficient design environment for designers. In addition, by providing a simulation device that simplifies the operation of displaying the characteristics of a multi-terminal capacitor and comparing the characteristics, it is possible to make the part selection work of a designer more efficient. For example, when a desired multi-terminal capacitor is constructed by a user's operation on a Web page, the S-parameters of the multi-terminal capacitor can be measured, and an element for realizing the waveform of the frequency characteristic of the S-parameter can be selected, and an equivalent circuit model corresponding to the above waveform can be created by combining the selected elements. Then, the created equivalent circuit model of the multi-terminal capacitor can be used to calculate the characteristics of the multi-terminal capacitor or the characteristics of a circuit including the multi-terminal capacitor.

[0123] That is, the simulation device shown in FIG. 52 is a device that calculates the characteristics of a multi-terminal capacitor or the characteristics of a circuit including a multi-terminal capacitor by using an equivalent circuit model of a multi-terminal capacitor created by using the above-mentioned equivalent circuit model creation method. This simulation device can realize a simulation method that calculates the characteristics of a multi-terminal capacitor or the characteristics of a circuit including a multi-terminal capacitor by using an equivalent circuit model of a multi-terminal capacitor created by using the above-mentioned equivalent circuit model creation method. The characteristics of a multi-terminal capacitor and the characteristics of a circuit having a multi-terminal capacitor, such as a circuit to which a multi-terminal capacitor is connected, can be evaluated by various methods such as the frequency domain and the time domain. By providing various equivalent circuit models of a multi-terminal capacitor as a library, the characteristics of a multi-terminal capacitor can be evaluated in a simulation environment specified by a user. In addition, by providing a dedicated simulation device, input operations such as model setting and output operations such as graph display are facilitated, improving user convenience.

[0124] (Equivalent circuit model creation program) A program for executing the equivalent circuit model creation method described with reference to Fig. 1 may be created and executed by a computer. This program is an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which positive external electrode terminals and negative external electrode terminals are arranged in a staggered manner so that adjacent terminals have different polarities, and causes a computer to execute the following steps: a first step of measuring S parameters of the multi-terminal capacitor, a second step of deriving an impedance of the entire multi-terminal capacitor based on measured values ​​of the S parameters measured in the first step, a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step, a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step, a fifth step of combining an equivalent circuit model of a parasitic component based on capacitive and inductive circuit elements with the equivalent circuit model of the unit cell derived in the fourth step to create a three-dimensional lattice topology, and a sixth step of setting terminals of the multi-terminal capacitor at nodes of the three-dimensional lattice topology created in the fifth step. This equivalent circuit model creation program is stored, for example, in the storage unit 105 in Fig. 52. This equivalent circuit model creation program is read out from the storage unit 105 and executed, for example, by the calculation unit 102 in Fig. 52. Note that this equivalent circuit model creation program may be stored in a storage medium that is removable from the computer. For example, the equivalent circuit model creation program may be stored in a USB flash drive (Universal Serial Bus flash drive), that is, a so-called USB memory.

[0125] (summary) According to the above method, it is possible to create an equivalent circuit model of a multi-terminal capacitor in which the external electrode terminals are arranged in a grid pattern. In addition, it is possible to arrange the rows of positive and negative electrodes of the external electrode terminals in a striped pattern, alternating in parallel. Furthermore, the impedance of the multi-terminal capacitor is derived from the measured values ​​of two-port S parameters when mounted on a board. Since a two-port measurement method is used instead of a multi-port method, the man-hours required for measurement and evaluation can be reduced.

[0126] In addition, a two-terminal equivalent circuit model can be created by fitting processing based on the derived overall impedance. The impedance of a unit cell can be derived from the overall impedance based on the periodic structure of the lattice-like equivalent circuit model. A two-dimensional lattice-like topology is created by combining the unit cell equivalent circuit model and the wiring equivalent circuit model as circuit elements, and an overall equivalent circuit model can be created by setting terminals at the nodes of the lattice. This makes it possible to create an equivalent circuit model with a topology corresponding to the structure of a multi-terminal capacitor. In addition, the amount of calculations required for circuit simulation can be reduced by repeatedly using the characteristics of the unit cell. Furthermore, a SPICE model with high accuracy and low calculation costs in both the time domain and the frequency domain can be provided. [Explanation of symbols]

[0127] 1, 1a, 1b Multi-Terminal Capacitor 1c, 10, 10a board 11 Jig 100 Simulation device 101 Input section 102 Arithmetic section 103 Output section 104, 105 Storage section

Claims

1. 1. A method for creating an equivalent circuit model of a multi-terminal capacitor having positive external electrode terminals and negative external electrode terminals arranged in a staggered manner so that adjacent terminals have different polarities, comprising: a first step of measuring S-parameters of the multi-terminal capacitor; A second step of deriving an impedance of the entire multi-terminal capacitor based on the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining an equivalent circuit model of a parasitic component due to capacitive and inductive circuit elements with the equivalent circuit model of the unit cell derived in the fourth step to create a three-dimensional lattice topology; A sixth step of setting terminals of the multi-terminal capacitor at nodes of the three-dimensional lattice topology created in the fifth step; The present invention relates to a method for creating an equivalent circuit model.

2. 2. The method for creating an equivalent circuit model according to claim 1, wherein in the third step, the two-terminal equivalent circuit model is created by a fitting process for bringing simulation values ​​closer to measured values ​​of the S parameters.

3. 3. The method for creating an equivalent circuit model according to claim 2, wherein in the fitting process, the two-terminal equivalent circuit model is created by successively connecting circuit elements so as to match the measured values ​​of the S parameters.

4. 4. The method for creating an equivalent circuit model according to claim 1, wherein in the fourth step, in order to divide the circuit into K unit cells connected in a matrix, resistance values ​​and induction values ​​are multiplied by K and capacitance values ​​are multiplied by 1 / K to allocate the resistance values ​​to the unit cells.

5. 5. The method for creating an equivalent circuit model according to claim 4, wherein in said fourth step, impedance values ​​of K unit cells connected in a matrix are multiplied by weighting coefficients according to locations of said unit cells in the matrix.

6. 6. The method for creating an equivalent circuit model according to claim 5, wherein in the fourth step, the unit cells are arranged on the periphery of the matrix, and if there is an extended portion of an electrode corresponding to the unit cell, a weighting coefficient is set taking the extended portion into consideration.

7. 2. The method for creating an equivalent circuit model according to claim 1, wherein in the first step, the S parameters are measured using a jig having a substrate on which the multi-terminal capacitor is mounted.

8. 1. An equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which positive external electrode terminals and negative external electrode terminals are arranged in a staggered manner so that adjacent terminals have different polarities, On the computer, a first step of measuring S-parameters of the multi-terminal capacitor; A second step of deriving an impedance of the entire multi-terminal capacitor based on the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining an equivalent circuit model of a parasitic component due to capacitive and inductive circuit elements with the equivalent circuit model of the unit cell derived in the fourth step to create a three-dimensional lattice topology; A sixth step of setting terminals of the multi-terminal capacitor at nodes of the three-dimensional lattice topology created in the fifth step; An equivalent circuit model creation program for executing the above.

9. A storage medium storing an equivalent circuit model creation program for creating an equivalent circuit model of a multi-terminal capacitor having a configuration in which positive external electrode terminals and negative external electrode terminals are arranged in a staggered manner so that adjacent terminals have different polarities, On the computer, a first step of measuring S-parameters of the multi-terminal capacitor; A second step of deriving an impedance of the entire multi-terminal capacitor based on the S-parameters measured in the first step; a third step of creating a two-terminal equivalent circuit model from the impedance of the entire multi-terminal capacitor derived in the second step; a fourth step of deriving an equivalent circuit model of a unit cell from the two-terminal equivalent circuit model created in the third step; a fifth step of combining an equivalent circuit model of a parasitic component due to capacitive and inductive circuit elements with the equivalent circuit model of the unit cell derived in the fourth step to create a three-dimensional lattice topology; A sixth step of setting terminals of the multi-terminal capacitor at nodes of the three-dimensional lattice topology created in the fifth step; A storage medium storing an equivalent circuit model creation program for executing the above.

10. 2. A simulation method for calculating characteristics of a multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor, by using an equivalent circuit model of the multi-terminal capacitor created by using the equivalent circuit model creation method according to claim 1.

11. 2. A simulation device that uses an equivalent circuit model of a multi-terminal capacitor created by using the equivalent circuit model creation method according to claim 1 to calculate characteristics of the multi-terminal capacitor or characteristics of a circuit including the multi-terminal capacitor.

Images