Delay compensation circuit and driver circuit

Abstract

The purpose of the present invention is to make a delay correction circuit more compact.　This delay correction circuit is provided with a standard delay circuit, a phase comparator, a delay adjustment unit, and a standard delay circuit power source unit. The standard delay circuit generates a standard delay duration to serve as a standard delay duration of a signal for a signal delay circuit that delays that signal. The phase comparator compares the phases of that signal as delayed by the signal delay circuit and that signal as delayed by the standard delay circuit. The delay adjustment unit adjusts the delay duration of that signal delay circuit on the basis of phase comparison results. The standard delay circuit power source unit supplies power to the standard delay circuit.

Description

[Technical field]

[0001] The present disclosure relates to a delay correction circuit and a drive circuit, and more particularly to a delay correction circuit that corrects a delay time of a delay circuit and a drive circuit that uses the delay correction circuit. [Background technology]

[0002] Conventionally, devices that drive a light source such as a laser diode at a predetermined timing are used, such as distance measuring devices that measure the distance to an object. In these distance measuring devices, the distance to the object is measured by timing the time it takes for light to travel back and forth between the object and the light source. Specifically, light is output by driving the light source of the distance measuring device. This light is reflected by the object and becomes reflected light. This reflected light is detected by an optical sensor of the distance measuring device. The time from the output of this light to the detection of the reflected light is measured, and the distance is calculated. In such distance measuring devices, it is necessary to adjust the timing at which the light source is driven. This is to synchronize the output of light and the operation of detecting the reflected light. In order to adjust the timing at which the light source is driven, a delay circuit is used that delays the drive signal of the light source by a predetermined period.

[0003] The delay time of this delay circuit needs to be strictly controlled in order to improve the accuracy of distance measurement. The delay time can be controlled by correcting the delay time. For example, a distance measuring system is used that includes a circuit that sets the delay time of each delay element of a delay circuit that is configured by cascading multiple delay elements (see, for example, Patent Document 1).

[0004] In this distance measuring system, the drive timing is corrected by first and second delay time control circuits that control the delay time of the drive signal. The delay times of the first and second delay time control circuits are managed to a predetermined delay time by a delay locked loop circuit. To prevent changes in the delay time of the delay locked loop circuit due to environmental fluctuations, the delay time is corrected by a reference clock signal. This correction is performed by aligning the delay time of the delay locked loop circuit to the period of the reference clock signal using a DLL (Delay Locked Loop). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2013-200186 A Summary of the Invention [Problem to be solved by the invention]

[0006] The above-mentioned conventional technology has a problem of increasing the circuit size. The DLL is provided with a phase comparator that detects the phase difference between a reference clock signal and a reference clock signal that has passed through a delay locked loop circuit, and a low-pass filter that passes low-frequency signals from the output signal of the phase comparator. This low-pass filter is made up of passive elements such as a capacitor, and is configured to occupy a relatively large area. For this reason, the above-mentioned conventional technology delay compensation circuit has a problem of increasing the circuit size.

[0007] The present disclosure has been made in consideration of the above-mentioned problems, and aims to reduce the size of a delay correction circuit. [Means for solving the problem]

[0008] The present disclosure has been made to solve the above-mentioned problems, and a first aspect thereof is a delay correction circuit comprising: a reference delay circuit that generates a reference delay time that serves as a basis for the delay time of a signal of a signal delay circuit that delays a signal; a phase comparator that compares the phase of the signal delayed by the signal delay circuit with the phase of the signal delayed by the reference delay circuit; a delay adjustment unit that adjusts the delay time of the signal delay circuit based on the phase comparison result; and a reference delay circuit power supply unit that supplies power to the reference delay circuit.

[0009] In the first aspect, the reference delay circuit power supply section may include a temperature compensation power supply whose output voltage changes based on a predetermined temperature coefficient.

[0010] In addition, in this first aspect, the reference delay circuit power supply section may further include a temperature coefficient selection section that selects the predetermined temperature coefficient.

[0011] In addition, in this first aspect, the reference delay circuit power supply section may further include a temperature coefficient holding section that holds a selection result in the temperature coefficient selection section.

[0012] In this first aspect, the signal delay circuit may include a plurality of delay circuits having different delay times, and the delay adjustment section may adjust the delay times of the plurality of delay circuits.

[0013] In addition, in this first aspect, an adjustment result storage unit may be further provided which stores the adjustment result of the delay in the delay adjustment unit.

[0014] In addition, in the first aspect, a reference delay adjustment unit that adjusts the reference delay time may be further provided.

[0015] In addition, in the first aspect, a reference delay adjustment result holding unit may be further provided, which holds a result of adjustment of the reference delay time in the reference delay adjustment unit.

[0016] In this first aspect, the reference delay adjustment section may adjust the reference delay time to a middle delay time of the signal delay circuit.

[0017] Also, a second aspect of the present disclosure is a drive circuit including a signal delay circuit that delays a drive signal, a reference delay circuit that generates a reference delay time that serves as a basis for the delay time of the drive signal, a phase comparator that compares the phase of the drive signal delayed by the signal delay circuit with the phase of the drive signal delayed by the reference delay circuit, a delay adjustment unit that adjusts the delay time of the signal delay circuit based on the phase comparison result, and a reference delay circuit power supply unit that supplies power to the reference delay circuit.

[0018] According to the aspect of the present disclosure, an effect is achieved in that the delay time of the signal delay circuit is adjusted by the reference delay circuit to which power is supplied from the reference delay circuit power supply unit, and it is assumed that the power supply from the reference delay circuit power supply unit to the signal delay circuit is reduced. [Brief description of the drawings]

[0019] [Figure 1] 1 is a diagram illustrating a configuration example of a light source device according to a first embodiment of the present disclosure. [Diagram 2] 2 is a diagram illustrating a configuration example of a first signal delay circuit according to an embodiment of the present disclosure. [Diagram 3] FIG. 4 is a diagram illustrating a configuration example of a second signal delay circuit according to an embodiment of the present disclosure. [Figure 4] 4 is a diagram illustrating an example of a configuration of a light emission drive signal generating unit according to an embodiment of the present disclosure. FIG. [Diagram 5] 5A and 5B are diagrams illustrating a configuration example of a drive unit according to an embodiment of the present disclosure. [Figure 6] FIG. 4 is a diagram illustrating an example of driving a light source according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is a diagram illustrating a configuration example of a delay correction circuit according to an embodiment of the present disclosure. [Figure 8] 1 is a diagram illustrating a configuration example of a reference delay circuit according to an embodiment of the present disclosure; [Figure 9]1 is a diagram illustrating an example of a configuration of a reference delay circuit power supply unit according to an embodiment of the present disclosure; [Figure 10] FIG. 11 is a diagram illustrating an example of a calibration process according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram illustrating an example of an adjustment process according to an embodiment of the present disclosure. [Figure 12] 6 is a diagram illustrating an example of the configuration of a light source device according to a second embodiment of the present disclosure. [Figure 13] 1 is a diagram showing an example configuration of an imaging device related to a distance measuring device to which the technology according to the present disclosure can be applied; [Figure 14] 1 is a diagram illustrating an example of the configuration of a light receiving element in a distance measuring device to which the technology according to the present disclosure can be applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Next, a mode for carrying out the present disclosure (hereinafter, referred to as an embodiment) will be described with reference to the drawings. In the following drawings, the same or similar parts are given the same or similar reference numerals. The embodiment will be described in the following order. 1. First embodiment 2. Second embodiment 3. Application to distance measuring devices

[0021] <1. First embodiment> [Light source configuration] 1 is a diagram showing a configuration example of a light source device according to a first embodiment of the present disclosure. The diagram shows a configuration example of a light source device 4. The light source device 4 includes a light source 41 and a drive circuit .

[0022] The light source 41 emits light and may be formed of, for example, a laser diode.

[0023] The drive circuit 42 is a circuit that drives the light source 41. The drive circuit 42 drives the light source 41 by supplying a light-emitting current to the light source 41. The light-emitting current is a current that flows through the light source 41 to make the light source 41 emit light. The drive circuit 42 drives the light source 41 based on a drive signal supplied from an external circuit. The drive signal is supplied via a differential transmission line composed of two lines. In the differential transmission line, drive signals of opposite phases are transmitted by two signal lines. For example, LVDS (Low Voltage Differential Signaling) can be adopted as an interface for this differential signal.

[0024] The drive circuit 42 includes a receiving section 600 , a first signal delay circuit 200 , a second signal delay circuit 300 , a light emission drive signal generating section 400 , a drive section 500 , and a delay correction circuit 100 .

[0025] The receiving unit 600 receives the drive signal. The receiving unit 600 receives the drive signal that has been converted into a differential signal and transmitted. The receiving unit 600 converts the received drive signal into a single-ended drive signal and outputs it to the first signal delay circuit 200 and the light emission drive signal generating unit 400. The receiving unit 600 also receives a calibration signal, which will be described later, and outputs it to the first signal delay circuit 200, etc.

[0026] The first signal delay circuit 200 is a circuit that delays the drive signal output from the receiving unit 600 by a predetermined delay time. The first signal delay circuit 200 outputs the delayed drive signal to the second signal delay circuit 300. The delay time of the first signal delay circuit 200 is adjusted by an adjustment signal output from a delay correction circuit 100 described below. The delay time of the first signal delay circuit 200 is longer than the delay time of the second signal delay circuit 300 described next. Therefore, the resolution of the delay time during adjustment is small. The adjustment of the delay time in the first signal delay circuit 200 corresponds to a coarse adjustment. The configuration of the first signal delay circuit 200 will be described in detail later.

[0027] The second signal delay circuit 300 is a circuit that delays the drive signal output from the first signal delay circuit 200 by a predetermined delay time. This second signal delay circuit 300 outputs the delayed drive signal to the light emission drive signal generating unit 400. The delay time of the second signal delay circuit 300 is adjusted by an adjustment signal output from a delay correction circuit 100 described later. The delay time of the second signal delay circuit 300 is shorter than the delay time of the first signal delay circuit 200, and has a higher resolution. The adjustment of the delay time in the second signal delay circuit 300 corresponds to fine adjustment. The second signal delay circuit 300 outputs two drive signals (delay drive signal 1 and delay drive signal 2 described later) with different delay times. The configuration of the second signal delay circuit 300 will be described later in detail.

[0028] The light emission drive signal generating unit 400 generates a light emission drive signal from the drive signal output from the receiving unit 600 and the second signal delay circuit 300. Here, the light emission drive signal is a drive signal for an element of the drive unit 500, which will be described later. The drive signal generated by the light emission drive signal generating unit 400 is output to the drive unit 500 and the delay correction circuit 100. The configuration of the light emission drive signal generating unit 400 will be described in detail later.

[0029] The driving section 500 supplies a driving current to the light source 41. The driving section 500 supplies the driving current based on the light emission driving signal generated by the light emission driving signal generating section 400. The configuration of the driving section 500 will be described in detail later.

[0030] The delay correction circuit 100 corrects the delay times of the first signal delay circuit 200 and the second signal delay circuit 300. The delay correction circuit 100 includes a reference delay circuit (a reference delay circuit 110 described later) that generates a reference delay time that serves as a reference for the delay time, and adjusts the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 by comparing the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 with the delay time of the reference delay circuit 110.

[0031] Specifically, the delay correction circuit 100 generates a calibration signal for adjusting the delay time, and inputs the calibration signal to the first signal delay circuit 200 via the receiving unit 600. After that, the light emission drive signal generated by the light emission drive signal generating unit 400 based on the drive signal delayed by the first signal delay circuit 200 and the second signal delay circuit 300 is input to the delay correction circuit 100. Meanwhile, the delay correction circuit 100 generates a calibration signal delayed by the reference delay time by inputting the calibration signal to its own reference delay circuit 110. Then, the delay correction circuit 100 compares the input light emission drive signal with the delayed calibration signal, and adjusts the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 to synchronize the light emission drive signal with the delayed calibration signal. This allows the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 to be adjusted to the reference delay time.

[0032] Hereinafter, the process of adjusting the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 will be referred to as an adjustment process. The adjustment of the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 is performed by adjustment signals outputted individually. The configuration of the delay correction circuit 100 will be described in detail later. The drive signal is an example of a signal described in the claims.

[0033] [Configuration of the first signal delay circuit] 2 is a diagram showing a configuration example of a first signal delay circuit according to an embodiment of the present disclosure. The diagram shows a configuration example of a first signal delay circuit 200. The first signal delay circuit 200 in the diagram includes an inverting gate 201, a delay unit 210, a delay unit 220, a delay unit 230, a delay unit 240, a delay unit 250, a delay unit 260, a delay unit 270, and a delay unit 280, and a selection unit 290.

[0034] Inverting gate 201 is a gate that inverts the drive signal output from receiving unit 600. The drive signal output from receiving unit 600 will hereinafter be referred to as "drive signal'". The output of inverting gate 201 is input in common to delay unit 210, delay unit 220, delay unit 230, delay unit 240, delay unit 250, delay unit 260, delay unit 270 and delay unit 280.

[0035] Delay unit 210, delay unit 220, delay unit 230, delay unit 240, delay unit 250, delay unit 260, delay unit 270 and delay unit 280 are circuits that delay the drive signal'. These delay units 210 and the like are configured by the same circuit and are connected in cascade. That is, the output of delay unit 210 is connected to the input of delay unit 220, and the output of delay unit 220 is connected to the input of delay unit 230. The connections are made in the following order, and the output of delay unit 280 becomes the output of the first signal delay circuit 200 and is connected to the second signal delay circuit 300. The input of delay unit 210 is grounded and a value of "0" is input thereto.

[0036] The circuit configuration will be described by taking the delay unit 210 as an example. The delay unit 210 includes two-input NOR gates 211 and 212 and an inverting gate 213. Signal line 209 and signal line 291a are connected to the inputs of the NOR gate 211. Here, the signal line 209 is a signal line that transmits the output signal of the inverting gate 201 described above. An inverted driving signal' is input from the signal line 209 to the NOR gate 211. The signal line 291a is a signal line that transmits a selection signal from the selection unit 290 described later. The output of the NOR gate 211 and signal line 219 are connected to the inputs of the NOR gate 212. Note that the signal line 219 corresponds to the input node of the delay unit 210, and is a node to which the output signal of the previous delay unit is input. As described above, the signal line 219 is grounded and a value "0" is input. The output of the NOR gate 212 is connected to the input of the inverting gate 213, and the output of the inverting gate 213 is connected to a signal line 229. The signal line 229 corresponds to the output node of the delay unit 210 and also to the input node of the delay unit in the next stage. The delay time per stage by the delay unit 210 etc. is the sum of the delay times of the NOR gate and the inverting gate, and is 100 to 150 ps.

[0037] The selection unit 290 selects one of the delay units 210, etc., based on an adjustment signal from the delay correction circuit 100. The selection unit 290 selects the delay units 210, etc., by outputting a selection signal to one of a plurality of signal lines 291. The selection unit 290 adjusts the delay time of the first signal delay circuit 200 by selecting the delay unit 210, etc. The selection unit 290 selects the delay unit 210, etc., by outputting a value of "0" to the signal line 291 connected to the selected delay unit 210, etc., and outputting a value of "1" to the other delay units 210, etc.

[0038] The operation of the first signal delay circuit 200 will be described by taking the case where the delay unit 210 is selected as an example. The selection unit 290 outputs a value of "0" to the signal line 291a. As a result, the inverted drive signal' input via the signal line 209 is further inverted and output to the output of the NOR gate 211. Since the value "0" is input to the other input of the two-input NOR gate 212 via the signal line 219, the inverted drive signal' is output to the output of the NOR gate 212. This inverted drive signal' is inverted again by the inverting gate 213 and output to the signal line 229, and input to the delay unit 220. Since the value "1" is output to the signal line 291b of the delay unit 220 from the selection unit 290, the output of the NOR gate 221 of the delay unit 220 becomes a value of "0", and the drive signal' input to the delay unit 220 is output to the next-stage delay unit 230 via the NOR gate 222 and the inverting gate 223. Thereafter, the drive signal' is transmitted in order from delay unit 230 to delay unit 280. In this case, eight stages of delay time can be obtained.

[0039] When the delay unit 220 is selected, a value "0" is output to the signal line 291b. The driving signal' passes through the NOR gate 221 of the delay unit 220. On the other hand, the delay unit 210 that is not selected outputs the signal of the signal line 219 to the signal line 229. Since the value "0" is input to the signal line 219, the delay unit 210 outputs the value "0" to the signal line 229. The value "0" is input to the input node of the delay unit 220, and is input to the NOR gate 222. Therefore, the driving signal' is transmitted from the delay unit 220 to the delay unit 280. The delay time is 7 stages. In this way, the delay time of the first signal delay circuit 200 can be adjusted according to the position of the delay unit 210 selected by the selection unit 290.

[0040] For example, a 3-bit digital signal can be used as the adjustment signal from the delay compensation circuit 100. The delay compensation circuit 100 sets the number of delay stages in the first signal delay circuit 200 by using this 3-bit adjustment signal. The delay unit 210 or the like corresponding to this number of delay stages is selected by the selection unit 290. This allows the delay time of the first signal delay circuit 200 to be adjusted by the delay compensation circuit 100. For example, the selection unit 290 can select the delay unit 210 when an adjustment signal with a value of "0" is input, and select the delay unit 280 when an adjustment signal with a value of "7" is input. In this case, when a medium delay time is set in the first signal delay circuit 200, an adjustment signal with a value of "4" is input to the selection unit 290. Here, the medium delay time corresponds to a delay time that is approximately half the maximum delay time that can be set in the first signal delay circuit 200 or the like.

[0041] [Configuration of the second signal delay circuit] 3 is a diagram showing a configuration example of a second signal delay circuit according to an embodiment of the present disclosure. The diagram shows a configuration example of the second signal delay circuit 300. Note that A in the diagram shows a circuit diagram of the second signal delay circuit 300, and B in the diagram shows a circuit diagram showing a configuration example of a delay unit used in the second signal delay circuit 300.

[0042] The second signal delay circuit 300 shown in A in the figure includes a delay unit 310, a delay unit 320, a delay unit 330, a delay unit 340, a delay unit 350, a delay unit 360, a delay unit 370, and a delay unit 380, as well as a selection unit 390.

[0043] The delay unit 310, the delay unit 320, the delay unit 330, the delay unit 340, the delay unit 350, the delay unit 360, the delay unit 370, and the delay unit 380 are circuits that delay the drive signal' output from the first signal delay circuit 200. As with the above-mentioned delay unit 210, the delay units 310 are configured with the same circuit and are connected in cascade. The delay units 310 are configured with an inverting gate that can change the delay time. A signal line 391 for transmitting a selection signal from the selection unit 390 is wired to each of the delay units 310. The delay time of the delay units 310 is changed by this selection signal. For example, a configuration can be adopted in which the delay unit 310 to which a selection signal of value "1" is input has a long delay time, and the delay unit 310 to which a selection signal of value "0" is input has a short delay time.

[0044] The output of the delay section 380 becomes the output of the second signal delay circuit 300, which outputs a delayed drive signal 2, which is a signal obtained by delaying the drive signal' output from the first signal delay circuit 200 by all the delay sections 310, etc. The second signal delay circuit 300 further outputs a delayed drive signal 1, which is a signal delayed by some of the delay sections 310, etc. The delayed drive signal 1 can be obtained from the output of a delay section in the middle stage among the cascaded delay sections 310, etc. In the same figure, A shows an example in which the delayed drive signal 1 is generated from the output of the delay section 340.

[0045] The selection unit 390 selects the delay units 310 etc. based on the adjustment signal from the delay correction circuit 100. The selection unit 390 selects the delay units 310 etc. by outputting a selection signal to a plurality of signal lines 391. The selection unit 390 adjusts the delay time of the second signal delay circuit 300 by selecting the delay units 310 etc. The selection unit 390 can output a value of "0" as a selection signal. In this case, the selection unit 390 outputs a value of "1" to the non-selected delay units 310 etc. The delay units 310 etc. to which the value of "0" is input as a selection signal change to a shorter delay time. Therefore, the delay time of the second signal delay circuit 300 can be adjusted according to the number of delay units 310 etc. to be selected.

[0046] For example, a 3-bit digital signal can be used as the adjustment signal from the delay compensation circuit 100. The delay compensation circuit 100 sets the number of delay stages in the second signal delay circuit 300 using this 3-bit adjustment signal, and the delay unit 310 etc. corresponding to this delay stage are selected by the selection unit 390. This allows the delay time of the second signal delay circuit 300 to be adjusted by the delay compensation circuit 100. For example, the selection unit 390 can deselect all the delay units 310 etc. (output a value of "1") when an adjustment signal of value "0" is input, and select all the delay units 310 (output a value of "0") when an adjustment signal of value "7" is input. In this case, when a medium delay time is set in the second signal delay circuit 300, an adjustment signal of value "4" is input to the selection unit 390.

[0047] In the figure, B is a circuit diagram showing the configuration of the delay unit 310 and the like. The delay unit 310 will be described as an example. The delay unit 310 includes MOS transistors 311 to 316 and an inverting gate 317. The MOS transistors 311 to 313 can be p-channel MOS transistors. The MOS transistors 314 to 316 can be n-channel MOS transistors. Vdd1 is a power supply line that supplies power to the delay unit 310. Signal lines 319 and 329 are signal lines that correspond to the input node and output node of the delay unit 310, respectively.

[0048] The source of the MOS transistor 311, the source of the MOS transistor 312, and the gate of the MOS transistor 315 are connected to Vdd1. The source of the MOS transistor 315, the source of the MOS transistor 316, and the gate of the MOS transistor 311 are grounded. The drain of the MOS transistor 311 is connected to the drain of the MOS transistor 312 and the source of the MOS transistor 313. The gate of the MOS transistor 312 and the input of the inverting gate 317 are commonly connected to a signal line 391. The output of the inverting gate 317 is connected to the gate of the MOS transistor 316. The drain of the MOS transistor 316 is connected to the drain of the MOS transistor 315 and the source of the MOS transistor 314. The gate of the MOS transistor 313 and the gate of the MOS transistor 314 are commonly connected to a signal line 319. The drain of the MOS transistor 313 and the drain of the MOS transistor 314 are commonly connected to a signal line 329.

[0049] The MOS transistors 313 and 314 constitute an inverter. The inverter consisting of the MOS transistors 313 and 314 is supplied with a power supply voltage via the MOS transistors 311 and 312 connected in parallel, and is grounded via the MOS transistors 315 and 316 connected in parallel. The gate of the MOS transistor 311 is grounded, and the gate of the MOS transistor 315 is connected to Vdd1, so that the MOS transistors 311 and 315 are turned on. On the other hand, a selection signal is input to the gate of the MOS transistor 312 via a signal line 391, and a selection signal is input to the gate of the MOS transistor 316 via an inverting gate 317. Therefore, when a selection signal of value "0" is input, the MOS transistors 312 and 316 are turned on. When the MOS transistors 312 and 316 are turned on, the power supply voltage supplied to the inverter consisting of the MOS transistors 313 and 314 rises, and the gm of the MOS transistors 313 and 314 becomes high. Therefore, the MOS transistors 313 and 314 operate at high speed, and the delay time becomes short. This makes it possible to shorten the delay time of one delay section 310 by approximately 10 ps.

[0050] [Configuration of the light emission drive signal generation unit] 4 is a diagram showing a configuration example of a light emission drive signal generating unit according to an embodiment of the present disclosure. The figure is a circuit diagram showing a configuration example of a light emission drive signal generating unit 400. The light emission drive signal generating unit 400 in the figure includes an inverting gate 401, a two-input AND gate 402, a two-input OR gate 403, and non-inverting buffers 405 to 407.

[0051] The non-inverting buffers 405 to 407 are buffers that output light emission drive signals. The non-inverting buffers 405 to 407 are buffers that supply signals to the gates of MOS transistors in the drive section, which will be described later. The non-inverting buffer 405 outputs light emission drive signal 3, the non-inverting buffer 406 outputs light emission drive signal 2, and the non-inverting buffer 407 outputs light emission drive signal 1. The light emission drive signal 1 is a drive signal for causing a light emission current to flow through the light source 41. The light emission drive signal 2 is a drive signal for causing a bias current to flow through the light source 41. The light emission drive signal 3 is a drive signal for making the rise of the light emission current of the light source 41 steeper.

[0052] A signal obtained by performing a logical AND operation on an inverted delayed drive signal 2 and delayed drive signal 1 is input to the input of non-inverting buffer 405. A signal obtained by performing a logical OR operation on delayed drive signal 1 and drive signal' is input to the input of non-inverting buffer 406. Delayed drive signal 1 is input to the input of non-inverting buffer 407. Light emission drive signals 1 and 3 are output to drive unit 500. Furthermore, light emission drive signal 2 is output to drive unit 500 and to phase comparator 140 of delay correction circuit 100 described later.

[0053] [Drive configuration] FIG. 5 is a diagram showing a configuration example of a driving unit according to an embodiment of the present disclosure. The figure is a circuit diagram showing a configuration example of a driving unit 500. The driving unit 500 in the figure includes MOS transistors 501 to 505 and constant current circuits 506 and 507. The figure also shows a light source 41. The light source 41 in the figure is assumed to be a laser diode. Vdd2 in the figure is a power supply line that supplies power to the MOS transistors 501 to 503. Also, Vcc is a power supply line that supplies power to the light source 41. The MOS transistors 501 to 505 can be n-channel MOS transistors.

[0054] A light emission drive signal 1 is input to the gate of the MOS transistor 504. The drain of the MOS transistor 504 is connected to the source of the MOS transistor 503, and the source of the MOS transistor 504 is grounded. A light emission drive signal 2 is input to the control terminal of the constant current circuit 507. The source terminal of the constant current circuit 507 is grounded. The sink terminal of the constant current circuit 507, the drain of the MOS transistor 503, and the drain of the MOS transistor 505 are commonly connected to the cathode of the light source 41. The anode of the light source 41 is connected to Vcc. A light emission drive signal 3 is input to the gate of the MOS transistor 505. The source of the MOS transistor 505 is grounded. The gate of the MOS transistor 503 is connected to the gate of the MOS transistor 501, the drain of the MOS transistor 501, and the source terminal of the constant current circuit 506. The sink terminal of the constant current circuit 506 and the gate of the MOS transistor 502 are connected to Vdd2. The source of the MOS transistor 502 is grounded, and the drain of the MOS transistor 502 is connected to the source of the MOS transistor 501 .

[0055] The MOS transistor 504 is a MOS transistor that passes a light emission current to the light source 41. 5 04 is controlled by a light emission drive signal 1. The light emission current is a current for emitting laser light of a desired intensity, and is determined by a MOS transistor 503 connected in series to a MOS transistor 504. The MOS transistors 503 and 501 are connected as a current mirror, and a current equal to the current supplied by a constant current circuit 506 flows through the MOS transistor 503. Therefore, the light emission current is determined by the current of the constant current circuit 506. The MOS transistor 502 is a MOS transistor arranged to align the source potential of the MOS transistor 501 with the source potential of the MOS transistor 503.

[0056] The constant current circuit 507 is a circuit that supplies a bias current to the light source 41. The constant current circuit 507 has a control terminal, and the bias current is turned on and off by the light emission drive signal 2 input to the control terminal. The bias current is a current that is less than the light emission threshold of the light source 41, and is a current that is passed in order to speed up the response of the light source 41.

[0057] The MOS transistor 505 is a MOS transistor that passes an auxiliary drive current. Here, the auxiliary drive current is a current that is superimposed on the light emission current and makes the rise of the light emission current steeper. An inductance component exists in the wiring of the light source 41. This inductance component slows the rise of the light emission current. Therefore, by applying a relatively high voltage to the light source 41 during the rise period of the light emission current to pass the auxiliary drive current, it is possible to compensate for the delay in the rise caused by the inductance component. The auxiliary drive current can be passed by grounding the cathode of the light source 41 using the MOS transistor 505.

[0058] [Drive circuit operation] FIG. 6 is a diagram showing an example of driving a light source according to an embodiment of the present disclosure. The figure shows an example of driving a light source 41 in a driving circuit 42, and shows the relationship between a driving signal and a light emission current of the light source 41. In the figure, "drive signal", "delayed drive signal 1", "delayed drive signal 2", "light emission drive signal 1", "light emission drive signal 2" and "light emission drive signal 3" show binarized signal waveforms. The period of the drive signal value "1" corresponds to the period during which a light emission current flows to the light source 41. Also, "current of light source 41" in the figure shows the waveform of a current flowing through a laser diode constituting the light source 41.

[0059] The drive signal in the figure is delayed by a first signal delay circuit 200 and a second signal delay circuit 300 to generate delayed drive signals 1 and 2. The light emission drive signal generation unit 400 generates light emission drive signals 1 to 3 with the pulse widths shown in the figure using delayed drive signals 1 and 2 and the drive signal, and supplies them to the drive unit 500.

[0060] When the light emission drive signal 2 becomes "1", the constant current circuit 507 described in FIG. 5 operates and a bias current flows. Next, when the light emission drive signal 1 becomes "1", the MOS transistor 504 becomes conductive and the light emission current starts to flow. At this time, the light emission drive signal 3 becomes "1", the MOS transistor 505 described in FIG. 5 becomes conductive and the auxiliary drive current flows, shortening the rise time of the light emission current. The dashed line in the figure represents the current of the light source 41 when the auxiliary drive current is not flowing. Due to the influence of the inductance component of the wiring of the light source 41, the rise of the light emission current is delayed.

[0061] When the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 change, the delay times of the light emission drive signals 1 to 3 relative to the drive signal change, and the delay time of the light emission of the light source 41 changes. This results in a decrease in the accuracy of the distance measurement. It becomes necessary to adjust the changed delay times of the first signal delay circuit 200, etc.

[0062] [Configuration of delay compensation circuit] 7 is a diagram showing a configuration example of a delay correction circuit according to an embodiment of the present disclosure. The diagram shows a configuration example of a delay correction circuit 100. The delay correction circuit 100 in the diagram includes a reference delay circuit 110, a reference delay circuit power supply unit 120, a phase comparator 140, a delay adjustment unit 150, a calibration signal generation unit 160, a reference delay adjustment unit 170, an adjustment result holding unit 180, and a reference delay adjustment result holding unit 190.

[0063] The calibration signal generating section 160 generates a calibration signal. A rectangular wave with a predetermined pulse width can be used as the calibration signal. When adjusting the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 to the reference delay time, the calibration signal generating section 160 generates a calibration signal and outputs it to the reference delay circuit 110 and the receiving section 600 described in FIG. 1.

[0064] The reference delay circuit 110 is a circuit that generates a reference delay time that is a reference for the delay time of the delay circuit arranged in the drive circuit 42. The reference delay circuit 110 in the figure generates a reference delay time for the first signal delay circuit 200 and the second signal delay circuit 300. Specifically, the reference delay circuit 110 outputs a calibration signal that is delayed by the reference delay time with respect to the calibration signal input from the calibration signal generating unit 160. This reference delay circuit 110 can be configured, for example, in the same manner as the first signal delay circuit 200 described in FIG. 2. Details of the configuration of the reference delay circuit 110 will be described later.

[0065] The reference delay circuit power supply unit 120 is a circuit that supplies power to the reference delay circuit 110. The reference delay circuit power supply unit 120 can be configured with a stabilized power supply whose output voltage is calibrated. For example, a band gap reference power supply can be used for this stabilized power supply. By using a stabilized power supply, it is possible to reduce the variation in the power supply voltage for each device, and the variation in the reference delay time for each device can be reduced. In addition, by using a stabilized power supply, it is also possible to reduce the variation in the power supply voltage due to changes in the environmental temperature. When the power supply voltage changes, the delay unit 210 of the first signal delay circuit 200 and the like changes gm, and the delay time changes. The reference delay circuit 110, which has a configuration similar to that of the first signal delay circuit 200, also changes its delay time due to the variation in the power supply voltage. Therefore, by arranging the reference delay circuit power supply unit 120 and supplying a power supply with small voltage variation to the reference delay circuit 110, it is possible to reduce the variation in the delay time of the reference delay circuit 110.

[0066] Also, a power supply whose voltage changes based on a predetermined temperature coefficient can be arranged in the reference delay circuit power supply unit 120. The delay time of the delay unit 210 of the first signal delay circuit 200 increases as the temperature rises. Therefore, by increasing the power supply voltage when the temperature rises, the change in the delay time can be compensated for. By arranging a power supply having a positive temperature coefficient in the reference delay circuit power supply unit 120, the variation in the delay time of the reference delay circuit 110 can be further reduced. The configuration of the reference delay circuit power supply unit 120 will be described in detail later.

[0067] The phase comparator 140 detects a phase difference by comparing the output signal of the reference delay circuit 110 with the light emission drive signal 2. The light emission drive signal 2 is a signal that has passed through all the delay units 310 of the first signal delay circuit 200 and the second signal delay circuit 300. By inputting a calibration signal to the first signal delay circuit 200 via the receiving unit 600, the calibration signal delayed by the first signal delay circuit 200 and the second signal delay circuit 300 is input to the phase comparator 140 as the light emission drive signal 2. The light emission drive signal 2 and the calibration signal delayed by the reference delay circuit 110 are compared by the phase comparator 140. The comparison result by the phase comparator 140 is output to the delay adjustment unit 150 and the reference delay adjustment unit 170. A known phase comparator can be used for the phase comparator 140.

[0068] The delay adjustment section 150 generates an adjustment signal and outputs it to each of the first signal delay circuit 200 and the second signal delay circuit 300. Furthermore, during adjustment processing of the first signal delay circuit 200 and the second signal delay circuit 300, the delay adjustment section 150 generates an adjustment signal based on the comparison result of the phase comparator 140 and adjusts the delay times of the first signal delay circuit 200 and the second signal delay circuit 300.

[0069] This adjustment can be performed as follows based on the comparison result from the phase comparator 140. When the light emission drive signal 2 lags the output signal of the reference delay circuit 110, the delay adjustment unit 150 shortens the delay times of the first signal delay circuit 200 and the second signal delay circuit 300. Specifically, the adjustment signal of the first signal delay circuit 200 is set to a lower value, and the adjustment signal of the second signal delay circuit 300 is set to a lower value. Also, when the light emission drive signal 2 leads the output signal of the reference delay circuit 110, the delay adjustment unit 150 lengthens the delay times of the first signal delay circuit 200 and the second signal delay circuit 300. Specifically, the adjustment signals of the first signal delay circuit 200 and the second signal delay circuit 300 are set to a higher value. This process is repeated until the output signal of the reference delay circuit 110 and the light emission drive signal 2 are synchronized, thereby making the adjustment possible. This makes it possible to make the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 equal to the reference delay time.

[0070] The adjustment result holding unit 180 holds the adjustment results of the first signal delay circuit 200 and the second signal delay circuit 300 after adjustment by the delay adjustment unit 150. The adjustment result holding unit 180 can be configured, for example, by a memory that holds the value of the adjustment signal after adjustment. After the adjustment process, the delay adjustment unit 150 transfers the adjustment results of the first signal delay circuit 200 and the second signal delay circuit 300 to the adjustment result holding unit 180 to hold them. In addition, the adjustment result holding unit 180 can supply the held adjustment results to the delay adjustment unit 150. The delay adjustment unit 150 can generate an adjustment signal based on the adjustment result supplied from the adjustment result holding unit 180 and output it to the first signal delay circuit 200 and the second signal delay circuit 300.

[0071] The reference delay adjustment section 170 generates and outputs an adjustment signal for the reference delay circuit 110. Furthermore, the reference delay adjustment section 170 controls the calibration signal generation section 160 and the delay adjustment section 150 during the above-mentioned adjustment processing.

[0072] Moreover, the reference delay adjustment unit 170 further adjusts the reference delay time. The reference delay adjustment unit 170 adjusts the reference delay time by adjusting the delay time of the reference delay circuit 110. Hereinafter, the process of adjusting the delay time of the reference delay circuit 110 is referred to as a calibration process. The calibration process can be performed as follows. First, the reference delay adjustment unit 170 controls the delay adjustment unit 150 to output an adjustment signal, and sets the first signal delay circuit 200 and the second signal delay circuit 300 to a medium delay time. Next, the reference delay adjustment unit 170 causes the calibration signal generation unit 160 to output a calibration signal, and acquires a comparison result from the phase comparator 140. Next, the reference delay adjustment unit 170 generates an adjustment signal based on the comparison result from the phase comparator 140, and adjusts the delay time of the reference delay circuit 110. The delay time of the reference delay circuit 110 is adjusted until the delay time of the reference delay circuit 110 becomes equal to the medium delay time of the first signal delay circuit 200 and the second signal delay circuit 300. This allows the calibration process to be performed.

[0073] The reference delay adjustment result holding unit 190 holds the adjustment result of the reference delay circuit 110 after adjustment by the reference delay adjustment unit 170. This reference delay adjustment result holding unit 190 can be configured by a memory that holds the value of the adjustment signal after adjustment, similar to the adjustment result holding unit 180. After the calibration process, the reference delay adjustment unit 170 transfers the adjustment result of the reference delay circuit 110 to the reference delay adjustment result holding unit 190 to hold it. In addition, the reference delay adjustment result holding unit 190 can supply the held adjustment result to the reference delay adjustment result holding unit 190. During the above-mentioned adjustment process, the reference delay adjustment unit 170 can generate an adjustment signal based on the adjustment result supplied from the reference delay adjustment result holding unit 190 and output it to the reference delay circuit 110.

[0074] [Reference delay circuit configuration] 8 is a diagram showing a configuration example of a reference delay circuit according to an embodiment of the present disclosure. The diagram shows a configuration example of a reference delay circuit 110. Power is supplied to the reference delay circuit 110 in the diagram from a reference delay circuit power supply unit 120. Vdd3 in the diagram represents a power supply line to which power is supplied from the reference delay circuit power supply unit 120. The reference delay circuit 110 in the diagram also includes an inverting gate 109, delay units 111 to 118, and a selection unit 119.

[0075] Inverting gate 109 in the same figure To A calibration signal generated by the calibration signal generating unit 160 is input to the delay unit 111 etc. in the same figure. The delay unit 111 etc. in the same figure can have the same configuration as the delay unit 210 etc. described in FIG. 2. Also, the inverting gate 109 and the selecting unit 119 in the same figure can have the same configuration as the inverting gate 201 and the selecting unit 290 described in FIG. 2. The delay unit 111 etc. in the same figure differs from the delay unit 210 etc. in FIG. 2 in that power is supplied from the power supply line Vdd3. Since power is supplied from the reference delay circuit power supply unit 120 to the delay unit 111 etc., the variation in delay time is reduced. Other than this, the configuration of the reference delay circuit 110 is the same as that of the first signal delay circuit 200, and therefore a description thereof will be omitted.

[0076] [Reference delay circuit power supply configuration] 9 is a diagram showing a configuration example of a reference delay circuit power supply unit according to an embodiment of the present disclosure. The figure is a circuit diagram showing a configuration example of a reference delay circuit power supply unit 120. The reference delay circuit power supply unit 120 in the figure includes a transistor 122, resistors 124 to 128, a voltage source 121, a constant current circuit 123, a buffer amplifier 136, a temperature coefficient selection unit 130, and a temperature coefficient holding unit 135. An npn transistor can be used for the transistor 122. Note that Vdd4 in the figure is a power supply line that supplies power for operating the reference delay circuit power supply unit 120.

[0077] The collector of the transistor 122 is connected to Vdd4, and the emitter is connected to a sink side terminal of the constant current circuit 123. The source side terminal of the constant current circuit 123 is grounded. The base of the transistor 122 is connected to a high potential terminal of the voltage source 121, and the low potential terminal of the voltage source 121 is grounded. The resistors 124 to 128 connected in series are connected between the base and the emitter of the transistor 122. The multiple signal lines 131 of the temperature coefficient selection unit 130 are connected to both ends of the resistors 124 to 128 connected in series and to the respective nodes where the resistors are connected to each other. In addition, the output of the temperature coefficient selection unit 130 is connected to the input of a buffer amplifier 136, and the output of the buffer amplifier 136 is connected to the reference delay circuit 110 as the output of the reference delay circuit power supply unit 120.

[0078] The voltage source 121 is a voltage source that corresponds to the above-mentioned stabilized power source. This voltage source 121 can be configured, for example, by a bandgap reference power source.

[0079] The constant current circuit 123 is a current source that supplies an emitter current of the transistor 122. The constant current circuit 123 supplies a sink current to the transistor 122.

[0080] The resistors 124 to 128 are resistors that divide the base-emitter voltage Vbe of the transistor 122. The reference delay circuit power supply unit 120 in the figure shows an example in which Vbe is divided by 5. The voltage of Vbe changes with a temperature coefficient of -2 mV / °C. By subtracting this Vbe from the output voltage of the voltage source 121, a power supply circuit in which the voltage changes based on a temperature coefficient of 2 mV / °C can be configured. In addition, by connecting the resistors 124 to 128 for voltage division, the temperature coefficient can be switched between 0 and 2 mV / °C. The circuit formed by the voltage source 121, the transistor 122, the constant current circuit 123, and the resistors 124 to 128 is an example of a temperature-compensated power supply as described in the claims.

[0081] The temperature coefficient selection unit 130 selects the temperature coefficient of the power supply output from the reference delay circuit power supply unit 120. This temperature coefficient selection unit 130 can select the temperature coefficient by selecting one of the signal lines 131, extracting a voltage, and outputting it to the buffer amplifier 136.

[0082] The temperature coefficient holding unit 135 holds the selection result by the temperature coefficient selection unit 130. This temperature coefficient holding unit 135 can hold the selection result by holding the selection result of the signal line 131 by the temperature coefficient selection unit 130. The temperature coefficient selection unit 130 selects the signal line 131 based on the selection result held in the temperature coefficient holding unit 135. The temperature coefficient holding unit 135 can be configured with a memory.

[0083] The buffer amplifier 136 is a buffer that amplifies the power supply voltage output from the temperature coefficient selection section 130 .

[0084] [Proofreading] FIG. 10 is a diagram showing an example of a calibration process according to an embodiment of the present disclosure. First, the reference delay adjustment unit 170 sets the initial values ​​of the adjustment signals of the first signal delay circuit 200, the second signal delay circuit 300, and the reference delay circuit 110 (S101). For the first signal delay circuit 200 and the second signal delay circuit 300, for example, the reference delay adjustment unit 170 can control the delay adjustment unit 150 to output an adjustment signal for a medium delay. As described above, the first signal delay circuit 200 and the second signal delay circuit 300 can be set to a medium delay time by outputting an adjustment signal of value "4". In addition, the reference delay circuit 110 can also be set to output an adjustment signal for a medium delay. The reference delay adjustment unit 170 can set the reference delay circuit 110 to a medium delay time and set the initial value by outputting an adjustment signal of value "4" to the reference delay circuit 110.

[0085] Next, a calibration signal is output (S102). This can be done by the reference delay adjustment unit 170 controlling the calibration signal generation unit 160 to output the calibration signal.

[0086] Next, it is determined whether the adjustment of the reference delay circuit 110 has been completed (S103). This is determined by the reference delay adjustment unit 170 based on the comparison result of the phase comparator 140. If the comparison result of the phase comparator 140 indicates that the phase difference between the output signal of the reference delay circuit 110 and the light emission drive signal 2 output from the light emission drive signal generation unit 400 is greater than a predetermined value, for example, 150 ps, ​​the reference delay adjustment unit 170 can determine that the adjustment of the reference delay circuit 110 has not been completed (S103: No). In this case, the process proceeds to S104.

[0087] On the other hand, if the phase difference between the output signal of the reference delay circuit 110 and the light emission drive signal 2 output from the light emission drive signal generation unit 400 is equal to or less than the above-mentioned predetermined value (150 ps), the reference delay adjustment unit 170 can determine that the adjustment of the reference delay circuit 110 is completed (S103: Yes). In this case, the process proceeds to S105.

[0088] In S104, the reference delay adjustment unit 170 adjusts the delay time of the reference delay circuit 110 (S104). This can be done by changing the adjustment signal of the reference delay circuit 110. When the output signal of the reference delay circuit 110 is in phase with respect to the light emission drive signal 2 output from the light emission drive signal generation unit 400, the reference delay adjustment unit 170 increases the delay time of the reference delay circuit 110. Specifically, the reference delay adjustment unit 170 generates and outputs an adjustment signal of a smaller value. For example, when an adjustment signal of a value "4" that is a medium delay time has been generated, the reference delay adjustment unit 170 generates and outputs an adjustment signal of a value "2" that is an even medium delay time.

[0089] On the other hand, when the output signal of the reference delay circuit 110 is delayed in phase with respect to the light emission drive signal 2 output from the light emission drive signal generation unit 400, the reference delay adjustment unit 170 decreases the delay time of the reference delay circuit 110. Specifically, the reference delay adjustment unit 170 generates and outputs an adjustment signal of a larger value. For example, when an adjustment signal of value "4" has been generated, an adjustment signal of value "5" or "6" is generated and output. Then, the process of S103 is executed again.

[0090] In S105, the reference delay adjustment unit 170 holds the calibration result (S105). This can be done by the reference delay adjustment unit 170 causing the value of the adjustment signal to be held in the reference delay adjustment result holding unit 190. Then, the calibration process ends.

[0091] By the above procedure, it is possible to perform the calibration process in the delay correction circuit 100. This calibration process can be performed during inspection after manufacturing in a factory. It can also be performed after the product is shipped, when the usage environment, such as the place of use, is changed.

[0092] [Adjustment processing] 11 is a diagram showing an example of an adjustment process according to an embodiment of the present disclosure. First, a calibration signal is output (S111). This can be performed by the reference delay adjustment unit 170 controlling the calibration signal generation unit 160 to output the calibration signal.

[0093] Next, it is determined whether the adjustment of the first signal delay circuit 200 has been completed (S112). This is determined by the delay adjustment unit 150 based on the comparison result of the phase comparator 140. If the comparison result of the phase comparator 140 shows that the phase difference between the output signal of the reference delay circuit 110 and the light emission drive signal 2 output from the light emission drive signal generation unit 400 is greater than a predetermined value, for example, 100 ps, ​​the delay adjustment unit 150 can determine that the adjustment of the first signal delay circuit 200 has not been completed (S112: No). In this case, the process proceeds to S113.

[0094] On the other hand, if the phase difference between the output signal of the reference delay circuit 110 and the light emission drive signal 2 output from the light emission drive signal generation unit 400 is equal to or less than the above-mentioned predetermined value (100 ps), the delay adjustment unit 150 can determine that the adjustment of the first signal delay circuit 200 is completed (S112: Yes). In this case, the process proceeds to S114.

[0095] In S113, the delay adjustment unit 150 adjusts the delay time of the first signal delay circuit 200 (S113). This can be done by changing the adjustment signal of the first signal delay circuit 200. When the light emission drive signal 2 is in phase with respect to the output signal of the reference delay circuit 110, the delay adjustment unit 150 increases the delay time of the first signal delay circuit 200. Specifically, the delay adjustment unit 150 generates an adjustment signal of a smaller value and outputs it to the first signal delay circuit 200.

[0096] On the other hand, when the light emission drive signal 2 has a delayed phase with respect to the output signal of the reference delay circuit 110, the delay adjustment unit 150 decreases the delay time of the first signal delay circuit 200. Specifically, the delay adjustment unit 150 generates and outputs an adjustment signal with a larger value. Then, the process of S112 is executed again.

[0097] In S114, it is determined whether the adjustment of the second signal delay circuit 300 has been completed (S114). This is determined by the delay adjustment unit 150 based on the comparison result of the phase comparator 140. If the comparison result of the phase comparator 140 shows that the phase difference between the output signal of the reference delay circuit 110 and the light emission drive signal 2 is greater than a predetermined value, for example, 10 ps, ​​the delay adjustment unit 150 can determine that the adjustment of the second signal delay circuit 300 has not been completed (S114: No). In this case, the process proceeds to S115.

[0098] On the other hand, if the phase difference between the output signal of the reference delay circuit 110 and the light emission drive signal 2 is equal to or less than the above-mentioned predetermined value (10 ps), the delay adjustment unit 150 can determine that the adjustment of the second signal delay circuit 300 is completed (S114: Yes). In this case, the process proceeds to S116.

[0099] In S115, the delay adjustment unit 150 adjusts the delay time of the second signal delay circuit 300 (S115). This can be done by changing the adjustment signal of the second signal delay circuit 300. When the light emission drive signal 2 is in phase with respect to the output signal of the reference delay circuit 110, the delay adjustment unit 150 increases the delay time of the second signal delay circuit 300. Specifically, the delay adjustment unit 150 generates an adjustment signal of a smaller value and outputs it to the second signal delay circuit 300. For example, when an adjustment signal of a value "4" that is a medium delay time has been generated, the delay adjustment unit 150 generates and outputs an adjustment signal of a value "2" that is an even more medium delay time.

[0100] On the other hand, when the light emission drive signal 2 has a delayed phase with respect to the output signal of the reference delay circuit 110, the delay adjustment unit 150 decreases the delay time of the second signal delay circuit 300. Specifically, the delay adjustment unit 150 generates an adjustment signal of a larger value and outputs it to the second signal delay circuit 300. For example, when an adjustment signal of value "4" has been generated, an adjustment signal of value "5" or "6" which is an intermediate delay time is further generated and output. Then, the process of S114 is executed again.

[0101] In S116, the delay adjustment unit 150 holds the adjustment result (S116). This can be done by the delay adjustment unit 150 causing the value of the adjustment signal to be held in the adjustment result holding unit 180. Thereafter, the adjustment process ends.

[0102] The above procedure allows the adjustment process in the delay correction circuit 100 to be performed. Among these, the process (S112) of adjusting the first signal delay circuit 200 corresponds to a coarse adjustment of the delay time in the drive circuit 42. The process (S114) of adjusting the second signal delay circuit 300 corresponds to a fine adjustment of the delay time in the drive circuit 42. By arranging the first signal delay circuit 200 and the second signal delay circuit 300, each having a different delay time, in this way and performing the coarse adjustment and the fine adjustment individually, the accuracy of the delay time adjustment can be improved and the time required for the adjustment can be shortened.

[0103] As described above, the reference delay circuit power supply unit 120 is provided to supply a highly stabilized power supply to the reference delay circuit 110, thereby reducing the variation in the delay time of the reference delay circuit 110. The reference delay circuit 110 is used to adjust the delay times of the first signal delay circuit 200 and the second signal delay circuit 300, thereby reducing the variation in the delay times of the first signal delay circuit 200 and the second signal delay circuit 300. It is also possible to reduce the variation in the delay times of the first signal delay circuit 200 and the like by providing a high-performance power supply circuit similar to the reference delay circuit power supply unit 120 to the first signal delay circuit 200 and the second signal delay circuit 300. However, in this case, the circuit scale of the drive circuit 42 becomes large. In order to prevent deterioration of the waveform of the drive signal to be transmitted, the first signal delay circuit 200 and the second signal delay circuit 300 must be configured with a high-speed circuit. This is because such a high-speed circuit consumes a lot of power and requires a large-capacity power supply circuit.

[0104] As described above, the delay correction circuit 100 according to the first embodiment of the present disclosure adjusts the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 by matching the delay times of the first signal delay circuit 200 and the second signal delay circuit 300 with the delay time of the reference delay circuit 110. This allows the delay correction circuit 100 to be miniaturized.

[0105] <2. Second embodiment> The driving circuit 42 of the first embodiment described above uses the first signal delay circuit 200 and the second signal delay circuit 300. In contrast, the driving circuit 42 of the second embodiment of the present disclosure differs from the first embodiment described above in that it uses a plurality of first signal delay circuits 200 and second signal delay circuits 300.

[0106] [Light source configuration] Fig. 12 is a diagram showing a configuration example of a light source device according to a second embodiment of the present disclosure. Similar to Fig. 1, this diagram shows a configuration example of a light source device 4. This differs from the light source device 4 described in Fig. 1 in that two sets of a first signal delay circuit 200 and a second signal delay circuit 300 are arranged in each of the drive circuits 42.

[0107] The driving circuit 42 in the figure is different from the driving circuit 42 in FIG. 1 in that it includes first signal delay circuits 200a and 200b and second signal delay circuits 300a and 300b. The first signal delay circuit 200a and the second signal delay circuit 300a generate the delayed driving signal 1 described in FIG. 6. That is, the delayed driving signal 1 is generated by delaying the driving signal'. On the other hand, the first signal delay circuit 200b and the second signal delay circuit 300b generate the delayed driving signal 2 described in FIG. 6. That is, the delayed driving signal 2 is generated by delaying the driving signal'. Therefore, even if the delay times of the delayed driving signals 1 and 2 are significantly different, these signals can be generated.

[0108] The delay compensation circuit 100 in the figure generates and outputs adjustment signals for the first signal delay circuits 200a and 200b and the second signal delay circuits 300a and 300b. During the adjustment process, the delay compensation circuit 100 adjusts the first signal delay circuit 200a and the second signal delay circuit 300a and adjusts the first signal delay circuit 200b and the second signal delay circuit 300b separately.

[0109] Other than this, the configuration of the light source device 4 is similar to the configuration of the light source device 4 described in the first embodiment of the present disclosure, and therefore a description thereof will be omitted.

[0110] As described above, the light source device 4 according to the second embodiment of the present disclosure includes two sets of the first signal delay circuit 200 and the second signal delay circuit 300, and adjusts the delay time of each delay circuit by one reference delay circuit 110. This makes it possible to reduce an increase in the circuit scale of the drive circuit 42.

[0111] <3. Application to distance measuring device> The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be applied to a distance measuring device. Here, the distance measuring device is a device that measures the distance to an object.

[0112] [Configuration of imaging device] 13 is a diagram showing a configuration example of an imaging device related to a distance measuring device to which the technology according to the present disclosure can be applied. The figure is a block diagram showing a configuration example of an imaging device 1 constituting a distance measuring device. The imaging device 1 in the figure includes a light receiving element 2, a control unit 3, a light source device 4, and a lens 5. Note that the figure shows an object 901 for distance measurement.

[0113] The lens 5 is a lens that forms an image of an object on the light receiving element 2. The configuration of the light receiving element 2 will be described later.

[0114] The light source device 4 emits light to an object for distance measurement. For this light source device 4, for example, a laser light source that emits infrared light can be used.

[0115] The control unit 3 controls the entire imaging device 1. Specifically, the control unit 3 controls the light source device 4 to emit emitted light 902 to the object 901, and notifies the light receiving element 2 of the start of the emission. The light receiving element 2, which has been notified of the emission of the emitted light 902, detects reflected light 903 from the object 901, measures the time from the emission of the emitted light 902 to the detection of the reflected light 903, and measures the distance to the object 901. This measured distance is output to the outside of the imaging device 1 as distance data.

[0116] [Photodetector configuration] 14 is a diagram showing an example of the configuration of a light receiving element in a distance measuring device to which the technology disclosed herein can be applied. The light receiving element 2 in the figure includes a pixel array section 21, a bias power supply section 25, and a light receiving signal processing section 26.

[0117] The pixel array section 21 is configured by arranging a plurality of pixels 22 having a photoelectric conversion section that performs photoelectric conversion of incident light in a two-dimensional lattice pattern. The pixels 22 detect the incident light and output a light reception signal as a detection result. For example, an APD (Avalanche Photo Diode) or a SPAD (Single Photon Avalanche Diode) can be used as the photoelectric conversion section. Hereinafter, it is assumed that a SPAD is arranged as the photoelectric conversion section in the pixel 22. Signal lines 23 and 24 are connected to each pixel 22. The signal line 23 is a signal line that supplies a bias voltage to the pixel 22. The signal line 24 is a signal line that transmits a light reception signal from the pixel 22. Note that, in the pixel array section 21 of the same figure, an example in which the pixels 22 are arranged in 4 rows and 5 columns is described, but the number of pixels 22 arranged in the pixel array section 21 is not limited.

[0118] The bias power supply unit 25 is a power supply that supplies a bias voltage to the pixels 22. The bias power supply unit 25 supplies the bias voltage via the signal line .

[0119] The light receiving signal processing unit 26 processes the light receiving signals output from the multiple pixels 22 arranged in the pixel array unit 21. The processing of the light receiving signal processing unit 26 corresponds to, for example, processing to detect the distance to an object based on incident light detected by the pixels 22. Specifically, the light receiving signal processing unit 26 can perform distance detection processing of a ToF (Time of Flight) method used when measuring the distance to a distant object in an imaging device such as an in-vehicle camera. This distance detection processing is processing to detect the distance by irradiating light to the object using a light source arranged in the imaging device, detecting the light reflected by the object, and measuring the time it takes for the light from the light source to travel back and forth between the object and the object. A SPAD capable of high-speed light detection is used for such a device that performs distance detection processing.

[0120] The technology according to the present disclosure can also be applied to devices other than distance measuring devices, for example, to a delay circuit for varying the sampling timing of an analog-to-digital converter.

[0121] Finally, the above-mentioned embodiments are merely examples of the present disclosure, and the present disclosure is not limited to the above-mentioned embodiments. Therefore, even if the embodiments are different from the above-mentioned embodiments, various modifications can be made depending on the design, etc., as long as they do not deviate from the technical idea of ​​the present disclosure.

[0122] In addition, the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0123] In addition, the drawings in the above-mentioned embodiments are schematic, and the dimensional ratios of the various parts do not necessarily correspond to the actual ones. In addition, the drawings may include parts whose dimensional relationships and ratios differ from one another.

[0124] The processing procedures described in the above embodiments may be regarded as a method having a series of procedures, or as a program for causing a computer to execute the series of procedures or a recording medium for storing the program. For example, a CD (Compact Disc), a DVD (Digital Versatile Disc), a memory card, etc. may be used as the recording medium.

[0125] The present technology can also be configured as follows. (1) a reference delay circuit that generates a reference delay time that is a reference for a delay time of a signal in a signal delay circuit that delays the signal; a phase comparator for comparing the phase of the signal delayed by the signal delay circuit with the phase of the signal delayed by the reference delay circuit; a delay adjustment unit that adjusts a delay time of the signal delay circuit based on a result of the phase comparison; a reference delay circuit power supply unit for supplying power to the reference delay circuit; A delay compensation circuit comprising: (2) The delay correction circuit according to (1), wherein the reference delay circuit power supply unit includes a temperature compensation power supply whose output voltage changes based on a predetermined temperature coefficient. (3) The delay correction circuit according to (2), wherein the reference delay circuit power supply unit further includes a temperature coefficient selection unit that selects the predetermined temperature coefficient. (4) The delay correction circuit according to (3), wherein the reference delay circuit power supply unit further includes a temperature coefficient holding unit that holds a selection result in the temperature coefficient selection unit. (5) The signal delay circuit includes a plurality of delay circuits each having a different delay time; The delay adjustment unit adjusts the delay times of the plurality of delay circuits. A delay correction circuit according to any one of (1) to (4). (6) The delay correction circuit according to any one of (1) to (5), further comprising an adjustment result holding unit that holds the delay adjustment result in the delay adjustment unit. (7) The delay correction circuit according to any one of (1) to (6), further comprising a reference delay adjustment unit that adjusts the reference delay time. (8) The delay correction circuit according to (7), further comprising a reference delay adjustment result holding unit that holds an adjustment result of the reference delay time in the reference delay adjustment unit. (9) The delay correction circuit according to (7), wherein the reference delay adjustment unit adjusts the reference delay time to a middle delay time of the signal delay circuit. (10) a signal delay circuit that delays the drive signal; a reference delay circuit that generates a reference delay time that is a reference for the delay time of the drive signal; a phase comparator that compares the phase of the drive signal delayed by the signal delay circuit with the phase of the drive signal delayed by the reference delay circuit; a delay adjustment unit that adjusts a delay time of the signal delay circuit based on a result of the phase comparison; a reference delay circuit power supply unit for supplying power to the reference delay circuit; A drive circuit comprising: [Explanation of symbols]

[0126] 1. Imaging device 2 Light receiving element 4 Light source device 41 Light source 42 Driver circuit 100 Delay compensation circuit 110 Reference Delay Circuit 111~118, 210, 220, 230, 240, 250, 260, 270, 280, 310, 320, 330, 340, 350, 360, 370, 380 Delay section 119, 290, 390 Selection section 120 Reference delay circuit power supply section 121 Voltage Source 122 Transistor 123 Constant current circuit 124~128 Resistance 130 Temperature coefficient selection section 135 Temperature coefficient retention section 136 Buffer Amplifier 140 Phase comparator 150 Delay adjustment unit 160 Calibration signal generation section 170 Reference delay adjustment unit 180 Adjustment result holding section 190 Reference delay adjustment result storage unit 200, 200a, 200b First signal delay circuit 300, 300a, 300b Second signal delay circuit 400 Light emission drive signal generation unit 500 Drive unit 600 Receiver

Claims

1. a reference delay circuit that generates a reference delay time that is a reference for a delay time of a signal in a signal delay circuit that delays the signal; a phase comparator for comparing the phase of the signal delayed by the signal delay circuit with the phase of the signal delayed by the reference delay circuit; a delay adjustment unit that adjusts a delay time of the signal delay circuit based on a result of the phase comparison; a reference delay circuit power supply unit that supplies power to the reference delay circuit; The reference delay circuit power supply unit includes a temperature compensation power supply whose output voltage changes based on a predetermined temperature coefficient, and a temperature coefficient selection unit that selects the predetermined temperature coefficient. Delay compensation circuit.

2. 2. The delay correction circuit according to claim 1, wherein the reference delay circuit power supply section further comprises a temperature coefficient holding section that holds a result of the selection made by the temperature coefficient selection section.

3. the signal delay circuit includes a plurality of delay circuits each having a different delay time; The delay adjustment unit adjusts the delay times of the plurality of delay circuits.

3. The delay correction circuit according to claim 1.

4. 4. The delay correction circuit according to claim 1, further comprising an adjustment result holding section that holds an adjustment result of the delay in the delay adjustment section.

5. a reference delay circuit that generates a reference delay time that is a reference for a delay time of a signal in a signal delay circuit that delays the signal; a phase comparator for comparing the phase of the signal delayed by the signal delay circuit with the phase of the signal delayed by the reference delay circuit; a delay adjustment unit that adjusts a delay time of the signal delay circuit based on a result of the phase comparison; a reference delay circuit power supply unit for supplying power to the reference delay circuit; A reference delay adjustment unit that adjusts the reference delay time, The reference delay adjustment unit adjusts the reference delay time to a medium delay time of the signal delay circuit. Delay compensation circuit.

6. 6. The delay correction circuit according to claim 5, further comprising a reference delay adjustment result holding section for holding an adjustment result of said reference delay time in said reference delay adjustment section.

7. a signal delay circuit that delays the drive signal; a reference delay circuit that generates a reference delay time that is a reference for the delay time of the drive signal; a phase comparator that compares the phase of the drive signal delayed by the signal delay circuit with the phase of the drive signal delayed by the reference delay circuit; a delay adjustment unit that adjusts a delay time of the signal delay circuit based on a result of the phase comparison; a reference delay circuit power supply unit that supplies power to the reference delay circuit; The reference delay circuit power supply unit includes a temperature compensation power supply whose output voltage changes based on a predetermined temperature coefficient, and a temperature coefficient selection unit that selects the predetermined temperature coefficient. Drive circuit.

8. a signal delay circuit that delays the drive signal; a reference delay circuit that generates a reference delay time that is a reference for the delay time of the drive signal; a phase comparator that compares the phase of the drive signal delayed by the signal delay circuit with the phase of the drive signal delayed by the reference delay circuit; a delay adjustment unit that adjusts a delay time of the signal delay circuit based on a result of the phase comparison; a reference delay circuit power supply unit for supplying power to the reference delay circuit; A reference delay adjustment unit that adjusts the reference delay time, The reference delay adjustment unit adjusts the reference delay time to a medium delay time of the signal delay circuit. Drive circuit.

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