Soft error detection device and method

Abstract

This soft error detection device is provided with: a frequency dividing unit 10 which divides an external input clock signal; a code length selection unit 20 which selects a code length for a binary code representing the operating state of the frequency dividing unit 10; a first memory unit 31 which stores prescribed data; a second memory unit 32 which stores different data than the first memory unit 31; a first MUX 41 which selects the data in one of the first memory unit 31 and the second memory unit 32 on the basis of a selected binary code; a third memory unit 33 which stores the same data as the first memory unit 31; a fourth memory unit 34 which stores the same data as the second memory unit 32; a second MUX 42 which selects the data in one of the third memory unit 33 and the fourth memory unit 34 on the basis of the selected binary code; and a soft error detection unit 60 which compares a first output signal output by the first MUX 41 in synchronization with a clock signal and a second output signal output by the second MUX 42 in synchronization with the clock signal, and detects a soft error if the output signals do not match.

Description

[Technical field]

[0001] The present invention relates to a soft error detection device and method for detecting soft errors that occur in electronic equipment due to the incidence of particle radiation. [Background technology]

[0002] Particle radiation is a type of radiation that has particle properties, such as proton beams, alpha rays, and neutron beams. For example, neutrons are produced when cosmic rays raining down from space collide with oxygen or nitrogen in the atmosphere. When these neutrons collide with semiconductor devices (such as memory) in electronic devices, they cause "soft errors," in which stored data is rewritten. In some cases, "soft errors" can have a serious impact on social infrastructure.

[0003] In order to detect the above-mentioned soft errors, a technology is disclosed in, for example, Non-Patent Document 1, which uses an FPGA (Field Programmable Gate Array) to identify the energy of particle radiation that caused the soft error and measures the rate at which soft errors occur for each energy of particle radiation. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Hidenori Iwashita , Gentaro Funatsu, Hirotaka Sato, Takashi Kamiyama, Michihiro Furusaka, Stephen A. Wender, Eric Pitcher, and Yoshiaki Kiyanagi,"Energy-Resolved Soft-Error Rate Measurements for 1-800 MeV Neutrons by the Time-of-Flight Technique at LANSCE", IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 67, NO. 11, NOVEMBER 2020 Summary of the Invention [Problem to be solved by the invention]

[0005] The technology disclosed in Non-Patent Document 1 detects soft errors by rewriting data in a lookup table (corresponding to the memory described above) that determines the circuit configuration of an FPGA. However, only one bit is used for the register that specifies the range of the lookup table. In other words, only a part of the FPGA's lookup table can be used.

[0006] As described above, the conventional technology has a problem in that it does not fully utilize the memory area (semiconductor device) in which soft errors are detected.

[0007] The present invention has been made in view of the above problem, and has an object to provide a soft error detection device and method that can effectively utilize the memory area in which soft errors are detected. [Means for solving the problem]

[0008] A soft error detection device according to one aspect of the present invention detects soft errors caused by the incidence of particle radiation, and includes a frequency division unit that divides a clock signal input from an external source, a code length selection unit that selects a code length of a binary code representing an operating state of the frequency division unit, a first memory unit in which predetermined data is stored, a second memory unit in which data different from that of the first memory unit is stored, a first multiplexer that selects one of the data of the first memory unit and the second memory unit based on the selected binary code, a third memory unit in which the same data as that of the first memory unit is stored, a fourth memory unit in which the same data as that of the second memory unit is stored, a second multiplexer that selects one of the data of the third memory unit and the fourth memory unit based on the selected binary code, and a soft error detection unit that compares a first output signal output by the first multiplexer and a second output signal output by the second multiplexer in synchronization with the clock signal and detects the soft error if there is a mismatch.

[0009] Furthermore, a soft error detection method according to one aspect of the present invention is a soft error detection method performed by the above-mentioned soft error detection device, in which a frequency divider divides a clock signal input from outside, a code length selector selects a code length of a binary code representing an operating state of the frequency divider, a first multiplexer selects, based on the selected binary code, data from either a first memory unit in which predetermined data is stored or a second memory unit in which data different from that of the first memory unit is stored, and a second multiplexer selects, based on the selected binary code, data from either a third memory unit in which the same data as that of the first memory unit is stored or a fourth memory unit in which the same data as that of the second memory unit is stored, and compares a first output signal output by the first multiplexer and a second output signal output by the second multiplexer in synchronization with the clock signal, and detects the soft error if there is a mismatch. Effect of the Invention

[0010] According to the present invention, it is possible to provide a soft error detection device and method that can effectively utilize a memory area in which soft errors are detected. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing an example of a functional configuration of a soft error detection device according to a first embodiment of the present invention. [Diagram 2] 2 is a configuration diagram showing a specific example of a frequency division unit and a code length selection unit shown in FIG. 1. [Diagram 3] 2 is a configuration diagram showing a specific example of a first multiplexer shown in FIG. 1. [Figure 4] 2 is a time chart illustrating an example of the operation of the frequency division unit and the first and second registers illustrated in FIG. 1. [Diagram 5] 10 is a time chart illustrating another example of the operation of the frequency division unit and the first and second registers illustrated in FIG. [Figure 6] FIG. 2 is a diagram showing an example of the relationship between neutron energy and flight time. [Figure 7] FIG. 11 is a block diagram showing an example of the functional configuration of a soft error detection device according to a second embodiment of the present invention. [Figure 8] 2 is a flowchart showing a procedure of a soft error detection method performed by the soft error detection device shown in FIG. [Figure 9] FIG. 13 is a diagram illustrating an example of the relationship between the flight time of a neutron and the probability of occurrence of a logic fault. [Figure 10] FIG. 2 is a diagram showing an example of the relationship between neutron energy and flight time. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same reference characters are used to refer to the same parts, and the description will not be repeated.

[0013] [First embodiment] Fig. 1 is a block diagram showing an example of the functional configuration of a soft error detection device according to a first embodiment of the present invention. The soft error detection device 100 shown in Fig. 1 detects soft errors caused by the incidence of particle radiation.

[0014] Particle radiation refers to radiation that has particle properties (electrons, protons, neutrons), such as beta rays, proton rays, and neutron rays. When particle radiation is incident on a semiconductor device, it can cause the above-mentioned soft errors.

[0015] The soft error detection device 100 includes a frequency division unit 10, a code length selection unit 20, a first memory unit 31, a second memory unit 32, a first multiplexer 41, a third memory unit 33, a fourth memory unit 34, a second multiplexer 42, a first register 51, a second register 52, a soft error detection unit 60, and a memory initialization unit 70.

[0016] The frequency division unit 10 is a frequency division circuit that divides the frequency of the input clock signal, and can be configured with flip-flops. For example, the frequency division unit 10, which is made up of four T-type flip-flops connected in cascade, outputs frequencies obtained by dividing the frequency of the clock signal by 2, 4, 8, and 1 / 16.

[0017] The code length selection unit 20 selects the code length of the binary code representing the operating state of the frequency division unit 10. The code length selection unit 20 outputs the selected binary code with the selected code length. The operating state of the frequency division unit 10 is the state of each flip-flop in the process of dividing the clock signal. The frequency division unit 10, which is made up of four T-type flip-flops cascaded, has 16 operating states, 0 to F, expressed in hexadecimal. The frequency division unit 10 and the code length selection unit 20 will be described in detail later.

[0018] The first memory unit 31 stores predetermined data. The first memory unit 31 is configured, for example, with a RAM, and is set to all "0". The greater the amount of data in the first memory unit 31, the higher the efficiency of detecting "soft errors".

[0019] In other words, the larger the area of ​​the first memory section 31 in the semiconductor device, the easier it is for neutrons to collide with it. Therefore, it is preferable that the amount of data in the first memory section 31 is as large as possible.

[0020] For convenience of explanation, the data amount of the first memory unit 31 will be described as, for example, 8 bits. Note that, in Fig. 1, the data amount can be set to any size by arranging a large number of first memory units 31 in the depth direction of the drawing.

[0021] For example, when 32 first memory units 31 are stacked in the depth direction of Fig. 1 (not shown), the amount of data is 32 x 8 = 256 bits. In this way, the first memory unit 31 can be set to any amount of data by arranging the same configuration in parallel.

[0022] The second memory section 32 stores data different from that stored in the first memory section 31. All data are set to "1" in contrast to all data "0" in the first memory section 31. The other points are the same as those of the first memory section 31.

[0023] The first multiplexer 41 (hereinafter, first MUX 41) selects data from either the first memory unit 31 or the second memory unit 32 based on the selected binary code representing the operating state of the frequency division unit 10 selected by the code length selection unit 20. When the output of the code length selection unit 20 is "0", the first MUX 41 selects the data from the first memory unit 31. When the output of the code length selection unit 20 is "1", the first MUX 41 selects the data from the second memory unit 32.

[0024] Therefore, every time the state of the selected binary code changes, the first MUX 41 alternately selects data from the first memory unit 31 and the second memory unit 32. In this example, the first MUX 41 alternately selects data "0" from the first memory unit 31 and data "1" from the second memory unit 32 in accordance with the state of the selected binary code.

[0025] The third memory section 33 stores the same data as the first memory section 31. The third memory section 33 has the same configuration as the first memory section 31.

[0026] The fourth memory section 34 stores the same data as the second memory section 32. The fourth memory section 34 has the same configuration as the second memory section 32.

[0027] The second multiplexer 42 (hereinafter, second MUX 42) selects data from either the third memory unit 43 or the fourth memory unit 34 based on the selected binary code representing the operating state of the frequency division unit 10 selected by the code length selection unit 20. When the output of the code length selection unit 20 is "0", the second MUX 42 selects data from the third memory unit 43. When the output of the code length selection unit 20 is "1", the second MUX 42 selects data from the fourth memory unit 44.

[0028] In this way, the first memory unit 31 and the third memory unit 33, the second memory unit 32 and the fourth memory unit 34, and the first MUX 41 and the second MUX 42 are all the same. Therefore, when no soft errors occur (when the first memory unit 31 to the fourth memory unit 34 are not changed by neutrons), the first MUX 41 and the second MUX 42 select the same data.

[0029] The first register 51 holds the selection signal (first output signal) of the first MUX 41 in synchronization with the clock signal. The clock signal of the first register 51 is the same as the clock signal input to the frequency division unit 10, and is omitted from FIG.

[0030] The second register 52 holds the selection signal (second output signal) of the second MUX 42 in synchronization with the above clock signal. As with the first register 51, the clock signal of the second register 52 is omitted.

[0031] The soft error detection unit 60 compares the first output signal output by the first MUX 41 and the second output signal output by the second MUX 42 in synchronization with a clock signal, and detects a "soft error" if there is a mismatch. The soft error detection unit 60 is configured, for example, with an exclusive OR (EXOR gate).

[0032] For example, when 32 first memory units 31 are stacked in the depth direction of FIG. 1, 32 first MUXs 41, second MUXs 42, first registers 51, second registers 52, and soft error detection units 60 are also stacked.

[0033] In the following description, it is assumed that the data amount of each of the first memory unit 31 to the fourth memory unit 34 is 8 bits. Also, the first and second MUXes 41 and 42, the first and second registers 51 and 52, and the soft error detection unit 60 will each be described as an example.

[0034] (Divider and code length selector) 2 is a configuration diagram showing a specific example of the frequency division unit 10 and the code length selection unit 20 according to this embodiment. As is clear from the reference numerals, the first and second MUXes 41 and 42 and the first and second registers 51 and 52 shown in FIG. 2 are the same as those in FIG. 1.

[0035] The frequency division unit 10 has, for example, four T-type flip-flops (hereinafter, T-type FFs) connected in series. A clock signal is input to a T terminal of a first-stage T-type FF11, and a Q output of the T-type FF11 is input to a T terminal of a next-stage T-type FF12. A Q output of the T-type FF12 is input to a T terminal of a third-stage T-type FF13, and a Q output of the T-type FF13 is input to a T terminal of a fourth-stage T-type FF14. In this way, the frequency division unit 10 has four T-type FFs 11 to 14 connected in series.

[0036] The code length selection unit 20 is composed of, for example, four logical products (AND gates) that are enabled by the 4-bit control signals S1 to S4, respectively. The control signal S1 is connected to one terminal of the logical product 21, and the other terminal of the logical product 21 is connected to the Q output of the T-type FF 11.

[0037] The logical product 22 to which the Q output of the T-type FF 12 is connected is enabled by the control signal S2. The logical product 23 to which the Q output of the T-type FF 13 is connected is enabled by the control signal S3. The logical product 24 to which the Q output of the T-type FF 14 is connected is enabled by the control signal S4.

[0038] In this way, the code length selection unit 20 outputs a selected binary code whose code length is selected based on the control signals S1 to S4.

[0039] 3 is a configuration diagram showing a specific example of the first MUX 41. The first MUX 41 is composed of 15 MUXs (reference numbers omitted) controlled by the selected binary code output by the code length selection unit 20, and selects each bit of the first memory unit 31 and the second memory unit 32 in accordance with the state of the selected binary code. Each of the four selected binary codes is connected to the input terminals α to Δ of the first MUX 41.

[0040] The input terminals α to Δ of the first MUX 41 are inputs to a 4-input, 1-output address selection circuit. The first MUX 41 selects one bit from each of the bits of the first memory unit 31 and the second memory unit 32 in accordance with the state of the selected binary code (input terminals α to Δ).

[0041] Here, the state represented by 4 bits of the input terminals α to Δ is expressed as 16 states of 0 to F (15). When the state of the input terminals α to Δ is 0 (α=0, β=0, γ0, Δ=0), the first MUX 41 selects the first bit 311 of the first memory unit 31. When the state of the input terminals α to Δ is 1 (α=0, β=0, γ0, Δ=1), the first MUX 41 selects the first bit 321 of the second memory unit 32.

[0042] Similarly, when the state of the input terminals α to Δ is 2 (α=0, β=0, γ1, Δ=0), the second bit 312 of the first memory unit 31 is selected, and when the state is 3 (α=0, β=0, γ1, Δ=1), the second bit 322 of the second memory unit 32 is selected. Omitted in between, when the state is 14 (α=1, β=1, γ1, Δ=0), the eighth bit 318 of the first memory unit 31 is selected, and when the state is 15 (α=1, β=1, γ1, Δ=1), the eighth bit 328 of the second memory unit 32 is selected.

[0043] The above-described operation of the first MUX 41 is also the same for the second MUX 42. However, the second MUX 42 is different in that it selects one bit from each bit of the third memory section 33 and the fourth memory section 34.

[0044] Fig. 4 is a time chart showing the selected binary code output by the code length selection unit 20, the selection signal of the first MUX 41, and the selection signal of the second MUX 42. The horizontal direction in Fig. 4 represents the passage of time, and the vertical direction represents the state of each signal. Fig. 4 shows the selected binary code (input terminals α to Δ) when the control signals S1 to S4 are all "1".

[0045] Assuming that the T-type FFs 11-14 in the frequency division unit 10 change at the rising edge of the clock signal, the Q outputs of the T-type FFs 11-14 change from 0,0,0,0 (0) to 1,1,1,1 (F) at the rising edge of the clock signal. After that, the Q outputs of the T-type FFs 11-14 change in the following order in synchronization with the rising edge of the clock signal: E, D, C, B, A, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0. This F to 0 matches the selected binary code (input terminals α to Δ).

[0046] When the selected binary code is F, the first MUX 41 selects the eighth bit 328 of the second memory section 32. In addition, the second MUX in this case selects the eighth bit 348 of the fourth memory section .

[0047] When the selected binary code is E, the first MUX 41 selects the eighth bit 318 of the first memory unit 31. In addition, the second MUX 42 in this case selects the eighth bit 338 of the third memory unit 33.

[0048] In this way, the first MUX 41 selects one of the data in the first memory unit 31 and the second memory unit 32, both of which are set to the same data, and the second MUX 42 selects one of the data in the third memory unit 33 and the fourth memory unit 34, both of which are set to the same data.

[0049] The first register 51 (FIG. 1) holds the signal selected by the first MUX 41 in synchronization with the clock signal, and the second register 52 similarly holds the signal selected by the first MUX .

[0050] The soft error detection unit 60 compares the signals held by the first register 51 and the second register 52 (the output signals of each register), and detects a soft error if they do not match. If no soft error has occurred, the signals held by the first register 51 and the second register 52 always match. Therefore, the output of the soft error detection unit (EXOR gate) 60 is always "0".

[0051] When any bit in the first memory unit 31 to the fourth memory unit 34 changes due to a neutron, one of the signals held in the first register 51 and the second register 52 changes. As a result, the signals held in the first register 51 and the second register 52 do not match, and the soft error detection unit 60 detects a soft error.

[0052] When the Q outputs of the T-type FFs 11 to 14 are in a state of, for example, 8, if the signals held in the first register 51 and the second register 52 respectively do not match, the soft error detection unit 60 immediately detects a soft error (the output of the EXOR gate changes to "1" (not shown)). When a soft error is detected, the control unit (not shown) generates an initialization signal, and the memory initialization unit 70 initializes the first memory unit 31 to the fourth memory unit 34 to predetermined data.

[0053] The data for initializing the first memory unit 31 to the fourth memory unit 34 is, for example, all "0" or all "1". The data to be compared is not limited to all "0" or all "1". This process of detecting soft errors and initializing the memory units may be repeated.

[0054] When soft error detection is not performed repeatedly, there is no need to provide the memory initialization unit 70. The memory initialization unit 70 is controlled by a control unit (not shown). The control unit will be described in the second embodiment.

[0055] In this way, when the code length of the selected binary code is 4 bits, soft errors can be detected by comparing all the corresponding bits in the first memory unit 31 to the fourth memory unit 34. The comparison can be performed in 16 cycles of the clock signal.

[0056] Assuming that the frequency of the clock signal is 200 MHz, soft errors can be detected with a resolution of 80 ns (5 ns x 16).

[0057] Furthermore, if the code length of the selected binary code is 1 bit, only the input signal Δ is valid, and a portion of corresponding bits in the first memory unit 31 to the fourth memory unit 34 are compared to detect a soft error.

[0058] FIG. 5 is a time chart showing the selected binary code when the code length of the selected binary code is 1 bit, the selection signal of the first MUX 41, and the selection signal of the second MUX .

[0059] 5, when the code length of the selected binary code is 1 bit, the first MUX 41 alternately selects the 5th bit 315 and the 1st bit 311 of the first memory unit 31. The second MUX 42 alternately selects the 5th bit 335 and the 1st bit 331 of the third memory unit 33.

[0060] In this way, when the code of the selected binary code is 1 bit, a soft error is detected by comparing the corresponding 2 bits of the first memory unit 31 to the fourth memory unit 34. In this case, the memory area to be detected is narrower, but a soft error can be detected with a resolution of 10 ns (5 ns × 2).

[0061] Table 1 shows the relationship between the code length, detection resolution, and detection efficiency of the selected binary code.

[0062] [Table 1]

[0063] Here, the detection efficiency is the ratio of the size of the memory areas of the first memory unit 31 to the fourth memory unit 34 used to detect soft errors, and a detection efficiency of 1 is a ratio based on the case where the selected binary code is fixed to "0" or "1".

[0064] The detection resolution is the time interval for detecting soft errors. By reducing the size of the memory areas of the first memory unit 31 to the fourth memory unit 34 used for soft error detection, it is possible to detect soft errors with a reduced detection resolution. Note that reducing the detection resolution reduces the detection efficiency.

[0065] As shown in Table 1, the detection resolution and detection efficiency of soft errors can be varied by changing the code length of the selected binary code.

[0066] The energy of particle radiation is proportional to its flight speed, so by using a code length (selected binary code) that corresponds to the energy range of the particle radiation to be measured, it is possible to measure soft errors efficiently.

[0067] Fig. 6 is a diagram showing an example of the relationship between neutron energy and flight time, in which the horizontal axis represents neutron energy [MeV] and the vertical axis represents the neutral flight speed.

[0068] As shown in Figure 6, when the neutron energy is small, the time of flight is long, and when the energy is large, the time of flight is short. Therefore, by changing the code length according to the neutron energy to be measured, soft errors can be measured efficiently.

[0069] In other words, soft errors caused by fast neutrons can be detected in a short time, while soft errors caused by slow neutrons can be detected in a long time without omission.

[0070] As described above, the soft error detection device 100 according to this embodiment is a soft error detection device for detecting soft errors caused by the incidence of particle radiation, and includes a frequency division section 10 which divides a clock signal input from the outside, a code length selection section 20 which selects the code length of a binary code representing the operating state of the frequency division section 10, a first memory section 31 in which predetermined data is stored, a second memory section 32 in which data different from that stored in the first memory section 31, and a selection section 20 which selects whether the first memory section 31 or the second memory section 32 is to be read based on the selected binary code. The device includes a first MUX 41 which selects one of the data, a third memory section 33 in which the same data as that of the first memory section 31 is stored, a fourth memory section 34 in which the same data as that of the second memory section 32 is stored, a second MUX 42 which selects one of the data in the third memory section 33 and the fourth memory section 34 based on the selected binary code, and a soft error detection section 60 which compares the first output signal output by the first MUX 41 and the second output signal output by the second MUX 42 in synchronization with a clock signal and detects a soft error if they do not match. This makes it possible to provide a soft error detection device which can effectively utilize the memory area in which soft errors are detected.

[0071] Effective use of memory areas means reducing unused memory areas (or eliminating unused areas). According to this embodiment, the code length of the selected binary code is set to 4 bits, so that soft errors can be detected using all the bits of the first memory unit 31 to the fourth memory unit 34.

[0072] Each of the functional components of the above-mentioned first memory unit 31, second memory unit 32, third memory unit 33, fourth memory unit 34, first MUX 41, and second MUX 42 can be replaced with a lookup table (truth table) that realizes the combinational logic (circuit information of combinational logic) of the FPGA.

[0073] That is, the first memory unit 31, the second memory unit 32, the third memory unit 33, the fourth memory unit 34, the first MUX 41, and the second MUX 42 may be configured as lookup tables of an FPGA. In that case, the configuration including other functional components (such as the frequency divider unit 10) and sequential circuits can also be realized by the FPGA. This can reduce development costs.

[0074] Furthermore, the code length selection unit 20 selects the code length of the binary code representing the operating state of the frequency division unit 10 based on the control signals S1 to S4 input from the outside. This makes it possible to vary the detection resolution and detection efficiency of the soft error detection device 100 from the outside.

[0075] Second Embodiment Fig. 7 is a block diagram showing an example of the functional configuration of a soft error detection device according to a second embodiment of the present invention. The soft error detection device 200 shown in Fig. 7 is obtained by adding a particle energy calculation unit 210, a soft error cross section calculation unit 220, and a control unit 230 to the soft error detection device 100 (Fig. 1).

[0076] The particle energy calculation unit 210 calculates the particle energy of the particle radiation based on the difference between the generation time of the particle radiation and the detection time of the soft error.

[0077] The generation time of the particle radiation is obtained from a particle generation timing signal input from an external source. The particle generation timing signal is a signal that indicates the time when a target that generates the particle radiation is irradiated with, for example, protons.

[0078] The particle energy calculation unit 210 starts the measurement of an internal timer (not shown) in response to the input of the particle generation timing signal. After that, when the output of the soft error detection unit 60 (soft error detection device 100) changes (from "0" to "1"), the timer measurement is stopped and the flight time of the particle radiation is measured.

[0079] The soft error detection device 100 is placed in an environment where it is irradiated with particle radiation. Other functional components of the soft error detection device 200 (such as the particle energy calculation unit 210) are placed in an environment where it is not irradiated with particle radiation. The environment where it is not irradiated with particle radiation is, for example, a space surrounded by a shielding wall.

[0080] The particle energy calculation unit 210 measures the flight time of the particle radiation and calculates the particle energy E n Calculate.

[0081]

number

[0082] Here, m0 is the mass of the particle radiation, c is the speed of light, L is the distance between the target and the soft error detection device 100, and t is the difference mentioned above.

[0083] The soft error cross section calculation section 220 calculates the soft error cross section by dividing the number of detected soft errors by the number of particle radiation incident on a unit area.

[0084] The number of detected soft errors is obtained by repeatedly detecting changes in the output of the soft error detection unit 60 for a predetermined time. When a soft error is detected, the control unit 230 operates the memory initialization unit 70 to operate the soft error detection device 100 so as to repeat the operations of initializing the data in the first memory unit 31 to the fourth memory unit 34 and then detecting a soft error for a predetermined time. The number of times this repetition is the number of detected soft errors.

[0085] The number of particle radiation incident on a unit area may be measured by a measuring device in the environment where the particle radiation is irradiated, or may be stored in advance in the soft error cross section calculation unit 220 as a constant.

[0086] The soft error cross section represents the probability of a soft error occurring per unit area due to one particle of radiation. The soft error cross section is used to calculate the failure rate of semiconductor devices due to soft errors.

[0087] The soft error detection device 200 may include either a particle energy calculation unit 210 or a soft error cross section calculation unit 220, or both.

[0088] That is, the soft error detection device 200 includes a particle energy calculation unit 210 that calculates the particle energy of the particle radiation based on the difference between the generation time of the particle radiation and the detection time of the soft error. This makes it possible to calculate the particle energy of the particle radiation.

[0089] The soft error detection device 200 also includes a soft error cross section calculation section 220 that calculates a soft error cross section by dividing the number of detected soft errors by the number of particle radiation incident on a unit area. This makes it possible to calculate the soft error cross section.

[0090] (Soft error detection method) FIG. 8 is a flowchart showing the procedure of the soft error detection method performed by the soft error detection device 100.

[0091] When the soft error detection device 100 starts operation, the frequency divider 10 divides the frequency of the clock signal (step S1).

[0092] Next, the code length selection unit 20 outputs a selected binary code having a selected code length for the binary code representing the operating state of the frequency division unit 10 (step S2).

[0093] Next, the first MUX 41 selects data from either the first memory unit 31 or the second memory unit 32 based on the selected binary code. Then, the first register 51 holds the output signal of the second MUX 42 in synchronization with the clock signal (step S3).

[0094] Further, the second MUX 42 selects either the data in the third memory unit 33 or the data in the fourth memory unit 34 based on the selected binary code. Then, the second register 52 holds the output signal of the first MUX 41 in synchronization with the clock signal (step S4).

[0095] Then, the soft error detection unit 60 compares the first output signal output by the first MUX 41 with the second output signal output by the second MUX 42 in synchronization with the clock signal, and detects a soft error if they do not match (step S5). The processes of steps S1 to S4 are repeated until a soft error is detected (NO in step S5).

[0096] As described above, the soft error detection method according to the present embodiment is a soft error detection method performed by the soft error detection device 100 for detecting soft errors caused by the incidence of particle radiation, in which the frequency divider 10 divides the frequency of a clock signal input from the outside, the code length selector 20 selects the code length of a binary code representing the operating state of the frequency divider 10, the first MUX 41 selects either data from the first memory 31 in which a predetermined data is stored or data from the second memory 32 in which data different from that of the first memory 31 is stored based on the selected binary code, and the second MUX 42 selects either data from the third memory 33 in which the same data as that of the first memory 31 is stored or data from the fourth memory 34 in which the same data as that of the second memory 32 is stored based on the selected binary code, and compares the first output signal output by the first MUX 41 with the second output signal output by the second MUX 42 in synchronization with the clock signal, and detects a soft error if they do not match. This makes it possible to provide a soft error detection method that can effectively utilize the memory area in which soft errors are detected.

[0097] (effect) 9 is a diagram showing an example of the relationship between the flight time of neutrons (particle radiation) and the probability of logical fault occurrence. The horizontal axis of FIG. 9 is the flight time [ns], and the vertical axis is the probability of logical fault occurrence.

[0098] Neutrons with a short flight time cause many logic failures, as shown in Figure 9. Since flight time is proportional to neutron (particle radiation) energy (Figure 6), high-energy neutrons cause many logic failures (soft errors).

[0099] According to the soft error detection devices 100 and 200 of the present embodiment, the detection resolution can be set in accordance with the magnitude of the energy of the particle radiation. That is, the detection resolution is set small for neutrons with large energy, and large for neutrons with small energy. This makes it possible to reduce the statistical error of soft errors.

[0100] Fig. 10 is a diagram showing an example of the relationship between neutron energy and the soft error cross section, in which the horizontal axis represents neutron energy [Mev] and the vertical axis represents the soft error cross section.

[0101] 10, the soft error cross section for neutron energies of 3 Mev or less varies greatly. According to the soft error detection devices 100 and 200, the variation can be reduced by setting a high detection resolution for neutrons in this energy band.

[0102] In addition, for high-energy neutrons, measurement in a short time is possible by setting the detection resolution to a small value.

[0103] In this way, the soft error detection devices 100 and 200 can reduce statistical errors and shorten the measurement time.

[0104] In the above embodiment, the data amount of the first memory unit 31 to the fourth memory unit 34 is described as 8 bits as an example, but by configuring each memory unit in parallel, the data amount can be easily increased to, for example, the order of several tens of megabits.

[0105] Although the frequency division unit 10 has been described as having four T-type FFs connected in cascade, the present invention is not limited to this example. It may be configured with any number of stages corresponding to the amount of data in the memory.

[0106] Thus, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters related to the scope of the claims appropriate from the above description. [Explanation of symbols]

[0107] 10: Frequency dividing section 20: Code length selection section 31: First memory section 32: Second memory section 33: Third memory section 34: 4th memory section 41: First multiplexer 42: Second multiplexer 51: First register 52: Second register 60: Soft error detection unit 100,200:Soft error detection device 210: Particle energy calculation unit 220: Soft error cross section calculation unit

Claims

1. A soft error detection device for detecting soft errors caused by incidence of particle radiation, a frequency division unit that divides a frequency of a clock signal input from an external device; a code length selection unit that selects a code length of a binary code that represents an operating state of the frequency division unit; a first memory section in which predetermined data is stored; a second memory section in which data different from that in the first memory section is stored; a first multiplexer for selecting data from either the first memory section or the second memory section based on a selected binary code; a third memory section in which the same data as that in the first memory section is stored; a fourth memory section in which the same data as that in the second memory section is stored; a second multiplexer for selecting data from either the third memory section or the fourth memory section based on the selected binary code; a soft error detection unit that compares a first output signal output from the first multiplexer with a second output signal output from the second multiplexer in synchronization with the clock signal, and detects the soft error when the first output signal and the second output signal do not match; A soft error detection device comprising:

2. The first memory unit, the second memory unit, the third memory unit, the fourth memory unit, the first multiplexer, and the second multiplexer are look-up tables of an FPGA.

2. The soft error detection device according to claim 1.

3. The code length selection unit The code length of the binary code is selected based on a control signal input from an external device.

3. The soft error detection device according to claim 1 or 2.

4. a particle energy calculation unit that calculates particle energy of the particle radiation based on a difference between a generation time of the particle radiation and a detection time of the soft error; 4. The soft error detection device according to claim 1, further comprising:

5. A soft error cross section calculation unit that calculates a soft error cross section by dividing the number of detected soft errors by the number of the particle radiation incident on a unit area.

5. The soft error detection device according to claim 1, further comprising:

6. A soft error detection method performed by a soft error detection device for detecting soft errors caused by incidence of particle radiation, comprising the steps of: The frequency divider divides a clock signal input from an external device, a code length selection unit that selects a code length of a binary code that represents an operation state of the frequency division unit; a first multiplexer for selecting one of data from a first memory section in which predetermined data is stored and data from a second memory section in which data different from that stored in the first memory section is stored based on the selected binary code; a second multiplexer selects one of data from a third memory section in which the same data as the first memory section is stored and data from a fourth memory section in which the same data as the second memory section is stored based on the selected binary code; A first output signal output from the first multiplexer and a second output signal output from the second multiplexer are compared in synchronization with the clock signal, and the soft error is detected if the first output signal and the second output signal are not the same. Soft error detection methods.

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