Capacitor and manufacturing method thereof

Abstract

To increase the capacity density of a capacitor.SOLUTION: A capacitor includes substrates (1a, 1b) including a groove 3 formed on a main surface 1F thereof and a cavity 5 formed therein and continuing to the groove 3, at least one dielectric layer (6a to 6d) and at least one conductive layer (7a to 7d) stacked alternately on a surface of the groove 3 or the cavity 5, a first electrode (16, 18) electrically connected to at least one of the at least one conductive layer (7a to 7d) and the substrates (1a, 1b), and a second electrode (17, 19) electrically connected to at least one of the conductive layer (7a to 7d) not electrically connected to the first electrode (16, 18) or the substrates (1a, 1b) not electrically connected to the first electrode (16, 18).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a capacitor and a method for manufacturing the same. [Background technology]

[0002] A capacitor structure is known in which a plurality of first grooves parallel to one another are formed on the front surface of a semiconductor substrate, a plurality of second grooves parallel to one another are formed on the rear surface of the semiconductor substrate, and conductive films and dielectric films are alternately laminated inside the first and second grooves (see Patent Document 1). The longitudinal direction of the first grooves and the longitudinal direction of the second grooves intersect in a plan view, and the bottom of the first grooves and the bottom of the second grooves are connected. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-4819 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a conductive film and a dielectric film are laminated inside first and second grooves formed on the front and back surfaces of a semiconductor substrate. Because of this, the surface area of ​​the portion where the conductive film and the dielectric film are laminated is also limited due to the limited area of ​​the front and back surfaces of the semiconductor substrate, making it difficult to increase the capacitance density of the capacitor.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a capacitor capable of increasing the capacitance density and a method for manufacturing the same. [Means for solving the problem]

[0006] In order to solve the above problems, a capacitor according to one aspect of the present invention comprises: (1) a substrate having a groove formed on a main surface and a cavity formed inside the groove and connected to the groove; (2) at least one dielectric layer and at least one conductive layer alternately laminated on the surfaces of the grooves and cavities; (3) a first electrode electrically connected to at least one of the at least one conductive layer and the substrate; (4) A second electrode electrically connected to at least one of a conductive layer not electrically connected to the first electrode or a substrate not electrically connected to the first electrode. 、 (5) When viewed in a direction perpendicular to the main surface, the grooves and the cavities each form a striped pattern; (6) When viewed from a direction perpendicular to the main surface, the longitudinal direction of the groove intersects with the longitudinal direction of the cavity. Effect of the Invention

[0007] According to the present invention, the capacitance density of the capacitor can be increased. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a cross-sectional view (part 1) showing a process of a method for manufacturing the semiconductor device shown in FIG. [Figure 2B] FIG. 2B is a perspective view showing the step shown in FIG. 2A. [Figure 3A] FIG. 3A is a cross-sectional view (part 2) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 3B] FIG. 3B is a perspective view showing the step shown in FIG. 3A. [Figure 4] 4A to 4C are cross-sectional views (part 3) illustrating steps of the method for manufacturing the semiconductor device shown in FIG. [Figure 5A] FIG. 5A is a cross-sectional view (part 4) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 5B] FIG. 5B is a perspective view showing the step shown in FIG. 5A. [Figure 6] 6A to 6C are cross-sectional views (part 5) illustrating steps in the method for manufacturing the semiconductor device shown in FIG. [Figure 7]FIG. 7 is a cross-sectional view (part 6) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view (part 7) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view (part 8) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a ninth cross-sectional view showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view (part 10) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view (part 11) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view (part 12) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 15A] FIG. 15A is a cross-sectional view (part 1) showing a process of a method for manufacturing the semiconductor device shown in FIG. [Figure 15B] FIG. 15B is a perspective view showing the step shown in FIG. 15A. [Figure 15C] 15C is a cross-sectional view (part 2) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 15D] FIG. 15D is a perspective view showing the step shown in FIG. 15C. [Figure 16A] FIG. 16A is a cross-sectional view (part 3) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 16B] FIG. 16B is a perspective view showing the step shown in FIG. 16A. [Figure 17] FIG. 17 is a cross-sectional view (part 4) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 18] 18 is a cross-sectional view (part 5) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 19]FIG. 19 is a cross-sectional view (part 6) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view (part 7) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view (part 8) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 22] FIG. 22 is a sectional view (part 9) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 24A] FIG. 24A is a cross-sectional view (part 1) showing a process of a method for manufacturing the semiconductor device shown in FIG. [Figure 24B] FIG. 24B is a perspective view showing the step shown in FIG. 24A. [Figure 25A] FIG. 25A is a cross-sectional view (part 2) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 25B] FIG. 25B is a perspective view showing the step shown in FIG. 25A. [Figure 26] FIG. 26 is a cross-sectional view (part 3) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 27A] FIG. 27A is a perspective view showing the structure of a substrate 71 according to another embodiment. [Figure 27B] FIG. 27B is a perspective view showing a stacked structure of the four substrates (71 to 74) shown in FIG. 27A. [Figure 27C] FIG. 27C is a perspective view showing the structure of bonded substrate 81 formed by bonding the four substrates (71 to 74) shown in FIG. 27B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. In the description of the drawings, the same parts are given the same reference numerals and the description will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, and the like include parts that differ from the actual ones. In addition, there are parts where the dimensional relationships and ratios differ between the drawings.

[0010] (First embodiment) The configuration of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. 1. The semiconductor device according to the first embodiment includes substrates (1a, 1b). The substrates (1a, 1b) have a first main surface 1F (front surface) and a second main surface 1R (back surface) facing each other. A groove 3 is formed in the first main surface 1F of the substrates (1a, 1b). A cavity 5 connected to the groove 3 is formed inside the substrates (1a, 1b). In the example shown in FIG. 1, two grooves 3 are formed in the first main surface 1F, and a cavity 5 extending in a direction parallel to the first main surface 1F is formed inside the substrates (1a, 1b). All the grooves 3 and the cavity 5 are connected. The substrate is a semiconductor substrate, and is, for example, a single crystal substrate made of silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). The portion on the first main surface 1F side of the cavity 5 is called substrate 1a, and the portion on the second main surface 1R side of the cavity 5 is called substrate 1b.

[0011] The semiconductor device is a capacitor further comprising at least one dielectric layer (6a, 6b, 6c, 6d) and at least one conductive layer (7a, 7b, 7c, 7d) alternately stacked on the surfaces of the groove 3 and the cavity 5, a high potential electrode (16, 18) (first electrode) electrically connected to at least one of the at least one conductive layer (7a to 7d) and the substrates (1a, 1b), and a low potential electrode (17, 19) (second electrode) electrically connected to at least one of the conductive layers (7a to 7d) not electrically connected to the high potential electrode (16, 18) or the substrates (1a, 1b) not electrically connected to the high potential electrode (16, 18).

[0012] In the example shown in FIG. 1, four dielectric layers (6a-6d) and four conductive layers (7a-7d) are laminated inside the groove 3 and the cavity 5. Since all the grooves 3 and the cavities 5 are connected, each of the dielectric layers (6a-6d) and each of the conductive layers (7a-7d) are connected inside the groove 3 and the cavity 5. In addition, five dielectric layers (6a-6d, 6e) and four conductive layers (7a-7d) are laminated on the first main surface 1F and the second main surface 1R. Each of the dielectric layers (6a-6d) and each of the conductive layers (7a-7d) arranged on the first main surface 1F and inside the groove 3 are connected. Each of the dielectric layers (6a-6d) and each of the conductive layers (7a-7d) on the second main surface 1R is connected to each of the dielectric layers (6a-6d) and each of the conductive layers (7a-7d) arranged inside the cavity 5 at the side end portion of the semiconductor device. The number of layers is not limited to four, and one to three dielectric layers and one to three conductive layers may be arranged inside the groove 3 and the cavity 5, or five or more dielectric layers and conductive layers may be arranged.

[0013] The high potential electrodes (16, 18) are electrically connected to the two conductive layers (7a, 7c) and are electrically insulated from the substrates (1a, 1b) and the two conductive layers (7b, 7d), while the low potential electrodes (17, 19) are electrically connected to the substrates (1a, 1b) and the two conductive layers (7b, 7d) and are electrically insulated from the two conductive layers (7a, 7c).

[0014] When only one dielectric layer 7a and one conductive layer 6a are disposed inside the groove 3 and the cavity 5, the high potential electrode (16, 18) is electrically connected to the conductive layer 7a, and the low potential electrode (17, 19) is electrically connected to the substrate (1a, 1b). In the embodiment, the high potential electrode corresponds to the first electrode, and the low potential electrode corresponds to the second electrode, but the reverse may also be true.

[0015] The high potential electrodes (16, 18) include a high potential front electrode 16 disposed on the first main surface 1F and a high potential back electrode 18 disposed on the second main surface 1R. A part of the high potential front electrode 16 is embedded in a contact hole 8a penetrating the dielectric layers (6b-6e) and conductive layers (7b-7d) deposited on the first main surface 1F, via an interlayer insulating film 12. As a result, the high potential front electrode 16 is electrically connected to the conductive layer 7a exposed at the bottom of the contact hole 8a, and is electrically insulated from the conductive layers (7b-7d) by the interlayer insulating film 12. Another part of the high potential front electrode 16 is embedded in a contact hole 8b penetrating the dielectric layers (6d, 6e) and conductive layer 7d deposited on the first main surface 1F, via an interlayer insulating film 12. As a result, the high potential front electrode 16 is electrically connected to the conductive layer 7c exposed at the bottom of the contact hole 8b, and is electrically insulated from the conductive layer 7d by the interlayer insulating film 12.

[0016] Similar to the high-potential front surface electrode 16, a portion of the high-potential back surface electrode 18 is embedded in the contact holes (10a, 10b) formed on the second main surface 1R via the interlayer insulating film 12. Thus, the high-potential back surface electrode 18 is electrically connected to the conductive layers (7a, 7c) exposed at the bottom surfaces of the contact holes (10a, 10b), respectively, and is electrically insulated from the other conductive layers (7b, 7d) by the interlayer insulating film 12.

[0017] The low potential electrodes (17, 19) include a low potential front electrode 17 disposed on the first principal surface 1F side and a low potential back electrode 19 disposed on the second principal surface 1R side. A part of the low potential front electrode 17 is embedded in a contact hole 9a penetrating the dielectric layers (6a to 6e) and the conductive layers (7a to 7d) deposited on the first principal surface 1F, via an interlayer insulating film 12. As a result, the low potential front electrode 17 is electrically connected to the substrate 1a exposed at the bottom of the contact hole 9a, and is electrically insulated from the conductive layers (7a to 7d) by the interlayer insulating film 12. Another part of the low potential front electrode 17 is embedded in a contact hole 9b penetrating the dielectric layers (6c to 6e) and the conductive layers (7c, 7d) deposited on the first principal surface 1F, via an interlayer insulating film 12. As a result, the low potential surface electrode 17 is electrically connected to the conductive layer 7b exposed at the bottom surface of the contact hole 9b, and is electrically insulated from the conductive layers (7c, 7d) by the interlayer insulating film 12. Yet another part of the low potential surface electrode 17 is embedded in the contact hole 9c penetrating the dielectric layer 6e deposited on the first main surface 1F, via the interlayer insulating film 12. As a result, the low potential surface electrode 17 is electrically connected to the conductive layer 7d exposed at the bottom surface of the contact hole 9c.

[0018] Similar to the low-potential front surface electrode 17, a portion of the low-potential back surface electrode 19 is embedded in the contact holes (11a, 11b, 11c) formed on the second main surface 1R via the interlayer insulating film 12. Thus, the low-potential back surface electrode 19 is electrically connected to the substrate 1b and the conductive layers (7b, 7d) exposed at the bottoms of the contact holes (11a to 11c), respectively, and is electrically insulated from the other conductive layers (7a, 7c) by the interlayer insulating film 12.

[0019] The basic operation of the capacitor shown in Figure 1 will be described. A positive voltage is applied to the high potential electrodes (16, 18), and a negative voltage is applied to the low potential electrodes (17, 19). As a result, a positive charge is charged to the conductive layers (7a, 7c) electrically connected to the high potential electrodes (16, 18), and a negative charge is charged to the substrates (1a, 1b) and conductive layers (7b, 7d) electrically connected to the low potential electrodes (17, 19). At this time, polarization occurs inside the dielectric layers (6a-6d), generating capacitance.

[0020] As described above, each of the dielectric layers (6a-6d) and each of the conductive layers (7a-7d) arranged inside the groove 3, inside the cavity 5, on the first main surface 1F, and on the second main surface 1R are connected to each other. Therefore, a structure is formed in which four layers of capacitors stacked inside the groove 3, inside the cavity 5, on the first main surface 1F, and on the second main surface 1R are connected in parallel, and the capacitance density of the capacitors per unit area of ​​the first main surface 1F of the semiconductor substrate can be improved.

[0021] When viewed from a direction perpendicular to the first main surface 1F, the grooves 3 and cavities 5 form a repeating pattern of polygonal or circular dots, which makes it possible to fabricate a substrate (1a, 1b) having high mechanical strength.

[0022] All of the cavities 5 and the trenches 3 are connected. This allows the dielectric layers (6a to 6d) and the conductive layers (7a to 7d) to be grown along the regions of all of the cavities 5 and the trenches 3, thereby improving the capacitance density.

[0023] A plurality of dielectric layers (6a to 6d) and a plurality of conductive layers (7a to 7d) are alternately laminated on the surfaces of the groove 3 and the cavity 5. This makes it possible to improve the capacitance density.

[0024] Since silicon oxide films are used for the dielectric layers (6a to 6d), operation at high voltages is possible.

[0025] The dielectric layers (6a to 6d) may be made of silicon nitride films having a high dielectric constant, which can improve the capacitance density. Each of the dielectric layers (6a to 6d) may be made of a laminated film of a silicon oxide film and a silicon nitride film.

[0026] A polysilicon film is used for the conductive layers (7a to 7d), which allows the conductive layers (7a to 7d) to be grown uniformly along the surfaces of the trenches 3 and the cavity 5 using a low-pressure CVD method.

[0027] The conductive layers (7a to 7d) may be made of a metal, which can reduce the equivalent series resistance (ESR) of the conductive layers (7a to 7d).

[0028] In the embodiment, the substrates (1a, 1b) are semiconductors, but the substrates (1a, 1b) may be insulators or conductors. When the substrates (1a, 1b) are insulators, element separation becomes easy. When the substrates (1a, 1b) are conductors, the substrates (1a, 1b) can be used as electrodes.

[0029] When the substrates (1a, 1b) are silicon substrates, the substrates (1a, 1b) can be produced at low cost.

[0030] It is desirable that the surface of the groove 3 or cavity 5 is a surface equivalent to the (110) surface or the (111) surface, so that the groove 3 and cavity 5 can be fabricated by anisotropic wet etching.

[0031] Hereinafter, a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. Note that the method for manufacturing a semiconductor device described below is an example, and various other manufacturing methods may be used.

[0032] First, as shown in FIG. 2A and FIG. 2B, a part of the substrate 1 is etched from the first main surface 1F of the substrate 1 to form a groove 3. The substrate 1 is shown in a state before being separated into the substrate 1a and the substrate 1b. Specifically, a mask material 2 is first formed on the first main surface of the substrate 1. A silicon oxide film can be used as the mask material 2, and a thermal CVD method or a plasma CVD method can be used as a deposition method. Next, a resist is patterned on the mask material 2. A general photolithography method can be used as a patterning method. The mask material 2 is etched using the patterned resist as a mask. As shown in FIG. 2A and FIG. 2B, the mask material 2 has an opening in a portion where the groove 3 is to be formed. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. Next, the resist is removed with oxygen plasma, sulfuric acid, or the like. The substrate 1 exposed from the opening of the mask material 2 is etched by dry etching using the mask material 2 formed in this way, and the groove 3 is formed.

[0033] 3A and 3B, a mask material 4 is deposited along the first main surface 1F of the substrate 1. A silicon oxide film can be used as the mask material 4, and a thermal CVD method can be used as the deposition method, for example. When using the thermal CVD method, the silicon oxide film (mask material 4) can be deposited under normal pressure conditions so as to cover only the sidewalls of the trenches 3 from the openings of the trenches 3 to a certain depth.

[0034] Next, as shown in FIG. 4, the substrate 1 is etched by isotropic dry etching to form a cavity 5 extending horizontally inside the substrate 1. The portion of the surface of the substrate 1 covered with the mask material 4 is not etched, and only the portion exposed without the mask material 4, that is, the inner side of the groove 3, is selectively etched. The cavity 5 can be formed in any shape depending on the etching time. Here, for example, as shown in FIG. 5A and FIG. 5B, a shape in which adjacent cavities 5 are connected horizontally can be formed by etching for a long time. As a result, the cavity 5 extending in a direction parallel to the first main surface 1F is formed inside the substrate 1, and all the grooves 3 and the cavity 5 can be connected. Then, in the cross section shown in FIG. 5A, the substrate 1 can be separated into a portion (substrate 1a) on the first main surface 1F side of the cavity 5 and a portion (substrate 1b) on the second main surface 1R side of the cavity 5. However, as shown in FIG. 5B, the substrate 1a and the substrate 1b are connected to each other at the back side of the paper surface of FIG. 5A.

[0035] Next, as shown in Fig. 6, a dielectric layer (first dielectric layer 6a) is deposited on the surface of the substrate (1a, 1b) including the inner surfaces of the groove 3 and the cavity 5 and the first main surface 1F and the second main surface 1R so as to cover the substrate (1a, 1b). A silicon oxide film can be used as the dielectric layer, and a thermal oxidation method or a thermal CVD method can be used as the deposition method. When using the thermal CVD method, a silicon oxide film can be deposited with good coverage by reducing the pressure under reduced pressure conditions, even when the groove 3 and the cavity 5 are deep and have complex shapes.

[0036] Next, as shown in FIG. 7, a conductive layer (first conductive layer 7a) is deposited on the surface of the substrate (1a, 1b) including the inner surface of the groove 3 and the cavity 5 and the first main surface 1F and the second main surface 1R so as to cover the first dielectric layer 6a. Here, polysilicon is used as an example of the conductive layer. After the deposition of the polysilicon film, an annealing process is performed in POCL3 at 950° C. to form N-type polysilicon, which gives the conductive layer conductivity. Here, polysilicon is used as an example of the conductive layer, but other metals such as titanium (Ti) and aluminum (Al) and metal silicide films can also be used. A low pressure CVD method may be used as a method for depositing polysilicon. Through the above steps, the first dielectric layer 6a and the first conductive layer 7a are laminated in order on the surface of the substrate (1a, 1b).

[0037] Next, the deposition of the dielectric layer shown in FIG. 6 and the deposition of the conductive layer shown in FIG. 7 are alternately repeated three times. In this embodiment, as shown in FIG. 8, the inside of the groove 3 and the cavity 5 are backfilled with a total of four dielectric layers (6a to 6d) and four conductive layers (7a to 7d). The dielectric layers formed at this time are called the second dielectric layer 6b, the third dielectric layer 6c, and the fourth dielectric layer 6d. Meanwhile, the conductive layers formed at this time are called the second conductive layer 7b, the third conductive layer 7c, and the fourth conductive layer 7d. After the deposition of the fourth conductive layer 7d, a dielectric layer (a fifth dielectric layer 6e) is laminated above the first main surface 1F of the substrate 1a and below the second main surface 1R of the substrate 1b.

[0038] Next, as shown in FIG. 9, a mask material (not shown) is formed so as to partially cover the fifth dielectric layer 6e on each of the first main surface 1F and the second main surface 1R of the substrate 1a. The mask material has openings in areas where the contact holes (8a, 10a) are to be formed. The second dielectric layer 6b, the third dielectric layer 6c, the fourth dielectric layer 6d, the second conductive layer 7b, the third conductive layer 7c, and the fourth conductive layer 7d are dry-etched through the mask material. This forms the contact holes (8a, 10a) in which the high potential electrodes (16, 18) are embedded. Similarly, the contact holes (8b, 10b) in which the high potential electrodes (16, 18) are embedded and the contact holes (9a to 9c, 11a to 11c) in which the low potential electrodes (17, 19) are embedded are also formed by etching the dielectric layers and conductive layers through the mask material to the desired depths shown in FIG. 1.

[0039] 10, an interlayer film 12 is deposited on the fifth dielectric layer 6e on each of the first and second main surfaces 1F and 1R of the substrate 1a, and on the side and bottom surfaces of all the contact holes (8a, 8b, 9a, 9b, 9c, 10a, 10b, 11a, 11b, 11c). The interlayer film 12 may be a silicon oxide film. The thickness of the interlayer film 12 is thin enough that the contact holes (8a to 11c) are not backfilled with the interlayer film 12, and the width of the contact holes (8a to 11b) is wide enough that the contact holes (8a to 11c) are not backfilled with the interlayer film 12.

[0040] 11, the interlayer film 12 on the bottom of the contact holes (8a to 11c) is etched using the patterned mask material 13. The corresponding substrate 1a or conductive layer (7a to 7d) is exposed at the bottom of each contact hole. The interlayer film 12 is left on the side of each contact hole.

[0041] Next, as shown in FIG. 12, the front electrode 14 and the back electrode 15 are deposited so as to cover the first main surface 1F and the second main surface 1R of the substrate (1a, 1b). At this time, the inside of the contact holes (8a to 11c) is filled with the front electrode 14 or the back electrode 15, and the front electrode 14 and the back electrode 15 are electrically connected to the substrate 1a or the conductive layer (7a to 7d) exposed at the bottom of the contact holes (8a to 11c). Metal is generally used as the electrode material of the front electrode 14 and the back electrode 15. Specifically, titanium (Ti), nickel (Ni), and molybdenum (Mo) can be used. The front electrode 14 and the back electrode 15 may also be a laminated film of Ti / Ni / silver (Ag) or the like. The metal film can be formed by sputtering or electron beam (EB) deposition. The front surface electrode 14 corresponds to the high potential front surface electrode 16 and the low potential front surface electrode 17 before being divided, and the back surface electrode 15 corresponds to the high potential back surface electrode 18 and the low potential back surface electrode 19 before being divided.

[0042] 13, the mask material 20 is patterned by a general photolithography method, and a part of the front surface electrode 14 and the rear surface electrode 15 is etched by dry etching. As a result, the front surface electrode 14 is divided into a high-potential front surface electrode 16 and a low-potential front surface electrode 17, and the rear surface electrode 15 is divided into a high-potential rear surface electrode 18 and a low-potential rear surface electrode 19.

[0043] By removing the mask material 20, the semiconductor device according to the first embodiment shown in FIG. 1 is completed.

[0044] By forming the grooves 3 and the cavities 5 by dry etching, it is possible to form the grooves 3 and the cavities 5 with a high aspect ratio.

[0045] The grooves 3 and the cavities 5 may be formed by wet etching, which allows the grooves 3 and the cavities 5 to be formed at low cost.

[0046] The dielectric layers (6a to 6d) can be formed by low pressure CVD, which allows the dielectric layers (6a to 6d) to grow uniformly along the surfaces of the grooves 3 and the cavities 5.

[0047] The dielectric layers (6a-6d) may be formed by atomic layer deposition (ALD), which allows the dielectric layers (6a-6d) to grow uniformly along the surfaces of the trenches 3 and the cavities 5.

[0048] The conductive layers (7a to 7d) can be formed by atomic layer deposition (ALD), which allows the conductive layers (7a to 7d) to grow uniformly along the surfaces of the trenches 3 and the cavities 5.

[0049] The conductive layers (7a to 7d) may be formed by metal organic chemical vapor deposition (MOCVD), which allows the conductive layers (7a to 7d) to grow uniformly along the surfaces of the grooves 3 and the cavities 5.

[0050] The conductive layers (7a to 7d) may be formed by plating growth, which can reduce the equivalent series resistance (ESR).

[0051] Second embodiment The configuration of a semiconductor device according to a second embodiment of the present invention will be described with reference to Fig. 14. The semiconductor device according to the second embodiment includes a substrate 26. Substrate 26 has a first main surface 1F (front surface) and a second main surface 1R (rear surface) that face each other. A groove 3 is formed in first main surface 1F of substrate 26. A cavity 5 connected to groove 3 is formed inside substrate 26. Substrate 26 is a bonded substrate formed by bonding a first substrate in which groove 23 is formed and a second substrate in which cavity 25 is formed. The bonding method will be described in detail later.

[0052] 14, two grooves 3 are formed in the first main surface 1F, and a cavity 5 extending in a direction parallel to the first main surface 1F is formed inside the substrate 26. All of the grooves 3 and the cavities 5 are connected. In the second embodiment, a part of the cavity 5 is exposed to the second main surface 1R of the substrate 26. This makes it possible to form a hole (groove 3 and cavity 5) that penetrates from the front surface to the back surface of the substrate 26, and therefore it is possible to form wiring electrodes on both the front and back surfaces of the substrate 26.

[0053] The semiconductor device is a capacitor further including at least one dielectric layer (28a, 28b, 28c, 28d) and at least one conductive layer (29a, 29b, 29c, 29d) alternately stacked on the surfaces of the groove 3 and the cavity 5, a high potential electrode (38, 40) (first electrode) electrically connected to at least one of the at least one conductive layer (29a to 29d) and the substrate 26, and a low potential electrode (39, 41) (second electrode) electrically connected to the conductive layers (29a to 29d) not electrically connected to the high potential electrode (38, 40) and the substrate 26.

[0054] In the example shown in FIG. 14, four dielectric layers (28a-28d) and four conductive layers (29a-29d) are laminated inside the grooves 23 and the cavities 25. Since all the grooves 23 and the cavities 25 are connected, the dielectric layers (28a-28d) and the conductive layers (29a-29d) are connected inside the grooves 23 and the cavities 25. Five dielectric layers (28a-28e) and four conductive layers (29a-29d) are also laminated on the first main surface 1F and the second main surface 1R. The dielectric layers (28a-28d) and the conductive layers (29a-29d) arranged on the first main surface 1F, the second main surface 1R, the grooves 23, and the cavities 25 are connected to each other. The number of layers is not limited to four, and one to three dielectric layers and one to three conductive layers may be arranged inside the groove 23 and the cavity 25, or five or more dielectric layers and conductive layers may be arranged.

[0055] The high potential electrodes (38, 40) include a high potential front electrode 38 disposed on the first main surface 1F and a high potential back electrode 40 disposed on the second main surface 1R. A part of the high potential front electrode 38 is embedded in a contact hole 30a penetrating the dielectric layers (28b-28e) and conductive layers (29b-29d) deposited on the first main surface 1F, via an interlayer insulating film 34. As a result, the high potential front electrode 38 is electrically connected to the conductive layer 29a exposed at the bottom surface of the contact hole 30a, and is electrically insulated from the conductive layers (29b-29d) by the interlayer insulating film 34. Another part of the high potential front electrode 38 is embedded in a contact hole 30b penetrating the dielectric layers (28d, 28e) and conductive layer 29d deposited on the first main surface 1F, via the interlayer insulating film 34. As a result, the high potential surface electrode is electrically connected to the conductive layer 29c exposed at the bottom of the contact hole 30b, and is electrically insulated from the conductive layer 29d by the interlayer insulating film .

[0056] Similar to the high-potential front surface electrode 38, a portion of the high-potential back surface electrode 40 is embedded in the contact holes (32a, 32b) formed on the second main surface 1R via the interlayer insulating film 34. Thus, the high-potential back surface electrode 40 is electrically connected to the conductive layers (29a, 29c) exposed at the bottom surfaces of the contact holes (32a, 32b), respectively, and is electrically insulated from the other conductive layers (29b, 29d) by the interlayer insulating film 34.

[0057] The low potential electrodes (39, 41) include a low potential front electrode 39 disposed on the first principal surface 1F side and a low potential back electrode 41 disposed on the second principal surface 1R side. A part of the low potential front electrode 39 is embedded in a contact hole 31a penetrating the dielectric layers (28a to 28e) and the conductive layers (29a to 29d) deposited on the first principal surface 1F, via an interlayer insulating film 34. As a result, the low potential front electrode 39 is electrically connected to the substrate 26 exposed at the bottom of the contact hole 31a, and is electrically insulated from the conductive layers (29a to 29d) by the interlayer insulating film 34. Another part of the low potential front electrode 39 is embedded in a contact hole 31b penetrating the dielectric layers (28c to 28e) and the conductive layers (29c, 29d) deposited on the first principal surface 1F, via the interlayer insulating film 34. As a result, the low potential surface electrode 39 is electrically connected to the conductive layer 29b exposed at the bottom surface of the contact hole 31b, and is electrically insulated from the conductive layers (29c, 29d) by the interlayer insulating film 34. Yet another part of the low potential surface electrode 39 is embedded in the contact hole 31c penetrating the dielectric layer 28e deposited on the first main surface 1F, via the interlayer insulating film 34. As a result, the low potential surface electrode 39 is electrically connected to the conductive layer 29d exposed at the bottom surface of the contact hole 31c.

[0058] Similar to the low-potential front surface electrode 39, a portion of the low-potential back surface electrode 41 is embedded in the contact holes (33a, 33b, 33c) formed on the second main surface 1R via the interlayer insulating film 34. Thus, the low-potential back surface electrode 41 is electrically connected to the substrate 26 and the conductive layers (29b, 29d) exposed at the bottoms of the contact holes (33a to 33c), respectively, and is electrically insulated from the other conductive layers (29a, 29c) by the interlayer insulating film 34.

[0059] The basic operation of the capacitor shown in Fig. 14 will be described. A positive voltage is applied to the high potential electrodes (38, 40), and a negative voltage is applied to the low potential electrodes (39, 41). As a result, a positive charge is charged to the conductive layers (29a, 29c) electrically connected to the high potential electrodes (38, 40), and a negative charge is charged to the substrate 26 and conductive layers (29b, 29d) electrically connected to the low potential electrodes (39, 41). At this time, polarization occurs inside the dielectric layers (28a to 28d), generating capacitance.

[0060] Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. Note that the method for manufacturing a semiconductor device described below is an example, and various other manufacturing methods may be used.

[0061] First, as shown in FIG. 15A and FIG. 15B, a mask material 22 is patterned on the surface of the first substrate 21, and a part of the first substrate 21 is etched using the mask material 22, thereby forming a plurality of grooves 23 penetrating the front and back surfaces of the first substrate 21. In the cross-sectional view of FIG. 15A, the grooves 23 extend in a direction perpendicular to the paper. When the first substrate 21 is viewed in a direction perpendicular to its front surface, the grooves 23 form a stripe shape. Also, as shown in FIG. 15C and FIG. 15D, the mask material 22 is patterned on the surface of the second substrate 24, and a part of the second substrate 24 is etched using the mask material 22, thereby forming a plurality of cavities 25 penetrating the front and back surfaces of the second substrate 24. In the cross-sectional view of FIG. 15C, the cavities 25 extend in a direction parallel to the paper. When the second substrate 24 is viewed in a direction perpendicular to its front and back surfaces, the cavities 25 form a stripe shape. The first substrate 21 and the second substrate 24 may be etched by either dry etching or wet etching.

[0062] Next, as shown in FIG. 16A and FIG. 16B, the first substrate 21 and the second substrate 24 are bonded to prepare a bonded substrate 26. After bonding, the groove 23 on the first substrate 21 and the cavity 25 on the second substrate 24 are connected. As a result, the groove 23 and the cavity 25 form a hole 27 that spreads in the depth direction and horizontal direction of the bonded substrate 26. Here, as an example of a bonding method, a "thermal diffusion bonding" is used in which the surfaces of the first substrate 21 and the second substrate 24 are cleaned, and then the substrates are bonded together by annealing at a high temperature of 400°C or more. However, the substrates may be bonded together by placing a bonding agent between the first substrate 21 and the second substrate 24. After bonding, when the bonded substrate 26 is viewed from a direction perpendicular to its first main surface, the longitudinal direction of the groove 23 and the longitudinal direction of the cavity 25 intersect.

[0063] 17, a dielectric layer (first dielectric layer 28a) is deposited on the surface of bonding substrate 26 including the inner surfaces of groove 23 and cavity 25 and first and second main surfaces 1F and 1R so as to cover bonding substrate 26. Next, a conductive layer (first conductive layer 29a) is deposited on the surface of bonding substrate 26 so as to cover first dielectric layer 28a.

[0064] Next, in the same manner, deposition of the dielectric layers and deposition of the conductive layers are alternately repeated three times. In this embodiment, as shown in FIG. 17, the inside of the groove 23 and the cavity 25 are backfilled with a total of four dielectric layers (28a to 28d) and four conductive layers (29a to 29d). The dielectric layers formed at this time are called the second dielectric layer 28b, the third dielectric layer 28c, and the fourth dielectric layer 28d. Meanwhile, the conductive layers formed at this time are called the second conductive layer 29b, the third conductive layer 29c, and the fourth conductive layer 29d. After depositing the fourth conductive layer 29d, a dielectric layer (fifth dielectric layer 28e) is laminated above the first main surface 1F of the substrate 26 and below the second main surface 1R of the substrate 26.

[0065] 18, the dielectric layers (28a-28e) and the conductive layers (29a-29d) are etched using the mask material to form a plurality of contact holes (30a, 30b, 31a, 31b, 31c, 32a, 32b, 33a, 33b, 33c). Contact holes of the same depth, for example, the contact holes (30a, 32a), can be formed simultaneously using the same mask material, but contact holes of different depths are formed individually using different mask materials.

[0066] 19, an interlayer film 34 is deposited on the fifth dielectric layer 28e on each of the first and second main surfaces 1F and 1R of the substrate 26, and on the side and bottom surfaces of all the contact holes (30a-33c). A silicon oxide film can be used as the interlayer film 34. The thickness of the interlayer film 34 is thin enough to prevent the contact holes (30a-33c) from being backfilled with the interlayer film 34, and the width of the contact holes (30a-33c) is wide enough to prevent the contact holes (30a-33c) from being backfilled with the interlayer film 34.

[0067] 20, the interlayer film 34 on the bottom of the contact holes (30a to 33c) is etched using the patterned mask material 35. The corresponding substrate 26 or conductive layer (29a to 29d) is exposed at the bottom of each contact hole. The interlayer film 34 is left on the side of each contact hole.

[0068] Next, as shown in FIG. 21, the front electrode 36 and the back electrode 37 are deposited so as to cover the first main surface 1F and the second main surface 1R of the substrate 26. At this time, the inside of the contact holes (30a to 33c) is filled with the front electrode 36 or the back electrode 37, and the front electrode 36 and the back electrode 37 are electrically connected to the substrate 26 or the conductive layer (29a to 29d) exposed at the bottom of the contact holes (30a to 33c). Metal is generally used as the electrode material of the front electrode 36 and the back electrode 37. Specifically, Ti, Ni, and Mo can be used. The front electrode 36 and the back electrode 37 may be a laminated film such as Ti / Ni / Ag. The metal film can be formed by sputtering or electron beam (EB) deposition. The front electrode 36 corresponds to the high potential front electrode 38 and the low potential front electrode 39 before being divided, and the back electrode 37 corresponds to the high potential back electrode 40 and the low potential back electrode 41 before being divided.

[0069] 22, the mask material 42 is patterned by a general photolithography method, and parts of the front surface electrode 36 and the rear surface electrode 37 are etched by dry etching. As a result, the front surface electrode 36 is divided into a high-potential front surface electrode 38 and a low-potential front surface electrode 39, and the rear surface electrode 37 is divided into a high-potential rear surface electrode 40 and a low-potential rear surface electrode 41.

[0070] By removing the mask material 42, the semiconductor device according to the second embodiment shown in FIG. 14 is completed.

[0071] According to the second embodiment, in addition to obtaining the same effects as those of the first embodiment, the following effects can also be obtained.

[0072] When the first substrate 21 and the second substrate 24 are viewed in a direction perpendicular to their front and back surfaces, the grooves 23 and the cavities 25 each form a striped pattern. This makes it possible to prevent a decrease in capacitance when a multi-layer structure is formed of the dielectric layers (28a to 28d) and the conductive layers (29a to 29d).

[0073] When the bonded substrate 26 is viewed from a direction perpendicular to its first main surface after bonding, the longitudinal direction of the groove 23 intersects with the longitudinal direction of the cavity 25. By forming the intersecting stripe-shaped hole 27 (groove 23 and cavity 25), the aspect ratio of the hole 27 can be made higher than that of a single stripe shape.

[0074] A first substrate 21 having a groove 23 formed therein and a second substrate 24 having a cavity 25 formed therein are bonded together to form a substrate (bonded substrate 26). This makes it possible to form substrate 26 having hole 27 with a high aspect ratio. Therefore, a capacitor having a high capacitance density per unit area of ​​substrate 26 can be fabricated.

[0075] The first substrate 21 and the second substrate 24 are bonded together by thermal diffusion bonding, which allows the substrates to be bonded together with a strong bond.

[0076] The first substrate 21 and the second substrate 24 may be bonded together using an adhesive, which allows the substrates to be bonded together in a short time.

[0077] Third embodiment The configuration of a semiconductor device according to a third embodiment of the present invention will be described with reference to Fig. 23. The semiconductor device according to the third embodiment includes a substrate 47. The substrate 47 has a first main surface 1F (front surface) and a second main surface 1R (rear surface) that face each other. A groove 51 is formed in the first main surface 1F of the substrate 47. A cavity 48 connected to the groove 51 is formed inside the substrate 47.

[0078] 23, all of the grooves 51 and cavities 48 are connected, and some of the cavities 48 are exposed to the second main surface 1R of the substrate 47. This makes it possible to form holes (grooves 51 and cavities 48) that penetrate from the front surface to the back surface of the substrate 47, so that wiring electrodes can be formed on both the front and back surfaces of the substrate 47.

[0079] Substrate 47 shown in Fig. 23 corresponds to a bonded substrate obtained by overlapping and bonding the front and back surfaces of two substrates 26 shown in Fig. 14. That is, substrate 47 is a bonded substrate obtained by bonding a total of four substrates including a first substrate having groove 51 formed therein and second to fourth substrates having cavity 25 formed therein. The bonding method is the same as in the second embodiment, and description thereof will be omitted.

[0080] The semiconductor device according to the third embodiment is a capacitor that further includes at least one dielectric layer (28a, 28b, 28c, 28d) and at least one conductive layer (29a, 29b, 29c, 29d) alternately stacked on the surfaces of the groove 51 and the cavity 48, a high potential electrode (38, 40) (first electrode) electrically connected to at least one of the at least one conductive layer (29a to 29d) and the substrate 47, and a low potential electrode (39, 41) (second electrode) electrically connected to the conductive layer (29a to 29d) not electrically connected to the high potential electrode (38, 40) and the substrate 26, as in the second embodiment. The details of the operation of the dielectric layers (28a to 28d), the conductive layers (29a to 29d), the high potential electrodes (38, 40), the low potential electrodes (39, 41), and the capacitor are the same as those in the second embodiment, and therefore will not be described here.

[0081] Hereinafter, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to the drawings. Note that the method for manufacturing a semiconductor device described below is an example, and various other manufacturing methods may be used. Explanations of the same parts as in the second embodiment will be omitted.

[0082] First, as shown in Figures 24A and 24B, a portion of the first substrate 43, the second substrate 44, the third substrate 45, and the fourth substrate 46 is etched using a mask material to form a plurality of grooves 51 or cavities (52, 53, 54) penetrating the front and rear surfaces of the first substrate 43, the second substrate 44, the third substrate 45, and the fourth substrate 46. In the cross-sectional view of Figure 24A, the grooves 51 and the cavities 53 extend in a direction perpendicular to the paper surface. In the cross-sectional view of Figure 24A, the cavities (52, 54) extend in a direction parallel to the paper surface. When the first substrate 43, the second substrate 44, the third substrate 45, and the fourth substrate 46 are viewed in a direction perpendicular to their surfaces, the grooves 51 and the cavities (52, 53, 54) each have a stripe shape.

[0083] 25A and 25B, the first substrate 43 to the fourth substrate 46 are bonded together with their front and back surfaces overlapped to produce a bonded substrate 47. After bonding, the groove 51 on the first substrate 43, the cavity 52 on the second substrate 44, the cavity 53 on the third substrate 45, and the cavity 54 on the fourth substrate 46 are all connected. As a result, the groove 51 and the cavities (52 to 54) form holes that extend in the depth direction and horizontal direction of the bonded substrate 47. After bonding, when the bonded substrate 47 is viewed from a direction perpendicular to the first main surface 1F, the longitudinal direction of the groove 23 and the cavity 53 intersects with the longitudinal direction of the cavities (52, 54).

[0084] Next, similarly to the second embodiment, deposition of a dielectric layer and deposition of a conductive layer are alternately repeated four times. After deposition of the fourth conductive layer 29d, a dielectric layer (fifth dielectric layer 28e) is laminated above the first main surface 1F of the substrate 47 and below the second main surface 1R of the substrate 47, respectively.

[0085] Thereafter, the same processes as in the second embodiment are carried out to form contact holes (30a to 33c), high potential electrodes (38, 40), and low potential electrodes (39, 41), thereby completing the semiconductor device according to the third embodiment shown in FIG.

[0086] According to the third embodiment, the same effects as those of the second embodiment can be obtained.

[0087] (Other embodiments) For example, as shown in Fig. 27A, a substrate 71 is prepared having stripe-shaped grooves (61a-61c, 62a-62d) formed on its front and back surfaces. As shown in Fig. 27B, a plurality of similar substrates (71-74) are prepared. As shown in Fig. 27C, these substrates (71-74) may be bonded together with their front and back surfaces overlapping to form a single bonded substrate 81 (substrate).

[0088] The grooves (61a-61c) of the substrate 71 are formed on the front surface (first main surface) of the bonded substrate 81. A cavity connected to the grooves (61a-61c) of the substrate 71 is formed inside the bonded substrate 81. Here, the "cavity" in FIG. 27C includes the grooves (62a-62d) of the substrate 71 and the grooves (61a-61c, 62a-62d) of the substrates (72-74). All the grooves (61a-61c) of the substrate 71 and the "cavity" are connected, and a part of the "cavity", i.e., the grooves (62a-62d) of the substrate 74, is exposed on the back surface of the bonded substrate 81.

[0089] In the first to third embodiments, the width of the grooves and cavities in the direction parallel to the first main surface 1F is constant. However, the width of the grooves and cavities may be changed according to the depth of the grooves and cavities. Specifically, the width of at least one of the grooves and cavities in the direction parallel to the first main surface 1F may be wider as it approaches from the first main surface 1F to the second main surface 1R. Alternatively, the width of at least one of the grooves and cavities in the direction parallel to the first main surface 1F may be narrower as it approaches from the first main surface 1F to the second main surface 1R. By changing the width of the grooves and cavities along the depth direction of the substrate, it is possible to easily fill the grooves and cavities with the dielectric layer and the conductive layer. In addition, the surface area inside the grooves and cavities can be increased, so that the capacity density can be further increased.

[0090] The above-described embodiment is an example of a form for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible depending on the design and the like, even if the embodiment is other than the above, as long as the modifications do not deviate from the technical idea of ​​the present invention. [Explanation of symbols]

[0091] 1, 1a, 1b, 26, 47, 81 board 1F 1st main surface 1R Second main surface 3, 23, 51, 61a~61c groove 5, 25, 48, 52, 53, 54, 62a~62d hollow 6a-6e, 28a-28e Dielectric layers 7a~7d, 29a~29d conductive layer 16, 18, 38, 40 1st electrode (high potential electrode) 17, 19, 39, 41 2nd electrode (low potential electrode)

Claims

1. a substrate having a first main surface and a second main surface opposed to each other, a groove formed in the first main surface, and a cavity formed inside the substrate and connected to the groove; at least one dielectric layer and at least one conductive layer alternately stacked on the surfaces of the groove and the cavity; a first electrode electrically connected to at least one of the at least one conductive layer and the substrate; a second electrode electrically connected to at least one of the conductive layer not electrically connected to the first electrode or the substrate not electrically connected to the first electrode; Equipped with When viewed from a direction perpendicular to the first main surface, the grooves and the cavities each form a striped pattern; When viewed from a direction perpendicular to the first main surface, the longitudinal direction of the groove intersects with the longitudinal direction of the cavity. Capacitor.

2. A substrate having a first main surface and a second main surface opposed to each other, a groove formed in the first main surface, and a cavity formed inside the substrate and connected to the groove; at least one dielectric layer and at least one conductive layer alternately stacked on the surfaces of the groove and the cavity; a first electrode electrically connected to at least one of the at least one conductive layer and the substrate; a second electrode electrically connected to at least one of the conductive layer not electrically connected to the first electrode or the substrate not electrically connected to the first electrode; Equipped with A portion of the cavity is exposed to the second main surface. Capacitor.

3. A substrate having a first main surface and a second main surface opposed to each other, a groove formed in the first main surface, and a cavity formed inside the substrate and connected to the groove; at least one dielectric layer and at least one conductive layer alternately stacked on the surfaces of the groove and the cavity; a first electrode electrically connected to at least one of the at least one conductive layer and the substrate; a second electrode electrically connected to at least one of the conductive layer not electrically connected to the first electrode or the substrate not electrically connected to the first electrode; Equipped with The substrate is an insulator. Capacitor.

4. A substrate having a first main surface and a second main surface opposed to each other, a groove formed in the first main surface, and a cavity formed inside the substrate and connected to the groove; at least one dielectric layer and at least one conductive layer alternately stacked on the surfaces of the groove and the cavity; a first electrode electrically connected to at least one of the at least one conductive layer and the substrate; a second electrode electrically connected to at least one of the conductive layer not electrically connected to the first electrode or the substrate not electrically connected to the first electrode; Equipped with The surface of the groove or cavity is a (110) surface or a surface equivalent to a (111) surface. Capacitor.

5. The capacitor according to any one of claims 1 to 4, wherein the grooves or cavities form a repeating pattern of circular dots when viewed from a direction perpendicular to the first main surface.

6. 5. The capacitor according to claim 2, wherein the grooves and the cavities each form a striped pattern when viewed from a direction perpendicular to the first main surface.

7. The capacitor according to any one of claims 1 to 6, wherein the width of at least one of the groove and the cavity in a direction parallel to the first main surface becomes wider as it approaches the second main surface from the first main surface.

8. The capacitor according to any one of claims 1 to 6, wherein the width of at least one of the groove and the cavity in a direction parallel to the first main surface becomes narrower as it approaches the second main surface from the first main surface.

9. 9. The capacitor according to claim 1, wherein all of the cavities and the grooves are connected to each other.

10. 10. The capacitor according to claim 1, wherein a plurality of dielectric layers and a plurality of conductive layers are alternately laminated on the surfaces of the groove and the cavity.

11. 11. The capacitor according to claim 1, wherein the dielectric layer is a silicon oxide film.

12. 12. The capacitor according to claim 1, wherein the dielectric layer is a silicon nitride film.

13. 13. The capacitor according to claim 1, wherein the conductive layer is a polysilicon film.

14. 13. The capacitor according to claim 1, wherein the conductive layer is made of a metal.

15. The capacitor of claim 1, 2, or 4, wherein the substrate is an electrical conductor.

16. The capacitor of any one of claims 1, 2 and 4, wherein the substrate is a silicon substrate.

17. A substrate having a first main surface and a second main surface opposed to each other, a groove formed in the first main surface, and a cavity formed inside the substrate and connected to the groove; at least one dielectric layer and at least one conductive layer alternately stacked on the surfaces of the groove and the cavity; a first electrode electrically connected to at least one of the at least one conductive layer and the substrate; a second electrode electrically connected to at least one of the conductive layer not electrically connected to the first electrode or the substrate not electrically connected to the first electrode; 1. A method for manufacturing a capacitor comprising: A method for manufacturing a capacitor, comprising bonding a first substrate in which the groove is formed and a second substrate in which the cavity is formed to form the substrate.

18. The method for manufacturing a capacitor according to claim 17 , wherein the first substrate and the second substrate are bonded by thermal diffusion bonding.

19. The method for manufacturing a capacitor according to claim 17 , wherein the first substrate and the second substrate are bonded together using an adhesive.

20. The method for producing a capacitor according to any one of claims 17 to 19, wherein the groove and the cavity are formed by dry etching.

21. The method for manufacturing a capacitor according to any one of claims 17 to 19, wherein the groove and the cavity are formed by wet etching.

22. The method for producing a capacitor according to any one of claims 17 to 21, wherein the dielectric layer is formed by a low pressure CVD method.

23. The method for producing a capacitor according to any one of claims 17 to 21, wherein the dielectric layer is formed by atomic layer deposition.

24. The method for producing a capacitor according to any one of claims 17 to 23, wherein the conductive layer is formed by atomic layer deposition.

25. The method for producing a capacitor according to any one of claims 17 to 23, wherein the conductive layer is formed by metal organic chemical vapor deposition.

26. The method for producing a capacitor according to any one of claims 17 to 23, wherein the conductive layer is formed by plating growth.

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