Capacitor and manufacturing method thereof

Abstract

To suppress an increase in the number of contact holes even when the number of conductive layers laminated inside a groove 2 increases.SOLUTION: A conductive layer (4a to 4c) electrically connected to a first electrode 18 embedded in a first contact hole (15a, 15b) is arranged in the region excluding a region (6a to 6c) in which at least a second contact hole (13a, 13b) is formed in a first main surface 1F. A conductive layer (7a, 7b) electrically connected to a second electrode 19 embedded in a second contact hole (13a, 13b) is arranged in a region excluding a region (9a, 9b) in which at least the first contact hole (15a, 15b) is formed in the first main surface 1F.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a capacitor and a method for manufacturing the same. [Background technology]

[0002] Trench capacitors are known in which a layer sequence of alternating conductive polysilicon layers and dielectric layers is buried inside a pore in a substrate (see US Pat. No. 5,399,313), in which the layer sequence buried inside the pore is continued on the top surface of the substrate and contact structures for the electrodes are provided. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2009-515353 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a portion (contact hole) for connecting each conductive polysilicon layer to an electrode is provided on the surface of the substrate for each conductive polysilicon layer. Therefore, when the number of laminated conductive polysilicon layers increases, the number of contact holes provided on the surface of the substrate also increases.

[0005] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a capacitor and a manufacturing method thereof that can suppress an increase in the number of contact holes even if the number of conductive layers stacked inside a groove increases. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, in a capacitor according to one aspect of the present invention, a conductive layer electrically connected to a first electrode embedded in a first contact hole is disposed in a region of the first main surface excluding at least a region in which a second contact hole is formed, and a conductive layer electrically connected to a second electrode embedded in a second contact hole is disposed in a region of the first main surface excluding at least a region in which a first contact hole is formed. Effect of the Invention

[0007] According to one aspect of the present invention, even if the number of conductive layers stacked inside the trench increases, an increase in the number of contact holes can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a cross-sectional view (part 1) showing a process of a method for manufacturing the semiconductor device shown in FIG. [Figure 2B] FIG. 2B is a perspective view showing the step shown in FIG. 2A. [Diagram 3] 3A to 3C are cross-sectional views (part 2) illustrating steps of the method for manufacturing the semiconductor device shown in FIG. [Figure 4] 4A to 4C are cross-sectional views (part 3) illustrating steps of the method for manufacturing the semiconductor device shown in FIG. [Diagram 5] 5A to 5C are cross-sectional views (part 4) illustrating steps in the method for manufacturing the semiconductor device shown in FIG. [Figure 6] 6A to 6C are cross-sectional views (part 5) illustrating steps in the method for manufacturing the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view (part 6) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view (part 7) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 9]FIG. 9 is a cross-sectional view (part 8) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a ninth cross-sectional view showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view (part 10) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view (part 11) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view (part 12) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view (part 13) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 16] 16A to 16C are cross-sectional views (part 1) showing steps of a method for manufacturing the semiconductor device shown in FIG. [Figure 17] 17A to 17C are cross-sectional views (part 2) showing the steps of the method for manufacturing the semiconductor device shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view (part 3) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view (part 4) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view (part 5) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view (part 6) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view (part 7) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Diagram 23] FIG. 23 is a cross-sectional view (part 8) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 24]FIG. 24 is a sectional view (part 9) showing a process of the method for manufacturing the semiconductor device shown in FIG. [Figure 25A] FIG. 25A is a perspective view corresponding to the cross-sectional view shown in FIG. [Figure 25B] FIG. 25B is a perspective view (part 1) corresponding to the cross-sectional view shown in FIG. [Figure 25C] FIG. 25C is a perspective view (part 2) corresponding to the cross-sectional view shown in FIG. [Figure 25D] FIG. 25D is a perspective view corresponding to the cross-sectional view shown in FIG. [Figure 26] FIG. 26 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. In the description of the drawings, the same parts are given the same reference numerals and the description will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, and the like include parts that differ from the actual ones. In addition, there are parts where the dimensional relationships and ratios differ between the drawings.

[0010] (First embodiment) The configuration of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. 1. The semiconductor device according to the first embodiment includes a substrate 1. The substrate 1 has a first main surface 1F and a second main surface 1R facing each other, and a groove 2 formed on the first main surface 1F. As shown in the perspective view of FIG. 25A, the substrate 1 is made of a plurality of comb teeth 41 and a support portion 42 that supports the comb teeth 41. The cross-sectional view of FIG. 1 shows the cross-sectional structure of the plurality of comb teeth 41 shown in FIG. 25A. The groove 2 is a gap disposed between adjacent comb teeth 41, and the groove 2 penetrates the substrate 1 to reach the second main surface 1R. The substrate 1 is a single crystal substrate made of silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). The substrate 1 is doped with a high concentration of N-type or P-type impurities, and is used as a conductor like a conductive layer described later.

[0011] The semiconductor device includes at least one dielectric layer 3 and at least one conductive layer (4a-4c, 7a, 7b) alternately stacked on at least the groove 2 and the first main surface. In the first embodiment, five dielectric layers 3 and five conductive layers (4a-4c, 7a, 7b) are alternately stacked inside the groove 2, the first main surface 1F, and the second main surface 1R. The conductive layers (4a-4c, 7a, 7b) are electrically insulated from each other by the dielectric layer 3. Each of the five conductive layers (4a-4c, 7a, 7b) and the five dielectric layers 3 is continuously formed on the first main surface 1F, inside the groove 2, and the second main surface 1R. The number of dielectric layers and conductive layers stacked inside the groove 2 is determined by the width of the groove and the thickness of the dielectric layers and conductive layers, and may be 1 to 3 layers, or 5 layers or more.

[0012] Hereinafter, the five conductive layers (4a to 4c, 7a, 7b) shown in FIG. 1 may be individually referred to as the first high potential conductive layer 4a, the first low potential conductive layer 7a, the second high potential conductive layer 4b, the second low potential conductive layer 7b, and the third high potential conductive layer 4c, in that order from the side closest to the substrate 1.

[0013] The semiconductor device includes a high potential surface electrode 18 (first electrode) embedded in a first contact hole (15a, 15b) formed on the first main surface 1F, and a low potential surface electrode 19 (second electrode) embedded in a second contact hole (13a, 13b) formed on the first main surface 1F. The high potential surface electrode 18 is electrically connected to at least one of at least one conductive layer (4a to 4c) and the substrate 1. The low potential surface electrode 19 is electrically connected to a conductive layer (7a, 7b) that is not electrically connected to the high potential surface electrode 18 and the substrate 1. In the embodiment, the high potential surface electrode corresponds to the first electrode, and the high potential surface electrode corresponds to the second electrode, but the opposite is also possible.

[0014] In the first embodiment, two first contact holes (15a, 15b) are formed on the first main surface 1F, and a high-potential surface electrode 18 is formed on the side and bottom surfaces of the first contact holes (15a, 15b). The high-potential surface electrode 18 is in contact with and electrically connected to the first high-potential conductive layer 4a at the bottom surfaces of the first contact holes (15a, 15b), and is in contact with and electrically connected to the second high-potential conductive layer 4b and the third high-potential conductive layer 4c at the side surfaces of the first contact holes (15a, 15b).

[0015] Similarly, two second contact holes (13a, 13b) are formed on the first main surface 1F, and low potential surface electrodes 19 are formed on the side and bottom surfaces of the second contact holes (13a, 13b). The low potential surface electrode 19 is in contact with and electrically connected to the substrate 1 at the bottom surfaces of the second contact holes (13a, 13b), and is in contact with and electrically connected to the first low potential conductive layer 7a and the second low potential conductive layer 7b at the side surfaces of the second contact holes (13a, 13b).

[0016] The conductive layers (first low potential conductive layer 7a and second low potential conductive layer 7b) electrically connected to the low potential surface electrode 19 (second electrode) are arranged in a region of the first main surface 1F excluding at least the region (9a, 9b) in which the first contact holes (15a, 15b) are formed. That is, the first low potential conductive layer 7a and the second low potential conductive layer 7b are not arranged in the region (9a, 9b) in which the first contact holes (15a, 15b) are formed on the first main surface 1F. Therefore, the first low potential conductive layer 7a and the second low potential conductive layer 7b are not exposed to the side surfaces of the first contact holes (15a, 15b), and the high potential surface electrode 18 is electrically insulated from the first low potential conductive layer 7a and the second low potential conductive layer 7b.

[0017] The conductive layers (first high potential conductive layer 4a, second high potential conductive layer 4b, and third high potential conductive layer 4c) electrically connected to the high potential surface electrode 18 (first electrode) are arranged in a region of the first main surface 1F excluding at least the region (6a to 6c) in which the second contact holes (13a, 13b) are formed. That is, the first high potential conductive layer 4a, the second high potential conductive layer 4b, and the third high potential conductive layer 4c are not arranged in the region (6a to 6c) in which the second contact holes (13a, 13b) are formed on the first main surface 1F. Therefore, the first high potential conductive layer 4a, the second high potential conductive layer 4b, and the third high potential conductive layer 4c are not exposed to the side surfaces of the second contact holes (13a, 13b), and the low potential surface electrode 19 is electrically insulated from the first high potential conductive layer 4a, the second high potential conductive layer 4b, and the third high potential conductive layer 4c.

[0018] A silicon oxide film can be used for the dielectric layer 3. This allows operation at a high voltage. Alternatively, a silicon nitride film with a high dielectric constant can be used for the dielectric layer 3. This allows the capacitance density to be improved. Alternatively, a laminated film of a silicon oxide film and a silicon nitride film can be used for each dielectric layer 3.

[0019] The conductive layers (4a to 4c, 7a, 7b) may be made of polysilicon. This allows the conductive layers (4a to 4c, 7a, 7b) to be uniformly grown along the surfaces of the trenches 2 using a low-pressure CVD method. Alternatively, the conductive layers (4a to 4c, 7a, 7b) may be made of metal. In this case, the equivalent series resistance (ESR) of the conductive layers (4a to 4c, 7a, 7b) may be reduced.

[0020] The basic operation of the semiconductor device shown in FIG. 1 as a capacitor will be described. A positive voltage is applied to the high potential surface electrode 18, and a negative voltage is applied to the low potential surface electrode 19. As a result, a positive charge is charged to the conductive layers (4a to 4c) electrically connected to the high potential surface electrode 18, and a negative charge is charged to the substrate 1 and conductive layers (7a, 7b) electrically connected to the low potential surface electrode 19. At this time, polarization occurs inside the dielectric layer 3, generating capacitance. A low potential voltage is applied to the substrate 1 and the two low potential conductive layers (7a, 7b), and a high potential voltage is applied to the three high potential conductive layers (4a to 4c), resulting in a structure in which five layers of capacitors are connected in parallel, and the capacitance density per unit area can be greatly improved.

[0021] By embedding the high potential surface electrode 18 and the low potential surface electrode 19 in the first contact holes (15a, 15b) and the second contact holes (13a, 13b), respectively, the high potential surface electrode 18 and the low potential surface electrode 19 can be electrically connected together to the conductive layers (4a to 4c, 7a, 7b) and / or the substrate 1. Since it is not necessary to form contact holes (15a, 15b, 13a, 13b) for each conductive layer (4a to 4c, 7a, 7b) or for each of the conductive layers (4a to 4c, 7a, 7b) and the substrate 1, the number of contact holes required on the first main surface 1F is reduced. Therefore, even if the number of conductive layers stacked inside the groove increases, it is possible to suppress an increase in the number of contact holes formed on the first main surface 1F. In addition, by increasing the area of ​​the conductive layers stacked on the first main surface 1F of the substrate 1, the capacitance density of the capacitor can be improved.

[0022] The high-potential conductive layers (4a to 4c) electrically connected to the high-potential surface electrode 18 are disposed in a region of the first main surface 1F excluding at least the region (6a to 6c) in which the second contact holes (13a, 13b) are formed, so that the high-potential conductive layers (4a to 4c) electrically connected to the high-potential surface electrode 18 can be electrically insulated from the low-potential surface electrode 19 embedded in the second contact holes (13a, 13b). On the other hand, the conductive layers (7a, 7b) electrically connected to the low-potential surface electrode 19 are disposed in a region of the first main surface 1F excluding at least the region (9a, 9b) in which the first contact holes (15a, 15b) are formed, so that the conductive layers (7a, 7b) electrically connected to the low-potential surface electrode 19 can be electrically insulated from the high-potential surface electrode 18 embedded in the first contact holes (15a, 15b). This ensures electrical insulation between the high potential electrode 18 and the high potential conductive layers (4a to 4c) constituting the capacitor and the low potential electrode 19 and the low potential conductive layers (7a, 7b).

[0023] The high potential surface electrode 18 is electrically connected to at least one conductive layer (4a, 4b, 4c) through the first contact holes (15a, 15b). In this embodiment, the high potential surface electrode 18 is electrically connected to three conductive layers (4a, 4b, 4c) through the first contact holes (15a, 15b). Since the high potential surface electrode 18 can be electrically connected to multiple conductive layers (4a, 4b, 4c) through each of the first contact holes (15a, 15b), the number of contact holes can be reduced.

[0024] The low potential surface electrode 19 is electrically connected through the second contact holes (13a, 13b) to the conductive layers (7a, 7b) that are not electrically connected to the high potential surface electrode 18 and to the substrate 1. Since the low potential surface electrode 19 can be electrically connected to a plurality of conductive layers (7a, 7b) and the substrate 1 through the second contact holes (13a, 13b), the number of contact holes can be reduced.

[0025] The high potential surface electrode 18 is electrically connected to at least one conductive layer (4b, 4c) on the side of the first contact hole (15a, 15b). In this embodiment, the high potential surface electrode 18 is electrically connected to two conductive layers (4b, 4c) on the side of each of the first contact holes (15a, 15b). Electrical connections with multiple conductive layers (4b, 4c) can be easily formed within one contact hole (15a, 15b).

[0026] The low potential surface electrode 19 is electrically connected on the side surface of the second contact hole (13a, 13b) to the conductive layer (7a, 7b) that is not electrically connected to the high potential surface electrode 18. Electrical connections with multiple conductive layers (7a, 7b) can be easily formed within one contact hole (13a, 13b).

[0027] The groove 2 reaches the second main surface 1R of the substrate 1. By forming the trench (groove) in the substrate 1 until it reaches the back surface (second main surface 1R) of the substrate 1, the dielectric layer 3 and the conductive layer (4a to 4c, 7a, 7b) having a symmetric structure can be formed on the front surface (first main surface 1F) and the back surface (second main surface 1R) of the substrate 1, respectively, and warping of the substrate 1 caused by the stress of the dielectric layer 3 can be mitigated.

[0028] At least one dielectric layer 3 and at least one conductive layer (4a-4c, 7a, 7b) are alternately laminated on the second main surface 1R of the substrate 1. This allows the dielectric layer 3 and the conductive layer (4a-4c, 7a, 7b) having a symmetric structure to be formed on the front surface (first main surface 1F) and back surface (second main surface 1R) of the substrate 1, respectively, and makes it possible to reduce warping of the substrate 1 caused by the stress of the dielectric layer 3.

[0029] The substrate 1 is a conductor. Since the substrate 1 can be used as a conductive layer, the capacitance density of the capacitor is improved. Of course, this is not limited to this, and the substrates (1a, 1b) may be semiconductors or insulators. Being an insulator makes it easier to separate elements.

[0030] Hereinafter, a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. Note that the method for manufacturing a semiconductor device described below is an example, and various other manufacturing methods can be used.

[0031] First, a semiconductor substrate (substrate 1) doped with a high concentration of N-type or P-type impurities is prepared. When using a Si substrate, an N-type semiconductor substrate can be manufactured by adding a pentavalent element impurity such as phosphorus (P) or arsenic (As), and a P-type semiconductor substrate can be manufactured by adding a trivalent element impurity such as boron (B) or gallium (Ga).

[0032] Next, as shown in FIG. 2A and FIG. 2B, a part of the substrate 1 is etched from the first main surface 1F to the second main surface 1R of the substrate 1 to form a groove 2. The cross-sectional view of FIG. 2A shows the AA cut surface of FIG. 2B. The substrate 1 of FIG. 2A corresponds to the comb-tooth portion 41 of the substrate 1 in FIG. 2B. Specifically, first, a mask material is formed on the first main surface 1F of the substrate 1. A silicon oxide film can be used as the mask material, and a thermal CVD method or a plasma CVD method can be used as a deposition method. Next, a resist is patterned on the mask material. A general photolithography method can be used as a patterning method. The mask material is etched using the patterned resist as a mask. As shown in FIG. 2A and FIG. 2B, the mask material has an opening in a portion where the groove 2 is to be formed. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. Next, the resist is removed with oxygen plasma, sulfuric acid, or the like. Using the mask material thus formed, the substrate 1 exposed through the openings in the mask material is etched by dry etching to form the grooves 2.

[0033] 2A and 2B, a dielectric layer 3 is deposited on the inner surface of the trench 2 and the surface of the substrate 1 including the first main surface 1F and the second main surface 1R so as to cover the substrate 1. A silicon oxide film can be used as the dielectric layer 3, and a thermal oxidation method or a thermal CVD method can be used as the deposition method. When using the thermal CVD method, a silicon oxide film can be deposited with good coverage by reducing the pressure under reduced pressure conditions, even if the trench 2 is deep.

[0034] Next, as shown in FIG. 3, a conductive layer (first high-potential conductive layer 4a) is deposited on the surface of the substrate 1 including the inner surface of the groove 2 and the first and second main surfaces 1F and 1R so as to cover the dielectric layer 3. Here, a polysilicon film is used as an example of the conductive layer. After the deposition of the polysilicon film, an annealing process is performed in POCL3 at 950° C. to form an N-type polysilicon film, which makes the conductive layer conductive. Here, a polysilicon film is used as an example of the conductive layer, but other metal films such as titanium (Ti) and aluminum (Al) and metal silicide films can also be used. A low-pressure CVD method can be used as a method for depositing the polysilicon film. Through the above steps, the dielectric layer 3 and the first high-potential conductive layer 4a are laminated in order on the surface of the substrate 1.

[0035] Next, as shown in FIG. 4, a mask material 5 made of a silicon oxide film is formed on the first main surface 1F of the substrate 1, and the mask material 5 is patterned using lithography and etching techniques. The patterned mask material 5 has openings in regions 6a where the second contact holes (13a, 13b) are to be formed. Etching is performed using the mask material 5, and the first high-potential conductive layer 4a exposed from the openings in the mask material 5 is selectively etched. Anisotropic etching may be used as the etching method. The first high-potential conductive layer 4a in the region 6a is removed, and the dielectric layer 3 is exposed. By providing directionality to the etching direction, the region 6a can be formed without etching the dielectric layer 3 and the first high-potential conductive layer 4a deposited on the side surface of the groove 2.

[0036] At this time, as shown in Fig. 25B, the openings (regions 6a) of the mask material 5 are formed only in portions 51 on the tip side of the comb-tooth portions 41. Therefore, the remaining main body portions 52 including the base portions and support portions of the comb-tooth portions 41 are covered with the mask material 5, and the first high potential conductive layers 4a are left without being removed. As a result, as shown in Fig. 25C, the first high potential conductive layers 4a left on the side surfaces of the grooves 2 are electrically connected to each other via the main body portions 52.

[0037] 5, a dielectric layer 3 is deposited on the inner surface of the groove 2 and the surface of the substrate 1 including the first main surface 1F and the second main surface 1R so as to cover the first high potential conductive layer 4a. At this time, the dielectric layer 3 is also formed in the region 6a where the second contact holes (13a, 13b) are to be formed.

[0038] 6, a first low potential conductive layer 7a is deposited on the surface of the substrate 1 including the inner surface of the groove 2 and the first and second main surfaces 1F and 1R so as to cover the dielectric layer 3. The material and deposition method of the first low potential conductive layer 7a are the same as those of the first high potential conductive layer 4a.

[0039] Next, as shown in FIG. 7, a mask material 8 made of a silicon oxide film is formed on the first main surface 1F of the substrate 1, and the mask material 8 is patterned using lithography and etching techniques. The patterned mask material 8 has openings in regions 9a where the first contact holes (15a, 15b) are to be formed. Etching is performed using the mask material 8, and the first low-potential conductive layer 7a exposed from the openings in the mask material 8 is selectively etched. Anisotropic etching may be used as the etching method. The first low-potential conductive layer 7a in the region 9a is removed, and the dielectric layer 3 is exposed. By providing directionality to the etching direction, the region 9a can be formed without etching the dielectric layer 3 and the first low-potential conductive layer 7a deposited on the side surface of the groove 2.

[0040] At this time, similarly to the first high-potential conductive layer 4a, the openings (regions 9a) of the mask material 8 are formed only in portions 51 on the tip side of the comb-tooth portions 41. Therefore, the main body portions 52 including the base portions of the comb-tooth portions 41 and the support portions 42 are covered with the mask material 8, and the first low-potential conductive layers 7a are left without being removed. As a result, the first low-potential conductive layers 7a left on the side surfaces of the grooves 2 are electrically connected to each other via the main body portions 52.

[0041] Next, the deposition of the dielectric layer 3 shown in Figures 2A and 2B, the deposition and etching of the conductive layer (first high potential conductive layer 4a) shown in Figures 3 and 4, the deposition of the dielectric layer 3 shown in Figure 5, and the deposition and etching of the conductive layer (first low potential conductive layer 7a) shown in Figures 6 and 7 are repeatedly performed. As a result, as shown in Figure 8, the first high potential conductive layer 4a, the first low potential conductive layer 7a, the second high potential conductive layer 4b, the second low potential conductive layer 7b, and the first high potential conductive layer 4c are laminated on the surface of the substrate 1 via the dielectric layer 3, in order from the side closest to the substrate 1, and the groove 2 is backfilled. The two high potential conductive layers (4a, 5b) are formed in the first main surface 1F of the substrate 1, except for the regions (6a, 6b) where the second contact holes (13a, 13b) are to be formed. The two low potential conductive layers (7a, 7b) are formed on the first main surface 1F of the substrate 1 except for the regions (9a, 9b) where the first contact holes (15a, 15b) are to be formed.

[0042] Next, as shown in FIG. 9, a mask material 10 made of a silicon oxide film is formed on the first main surface 1F of the substrate 1, and the mask material 10 is patterned using lithography and etching techniques. The patterned mask material 5 has openings in regions 6c where second contact holes (13a, 13b) are to be formed. Etching is performed using the mask material 10, and the third high potential conductive layer 4c exposed from the openings in the mask material 10 is selectively etched. Anisotropic etching may be used as the etching method. The third high potential conductive layer 4c in the region 6c is removed to expose the dielectric layer 3.

[0043] 10, an interlayer film 11 is deposited on the first main surface 1F and the second main surface 1R of the substrate 1. The interlayer film 11 may be a silicon oxide film.

[0044] 11, a mask material 12 is formed on the first main surface 1F of the substrate 1, and the mask material 12 is patterned using lithography and etching techniques. The patterned mask material 12 has openings for forming second contact holes (13a, 13b). Using the mask material 12, the interlayer film 11, the dielectric layer 3, the second low potential conductive layer 7b, the dielectric layer 3, the first low potential conductive layer 7a, and the dielectric layer 3 exposed from the openings of the mask material 12 are etched in this order. As a result, the second contact holes (13a, 13b) are formed through which the substrate 1 is exposed.

[0045] 12, a mask material 14 is formed on the first main surface 1F of the substrate 1, and the mask material 14 is patterned using lithography and etching techniques. The patterned mask material 14 has openings for forming first contact holes (15a, 15b). Using the mask material 14, the interlayer film 11, the third high potential conductive layer 4c, the dielectric layer 3, the second high potential conductive layer 4b, and the dielectric layer 3 exposed from the openings of the mask material 14 are etched in this order. As a result, the first contact holes (15a, 15b) are formed through which the first high potential conductive layer 4a is exposed.

[0046] Next, as shown in FIG. 13, the surface electrode 16 is deposited so as to cover the first main surface 1F of the substrate 1. At this time, the surface electrode 16 is also deposited on the bottom and side surfaces of the contact holes (15a, 15b, 13a, 13b). The surface electrode 16 is electrically connected to the substrate 1 and the conductive layers (4a to 4c, 7a, 7b) exposed on the bottom and side surfaces of the contact holes (15a, 15b, 13a, 13b). Metal is generally used as the electrode material of the surface electrode 16. Specifically, titanium (Ti), nickel (Ni), and molybdenum (Mo) can be used. The surface electrode 16 may also be a laminated film of Ti / Ni / silver (Ag) or the like. The metal film can be formed by sputtering or electron beam (EB) deposition. The surface electrode 16 corresponds to the high potential surface electrode 18 and the low potential surface electrode 19 before being divided.

[0047] 14, the mask material 17 is patterned by a typical photolithography method, and a part of the surface electrode 16 is etched by dry etching using the patterned mask material 17. As a result, the surface electrode 16 is divided into a high-potential surface electrode 18 and a low-potential surface electrode 19.

[0048] By removing the mask material 17, the semiconductor device according to the first embodiment shown in FIG. 1 is completed.

[0049] By forming the grooves 2 by dry etching, it is possible to form the grooves 2 with a high aspect ratio.

[0050] The grooves 2 may be formed by wet etching, which allows the grooves 2 to be formed at low cost.

[0051] By removing the high potential conductive layers (4a to 4c) in the regions (6a to 6c) where the second contact holes (13a, 13b) are to be formed by dry etching, the size of the second contact holes (13a, 13b) can be made smaller.

[0052] The dielectric layer 3 may be formed by low pressure CVD. This allows the dielectric layer 3 to grow uniformly along the surface of the trench 2. The dielectric layer 3 may also be formed by atomic layer deposition (ALD). This allows the dielectric layer 3 to grow uniformly along the surface of the trench 2.

[0053] The conductive layers (4a to 4c, 7a, 7b) can be formed by atomic layer deposition (ALD). This allows the conductive layers (4a to 4c, 7a, 7b) to grow uniformly along the surface of the groove 2. The conductive layers (4a to 4c, 7a, 7b) may be formed by metal organic chemical vapor deposition (MOCVD). This allows the conductive layers (4a to 4c, 7a, 7b) to grow uniformly along the surface of the groove 2. The conductive layers (4a to 4c, 7a, 7b) may be formed by plating growth. This allows the equivalent series resistance (ESR) to be reduced.

[0054] Second embodiment The configuration of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. 15. The semiconductor device according to the second embodiment is different from the semiconductor device shown in FIG. 1 in that the second main surface 1R of the substrate 1 further includes electrodes similar to the high potential surface electrode 18 and the low potential surface electrode 19 on the first main surface 1F, that is, a high potential back surface electrode 22 (first electrode) and a low potential back surface electrode 23 (second electrode). The conductive layers (first high potential conductive layer 4a, second high potential conductive layer 4b, and third high potential conductive layer 4c) electrically connected to the high potential back surface electrode 22 are disposed in the second main surface 1R, except for the region (6d to 6f) in which the second contact holes (20a, 20b) are formed. The conductive layers (first low potential conductive layer 7a and second low potential conductive layer 7b) electrically connected to the low potential back surface electrode 23 are disposed in the second main surface 1R, except for the region (9c, 9d) in which the first contact holes (21a, 21b) are formed.

[0055] In addition, the substrate 1, the first high potential conductive layer 4a, the first low potential conductive layer 7a, the second high potential conductive layer 4b, the second low potential conductive layer 7b, the third high potential conductive layer 4c, the dielectric layer 3, the contact holes (13a, 13b, 15a, 15b) on the first main surface 1F side, the high potential surface electrode 18, and the low potential surface electrode 19 are the same as those in Figure 1, so a repeated explanation will be omitted.

[0056] The semiconductor device according to the second embodiment includes a high-potential back electrode 22 (first electrode) embedded in a first contact hole (21a, 21b) formed on the second main surface 1R, and a low-potential back electrode 23 (second electrode) embedded in a second contact hole (20a, 20b) formed on the second main surface 1R. The high-potential back electrode 22 is electrically connected to at least one of at least one conductive layer (4a to 4c) and the substrate 1. The low-potential back electrode 23 is electrically connected to a conductive layer (7a, 7b) that is not electrically connected to the high-potential back electrode 22 and the substrate 1. In the embodiment, the high-potential back electrode corresponds to the first electrode, and the high-potential back electrode corresponds to the second electrode, but the reverse may be true.

[0057] In the second embodiment, two first contact holes (21a, 21b) are formed on the second main surface 1R, and a high-potential back electrode 22 is formed on the side and bottom surfaces of the first contact holes (21a, 21b). The high-potential back electrode 22 is in contact with and electrically connected to the first high-potential conductive layer 4a at the bottom surfaces of the first contact holes (21a, 21b), and is in contact with and electrically connected to the second high-potential conductive layer 4b and the third high-potential conductive layer 4c at the side surfaces of the first contact holes (21a, 21b).

[0058] Similarly, two second contact holes (20a, 20b) are formed on the second main surface 1R, and a low-potential back electrode 23 is formed on the side and bottom surfaces of the second contact holes (20a, 20b). The low-potential back electrode 23 is in contact with and electrically connected to the substrate 1 at the bottom surfaces of the second contact holes (20a, 20b), and is in contact with and electrically connected to the first low-potential conductive layer 7a and the second low-potential conductive layer 7b at the side surfaces of the second contact holes (20a, 20b).

[0059] The conductive layers (first low potential conductive layer 7a and second low potential conductive layer 7b) electrically connected to the low potential back electrode 23 (second electrode) are arranged in a region of the second main surface 1R excluding at least the region (9c, 9d) in which the first contact holes (21a, 21b) are formed. That is, the first low potential conductive layer 7a and the second low potential conductive layer 7b are not arranged in the region (9c, 9d) in which the first contact holes (21a, 21b) are formed on the second main surface 1R. Therefore, the first low potential conductive layer 7a and the second low potential conductive layer 7b are not exposed to the side surfaces of the first contact holes (21a, 21b), and the high potential back electrode 22 is electrically insulated from the first low potential conductive layer 7a and the second low potential conductive layer 7b.

[0060] The conductive layers (first high potential conductive layer 4a, second high potential conductive layer 4b, and third high potential conductive layer 4c) electrically connected to the high potential back electrode 22 (first electrode) are arranged in a region of the second main surface 1R excluding at least the region (6d to 6f) in which the second contact holes (20a, 20b) are formed. That is, the first high potential conductive layer 4a, the second high potential conductive layer 4b, and the third high potential conductive layer 4c are not arranged in the region (6d to 6f) in which the second contact holes (20a, 20b) are formed on the second main surface 1R. Therefore, the first high potential conductive layer 4a, the second high potential conductive layer 4b, and the third high potential conductive layer 4c are not exposed to the side surfaces of the second contact holes (20a, 20b), and the low potential back electrode 23 is electrically insulated from the first high potential conductive layer 4a, the second high potential conductive layer 4b, and the third high potential conductive layer 4c.

[0061] The basic operation of the semiconductor device shown in FIG. 15 as a capacitor will be described. A positive voltage is applied to the high potential surface electrode 18 and the high potential back electrode 22, and a negative voltage is applied to the low potential surface electrode 19 and the low potential back electrode 23. As a result, a positive charge is charged to the conductive layers (4a-4c) electrically connected to the high potential surface electrode 18 and the high potential back electrode 22, and a negative charge is charged to the substrate 1 and the conductive layers (7a, 7b) electrically connected to the low potential surface electrode 19 and the low potential back electrode 23. At this time, polarization occurs inside the dielectric layer 3, and electrostatic capacitance is generated. At this time, a low potential voltage is applied to the substrate 1 and the two low potential conductive layers (7a, 7b), and a high potential voltage is applied to the three high potential conductive layers (4a-4c), resulting in a structure in which five layers of capacitors are connected in parallel, and the capacitance density per unit area can be greatly improved.

[0062] According to the capacitor shown in FIG. 15, in addition to the same effects as those of the first embodiment, the following effects can also be obtained.

[0063] The high-potential back electrode 22 is also embedded in the first contact holes (21a, 21b) formed on the second main surface 1R of the substrate 1. By providing the high-potential electrodes on both sides (1F, 1R) of the substrate 1, the capacitor (semiconductor device) can be easily mounted on a module or the like. By forming contact holes (15a, 15b, 13a, 13b, 21a, 21b, 20a, 20b) on both sides of the substrate 1, the number of contact holes per unit area of ​​the substrate 1 can be increased, and the ESR can be reduced.

[0064] The low potential back electrode 23 is also embedded in the second contact holes (20a, 20b) formed on the second main surface 1R of the substrate 1. By providing the low potential electrodes on both sides (1F, 1R) of the substrate 1, the capacitor (semiconductor device) can be easily mounted on a module or the like. By forming contact holes (15a, 15b, 13a, 13b, 21a, 21b, 20a, 20b) on both sides of the substrate 1, the number of contact holes per unit area of ​​the substrate 1 can be increased, and the ESR can be reduced.

[0065] Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. Note that the method for manufacturing a semiconductor device described below is an example, and various other manufacturing methods may be used.

[0066] First, a semiconductor substrate (substrate 1) doped with a high concentration of N-type or P-type impurities is prepared, and a groove 2 is formed by etching a part of the substrate 1 from the first main surface 1F to the second main surface 1R of the substrate 1, as shown in Fig. 16. Next, a dielectric layer 3 is deposited on the inner surface of the groove 2 and the surface of the substrate 1 including the first main surface 1F and the second main surface 1R so as to cover the substrate 1.

[0067] Next, as shown in FIG. 17, a conductive layer (first high potential conductive layer 4a) is deposited on the surface of the substrate 1 including the inner surfaces of the grooves 2 and the first and second main surfaces 1F and 1R so as to cover the dielectric layer 3.

[0068] Next, as shown in FIG. 18, a mask material 5 made of a silicon oxide film is formed on the first main surface 1F and the second main surface 1R of the substrate 1, and the mask material 5 is patterned using lithography and etching techniques. The patterned mask material 5 has openings in regions (6a, 6d) where the second contact holes (13a, 13b, 20a, 20b) are to be formed. Etching is performed using the mask material 5, and the first high potential conductive layer 4a exposed from the openings in the mask material 5 is selectively etched. By providing directionality to the etching direction, the regions (6a, 6d) can be formed without etching the dielectric layer 3 and the first high potential conductive layer 4a deposited on the side surface of the groove 2.

[0069] At this time, as shown in Fig. 25B, the openings (regions 6a) of the mask material 5 are formed only in portions 51 on the tip side of the comb-tooth portions 41. Therefore, the main body portions 52 are covered with the mask material 5, and the first high potential conductive layers 4a are left without being removed. As a result, as shown in Fig. 25C, the first high potential conductive layers 4a left on the side surfaces of the grooves 2 are electrically connected to each other via the main body portions 52 of the comb-tooth portions 41.

[0070] 19, a dielectric layer 3 is deposited on the inner surfaces of the grooves 2 and the surface of the substrate 1 including the first main surface 1F and the second main surface 1R so as to cover the first high potential conductive layer 4a. At this time, the dielectric layer 3 is also formed in the regions (6a, 6d) where the second contact holes (13a, 13b, 20a, 20b) are to be formed.

[0071] Next, as shown in FIG. 20, a first low potential conductive layer 7a is deposited on the surface of the substrate 1 including the inner surface of the groove 2 and the first and second main surfaces 1F and 1R so as to cover the dielectric layer 3.

[0072] Next, as shown in FIG. 21, a mask material 8 made of a silicon oxide film is formed on the first main surface 1F and the second main surface 1R of the substrate 1, and the mask material 8 is patterned using lithography and etching techniques. The patterned mask material 8 has openings in regions (9a, 9c) where the first contact holes (15a, 15b, 21a, 21b) are to be formed. Etching is performed using the mask material 8, and the first low-potential conductive layer 7a exposed from the openings in the mask material 8 is selectively etched. By providing directionality to the etching direction, the regions (9a, 9c) can be formed without etching the dielectric layer 3 and the first low-potential conductive layer 7a deposited on the side surface of the groove 2.

[0073] At this time, similarly to the first high-potential conductive layer 4a, the openings (regions 9a) of the mask material 8 are formed only in portions 51 on the tip side of the comb-tooth portions 41. Therefore, the main body portions 52 are covered with the mask material 8, and the first low-potential conductive layers 7a are left without being removed. As a result, the first low-potential conductive layers 7a left on the side surfaces of the grooves 2 are electrically connected to each other via the main body portions 52.

[0074] Next, the deposition of the dielectric layer 3 shown in Fig. 16, the deposition and etching of the conductive layer (first high potential conductive layer 4a) shown in Fig. 17 and Fig. 18, the deposition of the dielectric layer 3 shown in Fig. 19, and the deposition and etching of the conductive layer (first low potential conductive layer 7a) shown in Fig. 20 and Fig. 21 are repeatedly performed. Next, by the same method as in the first embodiment, the third high potential conductive layer 4c is selectively etched using a mask material having openings in regions (6c, 6f) on the first main surface 1F and the second main surface 1R where the second contact holes (13a, 13b, 20a, 20b) are to be formed.

[0075] 22, the first high potential conductive layer 4a, the first low potential conductive layer 7a, the second high potential conductive layer 4b, the second low potential conductive layer 7b, and the first high potential conductive layer 4c are laminated on the surface of the substrate 1 via the dielectric layer 3, and the groove 2 is backfilled. The two high potential conductive layers (4a, 5b) are formed in the first main surface 1F and the second main surface 1R of the substrate 1, excluding the regions (6a to 6f) where the second contact holes (13a, 13b, 20a, 20b) are to be formed. The two low potential conductive layers (7a, 7b) are formed in the first main surface 1F and the second main surface 1R of the substrate 1, excluding the regions (9a to 9d) where the first contact holes (15a, 15b, 21a, 21b) are to be formed.

[0076] Next, as shown in FIG. 23, a first contact hole (15a, 15b) and a second contact hole (13a, 13b) are formed on the first main surface 1F by the same method as in the first embodiment, and a high potential surface electrode 18 and a low potential surface electrode 19 are formed on the bottom and side surfaces of the contact holes (15a, 15b, 13a, 13b), respectively.

[0077] 24, similarly to the high potential surface electrode 18 and the low potential surface electrode 19 on the first main surface 1F side, first contact holes (21a, 21b) and second contact holes (20a, 20b) are formed on the second main surface 1R side of the substrate 1, and a high potential back surface electrode 22 and a low potential back surface electrode 23 are formed on the bottom and side surfaces of the contact holes (21a, 21b, 20a, 20b), respectively. Through the above steps, the semiconductor device according to the second embodiment shown in FIG. 15 is completed.

[0078] According to the method for manufacturing a semiconductor device according to the second embodiment, the same effects as those of the first embodiment can be obtained.

[0079] Third embodiment In the first and second embodiments, an example was shown in which the groove 2 penetrates from the first main surface 1F to the second main surface 1R of the substrate 1, but the groove 24 does not have to penetrate all the way through, as shown in Fig. 26. In the third embodiment, the groove 24 has side surfaces and a bottom surface, and the conductive layers (4a to 4c, 7a, 7b) and the dielectric layer 3 are laminated not only on the side surfaces but also on the bottom surface. Also in the third embodiment shown in FIG. 26, the semiconductor device comprises at least one dielectric layer 3 and at least one conductive layer (4a-4c, 7a, 7b) alternately stacked on at least the groove 24 and the first main surface 1F, a high-potential surface electrode 18 (first electrode) embedded in a first contact hole (15a, 15b) formed on the first main surface 1F, the high-potential surface electrode 18 being electrically connected to at least one of the at least one conductive layer (4a-4c) and the substrate 1, and a low-potential surface electrode 19 (second electrode) embedded in a second contact hole (13a, 13b) formed on the first main surface 1F, the low-potential surface electrode 19 being electrically connected to the conductive layer (7a, 7b) not electrically connected to the low-potential surface electrode 19 and the substrate 1. The high-potential conductive layers (4a-4c) electrically connected to the high-potential surface electrode 18 are disposed in a region of the first main surface 1F excluding at least the region (6a-6c) in which the second contact holes (13a, 13b) are formed. The low-potential conductive layers (7a, 7b) electrically connected to the low-potential surface electrode 19 are disposed in a region of the first main surface 1F excluding at least the region (9a, 9b) in which the first contact holes (15a, 15b) are formed. By adopting the structure of the third embodiment, the manufacturing process of the wirings (18, 19) is limited to the front surface (first main surface 1F) side of the substrate 1, making it possible to significantly reduce the process cost.

[0080] (Other embodiments) In addition, in the above embodiment, the substrate 1 is a conductor, but the substrate 1 may be an insulator. When the substrate has insulating properties, element isolation can be easily performed.

[0081] Although an N-type polysilicon film has been used as the conductive layer in the above description, a P-type polysilicon film may be used, or other semiconductor materials may be used. Furthermore, the conductive layer may be made of other conductive materials such as metal. For example, conductive polysilicon carbide (SiC), silicon germanium (SiGe), or aluminum (Al) may be used.

[0082] Although the etching process for the conductive layer, dielectric layer, and mask material has been described using dry etching, it may be wet etching using, for example, hydrofluoric acid or hot phosphoric acid.

[0083] The cross-sectional structures shown in FIG. 1 and FIG. 15 are unit structures (cell structures) of the semiconductor device (capacitor) according to the embodiment, and similar structures can be repeated in a direction parallel to the main surface (1F, 1R) of the substrate 1. For example, FIG. 25D shows a structure in which the unit structure of the capacitor is repeated twice in the direction in which the comb teeth extend. The unit structure of the capacitor shown in FIG. 25D includes three comb teeth having an area (9a) in which the first contact holes (15a, 15b) are to be formed, three comb teeth (41a, 41b) having an area (6a) in which the second contact holes (13a, 13b) are to be formed, one comb tooth in which no contact holes are to be formed, and a support portion (42a, 42). Of course, this unit structure can be repeated not only in the direction in which the comb teeth extend, but also in the direction in which the support portion (42a, 42) extends.

[0084] The above-described embodiment is an example of a form for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible depending on the design and the like, even if the embodiment is other than the above, as long as the modifications do not deviate from the technical idea of ​​the present invention. [Explanation of symbols]

[0085] 1 Board 1F 1st main surface 1R Second main surface 2 grooves 3 Dielectric Layer 4a~4c High potential conductive layer 6a to 6f: Regions in which second contact holes are formed 7a, 7b Low potential conductive layer 9a to 9d: Regions in which first contact holes are formed 13a, 13b, 20a, 20b Second contact holes 15a, 15b, 21a, 21b First contact hole 18 High potential surface electrode (1st electrode) 19 Low potential surface electrode (second electrode) 22 High potential back electrode (1st electrode) 23 Low potential back electrode (second electrode)

Claims

1. A substrate having a first main surface and a second main surface opposed to each other and a groove formed in the first main surface; at least two dielectric layers and at least two conductive layers alternately stacked on at least the groove and the first major surface; a first electrode embedded in a first contact hole formed on the first main surface, the first electrode being electrically connected to at least one conductive layer; a second electrode embedded in a second contact hole formed on the first main surface, the second electrode being electrically connected to the conductive layer not electrically connected to the first electrode and to the substrate; the conductive layer electrically connected to the first electrode is disposed in a region of the first main surface excluding at least a region in which the second contact hole is formed; the conductive layer electrically connected to the second electrode is disposed in a region of the first main surface excluding at least a region in which the first contact hole is formed. Capacitor.

2. 2. The capacitor according to claim 1, wherein the first electrode is electrically connected to the at least one conductive layer through the first contact hole.

3. 3. The capacitor according to claim 1, wherein the second electrode is electrically connected to the conductive layer that is not electrically connected to the first electrode and to the substrate through the second contact hole.

4. 3. The capacitor according to claim 2, wherein the first electrode is electrically connected to the at least one conductive layer at a side surface of the first contact hole.

5. 4. The capacitor according to claim 3, wherein the second electrode is electrically connected to the conductive layer at a side surface of the second contact hole, the conductive layer being not electrically connected to the first electrode.

6. The capacitor according to any one of claims 1 to 5, wherein the groove reaches the second main surface of the substrate.

7. 7. The capacitor of claim 6, wherein the at least two dielectric layers and the at least two conductive layers are alternately stacked on the second main surface.

8. 8. The capacitor according to claim 7, wherein the first electrode is also embedded in the first contact hole formed on the second main surface.

9. 9. The capacitor according to claim 7, wherein the second electrode is also embedded in the second contact hole formed on the second main surface.

10. The capacitor according to any one of claims 1 to 9, wherein the substrate is a conductor.

11. The capacitor according to any one of claims 1 to 10, wherein the substrate is an insulator.

12. A method for producing a capacitor according to any one of claims 1 to 11, comprising the steps of: The method for manufacturing a capacitor includes forming the grooves by dry etching.

13. A method for producing a capacitor according to any one of claims 1 to 11, comprising the steps of: In the method for manufacturing a capacitor, the groove is formed by wet etching.

14. A method for producing a capacitor according to any one of claims 1 to 11, comprising the steps of: a second contact hole formed on the conductive layer and formed on the second contact hole;

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