Voltage setting circuit, semiconductor integrated circuit, and voltage setting method

Abstract

This voltage setting circuit (11) comprises: a frequency comparator (14) for comparing the oscillation frequency of a first distributed voltage-controlled oscillator (13_1) and that of a second distributed voltage-controlled oscillator (13_2); and a frequency assessment circuit (15) for assessing the high / low of the oscillation frequencies of the first distributed voltage-controlled oscillator (13_1) and the second distributed voltage-controlled oscillator (13_2). A bias to be supplied to the first distributed voltage-controlled oscillator (13_1) and a bias to be supplied to the second distributed voltage-controlled oscillator (13_2) are determined in accordance with the assessment result; the bias when the high / low of the oscillation frequencies is inverted is determined as the optimal bias; and the optimal bias is supplied to a core circuit.　As a result, the present invention can provide a voltage setting circuit, a semiconductor integrated circuit, and a voltage setting method that enable easy control of the operation of a core circuit in a broadband.

Description

[Technical field]

[0001] The present invention relates to a voltage setting circuit for controlling an electronic circuit, a semiconductor integrated circuit, and a voltage setting method. [Background technology]

[0002] Wideband electronic circuits (e.g., amplifier circuits, mixer circuits, etc.) are required in various fields such as optical communication, wireless communication, and radar sensing. When designing a wideband circuit using bipolar transistors, it is necessary to apply a bias voltage (hereinafter referred to as "bias") so that each transistor in the core circuit has a current at which it operates at the fastest (hereinafter referred to as "optimum current"). For example, when a distributed amplifier circuit 51 (Non-Patent Document 1) shown in FIG. 8 is used as the core circuit, the bias dependency of the transmission characteristic (S21) (FIG. 9) is obtained. In this circuit example, the current flowing through the transistor of each unit cell changes depending on the bias of Vb. The optimal current flows at Vb=-1.45V, and the bandwidth is the widest (511 in the figure). It is confirmed that the frequency characteristic deteriorates when the bias (Vb) is higher than this bias (512 in the figure) and lower (513 in the figure).

[0003] On the other hand, since the manufactured circuit is affected by various variations in the process, voltage, temperature, etc., the optimal bias often deviates from the value at the time of design. Therefore, it is necessary to adjust the bias and set it to the optimal value every time it is actually used. Conventionally, as a method of detecting and setting the optimal bias, as shown in FIG. 10, a frequency sweep type measuring instrument 61 such as a VNA is used to monitor the frequency characteristics, and the bias output from a bias generator 65 is adjusted so that the band is the widest, and set in a core circuit 62 (Non-Patent Documents 1 and 2). [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] T. Jyo et al., "A 241-GHz-Bandwidth Distributed Amplifier with 10-dBm P1dB in 0.25-μm InP DHBT Technology," 2019 IEEE / MTT-S International Microwave Symposium (IMS), Boston, MA, USA, 2019, pp. 1430-1433, doi: 10.1109 / MWSYM.2019.8700975. [Non-Patent Document 2] T. Jyo et al., "A DC to 194-GHz Distributed Mixer in 250-nm InP DHBT Technology," 2020 IEEE / MTT-S International Microwave Symposium (IMS), Los Angeles, CA, USA, 2020, pp. 771-774, doi: 10.1109 / IMS30576.2020.9223832. Summary of the Invention [Problem to be solved by the invention]

[0005] However, the conventional method requires a high introduction cost because the frequency sweep type measuring device required is generally expensive. In addition, when using many core circuits, it is necessary to set the optimal bias for all the circuits, which results in a long time before the circuits can be used. Furthermore, when the operating environment (temperature, etc.) of the core circuits changes, the optimal bias also changes, which results in the need to reset the optimal bias every time the operating environment (temperature, etc.) of the core circuits changes. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, a voltage setting circuit according to the present invention is a voltage setting circuit that supplies an optimal bias to a core circuit, and includes a first distributed voltage controlled oscillator, a second distributed voltage controlled oscillator, a frequency comparator that compares the oscillation frequencies of the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, a frequency determination circuit that determines whether the oscillation frequencies of the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator are high or low, and a bias voltage setting circuit that supplies an optimal bias to the first distributed voltage controlled oscillator depending on the determination result. a bias generator control circuit that determines a bias to be supplied to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, and determines the bias when the oscillation frequency is inverted as the optimum bias; and a bias generator that generates the bias, supplies it to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, and supplies the optimum bias to the core circuit, wherein a unit cell of the first distributed voltage controlled oscillator and a unit cell of the second distributed voltage controlled oscillator have the same configuration as a unit cell of the core circuit. The core circuit is a distributed amplifier circuit. It is characterized by the above.

[0007] Further, a voltage setting circuit according to the present invention is a voltage setting circuit for supplying an optimal bias to a core circuit, comprising: a first distributed voltage controlled oscillator; a second distributed voltage controlled oscillator; a first current monitor for monitoring a current flowing in a power supply voltage of the first distributed voltage controlled oscillator; a second current monitor for monitoring a current flowing in a power supply voltage of the second distributed voltage controlled oscillator; a third current monitor for monitoring a current flowing in a power supply voltage of the core circuit; a frequency comparator for comparing an oscillation frequency of the first distributed voltage controlled oscillator with that of the second distributed voltage controlled oscillator; a frequency judgment circuit for judging whether the oscillation frequency of the first distributed voltage controlled oscillator is high or low; a bias generator control circuit that determines a bias to be supplied to the first distributed voltage controlled oscillator and a bias to be supplied to the second distributed voltage controlled oscillator, and controls the optimal bias to be supplied to the core circuit; and a bias generator that generates the bias and supplies it to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, and generates the optimal bias and supplies it to the core circuit, wherein the optimal bias is adjusted based on a current value of the first current monitor and a current value monitored by the second current monitor when the oscillation frequency is inverted, and the sizes of transistors in a unit cell of the first distributed voltage controlled oscillator, a unit cell of the second distributed voltage controlled oscillator, and a unit cell of the core circuit are the same. The core circuit is a distributed amplifier circuit. It is characterized by the above.

[0008] Further, a voltage setting method according to the present invention is a method for setting a voltage in a semiconductor integrated circuit including a first distributed voltage controlled oscillator, a second distributed voltage controlled oscillator, a core circuit, a frequency comparator, and a frequency determination circuit, comprising: the core circuit is a distributed amplifier circuit;A voltage setting method for setting an optimal bias for the core circuit, comprising the steps of: supplying a first bias to the first distributed voltage controlled oscillator; supplying a second bias having a predetermined voltage difference from the first bias to the second distributed voltage controlled oscillator; comparing an oscillation frequency of the first distributed voltage controlled oscillator with an oscillation frequency of the second distributed voltage controlled oscillator; increasing or decreasing a predetermined voltage for each of the first bias and the second bias when the oscillation frequency of the first distributed voltage controlled oscillator is higher than the oscillation frequency of the second distributed voltage controlled oscillator; the step of supplying an optimum bias to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, respectively; the step of comparing an oscillation frequency of the first distributed voltage controlled oscillator and an oscillation frequency of the second distributed voltage controlled oscillator at the increased or decreased first bias and the second bias, respectively; and the step of determining the second bias supplied to the second distributed voltage controlled oscillator as the optimum bias when the oscillation frequency of the first distributed voltage controlled oscillator and the oscillation frequency of the second distributed voltage controlled oscillator at the increased or decreased first bias and the second bias are inverted in level.

[0009] Further, a voltage setting method according to the present invention is a method for setting a voltage in a semiconductor integrated circuit including a first distributed voltage controlled oscillator, a second distributed voltage controlled oscillator, a core circuit, a frequency comparator, and a frequency determination circuit, comprising: the core circuit is a distributed amplifier circuit;A voltage setting method for setting an optimal bias for the core circuit, comprising the steps of: supplying a first bias to the first distributed voltage controlled oscillator; supplying a second bias having a predetermined voltage difference from the first bias to the second distributed voltage controlled oscillator; comparing an oscillation frequency of the first distributed voltage controlled oscillator with an oscillation frequency of the second distributed voltage controlled oscillator; when the oscillation frequency of the first distributed voltage controlled oscillator is higher than the oscillation frequency of the second distributed voltage controlled oscillator, increasing or decreasing the first bias and the second bias by a predetermined voltage; a step of comparing an oscillation frequency of the first distributed voltage controlled oscillator and an oscillation frequency of the second distributed voltage controlled oscillator at the increased or decreased first bias and the second bias, respectively; a step of monitoring a current flowing through the first distributed voltage controlled oscillator and a current flowing through the second distributed voltage controlled oscillator when the oscillation frequency of the first distributed voltage controlled oscillator and the oscillation frequency of the second distributed voltage controlled oscillator at the increased or decreased first bias and the second bias are inverted in height; and a step of determining the optimal bias to be supplied to the core circuit such that a current value determined based on the monitored current value flows through the core circuit. Effect of the Invention

[0010] According to the present invention, it is possible to provide a voltage setting circuit, a semiconductor integrated circuit, and a voltage setting method that can easily control the broadband operation of a core circuit. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. [Figure 2A]FIG. 2A is a block diagram showing a configuration of a core circuit in a semiconductor integrated circuit according to a first embodiment of the present invention. [Figure 2B] FIG. 2B is a diagram showing element characteristics of the core circuit in the semiconductor integrated circuit according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a block diagram showing a configuration of a distributed voltage controlled oscillator in a voltage setting circuit according to the first embodiment of the present invention. [Figure 3B] FIG. 3B is a diagram showing element characteristics of a distributed voltage controlled oscillator in the voltage setting circuit according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a flow chart for explaining the operation of the voltage setting circuit according to the first embodiment of the present invention. [Diagram 5] FIG. 5 is a block diagram showing an example of a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. [Figure 6] FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. [Figure 7] FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. [Figure 8] FIG. 8 is a block diagram showing a configuration of a conventional distributed amplifier circuit. [Figure 9] FIG. 9 is a diagram showing element characteristics of a conventional distributed amplifier circuit. [Figure 10] FIG. 10 is a diagram for explaining a conventional voltage setting method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] <First embodiment> A voltage setting circuit and a semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 5. FIG.

[0013] <Configuration of semiconductor integrated circuit and voltage setting circuit> As shown in FIG. 1, a semiconductor integrated circuit 10 according to this embodiment includes, on the same chip 1, a voltage setting circuit 11 and a core circuit 12 to which the voltage setting circuit 11 is connected.

[0014] The voltage setting circuit 11 includes two distributed voltage-controlled oscillators (hereinafter referred to as “VCOs”) 13_1 and 13_2, a frequency comparator 14, a frequency determination circuit 15, a bias generator control circuit 16, and a bias generator 17.

[0015] As shown in Fig. 2A, a distributed amplifier circuit is used for the core circuit 12. In the distributed amplifier circuit, unit cells each made up of a transistor circuit are connected in parallel via a transmission line and terminated at 50 Ω. A voltage Vb is applied to one of the terminated terminals, and in the semiconductor integrated circuit 10, a voltage Vb_opt optimized by a voltage setting circuit 11 is applied.

[0016] In the unit cell of the core circuit 12, two transistors 123, 124 are connected in series and connected to a transmission line 122. In one of the two transistors (first transistor) 123, the collector is connected to the transmission line 122 at a contact b on the output side, and Vcas1 is input to the base. In the other transistor (second transistor) 124, the base is connected to the transmission line 122 at a contact a on the side where Vb is applied, and a voltage VEE is supplied to the emitter.

[0017] In the core circuit 12, a transmission line 122 has L, C, and R as an equivalent circuit.

[0018] 2B shows the bias dependency of the transmission characteristic (S21) in the core circuit (distributed amplifier circuit) 12. In the core circuit (distributed amplifier circuit) 12, the current flowing through the transistors of each unit cell changes depending on the bias of Vb, and the frequency characteristics change. When Vb=-1.45V, the optimal current flows and the bandwidth is the widest (125 in the figure). Hereinafter, the bias (Vb) when the optimal current flows will be referred to as the "optimum bias". When the bias (Vb) is higher (126 in the figure) or lower (127 in the figure) than the optimal bias, the bandwidth becomes narrower and the frequency characteristics deteriorate.

[0019] The distributed VCO(1) 13_1 and VCO(2) 13_2 have the configuration shown in FIG. 3A, in which the unit cells and the capacitors are connected in parallel via transmission lines. The unit cells of the distributed VCO(1) 13_1 and VCO(2) 13_2 have the same configuration as the unit cell of the core circuit 12.

[0020] In the unit cells of the distributed VCO(1) 13_1 and VCO(2) 13_2, two transistors are connected in series in each unit cell and connected to a transmission line. In one of the two transistors (first transistors) 133_1 and 133_2, the collector is connected to the transmission lines 132_1 and 132_2 at the contact b on the output side, and Vcas1 is input to the base. In the other transistors (second transistors) 134_1 and 134_2, the contact a on the side where Vb is applied to the base is connected to the transmission lines 132_1 and 132_2, and the voltage VEE is supplied to the emitter.

[0021] 3B shows the bias dependence of the oscillation frequency of the distributed VCOs used in VCO(1) 13_1 and VCO(2) 13_2. When Vb=-1.45V, the optimum current flows through the transistor and the oscillation frequency is maximized.

[0022] Bias Vb1 and Vb2 are input to the distributed VCO(1) 13_1 and VCO(2) 13_2, and there is a voltage difference between the biases Vb1 and Vb2.

[0023] The frequency comparator 14 is formed of, for example, a Gilbert cell circuit. It outputs a signal indicating whether the frequency is high or low. For example, if the frequency of VCO(1) 13_1 is high, it outputs a high voltage signal H, and if the frequency of VCO(2) 13_2 is high, it outputs a low voltage signal L.

[0024] Frequency determination circuit 15 is configured with a digital processing circuit, and determines whether the output of frequency comparator 14 is at H level or L level. As a result, it determines which of the frequencies of the two signals input to frequency comparator 14 is higher.

[0025] The bias generator control circuit 16 determines the bias value to be generated by the bias generator 17 based on the result of the determination by the frequency determination circuit 15 , and controls the bias generator 17 .

[0026] The bias generator 17 generates a bias and inputs it to the distributed VCO(1) 13_1 and the VCO(2) 13_2. The bias generator 17 also generates an optimal bias and supplies it to the core circuit 12.

[0027] <Voltage setting circuit operation> The operation of the voltage setting circuit 11 according to this embodiment will be described below.

[0028] In the present invention, the optimum bias is detected by utilizing the property that the oscillation frequencies of the distributed VCO(1) 13_1 and VCO(2) 13_2 are highest when the optimum current flows through the transistors used in the distributed VCO(1) 13_1 and VCO(2) 13_2.

[0029] In the bias dependence of the oscillation frequency of VCO(1) 13_1 and VCO(2) 13_2 shown in Fig. 3B, an optimal current flows through the transistor and the oscillation frequency is maximized at Vb = -1.45 V. This bias (Vb = -1.45 V) coincides with the bias at which the core circuit (distributed amplifier circuit) 12 exhibits the widest frequency characteristics, as shown in Fig. 2B.

[0030] Therefore, by detecting the optimal bias at which the oscillation frequencies of distributed VCO(1) 13_1 and VCO(2) 13_2, which have the same unit cell as core circuit 12, are maximized, and setting this optimal bias as the bias for core circuit 12, core circuit 12 can be operated over the widest bandwidth.

[0031] In order to detect the optimal bias in the voltage setting circuit 11, the present invention uses two distributed VCOs (VCO(1) 13_1 and VCO(2) 13_2) of the same configuration. However, a predetermined voltage difference is provided between the biases supplied to the two distributed VCOs (1) 13_1 and VCO(2) 13_2. For example, when setting a bias Vb1 for the distributed VCO(1) 13_1 and a bias Vb2 for the distributed VCO(2) 13_2, a bias 10 mV higher is set for Vb1.

[0032] An example of the operation process of the voltage setting circuit 11 will be described with reference to the flow chart shown in FIG.

[0033] First, biases Vb1 and Vb2 (initial biases) are supplied to the two distributed VCOs, VCO(1) 13_1 and VCO(2) 13_2, respectively (step 201).

[0034] Next, the frequency comparator 14 and frequency determination circuit 15 compare the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 to determine whether the oscillation frequency of VCO(1) 13_1 is higher (step 202).

[0035] Next, if the frequency of VCO(1) 13_1 is higher, the bias generator control circuit 16 determines the voltage values ​​obtained by adding a predetermined voltage (e.g., 10 mV) to Vb1 and Vb2, and controls the bias generator 17 (step 203).

[0036] Next, the bias generator 17 supplies Vb1 and Vb2 to the VCO(1) 13_1 and VCO(2) 13_2 (step 204).

[0037] Next, the frequency comparator 14 and the frequency determination circuit 15 again compare the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 to determine whether the oscillation frequency of VCO(1) 13_1 is higher (step 205).

[0038] As a result, if the frequency of VCO(1) 13_1 is higher, the process returns to step 203, where the voltage values ​​obtained by adding a predetermined voltage to each of Vb1 and Vb2 are determined again, and the same steps are repeated.

[0039] On the other hand, when the frequency of VCO(1) 13_1 is not higher, that is, when the frequency of VCO(1) 13_1 is lower, or when the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 are equal, Vb2 is determined as the optimum bias Vb_opt. In this way, the bias when the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 are inverted is determined as the optimum bias Vb_opt (step 206).

[0040] Furthermore, in the above step 202, if the frequency of VCO(1) 13_1 is not higher (if the frequency of VCO(1) 13_1 is lower or if the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 are equal), bias generator control circuit 16 determines voltage values ​​for Vb1 and Vb2 that are reduced by a predetermined voltage (e.g., 10 mV), and controls bias generator 17 (step 207).

[0041] Next, the bias generator 17 supplies Vb1 and Vb2 to the VCO(1) 13_1 and VCO(2) 13_2 (step 208).

[0042] Next, the frequency comparator 14 and frequency determination circuit 15 again compare the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 to determine whether the oscillation frequency of VCO(1) 13_1 is higher (step 209).

[0043] As a result, if the frequency of VCO(1) 13_1 is not higher (if the frequency of VCO(1) 13_1 is lower, or if the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 are equal), the process returns to step 207, where voltage values ​​obtained by decreasing Vb1 and Vb2 by a predetermined voltage are determined again, and similar steps are repeated.

[0044] On the other hand, when the frequency of VCO(1) 13_1 is higher, Vb1 is determined as the optimum bias Vb_opt. In this manner, the bias when the oscillation frequencies of VCO(1) 13_1 and VCO(2) 13_2 are inverted is determined as the optimum bias Vb_opt (step 210).

[0045] Finally, the optimal bias Vb_opt determined as described above is supplied to the core circuit 12 .

[0046] In the present embodiment, an example has been shown in which a bias higher than that of VCO(1) 13_1 is supplied to VCO(1) 13_1, but a bias higher than that of VCO(1) 13_1 may be supplied to VCO(2) 13_2. Also, in step 202, the determination may be made using the oscillation frequency of VCO(2) 13_2.

[0047] In this manner, the voltage setting circuit 11 according to the present embodiment supplies voltages with a predetermined voltage difference to the two distributed VCOs (1) 13_1 and (2) 13_2, judges the high or low of the output frequency, and increases or decreases Vb1 and Vb2 stepwise according to the judgment result to detect the bias at which the oscillation frequency becomes maximum. This bias is determined as the optimal bias Vb_opt and is supplied to the core circuit 12.

[0048] As described above, the optimal voltage (bias) of the oscillator can be obtained based on the output (frequency) difference between two oscillators that are oscillated by applying different voltages, and the core circuit 12, which is made up of the same unit cell as the oscillator, can be controlled by this optimal voltage.

[0049] According to the voltage setting circuit of this embodiment, it is possible to detect and set the optimum bias within a chip, eliminating the need to use a frequency sweep type measuring instrument. It is therefore possible to easily detect and set the optimum bias, enable the core circuit to operate over a wide bandwidth, and reduce costs.

[0050] In addition, because the optimal bias is automatically detected and set, when using multiple circuits or when the usage environment changes, there is no need to measure the frequency characteristics every time the circuit is operated, which makes it possible to significantly reduce the time required to start using the circuit.

[0051] In this way, the voltage setting circuit according to the present embodiment determines and controls the optimal bias of the core circuit by determining the optimal bias of a distributed voltage controlled oscillator (VCO) having the same unit cell as the core circuit.

[0052] In the voltage setting circuit and semiconductor integrated circuit according to the present embodiment, it is desirable to place the distributed VCO close to the core circuit. Since the element characteristics are non-uniform within the chip surface, shortening the distance between elements can suppress the influence of the non-uniform distribution of characteristics. As a result, the setting accuracy of the optimal bias can be improved.

[0053] In the semiconductor integrated circuit 10 according to the present embodiment, an example has been shown in which two distributed VCOs (1) 13_1 and VCO (2) 13_2, a frequency comparator 14, a frequency determination circuit 15, a bias generator control circuit 16, and a bias generator 17 are provided on the same chip 1, but the present invention is not limited to this. As shown in Fig. 5, in the semiconductor integrated circuit 10_1, the frequency determination circuit 15, the bias generator control circuit 16, and the bias generator 17 do not need to be arranged on the same chip 1. Even in this arrangement, the output signal of the frequency comparator 14 and each bias are direct current (DC) signals, so that the accuracy of detecting and setting the optimal bias is not affected, and the same effect is achieved.

[0054] <Second embodiment> A voltage setting circuit and a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to FIG.

[0055] 6, a semiconductor integrated circuit 30 according to this embodiment includes a voltage setting circuit 31 and a core circuit 32 connected to the voltage setting circuit 31 on each of different substrates, a substrate (1) 2_1 and a substrate (2) 2_2, on the same chip 1. The other configurations and effects are similar to those of the first embodiment.

[0056] Here, decoupling capacitors 38_1 and 38_2 are connected to the terminals for the power supply voltage (VEE) of VCO(1) 33_1 and VCO(2) 33_2 and the terminal for the power supply voltage (VEE) of the core circuit 32, respectively. The decoupling capacitors 38_1 and 38_2 make it possible to prevent the noise of the oscillator from being coupled to the core circuit 32.

[0057] Here, it is desirable that the decoupling capacitors 38_1, 38_2 are disposed in the vicinity of the respective power supply voltages (VEE). The shorter the distance between the decoupling capacitors 38_1, 38_2 and the power supply voltage (VEE), the more the noise can be reduced.

[0058] Furthermore, by connecting a decoupling capacitor 38_3 to the wiring of Vb_opt supplied to the core circuit 32, it becomes possible to prevent oscillator noise from being coupled to the core circuit 32. Here, it is preferable to place the decoupling capacitor 38_3 in the vicinity of the core circuit 32, and the shorter the distance between the decoupling capacitor 38_3 and the core circuit 32, the more the noise can be reduced.

[0059] The voltage setting circuit 31 operates in the same manner as the operation process (FIG. 4) in the first embodiment.

[0060] The voltage setting circuit according to the present embodiment allows easy detection and setting of the optimum bias, enables the core circuit to operate over a wide bandwidth, reduces costs and time, and suppresses the effects of oscillator noise.

[0061] <Third embodiment> A voltage setting circuit and a semiconductor integrated circuit according to a third embodiment of the present invention will be described with reference to Fig. 7. In the first and second embodiments, a unit cell having the same configuration as the core circuit is used for the distributed VCO. A voltage setting circuit 41 according to this embodiment can be used in cases where it is difficult to use a unit cell having the same configuration as the core circuit 42 for the distributed VCO(1) 43_1 and VCO(2) 43_2.

[0062] <Configuration of semiconductor integrated circuit and voltage setting circuit> As shown in FIG. 7 , a semiconductor integrated circuit 40 according to this embodiment, like the first embodiment, includes a voltage setting circuit 41 and a core circuit 42 to which the voltage setting circuit 41 is connected, all on the same chip 1, and the voltage setting circuit 41 includes two distributed VCOs (1) 43_1 and VCO (2) 43_2, a frequency comparator 44, a frequency determination circuit 45, a bias generator control circuit 46, and a bias generator 47.

[0063] Furthermore, the semiconductor integrated circuit 40 includes current monitors 48_1, 48_2, and 48_3 having circuits for monitoring the currents flowing through the power supply voltages of the VCO(1) 43_1, VCO(2) 43_2, and core circuit 42, respectively.

[0064] Furthermore, the size (emitter length) of the transistors in VCO(1) 43_1 and VCO(2) 43_2 is the same as the size (emitter length) of the transistors in the core circuit 42.

[0065] <Voltage setting circuit operation> The operation of the voltage setting circuit 41 according to this embodiment will be described below.

[0066] First, as in the first embodiment, the biases Vb1 and Vb2 are increased and decreased stepwise, the oscillation frequencies of VCO(1) 43_1 and VCO(2) 43_2 are compared, and the bias at which the oscillation frequencies of both are inverted is determined as the optimal bias. In this way, the bias at which the oscillation frequency becomes maximum is detected as the optimal bias.

[0067] Next, the currents (optimum currents) at the optimum bias in the VCO(1) 43_1 and VCO(2) 43_2 are monitored by the current monitors 48_1 and 48_2.

[0068] Next, the optimal current in the core circuit 42 is determined based on the optimal current in VCO(1) 43_1 and VCO(2) 43_2. For the optimal current in the core circuit 42, for example, either the optimal current in VCO(1) 43_1 or the optimal current in VCO(2) 43_2 may be used, or the average current value of both may be used. In addition, when one unit cell is used in VCO(1) 43_1 or VCO(2) 43_2, and N unit cells are used in the core circuit 42, the optimal current of the core circuit = N × the optimal current of VCO(1) 43_1 or VCO(2) 43_2. For example, when one unit cell is used in VCO(1) 43_1 or VCO(2) 43_2, and six unit cells are used in the core circuit 42, the optimal current of the core circuit = 6 × the optimal current of VCO(1) 43_1 or VCO(2) 43_2.

[0069] Next, the current flowing through the core circuit 42 is monitored by the current monitor 48_3 of the core circuit 42, and the bias is adjusted so that the optimal current of the core circuit 42 described above flows through the core circuit 42 (the bias that results in the optimal current is the optimal bias Vb_opt).

[0070] According to the voltage setting circuit of this embodiment, it is possible to easily set an optimal current for the core circuit without using a unit cell having the same configuration as the core circuit in the distributed VCO, and to operate the core circuit over a wide band.

[0071] In the semiconductor integrated circuit according to this embodiment, similarly to the first embodiment, it is desirable to place the distributed VCO in a position close to the core circuit.

[0072] Furthermore, in the semiconductor integrated circuit according to this embodiment, similarly to the first embodiment, the frequency determination circuit, the bias generator control circuit, and the bias generator do not have to be arranged on the same chip.

[0073] Furthermore, in the semiconductor integration according to this embodiment, similarly to the second embodiment, different substrates on the same chip, substrate (1) and substrate (2), may each be provided with a voltage setting circuit and a core circuit to which the voltage setting circuit is connected.

[0074] Furthermore, in the first to third embodiments described above, after an optimal bias is set in the core circuit, the power supplies to the two distributed VCOs, the frequency comparator, and the frequency magnitude determination circuit are turned off, thereby making it possible to reduce power consumption and noise in the core circuit.

[0075] In the embodiment of the present invention, the unit cell of the distributed VCO of the voltage setting circuit and the unit cell common to the core circuit are configured with two transistors connected in series, but this is not limited to this. The unit cell may be configured with one transistor or multiple transistors, as long as it can configure an oscillation circuit and has the same configuration for the distributed VCO and the core circuit of the voltage setting circuit.

[0076] In the embodiment of the present invention, an example has been shown in which an amplifier circuit is used as the core circuit, but the present invention is not limited to this and a mixer may also be used.

[0077] In the embodiments of the present invention, examples of the structure, dimensions, materials, etc. of each component in the configuration of the voltage setting circuit and the semiconductor integrated circuit, the voltage setting method, etc. are shown, but the present invention is not limited to these. It is sufficient if the voltage setting circuit, the semiconductor integrated circuit, and the voltage setting method are effective. [Industrial Applicability]

[0078] The present invention can be applied to electronic circuits in equipment and devices used in optical communications, wireless communications, radar sensing, etc. [Explanation of symbols]

[0079] 11 Voltage setting circuit 12 Core Circuit 13_1, 13_2 Distributed Voltage Controlled Oscillator 14 Frequency Comparator 15 Frequency determination circuit 16 Bias generator control circuit 17 Bias Generator 121, 131_1, 131_2 unit cells

Claims

1. A voltage setting circuit for supplying an optimal bias to a core circuit, a first distributed voltage controlled oscillator; a second distributed voltage controlled oscillator; a frequency comparator that compares the oscillation frequencies of the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator; a frequency determination circuit that determines whether the oscillation frequencies of the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator are high or low; a bias generator control circuit that determines a bias to be supplied to the first distributed voltage controlled oscillator and a bias to be supplied to the second distributed voltage controlled oscillator according to the result of the determination, and determines the bias when the oscillation frequency is inverted as the optimum bias; a bias generator that generates the bias and supplies it to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, and supplies the optimal bias to the core circuit; A voltage setting circuit characterized in that a configuration of a unit cell of the first distributed voltage controlled oscillator and a unit cell of the second distributed voltage controlled oscillator are the same as a configuration of a unit cell of the core circuit, and the core circuit is a distributed amplifier circuit.

2. A voltage setting circuit for supplying an optimal bias to a core circuit, a first distributed voltage controlled oscillator; a second distributed voltage controlled oscillator; a first current monitor for monitoring a current flowing in a power supply voltage of the first distributed voltage controlled oscillator; a second current monitor for monitoring a current flowing in a power supply voltage of the second distributed voltage controlled oscillator; a third current monitor for monitoring a current flowing in a power supply voltage of the core circuit; a frequency comparator that compares the oscillation frequencies of the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator; a frequency determination circuit that determines whether the oscillation frequencies of the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator are high or low; a bias generator control circuit that determines a bias to be supplied to the first distributed voltage controlled oscillator and a bias to be supplied to the second distributed voltage controlled oscillator according to the result of the determination, and controls the optimal bias to be supplied to the core circuit; a bias generator that generates the bias and supplies it to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, and generates the optimum bias and supplies it to the core circuit; the optimum bias is adjusted based on the current value of the first current monitor and the current value monitored by the second current monitor when the oscillation frequency is inverted from high to low; A voltage setting circuit characterized in that the sizes of transistors in a unit cell of the first distributed voltage controlled oscillator, a unit cell of the second distributed voltage controlled oscillator, and a unit cell of the core circuit are the same, and the core circuit is a distributed amplifier circuit.

3. A voltage setting circuit according to claim 1 or 2; The core circuit A semiconductor integrated circuit comprising:

4. 4. The semiconductor integrated circuit according to claim 3, wherein the voltage setting circuit and the core circuit are provided on the same chip.

5. the voltage setting circuit is disposed on a first substrate; the core circuit is disposed on a second substrate; 5. The semiconductor integrated circuit according to claim 3, further comprising a decoupling capacitor connected to a power supply voltage terminal of the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, a power supply voltage terminal of the core circuit, and a wiring through which the optimal bias is supplied from the bias generator to the core circuit.

6. A voltage setting method for setting an optimal bias for a semiconductor integrated circuit including a first distributed voltage controlled oscillator, a second distributed voltage controlled oscillator, a core circuit, a frequency comparator, and a frequency determination circuit, the core circuit being a distributed amplifier circuit, comprising the steps of: providing a first bias to the first distributed voltage controlled oscillator; supplying a second bias having a predetermined voltage difference from the first bias to the second distributed voltage controlled oscillator; comparing an oscillation frequency of the first distributed voltage controlled oscillator with an oscillation frequency of the second distributed voltage controlled oscillator; increasing or decreasing a predetermined voltage for each of the first bias and the second bias when an oscillation frequency of the first distributed voltage controlled oscillator is higher than an oscillation frequency of the second distributed voltage controlled oscillator; supplying the increased or decreased first bias and the decreased second bias to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, respectively; comparing an oscillation frequency of the first distributed voltage controlled oscillator with an oscillation frequency of the second distributed voltage controlled oscillator at the increased or decreased first bias and the increased or decreased second bias; determining the second bias supplied to the second distributed voltage controlled oscillator as the optimum bias when the oscillation frequency of the first distributed voltage controlled oscillator and the oscillation frequency of the second distributed voltage controlled oscillator are inverted in terms of the increased or decreased first bias and second bias, respectively; A voltage setting method comprising:

7. A voltage setting method for setting an optimal bias for a semiconductor integrated circuit including a first distributed voltage controlled oscillator, a second distributed voltage controlled oscillator, a core circuit, a frequency comparator, and a frequency determination circuit, the core circuit being a distributed amplifier circuit, comprising the steps of: providing a first bias to the first distributed voltage controlled oscillator; supplying a second bias having a predetermined voltage difference from the first bias to the second distributed voltage controlled oscillator; comparing an oscillation frequency of the first distributed voltage controlled oscillator with an oscillation frequency of the second distributed voltage controlled oscillator; increasing or decreasing a predetermined voltage for each of the first bias and the second bias when an oscillation frequency of the first distributed voltage controlled oscillator is higher than an oscillation frequency of the second distributed voltage controlled oscillator; supplying the increased or decreased first bias and the decreased second bias to the first distributed voltage controlled oscillator and the second distributed voltage controlled oscillator, respectively; comparing an oscillation frequency of the first distributed voltage controlled oscillator with an oscillation frequency of the second distributed voltage controlled oscillator at the increased or decreased first bias and the increased or decreased second bias; monitoring a current flowing through the first distributed voltage controlled oscillator and a current flowing through the second distributed voltage controlled oscillator when the oscillation frequency of the first distributed voltage controlled oscillator and the oscillation frequency of the second distributed voltage controlled oscillator are inverted at the increased or decreased first bias and the increased or decreased second bias, respectively; determining the optimal bias to be supplied to the core circuit such that a current value determined based on the monitored current value flows through the core circuit; A voltage setting method comprising:

8. After setting the optimal bias to the core circuit, turning off the power supplies to the first distributed voltage controlled oscillator, the second distributed voltage controlled oscillator, the frequency comparator, and the frequency determination circuit. The voltage setting method according to claim 6 or 7, further comprising:

Images