Semiconductor light emitting device

Abstract

To provide a semiconductor light-emitting element that can achieve selective emission of a light-emitting layer of a semiconductor light-emitting element having an active layer with a three-dimensional microstructure.SOLUTION: A semiconductor light-emitting element 100 comprises: an n-type semiconductor layer 112; a plurality of columnar semiconductors 130 on the n-type semiconductor layer 112; an embedding layer 140 burying a gap between the plurality of columnar semiconductors 130; and a current suppression region X1 that suppresses a current. Each of the plurality of columnar semiconductors 130 has a hexagonal pillar part 131 having a hexagonal prism shape, and an active layer 132 covering the hexagonal pillar part 131. The hexagonal pillar part 131 has a hexagonal first surface 131a and a second surface 131b opposite to the first surface 131a. The first surfaces 131a of the plurality of columnar semiconductors 130 are opposed to the n-type semiconductor layer 112. The second surfaces 131b of the plurality of columnar semiconductors 130 are opposed to the current suppression region X1.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The technical field of the present specification relates to semiconductor light emitting devices. [Background technology]

[0002] A semiconductor light-emitting device emits light when holes and electrons recombine in the active layer. Conventionally, a flat sheet-like well layer has been used as the active layer. In recent years, active layers with three-dimensional structures such as columnar structures have been researched.

[0003] For example, Patent Document 1 discloses a semiconductor light-emitting element having an n-type nanowire layer 1031, an active layer 1032, a p-type semiconductor layer 1033, a p+ layer 1034, and an n+ layer 1035 (paragraph

[0038] of Patent Document 1). It also discloses that the buried semiconductor layer 104 fills the gaps between the columnar semiconductor layers 103 (paragraph

[0037] of Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-012744 A Summary of the Invention [Problem to be solved by the invention]

[0005] In a semiconductor with a nanowire structure as in Patent Document 1, active layer 1032 has a hexagonal cylindrical shape (FIGS. 1 and 2 in Patent Document 1). Active layer 1032 located on the side of n-type nanowire layer 1031 has a portion parallel to the m-plane. Active layer 1032 located on the opposite side of n-type nanowire layer 1031 to the substrate has a portion parallel to the c-plane or r-plane.

[0006] The m-plane is a non-polar plane. In the active layer formed parallel to the m-plane, no polarization occurs. Therefore, the quantum confined Stark effect (QCSE) does not occur in such an active layer. This is expected to improve the internal quantum efficiency. In the technology of Patent Document 1, an active layer is formed parallel to the c-plane or r-plane in addition to the m-plane. The emission wavelength and quality of the light-emitting layers formed on the m-plane, c-plane, and r-plane are different from each other. When a current is passed through the element, the light-emitting layers on the m-plane, c-plane, and r-plane emit light. This reduces the injection current into the m-plane. In addition, problems such as variation in the emission wavelength of the entire element and reduced light-emitting efficiency occur.

[0007] The problem that the technology of this specification aims to solve is to provide a semiconductor light-emitting element having an active layer with a three-dimensional fine structure, which is intended to selectively cause the light-emitting layer of the semiconductor light-emitting element to emit light. [Means for solving the problem]

[0008] The semiconductor light emitting device according to the first aspect is an n-type semiconductor layer, a tunnel junction on the n-type semiconductor layer, a p-type semiconductor layer on the tunnel junction, and a p-type semiconductor layer and filling the gaps between the multiple pillar-shaped semiconductors. It is an n-type semiconductor. The semiconductor pillars each have a hexagonal column shape. p type A hexagonal column portion, p type and an active layer covering the hexagonal column portion. p type The hexagonal column portion has a hexagonal first surface and a second surface opposite to the first surface. No. The first page is p-type semiconductor Facing the layer. No. Two faces face the current suppression region.

[0009] In this semiconductor light-emitting device, almost no current flows through the current suppression region. This suppresses light emission from the c-plane and r-plane that may exist around the current suppression region. The active layer with the m-plane emits light with high efficiency. Therefore, this semiconductor light-emitting device is less susceptible to wavelength variation, increased half-width, and reduced light-emitting efficiency. Effect of the Invention

[0010] This specification provides a semiconductor light emitting device having an active layer with a three-dimensional fine structure, which is intended to selectively cause a light emitting layer of the semiconductor light emitting device to emit light. [Brief description of the drawings]

[0011] [Figure 1] 1 is a perspective view showing a schematic configuration of a semiconductor light emitting device 100 according to a first embodiment. [Diagram 2] 1 is a conceptual diagram showing a cross section of a semiconductor light emitting element 100 according to a first embodiment. [Diagram 3] 2 is a diagram showing the internal structure of a pillar-shaped semiconductor 130 of the semiconductor light emitting device 100 of the first embodiment. FIG. [Figure 4] 4 is a first cross-sectional view showing a cross section taken along line IV-IV in FIG. [Diagram 5] 4 is a second cross-sectional view showing the VV cross section of FIG. 3. FIG. [Figure 6] 1A to 1C are diagrams (part 1) for explaining a manufacturing method of the semiconductor light emitting device 100 according to the first embodiment. [Figure 7] FIG. 2 is a second diagram for explaining the manufacturing method of the semiconductor light emitting device 100 according to the first embodiment. [Figure 8] 11A to 11C are views (part 3) for explaining the manufacturing method of the semiconductor light emitting device 100 according to the first embodiment. [Figure 9] FIG. 4 is a fourth diagram for explaining the method for manufacturing the semiconductor light emitting device 100 according to the first embodiment. [Figure 10] FIG. 5 is a diagram (part 5) for explaining the manufacturing method of the semiconductor light emitting device 100 of the first embodiment. [Figure 11] FIG. 6 is a diagram (part 6) for explaining the manufacturing method of the semiconductor light emitting device 100 of the first embodiment. [Figure 12] FIG. 7 is a diagram for explaining the manufacturing method of the semiconductor light emitting device 100 according to the first embodiment. [Figure 13] FIG. 8 is a diagram for explaining the manufacturing method of the semiconductor light emitting device 100 according to the first embodiment. [Figure 14]2A to 2C are diagrams conceptually illustrating the effects of the semiconductor light emitting device 100 of the first embodiment. [Figure 15] 11 is a diagram showing an internal structure of a columnar semiconductor 230 of a semiconductor light emitting device 200 according to a second embodiment. FIG. [Figure 16] 11 is a conceptual diagram showing a planar structure of a semiconductor light emitting element 300 according to a third embodiment. FIG. [Figure 17] FIG. 17 is a conceptual diagram showing the relationship between the XVII-XVII cross section of FIG. 16 and the average refractive index distribution. [Figure 18] FIG. 17 is a conceptual diagram showing the relationship between the XVIII-XVIII cross section of FIG. 16 and the average refractive index distribution. [Figure 19] 1 is a schematic diagram showing a case where pillar-shaped semiconductors 130 are arranged in three rows. [Figure 20] FIG. 11 is a schematic configuration diagram of a semiconductor light emitting device 400 according to a fourth embodiment. [Figure 21] 13 is a schematic configuration diagram of a semiconductor light emitting device 500 according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Specific embodiments will be described below with reference to the drawings, taking a semiconductor light-emitting device as an example. However, the technology of this specification is not limited to these embodiments. In this specification, the semiconductor light-emitting device includes an LED and a laser diode (LD). The stacked structure and electrode structure of each layer of the semiconductor light-emitting device described below are examples. There are cases where a stacked structure different from the embodiment may be used. Furthermore, the thickness ratio of each layer in each figure is conceptually shown, and does not indicate the actual thickness ratio.

[0013] (First embodiment) 1. Semiconductor light emitting element Fig. 1 is a perspective view showing a schematic configuration of a semiconductor light emitting device 100 according to a first embodiment. The semiconductor light emitting device 100 has an active layer having a three-dimensional shape. As shown in Fig. 1, the semiconductor light emitting device 100 has a substrate 110, a mask 120, a columnar semiconductor 130, a buried layer 140, a cathode electrode N1, and an anode electrode P1.

[0014] The substrate 110 is for supporting the mask 120 , the pillar-shaped semiconductor 130 , and the buried layer 140 .

[0015] The mask 120 is a material that does not allow a semiconductor to grow from the surface. As described later, the mask 120 has through holes. The mask 120 is preferably a transparent insulating film. In this case, the mask 120 hardly absorbs light. The current flows suitably to the columnar semiconductor 130 without passing through the mask 120. Examples of materials for the mask 120 include SiO2, SiNx, and Al2O3.

[0016] The pillar-shaped semiconductor 130 is a pillar-shaped Group III nitride semiconductor. The pillar-shaped semiconductor 130 is a semiconductor selectively grown from the surface of the semiconductor exposed in the opening of the mask 120. The pillar-shaped semiconductor 130 has a hexagonal pillar shape. The cross section perpendicular to the central axis direction of the pillar-shaped semiconductor 130 is a regular hexagon or a flattened hexagon.

[0017] The buried layer 140 is a layer for filling the gaps between the pillar-shaped semiconductors 130. The buried layer 140 covers the pillar-shaped semiconductors 130. The material of the buried layer 140 is, for example, n-type GaN.

[0018] The cathode electrode N1 is formed on a substrate 110.

[0019] The anode electrode P1 is formed on the buried layer 140. The anode electrode P1 may be formed on a semiconductor other than the buried layer 140.

[0020] 2. Columnar semiconductor 2-1.Arrangement of columnar semiconductors 2 is a conceptual diagram showing a cross section of the semiconductor light emitting device 100 of the first embodiment. The pillar-shaped semiconductors 130 are arranged in a square lattice pattern. As shown in FIG. 2, the pillar-shaped semiconductors 130 are periodically arranged at a first pitch interval J1.

[0021] The height of the pillar-shaped semiconductor 130 is, for example, 0.25 μm or more and 5 μm or less. The diameter of the pillar-shaped semiconductor 130 is, for example, 50 nm or more and 500 nm or less. Here, the diameter is the distance between the opposing vertices of the hexagon in a cross section perpendicular to the central axis direction. If the hexagon has a long side, it is the distance in the long side direction. The first pitch interval J1 of the pillar-shaped semiconductor 130 is, for example, 0.27 μm or more and 5 μm or less. These numerical values ​​are merely examples, and other numerical values ​​may be used.

[0022] 2-2. Internal structure of columnar semiconductor FIG. 3 is a diagram showing the internal structure of the pillar-shaped semiconductor 130 of the semiconductor light emitting device 100 of the first embodiment.

[0023] The substrate 110 includes a conductive base material 111 and an n-type semiconductor layer 112. The conductive base material 111 supports the n-type semiconductor layer 112 and the semiconductor layers thereover. The conductive base material 111 is, for example, a GaN substrate.

[0024] The n-type semiconductor layer 112 is a base layer for growing the columnar semiconductor 130. A part of the n-type semiconductor layer 112 is exposed in the opening 120a of the mask 120. The n-type semiconductor layer 112 is, for example, an n-type GaN layer or an n-type AlGaN layer. These are merely examples, and the n-type semiconductor layer 112 may have a structure other than those described above.

[0025] The pillar-shaped semiconductor 130 includes a pillar-shaped n-type semiconductor 131, an active layer 132, a cylindrical p-type semiconductor 133, a tunnel junction 134, and a current suppression region X1.

[0026] The side surface of the pillar-shaped n-type semiconductor 131 is an m-plane or a surface close to the m-plane. The m-plane is a non-polar plane. Therefore, in the active layer 132, there is almost no decrease in luminous efficiency due to piezoelectric polarization.

[0027] The columnar n-type semiconductor 131 is a hexagonal column part having a hexagonal column shape. The side surface of the hexagonal column is an m-plane. The top end surface of the hexagonal column is a c-plane. The cross section perpendicular to the axial direction of this hexagonal column is a regular hexagon or a flattened hexagon. The columnar n-type semiconductor 131 has a first surface 131a and a second surface 131b. The first surface 131a is shaped as the exposed surface of the opening 120a of the mask 120. The second surface 131b is a hexagon. The second surface 131b is the surface opposite to the first surface 131a. The first surface 131a faces and is in contact with the n-type semiconductor layer 112. The second surface 131b faces and is in contact with the current suppression region X1. The pillar-shaped n-type semiconductor 131 is a semiconductor layer selectively grown in a pillar shape starting from the n-type semiconductor layer 112 exposed in the opening 120a of the mask 120. The pillar-shaped n-type semiconductor 131 actually grows laterally as well. Therefore, the thickness of the pillar-shaped n-type semiconductor 131 is slightly larger than the opening width of the opening 120a of the mask 120. The pillar-shaped n-type semiconductor 131 is, for example, an n-type GaN layer.

[0028] The active layer 132 covers the columnar n-type semiconductor 131 and the current suppression region X1. The active layer 132 is formed along the outer periphery of the columnar n-type semiconductor 131 and the current suppression region X1, which are shaped like a hexagonal column. Therefore, the active layer 132 has a hexagonal cylindrical shape. The active layer 132 has, for example, one to five well layers and barrier layers sandwiching the well layers. The plate surface of the substrate 110 is a c-plane. The well layers of the active layer 132 are formed along an m-plane. Therefore, the well layers of the active layer 132 are disposed substantially perpendicular to the plate surface of the substrate 110. However, the top of the active layer 132 covers the top of the current suppression region X1. The top of the active layer 132 has at least one of a c-plane and an r-plane. The top of the active layer 132 may be substantially parallel to the plate surface of the substrate 110. For example, the well layers are InGaN layers, and the barrier layers are AlGaInN layers.

[0029] The cylindrical p-type semiconductor 133 is formed along the outer periphery of the active layer 132 having a hexagonal cylindrical shape. Therefore, the cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. The cylindrical p-type semiconductor 133 is in direct contact with the active layer 132, but is not in direct contact with the columnar n-type semiconductor 131. In addition, the cylindrical p-type semiconductor 133 is in contact with the tunnel junction 134. The cylindrical p-type semiconductor 133 is, for example, a p-type GaN layer.

[0030] The tunnel junction 134 is formed along the outer periphery of the cylindrical p-type semiconductor 133. The tunnel junction 134 is disposed at a position between the active layer 132 and the buried layer 140. The tunnel junction 134 has a hexagonal cylindrical shape. The tunnel junction 134 has a p+ layer 134a and an n+ layer 134b. The p+ layer 134a is an inner layer, and the n+ layer 134b is an outer layer. The p+ layer 134a is in contact with the cylindrical p-type semiconductor 133. The n+ layer 134b is in contact with the buried layer 140.

[0031] The current suppression region X1 suppresses current. The current suppression region X1 is located at the tip of the columnar n-type semiconductor 131. The current suppression region X1 is located farther from the substrate 110 than the columnar n-type semiconductor 131. The current suppression region X1 is surrounded by the columnar n-type semiconductor 131 and the active layer 132 while being in contact with the columnar n-type semiconductor 131 and the active layer 132. The current suppression region X1 is a semiconductor having a higher electrical resistivity than the columnar semiconductor 130. The electrical resistivity of the current suppression region X1 is sufficiently higher than the electrical resistivity of the columnar n-type semiconductor 131 and the active layer 132. The material of the current suppression region X1 is, for example, ud-GaN. The ud-GaN is undoped GaN.

[0032] 2-3. First cross-sectional shape Fig. 4 is a first cross-sectional view showing a cross section taken along line IV-IV in Fig. 3. Fig. 4 shows a cross section of the pillar-shaped semiconductor 130 parallel to the plate surface of the substrate 110. As shown in Fig. 4, the shape of a cross section perpendicular to the axial direction of the pillar-shaped semiconductor 130 is a regular hexagon. Then, from the inside of the hexagonal pillar-shaped pillar-shaped semiconductor 130, a pillar-shaped n-type semiconductor 131, an active layer 132, and a cylindrical p-type semiconductor 133 are arranged.

[0033] 2-4. Second cross-sectional shape Fig. 5 is a second cross-sectional view showing the VV cross section of Fig. 3. Fig. 5 shows a cross section parallel to the plate surface of the substrate 110 in the pillar-shaped semiconductor 130. As shown in Fig. 5, the shape of a cross section perpendicular to the axial direction of the pillar-shaped semiconductor 130 is a regular hexagon. Then, from the inside of the hexagonal pillar-shaped pillar-shaped semiconductor 130, a current suppression region X1, an active layer 132, and a cylindrical p-type semiconductor 133 are arranged.

[0034] 3. Manufacturing method of semiconductor light emitting element 3-1. Board preparation process 6, a substrate 110 is prepared. The substrate 110 is formed by laminating an n-type semiconductor layer 112 on a conductive base material 111 in this order.

[0035] 3-2. Mask formation process 7 and 8, a mask 120 is formed on the n-type semiconductor layer 112 of the substrate 110. A plurality of openings 120a that expose the n-type semiconductor layer 112 are formed in the mask 120. For this purpose, a technique such as etching may be used.

[0036] FIG. 8 is a diagram showing the arrangement of the openings 120a of the mask 120. FIG. 8 is a diagram showing the substrate 110 viewed from a direction perpendicular to the plate surface of the substrate 110. In FIG. 8, the shape of the columnar semiconductor 130 is drawn by a broken line for reference. As shown in FIG. 8, the openings 120a of the mask 120 are circular and arranged in a square lattice. The openings 120a of the mask 120 are arranged in a planar lattice with respect to the substrate 110 and the n-type semiconductor layer 112. The lattice arrangement is preferably an arrangement shown in the crystal structure restriction theorem. The planar lattice is, for example, an orthorhombic lattice, a hexagonal lattice, a square lattice, a rectangular lattice, or a parallelepiped lattice. Group III nitride semiconductors have a wurtzite structure. For this reason, a hexagonal lattice, a square lattice, or a rectangular lattice is preferable.

[0037] The shape of the pillar-shaped semiconductor 130 can be controlled by changing the shape of the opening 120a of the mask 120. When the shape of the opening 120a is circular, the pillar-shaped semiconductor 130 having a cross-sectional shape close to a regular hexagon can be formed. When the shape of the opening 120a is oval, the pillar-shaped semiconductor 130 having a cross-sectional shape close to a flat shape can be formed.

[0038] 3-3. Columnar semiconductor formation process 9, a hexagonal columnar n-type semiconductor 131 is selectively grown starting from the n-type semiconductor layer 112 exposed under the opening 120a of the mask 120. For this purpose, a known selective growth technique may be used. When the semiconductor layer is selectively grown in this manner, the m-plane is likely to be exposed as a facet.

[0039] For example, a semiconductor is epitaxially grown by MOCVD. The substrate temperature is, for example, 1100° C. to 1200° C. The pressure in the furnace is, for example, 1 kPa to 100 kPa.

[0040] As described above, since the openings 120a of the mask 120 are circular, the columnar n-type semiconductor 131 grows in the shape of a hexagonal column whose cross section is close to a regular hexagon.

[0041] At this point, the supply of the n-type dopant gas is stopped.

[0042] 10, a current suppression region X1 starts to grow on the pillar-shaped n-type semiconductor 131. The current suppression region X1 is, for example, ud-GaN. There is a possibility that ud-GaN may grow slightly on the side surface of the pillar-shaped n-type semiconductor 131. However, the growth rate in the lateral direction is sufficiently slow, so that almost no problem occurs.

[0043] 11, an active layer 132 is formed around a pillar-shaped n-type semiconductor 131. The active layer 132 is formed on the side surface of the pillar-shaped n-type semiconductor 131, which has a cross section shaped like a regular hexagon. The active layer 132 is also formed on the top of the pillar-shaped n-type semiconductor 131.

[0044] 12, a cylindrical p-type semiconductor 133 is formed on the active layer 132 so as to cover the outer periphery of the active layer 132. The cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. The cylindrical p-type semiconductor 133 is formed on the side surface of the active layer 132. The cylindrical p-type semiconductor 133 may also be formed on the top of the columnar n-type semiconductor 131 or the active layer 132. In this manner, the columnar semiconductor 130 is formed.

[0045] 13, a tunnel junction 134 is formed on a cylindrical p-type semiconductor 133 so as to cover the outer periphery of the cylindrical p-type semiconductor 133. The tunnel junction 134 has a hexagonal cylindrical shape.

[0046] 3-4. Buried layer formation process The gap between the pillar-shaped semiconductors 130 is filled with the burying layer 140 .

[0047] 3-5. Electrode formation process Next, a cathode electrode N1 is formed on the n-type semiconductor layer 112 of the substrate 110. In addition, an anode electrode P1 is formed on the buried layer 140.

[0048] 3-6.Other processes A heat treatment step, a step of forming a passivation film or the like on the surface of the semiconductor layer, or other steps may be performed.

[0049] 4. Effects of the First Embodiment Fig. 14 is a diagram conceptually explaining the effect of the semiconductor light emitting device 100 of the first embodiment. In Fig. 14, a current flows along the arrow J1. The semiconductor light emitting device 100 has a current suppression region X1 with high electrical resistivity. Therefore, the current flows avoiding the current suppression region X1. As a result, the active layer 132 in a region adjacent to the columnar n-type semiconductor 131 emits light. The active layer 132 in a region adjacent to the current suppression region X1 hardly emits light. Then, the light travels in the direction of the arrow K1.

[0050] In this way, in the semiconductor light emitting device 100, light emission in the active layer 132 surrounding the current suppression region X1 is suppressed. In other words, light emission in the c-plane and r-plane that may exist around the current suppression region X1 is suppressed. The active layer 132 having the m-plane emits light with high efficiency. This makes it difficult for wavelength variation, an increase in the half-width, and a decrease in light emission efficiency to occur.

[0051] 5. Variations 5-1.Conductive oxide layer A conductive oxide layer may be disposed between the buried layer 140 and the anode electrode P1. The conductive oxide layer may be, for example, a layer made of a transparent conductive oxide such as ITO or IZO.

[0052] 5-2. Array of columnar semiconductors and array of convex parts The plurality of pillar-shaped semiconductors 130 may be arranged in a honeycomb pattern. However, when the semiconductor light emitting device 100 is used as a laser device, the plurality of pillar-shaped semiconductors 130 are preferably arranged in a square lattice, because this makes it easier to generate coherent light.

[0053] 5-3. Mask pattern The shape of the opening of the mask may be other than circular, for example, hexagonal, but even in this case, the pillar-shaped n-type semiconductor 131 grows into a hexagonal pillar shape.

[0054] 5-4. Composition of the current suppression region The composition of the current suppression region X1 may be a group III nitride semiconductor other than ud-GaN. For example, ud-AlGaN. Alternatively, it may be a group III nitride semiconductor doped with Mg, C, O, or B. When doping with Mg, activation is not required. Alternatively, it may be a high resistance layer doped with both Mg, which is a p-type impurity, and Si, which is an n-type impurity. Of course, it may be other high resistance semiconductors.

[0055] 5-5. Composition of columnar semiconductor In this embodiment, the columnar n-type semiconductor 131 is an n-type GaN layer, the well layer is an InGaN layer, the barrier layer is an AlGaN layer, and the cylindrical p-type semiconductor 133 is a p-type GaN layer. These are merely examples, and other Group III nitride semiconductors may be used. Also, other semiconductors may be used.

[0056] 5-6. Composition of buried layer In this embodiment, the material of the buried layer 140 is n However, the buried layer 140 is a GaN layer. n -Instead of the GaN layer n An AlGaN layer can be used. The refractive index of the AlGaN layer is n The refractive index of the buried layer 140 is smaller than that of the GaN layer. Therefore, when forming an LD structure, the light confinement efficiency is improved. n It may be an AlInGaN layer.

[0057] 5-7.Area 3, when the semiconductor light emitting device 100 is a laser diode, the semiconductor light emitting device 100 has a waveguide region R1 and a conduction region R2. The waveguide region R1 is a region used for laser oscillation and for injecting carriers into the active layer 132. The conduction region R2 is a region that allows current to flow and confines light.

[0058] 5-8.Irregularized substrate The conductive base material 111 of the substrate 110 may be textured. In other words, the conductive base material 111 has a textured portion with periodically arranged projections and recesses on the surface on the semiconductor layer side. Examples of the textured shape include a cone shape and a hemisphere shape. These projections may be arranged, for example, in a square lattice shape or a honeycomb shape.

[0059] 5-9.Reflective layer The semiconductor light emitting device 100 may have a reflective layer on the back surface of the substrate 110 opposite the mask layer 120 .

[0060] 5-10.Electron barrier layer An electron barrier layer may be formed on the outer side of the active layer 132. The material of the electron barrier layer is, for example, AlGaInN.

[0061] 5-11.Tunnel junction It is not essential to provide the tunnel junction 134. In that case, the gaps between the pillar-shaped semiconductors 130 are filled with a p-type semiconductor layer.

[0062] 5-12. Cathode electrode The cathode electrode may be formed on the n-type semiconductor layer 112 of the substrate 110. In that case, another substrate may be used instead of the conductive substrate 111. The substrate is, for example, a sapphire substrate.

[0063] 5-13.Rectangular grid The pillar-shaped semiconductors 130 may be arranged at the lattice points of a rectangular lattice instead of a square lattice.

[0064] 5-14.Slope surface 3 and the like, c-plane and m-plane are depicted, but inclined planes inclined to the m-plane are not depicted. However, in reality, inclined planes such as r-planes may exist.

[0065] 5-15. Combination The above modifications may be freely combined.

[0066] Second embodiment A second embodiment will be described. The current suppression region of the second embodiment is different from that of the first embodiment. The differences will be mainly described.

[0067] 1. Semiconductor light emitting element Fig. 15 is a diagram showing the internal structure of the columnar semiconductor 230 of the semiconductor light emitting device 200 of the second embodiment. As shown in Fig. 15, the semiconductor light emitting device 200 has a substrate 110, a mask 120, a columnar semiconductor 230, a buried layer 140, a cathode electrode N1, and an anode electrode P1.

[0068] The pillar-shaped semiconductor 230 includes a pillar-shaped n-type semiconductor 131, an active layer 132, a cylindrical p-type semiconductor 133, a tunnel junction 134, a current suppression region X2, and a suspension portion Y2. Here, the pillar-shaped n-type semiconductor 131 is preferably n-type AlGaN having a high Al composition.

[0069] The current suppression region X2 is a void. The current suppression region X2 is filled with air.

[0070] The suspension Y2 is a semiconductor layer for forming the current suppression region X2.

[0071] 2. Manufacturing method of semiconductor light emitting device The points that differ from the first embodiment will be described.

[0072] The current suppression region X2 is formed by the method described in JP 2018-110172 A (paragraphs

[0057] to

[0066] of JP 2018-110172 A).

[0073] First, a pillar-shaped n-type semiconductor 131 is formed. An InGaN layer is formed as a decomposition layer on the pillar-shaped n-type semiconductor 131. Next, an AlGaN layer is formed as the suspension portion Y2. Next, the InGaN layer as the decomposition layer is decomposed by etching.

[0074] 3. Effects of the Second Embodiment The electrical resistivity of the current suppression region X2 of the semiconductor light emitting device 200 of the second embodiment is higher than the electrical resistivity of the current suppression region X1 of the first embodiment. Therefore, in the semiconductor light emitting device 200 of the second embodiment, light emission other than from the m-plane is further suppressed.

[0075] 4. Variations 4-1. Decomposition layer The decomposition layer may be a GaN layer.

[0076] 4-2.Other A variation of the first embodiment can be used.

[0077] (Third embodiment) The third embodiment will be described, focusing on the differences from the first embodiment.

[0078] 1. Semiconductor light emitting element Fig. 16 is a conceptual diagram showing a planar structure of a semiconductor light emitting device 300 of the third embodiment. The semiconductor light emitting device 300 has a substrate 110, a mask 120, a columnar semiconductor 130, an embedded layer 340, a cathode electrode N1, and an anode electrode P1. As shown in Fig. 16, the semiconductor light emitting device 300 has a gap Z1 between the columnar semiconductors 130.

[0079] The pillar-shaped semiconductors 130 are arranged in a planar lattice pattern. In Fig. 16, the pillar-shaped semiconductors 130 are arranged in a rectangular lattice pattern. A gap Z1 is formed in a region located at the center of a face of a unit cell of the planar lattice.

[0080] 2. Refractive index Fig. 17 is a conceptual diagram showing the relationship between the XVII-XVII cross section of Fig. 16 and the average refractive index distribution. As shown in Fig. 17, the refractive index of InGaN of the active layer 132 included in the pillar-shaped semiconductor 130 is high. Therefore, the average refractive index of the pillar-shaped semiconductor 130 is higher than the refractive index of GaN of the buried layer 340.

[0081] Fig. 18 is a conceptual diagram showing the relationship between the XVIII-XVIII cross section of Fig. 16 and the average refractive index distribution. In Fig. 18, the pillar-shaped semiconductor 130 is depicted by a dashed line. As shown in Fig. 18, the refractive index of the gap Z1 is smaller than the refractive index of the buried layer 340.

[0082] If the gap Z1 did not exist, the refractive index would be constant without spatial variation in FIG.

[0083] Thus, in the third embodiment, in the region where the columnar semiconductors 130 exist, the refractive index tends to be high in the region of the columnar semiconductors 130.

[0084] 3. Manufacturing method of semiconductor light emitting element To form the voids Z1, the formation of the buried layer 340 may be interrupted midway. The buried layer 340 grows from the m-plane of the pillar-shaped semiconductor 130. Therefore, the voids Z1 are formed at the midpoints of the pillar-shaped semiconductors 130 arranged in a square lattice pattern. The voids Z1 have a shape that occupies the inside of a hexagonal cylinder.

[0085] 4. Effects of the Third Embodiment In a laser element with such a structure, when the injected current exceeds the threshold current, stimulated emission occurs from the active layer on the m-plane. Then, laser oscillation occurs in a direction perpendicular to the XVII-XVII or XVIII-XVIII cross section. In this case, the refractive index distribution in the waveguide on the XVII-XVII and XVIII-XVIII cross sections becomes similar. This reduces scattering loss when the laser light is guided. This improves the slope efficiency.

[0086] FIG. 19 is a schematic diagram showing a case where the columnar semiconductors 130 are arranged in three rows. FIG. 19(b) shows the light intensity of the XIX-XIX cross section of FIG. 19(a). Here, the line L1 is the light intensity in the semiconductor light emitting device 300 of the third embodiment. The line L2 is the light intensity in the semiconductor light emitting device when the gap Z1 does not exist. By making the refractive index distribution tendency of the XVII-XVII cross section where the columnar semiconductors 130 are present and the XVIII-XVIII cross section where the columnar semiconductors 130 are not present closer to each other, the scattering loss is reduced. Therefore, the standing wave is easily formed stably. This realizes a super single mode with higher intensity.

[0087] 19, the light intensity reaches a maximum value where the pillar-shaped semiconductors 130 are present. That is, the light intensity is high where the pillar-shaped semiconductors 130 are present. The light intensity reaches a minimum value in the regions between the pillar-shaped semiconductors 130. And the light intensity is highest around the center column of the three columns.

[0088] 19, the maximum light value of the line L1 is greater than the maximum light value of the line L2, and the minimum light value of the line L1 is smaller than the minimum light value of the line L2.

[0089] In the semiconductor light emitting device 300, strong light can be transmitted through the columns of the columnar semiconductors 130. For this reason, for example, when a laser is oscillated by making light go back and forth in the direction of the arrow A1 in FIG. 1, a laser with strong intensity can be oscillated.

[0090] In this manner, by adjusting the refractive index in the region where the pillar-shaped semiconductor 130 does not exist, the light intensity at the location of the pillar-shaped semiconductor 130 can be increased.

[0091] 5. Variations 5-1. Pit Instead of the gap Z1, a pit may be formed. The shape of the pit may be a V-shape composed of a {10-1x} plane or a {11-2y} plane that is oblique to the {0001} plane of the III-nitride semiconductor. The pit may be composed of a plane perpendicular to the {0001} plane, such as a {10-10} plane or a {11-20} plane. Of course, the pit may have a shape that combines an oblique plane and a perpendicular plane. It is preferable that all of these pits have the same shape. In this case, the average refractive index of the region is also the same. This allows a more stable standing wave to exist.

[0092] 5-2.Other A modification of the first embodiment can be used. For example, the same effect can be obtained by filling the gaps Z1 or pits with a layer having a lower refractive index than the embedding layer 340. For example, when the embedding layer 340 is GaN, the gaps Z1 or pits may be filled with an AlGaN layer having a lower refractive index than GaN or a transparent electrode such as ITO. In this case, the flatter the surface after embedding, the easier it is to perform the subsequent electrode formation and device fabrication processes.

[0093] (Fourth embodiment) The fourth embodiment will be described, focusing on the differences from the first embodiment.

[0094] 1. Semiconductor light emitting element Fig. 20 is a schematic configuration diagram of a semiconductor light emitting device 400 of the fourth embodiment. As shown in Fig. 20, the semiconductor light emitting device 400 has a substrate 110, a mask 120, a columnar semiconductor 130, a buried layer 440, a cathode electrode N1, and an anode electrode P1.

[0095] The buried layer 440 includes a first layer 441, a second layer 442, and a third layer 443. The first layer 441, the second layer 442, and the third layer 443 are n-type semiconductor layers, for example, n-type GaN.

[0096] The first layer 441 covers the columnar semiconductor 130. The second layer 442 covers the first layer 441. The third layer 443 covers the second layer 442. The second layer 442 is sandwiched between the first layer 441 and the second layer 442. The third layer 443 is in contact with the anode electrode P1.

[0097] The Si concentration of the second layer 442 is higher than the Si concentration of the first layer 441. The Si concentration of the third layer 443 is higher than the Si concentration of the second layer 442. The Si concentration of the first layer 441 is, for example, 1×10 17 cm -3 More than 2×10 18 cm -3 The Si concentration of the second layer 442 is, for example, 2×10 18 cm -3 5×10 or more 18 cm -3 The Si concentration of the third layer 443 is, for example, 5×10 18 cm -3 5×10 or more 19 cm -3 The following is the result.

[0098] 2. Manufacturing method of semiconductor light emitting device The amount of the dopant gas containing Si may be increased to grow the buried layer 440. The amount of the dopant gas may be increased gradually or stepwise.

[0099] 3. Effects of the Fourth Embodiment The impurity concentration is low around the pillar-shaped semiconductor 130 in the buried layer 440. Therefore, light absorption is less likely to occur around the pillar-shaped semiconductor 130. Therefore, in an LED, a decrease in light extraction efficiency is suppressed. In a laser diode (LD), an increase in threshold current and a decrease in gain are suppressed. Here, the periphery of the pillar-shaped semiconductor 130 is, for example, the first layer 441.

[0100] In the region of the buried layer 440 away from the pillar-shaped semiconductor 130, the impurity concentration is high. In this region, the electrical resistivity is low. Therefore, current flows easily. Here, the region of the buried layer 440 away from the pillar-shaped semiconductor 130 is, for example, the third layer 443. In the region of the buried layer 440 away from the pillar-shaped semiconductor 130, light may be absorbed. However, this light passes through, for example, a region that hardly contributes to laser oscillation. Therefore, in the LD, the absorption of this light hardly affects the threshold current and gain.

[0101] That is, in the semiconductor light emitting device 400, an increase in threshold current and a decrease in gain are suppressed, and current flows easily.

[0102] 4. Variations 4-1. When there is no tunnel junction In the case where there is no tunnel junction, the buried layer in which the pillar-shaped semiconductor 130 is buried is a p-type layer. Even in this case, the Mg concentration may be made low around the pillar-shaped semiconductor 130 and may be made high as the distance from the pillar-shaped semiconductor 130 increases. The Mg concentration of the first layer is, for example, 1×10 18 cm -3 5×10 or more 19 cm -3 The Mg concentration in the second layer is, for example, 5×10 19 cm -3 More than 1×10 20 cm -3 The Mg concentration in the third layer is, for example, 1×10 20 cm -3 5×10 or more 20 cm -3 The following is the result.

[0103] In addition, when a p-type layer is embedded, it is preferable to have a p-type contact layer in contact with the anode electrode P1. The Mg concentration of the p-type contact layer is, for example, 5×10 20 cm -3 5×10 or more 21 cm -3 The following is the result.

[0104] 4-2.Other A variation of the first embodiment can be used.

[0105] Fifth embodiment The fifth embodiment will be described, focusing on the differences from the first embodiment.

[0106] 1. Semiconductor light emitting element Fig. 21 is a schematic configuration diagram of a semiconductor light emitting device 500 of the fifth embodiment. As shown in Fig. 21, the semiconductor light emitting device 500 has a substrate 510, a mask 120, a columnar semiconductor 530, a buried layer 540, a cathode electrode N2, and an anode electrode P2.

[0107] The substrate 510 has an n-type semiconductor layer 511, a tunnel junction 512, and a p-type semiconductor layer 513. The n-type semiconductor layer 511 is, for example, an n-type GaN layer. The p-type semiconductor layer 513 is, for example, a p-type GaN layer.

[0108] The tunnel junction 512 has a p+ layer 512a and an n+ layer 512b. The p+ layer 512a is disposed between the n+ layer 512b and the p-type semiconductor layer 513. The n+ layer 512b is disposed between the n-type semiconductor layer 511 and the p+ layer 512a. The p+ layer 512a is, for example, a p-type GaN layer. The n+ layer 512b is, for example, an n-type GaN layer. The Mg concentration of the p+ layer 512a is higher than the Mg concentration of the p-type semiconductor layer 513. The Si concentration of the n+ layer 512b is higher than the Si concentration of the n-type semiconductor layer 511.

[0109] The pillar-shaped semiconductor 530 includes a pillar-shaped p-type semiconductor 531 and an active layer 532. The pillar-shaped p-type semiconductor 531 is, for example, a p-type GaN layer.

[0110] The buried layer 540 fills the gaps between the columnar semiconductors 530. The buried layer 540 is an n-type semiconductor layer. The buried layer 540 is, for example, an n-type GaN layer.

[0111] The cathode electrode N2 is formed on the buried layer 540. The anode electrode P2 is formed on the substrate 510.

[0112] 2. Effects of the Fifth Embodiment Even in this case, the same effects as in the first embodiment can be obtained.

[0113] 3. Variations There are cases where it may be possible to combine it with the modified example of the first embodiment.

[0114] (Combination of embodiments) In some cases, the first to fifth embodiments may be combined.

[0115] (Additional Note) A semiconductor light emitting device according to a first aspect has an underlayer, a plurality of columnar semiconductors on the underlayer, a buried layer filling gaps between the plurality of columnar semiconductors, and a current suppression region suppressing a current. The plurality of columnar semiconductors have a hexagonal columnar portion having a hexagonal columnar shape and an active layer covering the hexagonal columnar portion. The hexagonal columnar portion has a hexagonal first surface and a second surface opposite to the first surface. The first surfaces of the plurality of columnar semiconductors face the underlayer. The second surfaces of the plurality of columnar semiconductors face the current suppression region.

[0116] In the semiconductor light emitting device according to the second aspect, the current suppression region is a semiconductor having an electrical resistivity higher than that of the plurality of columnar semiconductors.

[0117] In the semiconductor light emitting device according to the third aspect, the current suppression region is a gap.

[0118] In the semiconductor light emitting device according to the fourth aspect, the plurality of columnar semiconductors are arranged in a planar lattice pattern, and voids or pits are formed in regions located at the face centers of unit cells of the planar lattice.

[0119] In the semiconductor light emitting device according to a fifth aspect, the embedded layer has a first layer covering the plurality of columnar semiconductors and a second layer covering the first layer, The second layer has an impurity concentration higher than the impurity concentration of the first layer.

[0120] A sixth aspect of the present invention relates to a semiconductor light emitting device having a tunnel junction, the tunnel junction having a p-type layer and an n-type layer, and being disposed at a position between the active layer and the buried layer.

[0121] A seventh aspect of the present invention provides a semiconductor light emitting device having an anode electrode and a conductive oxide layer, the conductive oxide layer being disposed between the buried layer and the anode electrode. [Explanation of symbols]

[0122] 100...Semiconductor light emitting device 110...Substrate 111...Conductive base material 112...n-type semiconductor layer 120…Mask 130...Columnar semiconductor 131...Columnar n-type semiconductor 132...Active layer 133...Cylindrical p-type semiconductor 134…Tunnel junction 140…Buried layer N1: Cathode electrode P1…Anode electrode

Claims

1. An n-type semiconductor layer, a tunnel junction on the n-type semiconductor layer; a p-type semiconductor layer over the tunnel junction; A plurality of pillar-shaped semiconductors on the p-type semiconductor layer; a buried layer which is an n-type semiconductor and fills gaps between the plurality of pillar-shaped semiconductors; a current suppression region that suppresses the current; having Each of the pillar-shaped semiconductors is A p-type hexagonal column portion having a hexagonal column shape; an active layer covering the p-type hexagonal column portion, The p-type hexagonal column portion is a hexagonal first surface and a second surface opposite the first surface; The first surface is facing the p-type semiconductor layer, The second surface is Facing the current suppression region A semiconductor light emitting device comprising:

2. 2. The semiconductor light emitting device according to claim 1, The current suppression region is The semiconductor has a higher electrical resistivity than each of the pillar-shaped semiconductors. A semiconductor light emitting device comprising:

3. 2. The semiconductor light emitting device according to claim 1, The current suppression region is Being a void A semiconductor light emitting device comprising:

4. The semiconductor light emitting device according to any one of claims 1 to 3, The plurality of pillar-shaped semiconductors include They are arranged in a flat grid pattern, A void or pit is formed in an area located at the center of a face of a unit cell of the planar lattice. A semiconductor light emitting device comprising:

5. The semiconductor light emitting device according to any one of claims 1 to 4, The buried layer is A first layer covering the plurality of pillar-shaped semiconductors; a second layer covering the first layer, The impurity concentration of the second layer is The impurity concentration of the first layer is higher than that of the first layer. A semiconductor light emitting device comprising:

6. The semiconductor light emitting device according to any one of claims 1 to 5, An anode electrode; A conductive oxide layer; having The conductive oxide layer is being disposed between the buried layer and the anode electrode; A semiconductor light emitting device comprising:

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