Apparatus and method for maintaining stable clocking - Patents.com

Abstract

Both before and after a surprise clock stop, the apparatus and method of various embodiments provide a stable, continuous clock to the memory module using a unique configuration of circuit components, including a clock detector circuit, a clock smoothing circuit, and one or more PLLs. Upon detecting the stopped host clock, the first PLL seamlessly switches to an alternate reference clock from an onboard crystal oscillator. The clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period deviations greater than the natural jitter of a locked PLL, and one or more optional downstream PLLs may drive additional clock domains.

Description

[Background technology]

[0001] Several types of solid-state, high-density, non-volatile memories (NVM) provide persistent storage in commercial computer systems. Such technologies include Intel® Optane™ DC Persistent Memory, Spin-Transfer Torque-Magnetic Random Access Memory (STT-MRAM), Resistive RAM (ReRAM), NAND, Conductive Bridging RAM (CBRAM), or Phase Change Memory (PCM). These memories may be implemented on memory modules, where a memory controller links the non-volatile memory to a processor (e.g., a central processing unit (CPU)) through one or more high-speed interfaces, such as PCIe (Peripheral Component Interconnect Express) or DDR (Double Data Rate Interface). These memories rely on a stable clock for read and write purposes. A sudden or unexpected stop or loss of the clock can impair or halt an ongoing write operation. [Brief description of the drawings]

[0002] The embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure, which should not be construed as limiting the disclosure to the particular embodiments, but are merely for illustration and understanding.

[0003] [Figure 1] 1 illustrates a high-level architecture of a memory module with an apparatus for maintaining stable clocking in accordance with some embodiments of the present disclosure.

[0004] [Diagram 2] 1 illustrates a clocking architecture for a memory module having an apparatus for maintaining stable clocking in accordance with some embodiments of the present disclosure.

[0005] [Diagram 3] 1 illustrates an apparatus and associated timing diagram of a clock detector circuit according to some embodiments.

[0006] [Figure 4] 1 illustrates a phase-locked loop (PLL) coupled to a clock smoothing circuit for adjusting the up and down pulses, according to some embodiments.

[0007] [Diagram 5] 1 illustrates an apparatus for clock smoothing and associated timing diagrams according to some embodiments.

[0008] [Figure 6] 4 shows plots illustrating clock exchange performance of a PLL and clock smoothing circuit in accordance with some embodiments.

[0009] [Figure 7] 1 illustrates a smart device or computer system or SoC (system on chip) having an apparatus for maintaining stable clocking, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] For clocking and synchronization through the memory interface, the memory module relies on either a direct clock from the host processor (e.g., CPU) or a reference clock signal from the host processor used for on-board clock recovery within the memory module. Host or module power failure, module unseating, thermal trip, or other malfunction can cause an unexpected and unannounced loss of the host clock, which the memory module considers a "surprise clock stop."

[0011] One problem occurs during a surprise clock stop when the host processor (or simply the host) and the memory module may have very different views of the status of a transaction. The host believes that all writes the memory module receives before the surprise clock stop are safely stored in its persistent memory. However, the memory module uses hundreds or even thousands of clock cycles to complete the complex task of writing to the medium (e.g. persistent memory) after receiving the data. Furthermore, because a surprise clock stop may be caused by a power loss, the memory module is expected to complete these writes within a limited time window in which the hold-up capacitors can safely maintain the module's power supply level. If the clock stop occurs after the host transaction is complete but before the memory module has finished writing all the data, a number of data integrity and security issues are seen, including line instability, data loss, illegal register accesses, FIFO (first-in-first-out) underflows, and firmware state corruption. These issues can be avoided if the module maintains a continuous and stable clock after a surprise clock stop event.

[0012] To solve this problem, after a surprise clock stop, a reset sequence can be initiated that involves locking or relocking the phase-locked loop (PLL) to an alternative reference clock source, such as an on-module crystal oscillator, and then the output of the PLL drives the clock distribution network after the PLL has locked into a steady state.

[0013] However, reset sequences can take thousands of clock cycles just to lock the PLL and enable downstream clock circuits such as DLLs (delay locked loops) and clock-crossing queues. A much better use of this valuable time would be to complete ongoing operations on schedule to meet the required latency constraints for a given protocol or for a given physical media type. Furthermore, long reset sequences require the module to remain powered for a longer period after power loss, resulting in additional cost and area for either additional hold-up capacitors or more expensive materials such as tantalum.

[0014] Another way to solve the problem of sudden clock stoppage is to switch to a new clock source that directly drives the clock distribution network. The new clock source can be either an on-module crystal oscillator or an on-die ring oscillator.

[0015] However, when switched on, the new clock source can introduce glitches into the clock distribution network, either as runt pulses, stretched periods, or shortened periods. Runt pulses can evaporate intermittently at different physical locations in the memory controller; stretched periods can cause downstream delay lines to malfunction; and shortened periods can cause timing failures. Additionally, non-stationary clocks can cause synchronous clock crossings to fail. Furthermore, if the new clock is from an on-die ring oscillator, inherent device and power supply noise can cause increasingly uncorrected stretched or shortened periods over time as the noise accumulates, eventually leading to timing failures.

[0016] Another solution, for memory controllers that synthesize their clock from the host clock, is to handle a stalled clock by freezing the state of the PLL's oscillator control as a voltage on a capacitor (for analog PLLs) or a digital control word (for digital PLLs). In the case of a stalled clock scenario, the PLL is now operating in open-loop mode with a static oscillator control value, so there is no correction to the oscillator phase or frequency. Device and power supply noise can cause uncorrected stretched or shortened periods over time as the noise accumulates, eventually leading to timing failures.

[0017] Some embodiments solve the problem of sudden clock stop by ensuring a stable and continuous clock to the memory module even after a surprise clock stop event, thus ensuring timely completion of all on-module operations and preserving data integrity and security. An apparatus of an embodiment provides a stable and continuous clock to the memory module both before and after a surprise clock stop using a unique configuration of circuit components including a clock detector circuit, a clock smoothing circuit, and one or more PLLs. Upon detecting a stopped host clock, the first PLL seamlessly switches to an alternative reference clock, for example from an on-board crystal oscillator. The clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period deviations greater than the natural jitter of a locked PLL. In some embodiments, one or more downstream PLLs can drive additional clock domains from the first PLL.

[0018] The apparatus and methods of various embodiments allow the memory controller to continuously drive the clock distribution network of the memory module with a glitchless clock that is stable in both frequency and phase before and after a surprise clock stop. There may be no need to relock the PLL, and zero time may be wasted in reset sequences to relock the PLL or adjust downstream clock circuits such as DLLs or clock crossings. The apparatus and methods of various embodiments ensure completion of ongoing operations on the same schedule as normal operations, thus meeting required latency constraints for a given protocol or physical media type, maintaining data integrity, and reducing hold-up capacitor cost and board area. Other technical effects will be apparent from the various embodiments and figures.

[0019] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments of the present disclosure.

[0020] Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and / or may have arrows at one or more ends to indicate the primary information flow direction. Such designations are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate understanding of a circuit or logic unit. Any represented signal, as dictated by design need or preference, may actually include one or more signals that may travel in either direction and may be implemented with any suitable type of signaling.

[0021] Throughout the specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical or magnetic connection, between the things that are connected, without any intervening devices.

[0022] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intervening devices.

[0023] As used herein, the term "adjacent" generally refers to the location of an object that is next to another object (e.g., immediately adjacent or in close proximity with one or more objects between) or adjacent to (e.g., abutting) another object.

[0024] The term "circuit" or "module" may refer to one or more passive and / or active components configured to cooperate with each other to provide a desired functionality.

[0025] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "at" includes "in" and "on."

[0026] The term "scaling" generally refers to converting a design (diagrams and layout) from one process technology to another, which may then reduce the layout area. In some cases, scaling may also refer to upsizing a design from one process technology to another, which may then increase the layout area. The term "scaling" generally refers to making layouts and devices smaller or larger within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up -- i.e., scaling down or up, respectively) other parameters, such as signal frequency, relative to power supply levels. The terms "substantially," "close," "approximately," "near," and "about" generally refer to within ±10% of a target value.

[0027] Unless otherwise noted, the use of ordinal adjectives "first," "second," "third," etc. to describe a common object indicates merely that different instances of a similar object are being referred to, and is not intended to imply that the objects so described must be in a given sequence, temporally, spatially, in ranking, or in any other way.

[0028] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0029] In the specification and claims, terms such as "left," "right," "front," "rear," "top," "bottom," "upper," "lower," and the like, if any, are used for descriptive purposes and not necessarily to describe permanent relative positions.

[0030] It is pointed out that elements of a figure having the same reference number (or name) as elements of another figure may operate or function in a similar manner as described, but is not limited to such.

[0031] For purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are Metal Oxide Semiconductor (MOS) transistors or derivatives thereof, with MOS transistors including drain, source, gate, and bulk terminals. Transistors and / or MOS transistor derivatives also include other devices performing transistor functions, such as Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunnel FETs (TFETs), square wire or rectangular ribbon transistors, Ferroelectric FETs (FeFETs), or carbon nanotube or spintronic devices. The symmetrical source and drain terminals of a MOSFET are i.e., identical terminals, and are used interchangeably herein. On the other hand, TFET devices have asymmetrical source and drain terminals. Those skilled in the art will appreciate that other transistors, such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the present disclosure.

[0032] 1 illustrates a high level architecture 100 for a memory module with an apparatus for maintaining a stable clock in accordance with some embodiments of the present disclosure. The architecture 100 includes a host processor 101, a memory module 102, and a host-memory interface 103 (e.g., an interface such as DDR, PCIe, etc.). In various embodiments, the memory module 102 includes a memory controller 104 with a clock stabilizer 105, and N memory banks 106. 1~Nand n=n, where N is an integer greater than 1. The memory banks can be volatile or non-volatile memory. Examples of memory for the memory banks include: Spin Transfer Torque-Magnetic Random Access Memory (STT-MRAM), Resistive RAM, NAND, Conductive Bridging RAM (CBRAM), or Phase Change Memory (PCM). In various embodiments, the memory module 102 includes or is coupled to another clocking source 107. In this example, the additional clocking source is a crystal oscillator 107. The crystal oscillator 107 can be packaged in the same package as the memory module or can be external to the package. The interface 103 provides data, clock (strobe), and control signals. If the clock from the host processor 101 stops, the clock stabilizer 105 ensures that the memory controller 104 continues to operate as expected without data integrity and security issues, including circuit instability, data loss, incorrect register access, FIFO underflow, and firmware state corruption.

[0033] In some embodiments, both before and after a surprise clock stop from the host processor 101, the clock stabilizer 105 uses a clock detection circuit, a clock smoothing circuit, and one or more PLLs to provide a stable, continuous clock to the memory controller 104 and the memory banks 106. 1-N Upon detecting a stopped host clock, the first PLL seamlessly switches over from the on-board crystal oscillator 107 to the alternative reference clock by the clock stabilizer 105. The clock smoothing circuitry of the clock stabilizer 105 allows the first PLL to maintain a steady phase and frequency without inducing glitches or period deviations greater than the natural jitter of a locked PLL. In some embodiments, one or more optional downstream PLLs may drive additional clock domains within the memory module 102.

[0034] FIG. 2 illustrates a clocking architecture 200 of a memory module 102 with an apparatus for maintaining stable clocking, according to some embodiments of the present disclosure. In some embodiments, the clock stabilizer 105 of the clocking architecture 200 includes a frequency divider 201, a multiplexer 202, a clock detector circuit 203, a clock smoothing circuit 204 (e.g., 204). 1-M ), and one or more PLLs 205 1-M The clock detector circuit 203 allows on-the-fly switching of the reference clock (RefClk) input of the PLL 2051 while maintaining a stable and continuous output clock without relocking any PLLs in the memory controller 104. After a surprise clock stop event from the host processor 101, the clock stabilizer 105 detects the clock in the non-volatile memory 106 and 1-N This ensures on-scheduled completion of ongoing operations on the host clock, thus maintaining normal latency, preserving data integrity, and reducing the cost of hold-up capacitors. Under normal operation of the computer system, the divider 201 of the memory controller 104 divides down the high-speed host clock frequency (e.g., in the range of 500 MHz to 10 GHz) of the host clock and delivers a slower reference clock or host clock (e.g., in the range of 10 MHz to 200 MHz) to the first PLL[0] 2051. This slower reference frequency is matched in frequency (e.g., within 10%, or within 0.1%) to the crystal clock of the on-module crystal oscillator 107, which is not used in normal operation. In various embodiments, the controller 104 is designed to support a worst-case frequency accuracy specification in parts per million (PPM), whether it is the host crystal oscillator or the on-board oscillator.

[0035] The first PLL[0] 1051 then generates a high speed output clock (PLL[0] clock) that drives a clock distribution network 2061; and / or divider 207 provides a low speed reference clock for one or more additional downstream PLLs 2052 that drive additional clock distribution networks and clock domains 2062 and beyond. The output clock, clock0, of the distribution network 2061 is then fed to the clock domains (e.g., endpoint 208). 1-N ), where clock domain refers to logic or a group of logic that operates on a particular clock. Clock0 is also used by divider 207 to generate another reference clock for downstream PLL 2052. The output clock of PLL[1] 2052 is then received by clock distribution network 2062 to generate clock1. To reduce any significant phase noise in the downstream PLL, the downstream PLL has an associated clock smoothing circuit. For example, clock smoothing circuit 2042 operates in conjunction with PLL[1] 2052. Clock1 is then used by another clock domain (e.g., endpoint 209). 1-N ) is used by the memory array or bank 106. This clock (for example, clock1) or another downstream clock may be used by the memory array or bank 106. 1-N Examples of endpoints include sampling circuits, encoders, decoders, error correction logic, etc. In some embodiments, the clock smoothing circuit 2042 for PLL[1] and beyond may be removed.

[0036] After a surprise clock stop, the clock detector circuit 203 provides a continuous and stable clock to the memory module 102. In some embodiments, the clock detector 203 quickly detects the stopped host clock and initiates a swap from the slower host-derived reference clock to the slower on-module crystal oscillator 107 clock. In some embodiments, the clock detector circuit 203 detects the stopped host clock using digital circuitry. For example, the clock detector circuit 203 samples a divided-by-2 version of the high-speed host clock with the output of the first PLL[0] 2051 (PLL[0] clock), where a matched path delay centers the rising edge of the PLL[0] clock relative to the divided-by-2 host clock. When the current sample matches the previous sample, the clock detector circuit 203 asserts a clock select signal (e.g., Stopped Clock) indicating that the host clock has stopped. Although the output of the first PLL[0] 2051 may drift and eventually become unstable without the reference, the clock detection operation is completed within a few fast host clock cycles, which is short enough to ensure that the output of the first PLL[0] 2051 remains stable until a stopped host clock is detected (e.g., less than a slow reference clock cycle).

[0037] Upon detecting the stopped host clock, the clock stabilizer 105 performs an on-the-fly switch, via the multiplexer 202, to the on-module crystal oscillator 107 as the new reference clock source for the first PLL[0] 2051. In this example, the clock smoothing circuit 204 maintains a stable, continuous output clock from the PLL[0] 2051 even under this sudden change in the reference clock, so there is no need to relock any PLL. The clock smoothing circuit 204 allows the first PLL[0] 2051 to slowly and gradually track the phase of the new reference clock while maintaining a steady output frequency that is well within the timing tolerances.

[0038] Using the clock smoothing circuit 204, the PLL 2051 maintains a stable output clock frequency without relocking and under sudden phase changes such as may occur during a reference clock switch. The clock smoothing circuit 204 ensures minimal frequency and phase deviations on the output of the first PLL 2051 as it slowly aligns to the new reference clock. 2-M ), the frequency and phase deviations are even smaller due to its low-pass filter characteristics. In this example, PLL[0] 2051 is connected to downstream PLL[1:M] 2052 which clocks the various domains on the module. 2-M All PLL output clocks have negligible cycle-to-cycle frequency and phase deviations, such as those found under spread spectrum clocking or natural crystal oscillator drift, but maintain a consistent period, within a reasonable timing tolerance, both before and after the clock is stopped.

[0039] The low-pass filtering characteristic of the downstream PLL reduces the frequency deviation slightly (e.g., about 5%) at the output of the PLL [1] for an implementation without clock smoothing, while with clock smoothing a much smaller frequency deviation (e.g., less than 0.3%) is seen. A common reference clock keeps all on-module PLLs synchronized, and since there is no host clock, they no longer need to synchronize with the host. In some embodiments, clock multiplication is advantageous for high-speed outputs; the sudden maximum input phase error (e.g., 0.5 × T of RefClk) can be reduced by 100%. Period ), the clock smoothing circuit 204 limits the change in phase and / or frequency of the high speed oscillator output to less than a small percentage of the high speed clock period.

[0040] FIG. 3 illustrates an apparatus 300 and associated timing diagram of a clock detector circuit, according to some embodiments. The apparatus 300 includes flip-flops 301, 303, and 304, an inverter 302, and combinational logic 305 (e.g., an exclusive NOR gate) coupled together as shown. It samples a divided-by-two version of the high-speed host clock relative to the PLL[0] clock, with matched path delays centering the rising edge of the PLL[0] clock relative to the divided-by-two host clock (Host Clock div 2). When the current sample (sample N) from flip-flop 303 matches the previous sample (sample N-1) from flip-flop 304, the combinational logic 305 asserts a clock signal (Stopped Clock) indicating that the host clock has stopped. Depending on the clock speed, implementations may use additional sampling depth (e.g., four samples) to further increase robustness against jitter. In one example, two additional flip-flops (not shown) are used to generate sample N-2 and sample N-3, which are then compared to sample N and sample N-1 before the Clock Select signal is asserted to indicate that the host clock has indeed stopped. Although PLL[0] may drift and eventually become unstable without a reference, the clock detection operation is completed within a few fast host clock cycles, which is short enough to ensure that the PLL[0] clock remains stable until the stopped host clock is detected (indeed, less than a slow reference clock cycle). Some embodiments may not only increase the sampling depth, but also the width. For example, sample N and sample N-1 in FIG. 3 are shifted versions of Host Clock div 2, which is also a 1-bit counter. The counter width may be increased to N bits. And the number scheme may be implemented in any style, such as Gray code or binary counting.

[0041] 4 illustrates a phase-locked loop (PLL) coupled to a clock smoothing circuit for adjusting the up and down pulses, according to some embodiments. The PLL 400 includes a phase detector 401 or phase frequency detector (PFD), a charge pump 402, a filter 403, a voltage controlled oscillator (VCO) 404, a divider 405, and the clock smoothing circuit 204. Other components of the PLL, such as a lock detector, are not shown so as not to obscure the embodiments.

[0042] Phase detector 401 receives a reference clock (RefClk) and a feedback clock (FbClk) and generates up (Up) and down (Dn) signals. The Up and Dn signals are pulses that represent the different relative phases between RefClk and FbClk. In the absence of clock smoothing circuit 204, charge pump 402 receives the Up and Dn pulses and sources or sinks current at node V1. The signal on V1 is then filtered by filter 403 (e.g., low pass filter (LPF)) to generate a filtered control voltage Vctl. Vctl is then used to control the oscillation frequency of VCO 404. The output of VCO 404 is VcoClk. Divider 405 divides the frequency of VcoClk by a divider ratio to generate FbClk. During PLL lock, the Up and Dn signals provide evidence of dynamic phase error. The divider ratio can be programmable or fixed. The divider ratio can be an integer or fractional value. The dynamic phase error is the phase error between RefClk and FbClk before the PLL is declared locked when the phase difference between RefClk and FbClk falls below a predefined threshold.

[0043] Some implementations of phase detector 401 use analog circuit techniques, while others use digital circuits. Phase detector 401 can be designed to be sensitive to just phase or to frequency and phase. If the phase detector is only sensitive to the phase of RefClk and FbClk, it generates an output proportional to the phase difference between the two signals. If the phase difference between RefClk and FbClk is stationary, phase detector 401 generates a constant voltage. If there is a frequency difference between the two signals (RefClk and FbCLk), phase detector 401 generates a varying voltage. Examples of phase detector 401 include diode-based ring phase detectors, dedicated OR phase detectors, JK flip-flop-based comparators, and dual D-type phase detectors. In general, when a digital phase detector implements phase detector 401, short Up and Dn pulses are generated by the logic gates of the digital phase detector. The static phase error is the pulse width difference between the Up and Dn pulses, which is caused by leakage currents and mismatch of charge pump currents.

[0044] When the PLL is in normal operating mode, the PFD outputs pulses of duration proportional to the phase error between the PLL's RefClk and FBClk inputs. These pulses allow the charge pump to source or sink an amount of charge proportional to the magnitude and sign of the phase error. The charge is pumped into a capacitor (Cp) and filtered to provide a control voltage for the VCO 404, which speeds up or slows down its output frequency in response to changes in the control voltage (Vctl). Eventually, the PLL reaches a steady-state "locked" state with a nearly constant Vctl and minimal phase error. The divide-by-N divider 405 allows the PLL to output a frequency N times greater than the Refclk frequency.

[0045] A sudden change in the source of RefClk can introduce a large phase error at the input to PFD 401. As can be seen, the amount of charge that capacitor Cp sources or sinks to control VCO 404 is a function of the phase error. The amount of charge sampled on the capacitor per unit time is a function of the capacitor size (Cp) and the change in charge per unit time, i.e., current (Ip=dQ / dT). For a moment, this change in charge is multiplied by the number of RefClk periods (T Period ), we want to limit the maximum change in Vctl to less than the maximum that can be sourced or sunk over t0. Since the change in Vctl voltage is proportional to the current, this now limits the maximum change in Vctl to (Ip / (2πCp))*t0 (t0≪T Period ), which means that the gain of the PFD 401 and charge pump system 402 can be saturated and stop the VCO 404 from suddenly changing phase and / or frequency due to a sudden large phase error. In various embodiments, the clock smoothing circuit 204 intercepts the PFD outputs (up and dn) and limits the pulse length to t0<(1%*T Period ), thus providing modified up and down pulses (Up' and Dn') to the charge pump 402 to limit the amount of charge sinking or sourcing node V1. By limiting the pulse width to t0, the rate of change in the output phase and frequency of the fast oscillator clock is similarly reduced (e.g., to about 1%). Note that t0 may be a value other than 1% depending on the system design. With the clock smoothing circuit 204, the PLL maintains a stable output clock frequency under abrupt phase changes greater than t0, such as may occur during a reference clock exchange, without relocking. The clock smoothing circuit ensures minimal frequency and phase deviation on the output of the first PLL as it slowly aligns to the new reference clock.

[0046] Although the PLL 400 is shown as an analog PLL, any type of PLL may be used to generate the clock. For example, a mixed signal PLL, an all-digital PLL, etc. may be used along with the clock smoothing circuit 204. In some embodiments, the PFD 401 may be replaced with a time-to-digital converter (TDC). In some such embodiments, the digital clock smoothing circuit monitors the digital stream output of the TDC and digitally processes it to smooth out sudden large changes in phase. Here, the output may remain in digital format or may be converted to an analog output. In some embodiments, the filter 403 may be replaced with an all-digital filter using well-known digital filter implementations (e.g., finite impulse response (FIR) or infinite impulse response (IIR)). In some such embodiments, the digital filter receives a digital input from the clock smoothing circuit or an analog-to-digital converter. In some embodiments, the VCO 404 may be replaced with a digitally controlled oscillator or DCO. In one such embodiment, the DCO receives a digital input from a digital filter, or an analog input is converted to a digital representation via an analog-to-digital converter.

[0047] FIG. 5 illustrates an apparatus 500 for clock smoothing and associated timing diagrams, according to some embodiments. The apparatus 500 includes a delay line 501, an inverter 502, an AND gate 503, a delay line 504, an inverter 505, and an AND gate 506 coupled together as shown. Upon a surprise clock stop, a "Stopped Clock" signal (or clock select signal) asserts, initiating the swapping of the PLL[0] input reference clock from the slow host clock to the slow crystal oscillator clock. Note that since the ultimate source for the host clock is also a crystal oscillator, the frequencies of the two slow clocks match within parts per million (PPM). However, there can be any phase relationship between the two slow clocks, and thus the PLL[0] reference clock edge may suddenly have a large phase error with respect to the feedback clock. After clock swapping by multiplexer 202, this phase error (represented as an up / down signal from PFD 401 or also by the digital stream output from the TDC) may be a significant fraction of the reference clock period, which in turn would significantly slow down or speed up PLL[0] 2051 without the clock smoothing circuit 204. However, the clock smoothing circuit 204 intercepts the raw PFD output (up and dn) and sends it through a programmable inverting delay line (501 and 504) which is ANDed (by 503 and 506) with the raw PFD output (Up and Dn). This logic limits the phase error seen by PLL[0] (represented as an Up' / Dn' signal) and maintains a stable and continuous output clock to the clock distribution network.

[0048] As an example, with a 100MHz Refclk, a 1% limit on t0, and N=32, a sudden input phase error of 5ns will result in a 3.125ps (=0.01*T Period / N), which is on the order of the natural jitter from intrinsic sources of PLL noise (e.g., thermal noise, power supply noise, and feedthrough noise). In this context, we also get a more precise definition of maintaining a "continuous and stable" clock under surprise clock outages: it means that the output clock smoothing circuitry limits the magnitude of the phase or frequency deviations of the high-speed clock to be lower than those from intrinsic noise during normal operation of the locked PLL.

[0049] FIG. 6 illustrates a plot 600 showing clock swap performance of a PLL and clock smoothing circuit, according to some embodiments. Plot 600 shows the output clocks of PLL[0] 601 and PLL[1] 601, with additional PLLs having similar performance. In plot 600, both PLL[0] and PLL[1] first start and lock; then, as shown in the windowed portion of the waveform, a surprise clock stop occurs near the 3.4 μs mark. Circuit simulation includes feed-through noise that causes an inherent frequency deviation of approximately 20 MHz (or less than 1%) in the locked PLL[1]. After the surprise clock stop and switchover to the new reference clock, the clock smoothing circuit limits the additional noise introduced in the output clock of PLL[0] to less than 1 MHz, and limits the additional noise introduced in the output clock of PLL[1] to less than 20 MHz. The frequency deviation in the circuit simulation is much smaller than the total noise expected at the output of the PLL due to all sources of inherent noise during normal locked operation.

[0050] Although these embodiments are described with reference to an oscillator providing a slow clock to mux 202, the reverse process may also occur. For example, upon power-up of the memory module, oscillator 107 may be the only available clock, and the switchover to the host clock occurs when the host clock is stable. In some embodiments, the switchover may occur without a clock detection circuit, and instead the clock input switchover may occur based on an explicit external control signal.

[0051] 7 illustrates a smart device or computer system or SoC (system on chip) having an apparatus for maintaining a stable clock according to some embodiments of the present disclosure. It is noted that elements of FIG. 7 having the same reference numbers (or names) as elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0052] In some embodiments, device 2400 represents any suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop, an Internet of Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, etc. It will be understood that certain components are shown generically and that not all components of such a device are shown in device 2400.

[0053] In one example, device 2400 includes a system on a chip (SoC) 2401. An example boundary of SOC 2401 is shown in FIGURE 1 using a dotted line, and several example components are shown included within SOC 2401. However, SOC 2401 may include any suitable components of device 2400.

[0054] In some embodiments, the device 2400 includes a processor 2404. The processor 2404 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, a processing core, or other processing means. The processing operations performed by the processor 2404 include the execution of an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting the computing device 2400 to other devices, and / or similar operations. The processing operations may also include operations related to audio I / O and / or display I / O.

[0055] In some embodiments, the processor 2404 includes multiple processing cores (also referred to as cores) 2408a, 2408b, 2408c. Although only three cores 2408a, 2408b, 2408c are shown in FIG. 7, the processor 2404 may include any other suitable number of processing cores, for example, dozens or even hundreds of processing cores. The processor cores 2408a, 2408b, 2408c may be implemented on a single integrated circuit (IC) chip. Additionally, the chip may include one or more shared and / or dedicated caches, buses or interconnects, graphics and / or memory controllers, or other components.

[0056] In some embodiments, the processor 2404 includes a cache 2406. In one example, sections of the cache 2406 may be dedicated to individual cores 2408 (e.g., a first section of the cache 2406 dedicated to core 2408a, a second section of the cache 2406 dedicated to core 2408b, etc.). In one example, one or more sections of the cache 2406 may be shared between two or more cores 2408. The cache 2406 may be divided into different levels, e.g., a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0057] In some embodiments, processor core 2404 may include a fetch unit to retrieve instructions (including instructions with conditional branches) for execution by core 2404. Instructions may be fetched from any storage device, such as memory 2430. Processor core 2404 may also include a decode unit to decode the fetched instructions. For example, the decode unit may decode the fetched instructions into multiple micro-operations. Processor core 2404 may include a schedule unit to perform various operations related to storing the decoded instructions. For example, the schedule unit may hold data from the decode unit until the instruction is ready for dispatch, e.g., until all source values ​​of the decoded instruction are available. In some embodiments, the schedule unit may schedule and / or issue (or dispatch) the decoded instructions to an execution unit for execution.

[0058] The execution units may execute dispatched instructions after the instructions are decoded (e.g., by a decode unit) and dispatched (e.g., by a schedule unit). In some embodiments, the execution units may include two or more execution units (e.g., an imaging computation unit, a graphics computation unit, a general-purpose computation unit, etc.). The execution units may also perform various arithmetic operations such as addition, subtraction, multiplication, and / or division and may include one or more arithmetic logic units (ALUs). In some embodiments, a coprocessor (not shown) may perform various arithmetic operations in conjunction with the execution units.

[0059] Additionally, the execution units may execute instructions out of order. Thus, the processor core 2404 may be an out-of-order processor core in some embodiments. The processor core 2404 may also include a retirement unit. The retirement unit may retire an executed instruction after the instruction is committed. In some embodiments, retirement of an executed instruction may result in the processor state being committed from execution of the instruction, physical registers used by the instruction being deallocated, etc. The processor core 2404 may also include a bus unit that enables communication between components of the processor core 2404 and other components via one or more buses. The processor core 2404 may also include one or more registers that store data accessed by various components of the core 2404, such as values ​​related to assigned application priorities and / or subsystem state (mode) associations.

[0060] In some embodiments, the device 2400 has connectivity circuitry 2431. For example, the connectivity circuitry 2431 includes hardware devices (e.g., wireless and / or wired connectors and communications hardware) and / or software components (e.g., drivers, protocol stacks) that, for example, enable the device 2400 to communicate with external devices. The device 2400 may be separate from external devices, such as other computing devices, wireless access points or base stations.

[0061] In one example, the connectivity circuitry 2431 may include multiple different types of connectivity. Generalizing, the connectivity circuitry 2431 may include cellular connectivity circuitry, wireless connectivity circuitry, etc. The cellular connectivity circuitry of the connectivity circuitry 2431 generally refers to cellular network connectivity provided by a wireless carrier, such as provided via a Global System for Mobile Communications (GSM) or variants or derivatives, a Code Division Multiple Access (CDMA) or variants or derivatives, a Time Division Multiplexing (TDM) or variants or derivatives, a Third Generation Partnership Project (3GPP) Universal Mobile Telecommunications System (UMTS) system or variants or derivatives, a 3GPP Long Term Evolution (LTE) system or variants or derivatives, a 3GPP LTE-Advanced (LTE-A) system or variants or derivatives, a Fifth Generation (5G) radio system or variants or derivatives, a 5G Mobile Network system or variants or derivatives, a 5G New Radio (NR) system or variants or derivatives, or other cellular service standard. The wireless connectivity circuitry (or wireless interface) of the connectivity circuitry 2431 refers to non-cellular wireless connectivity and may include personal area networks (e.g., Bluetooth, near field, etc.), local area networks (e.g., Wi-Fi), and / or wide area networks (e.g., WiMax), and / or other wireless communications. In one example, the connectivity circuitry 2431 may include a network interface, such as a wired or wireless interface, such that a system embodiment may be incorporated into a wireless device, e.g., a mobile phone or personal digital assistant.

[0062] In some embodiments, device 2400 includes a control hub 2432 that represents hardware devices and / or software components related to interacting with one or more I / O devices. For example, processor 2404 can communicate with one or more of display 2422, one or more peripheral devices 2424, storage 2428, one or more other external devices 2429, etc. via control hub 2432. Control hub 2432 may be a chipset, a platform control hub (PCH), and / or the like.

[0063] For example, control hub 2432 represents one or more connection points for additional devices to connect to device 2400, e.g., through which a user may interact with the system. For example, devices that may be attached to device 2400 (e.g., device 2429) include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I / O devices for use in a particular application, such as card readers or other devices.

[0064] As described above, the control hub 2432 can interact with audio devices, the display 2422, and the like. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the device 2400. Additionally, audio output can be provided instead of or in addition to a display output. In another example, if the display 2422 includes a touch screen, the display 2422 also functions as an input device that can be at least partially managed by the control hub 2432. There may also be additional buttons or switches on the computing device 2400 to provide I / O functionality that is managed by the control hub 2432. In an embodiment, the control hub 2432 manages devices such as an accelerometer, a camera, a light sensor or other environmental sensors, or other hardware that can be included in the device 2400. The input may be part of a direct user interaction or may provide environmental input to the system that affects the operation of the system (e.g., filtering for noise, adjusting the display for brightness detection, applying a flash for the camera, or other functions).

[0065] In some embodiments, the control hub 2432 can couple to various devices using any suitable communications protocol, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High-Definition Multimedia Interface (HDMI), Firewire, etc.

[0066] In some embodiments, the display 2422 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and / or tactile display for a user to interact with the device 2400. The display 2422 may include a display interface, a display screen, and / or a hardware device used to provide a display to a user. In some embodiments, the display 2422 includes a touch screen (or touch pad) device that provides both output and input to a user. In one example, the display 2422 may be in direct communication with the processor 2404. The display 2422 may be one or more internal display devices, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In an embodiment, the display 2422 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0067] In some embodiments, although not shown, in addition to (or instead of) the processor 2404, the device 2400 may include a graphics processing unit (GPU) including one or more graphics processing cores that can control one or more aspects of displaying content on the display 2422.

[0068] The control hub 2432 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (eg, drivers, protocol stacks) for making peripheral connections, such as to the peripheral devices 2424 .

[0069] It will be appreciated that device 2400 may have peripheral devices connected to it as well as being a peripheral to other computing devices. Device 2400 may have a "docking" connector to connect to other computing devices for purposes of managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 2400. In addition, the docking connector may allow device 2400 to connect to certain peripherals that allow computing device 2400 to control content output, for example to audiovisual or other systems.

[0070] In addition to a proprietary docking connector or other proprietary connection hardware, device 2400 may make peripheral connections through common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any of several different hardware interfaces), DisplayPort, including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), Firewire, or other types.

[0071] In some embodiments, the connectivity circuitry 2431 may be coupled to a control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404. In some embodiments, the display 2422 may be coupled to a control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404.

[0072] In some embodiments, the apparatus 2400 includes a memory 2430 coupled to the processor 2404 via a memory interface 2434. The memory 2430 includes a memory device for storing information within the apparatus 2400.

[0073] In some embodiments, the memory 2430 includes a device for maintaining a stable clock, as described in connection with various embodiments. The memory may include non-volatile (whose state does not change when power to the memory device is interrupted) and / or volatile (whose state is indeterminate when power to the memory device is interrupted) memory devices. The memory device 2430 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device having suitable performance to act as a process memory. In some embodiments, the memory 2430 may operate as a system memory for the device 2400 to store data and instructions used by the one or more processors 2404 when executing applications or processes. The memory 2430 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) associated with the execution of applications and functions of the device 2400. In some embodiments, the storage device 2428 may include such devices.

[0074] Elements of various embodiments and examples are also provided as a machine-readable medium (e.g., memory 2430) for storing computer-executable instructions (e.g., instructions implementing any other process discussed herein). The machine-readable medium (e.g., memory 2430) may include, but is not limited to, flash memory, optical disks, CD-ROM, DVD ROM, RAM, EPROM, EEPROM, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) that may be transferred by data signal from a remote computer (e.g., server) to a requesting computer (e.g., client) over a communications link (e.g., modem or network connection).

[0075] In some embodiments, the device 2400 includes a temperature measurement circuit 2440, for example, to measure the temperature of various components of the device 2400. In one example, the temperature measurement circuit 2440 may be embedded in, coupled to, or attached to the various components whose temperatures are to be measured and monitored. For example, the temperature measurement circuit 2440 may measure the temperature of one or more of (or within) the cores 2408a, 2408b, 2408c, the voltage regulator 2414, the memory 2430, the motherboard of the SOC 2401, and / or any suitable components of the device 2400.

[0076] In some embodiments, the device 2400 includes a power measurement circuit 2442, for example, to measure power consumed by one or more components of the device 2400. In one example, in addition to or instead of measuring power, the power measurement circuit 2442 can measure voltage and / or current. In one example, the power measurement circuit 2442 can be embedded in, coupled to, or attached to various components whose power, voltage and / or current consumption is to be measured and monitored. For example, the power measurement circuit 2442 can measure power, current and / or voltage supplied by one or more voltage regulators 2414, power supplied to the SOC 2401, power supplied to the device 2400, power consumed by the processor 2404 (or any other component) of the device 2400, etc.

[0077] In some embodiments, the device 2400 includes one or more voltage regulator circuits, commonly referred to as voltage regulators (VRs) 2414. The VRs 2414 generate signals at appropriate voltage levels that may be provided to operate any appropriate components of the device 2400. By way of example only, the VRs 2414 are shown providing signals to the processor 2404 of the device 2400. In some embodiments, the VRs 2414 receive one or more voltage identification (VID) signals and generate voltage signals at appropriate levels based on the VID signals. Various types of VRs may be utilized for the VRs 2414. For example, the VRs 2414 may include a "buck" VR, a "boost" VR, a combination of buck and boost VRs, a low dropout (LDO) regulator, a switching DC-DC regulator, and the like. Buck VRs are generally used in power delivery applications where an input voltage needs to be converted to an output voltage at a ratio less than one. Boost VRs are generally used in power delivery applications where an input voltage needs to be converted to an output voltage at a ratio greater than one. In some embodiments, each processor core has its own VR controlled by the PCU 2410a / b and / or the PMIC 2412. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital LDOs, analog LDOs, or a combination of digital or analog LDOs.

[0078] In some embodiments, the apparatus 2400 includes one or more clock generator circuits, generally referred to as a clock generator 2416. The clock generator 2416 generates clock signals at appropriate frequency levels that may be provided to any appropriate components of the apparatus 2400. By way of example only, the clock generator 2416 is shown providing clock signals to the processor 2404 of the apparatus 2400. In some embodiments, the clock generator 2416 receives one or more frequency identification (FID) signals and generates clock signals at appropriate frequencies based on the FID signals.

[0079] In some embodiments, the device 2400 includes a battery 2418 that powers various components of the device 2400. By way of example only, the battery 2418 is shown powering the processor 2404. Although not shown in the figures, the device 2400 may include charging circuitry for recharging the battery based on an alternating current (AC) power supply received, for example, from an AC adapter.

[0080] In some embodiments, the device 2400 includes a power control unit (PCU) 2410 (also referred to as a power management unit (PMU), power controller, etc.). In one example, some sections of the PCU 2410 may be implemented by one or more processing cores 2408, and these sections of the PCU 2410 are symbolically depicted using dashed boxes and labeled PCU 2410a. In one example, some other sections of the PCU 2410 may be implemented outside of the processing cores 2408, and these sections of the PCU 2410 are symbolically depicted using dashed boxes and labeled PCU 2410b. The PCU 2410 can implement various power management operations for the device 2400. The PCU 2410 can include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) for implementing various power management operations for the device 2400.

[0081] In some embodiments, the device 2400 includes a power management integrated circuit (PMIC) 2412, for example, to implement various power management operations for the device 2400. In some embodiments, the PMIC 2412 is a reconfigurable power management IC (RPMIC) and / or IMVP (Intel® Mobile Voltage Positioning). In one example, the PMIC is in an IC chip separate from the processor 2404. The PMIC 2412 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 2400.

[0082] In one example, the device 2400 includes one or both of a PCU 2410 or a PMIC 2412. In one example, either one of the PCU 2410 or the PMIC 2412 may not be present in the device 2400, and thus these components are illustrated using dashed lines.

[0083] Various power management operations of the device 2400 may be performed by the PCU 2410, by the PMIC 2412, or by a combination of the PCU 2410 and the PMIC 2412. For example, the PCU 2410 and / or the PMIC 2412 may select a power state (e.g., a P-state) for the various components of the device 2400. For example, the PCU 2410 and / or the PMIC 2412 may select a power state (e.g., based on the ACPI (Advanced Configuration and Power Interface) specification) for the various components of the device 2400. By way of example only, the PCU 2410 and / or the PMIC 2412 may transition the various components of the device 2400 into a sleep state, an active state, an appropriate C-state (e.g., a C0 state based on the ACPI specification, or other appropriate C-state), etc. In one example, the PCU 2410 and / or the PMIC 2412 can control the voltage output by the VR 2414 and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or an FID signal, respectively. In one example, the PCU 2410 and / or the PMIC 2412 can control features related to battery power usage, charging of the battery 2418, and power saving operations.

[0084] The clock generator 2416 may include a phase-locked loop (PLL), a frequency-locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 2404 has its own clock source. Thus, each core may operate at a frequency that is independent of the operating frequencies of the other cores. In some embodiments, the PCU 2410 and / or the PMIC 2412 perform adaptive or dynamic frequency scaling or adjustment. For example, the clock frequency of a processor core may be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU 2410 and / or the PMIC 2412 determine the operating state of each core of the processor, and if the PCU 2410 and / or the PMIC 2412 determines that a core is operating below a target performance level, adjust the frequency and / or power supply voltage of that core accordingly without the core's clocking source (e.g., that core's PLL) losing lock. For example, if a core is drawing less current from the power supply rails than the total current allocated for that core or processor 2404, the PCU 2410 and / or PMIC 2412 may temporarily increase the power draw for that core or processor 2404 (e.g., by increasing the clock frequency and / or power supply voltage level) so that the core or processor 2404 can operate at a higher performance level. Thus, the voltage and / or frequency can be temporarily increased for the processor 2404 without violating product reliability.

[0085] In one example, the PCU 2410 and / or the PMIC 2412 may perform power management operations based at least in part on receiving measurements from, for example, the power measurement circuit 2442, the temperature measurement circuit 2440, the charge level of the battery 2418, and / or any other suitable information that may be used for power management. To this end, the PMIC 2412 is communicatively coupled to one or more sensors to sense / detect various values / variations in one or more factors that affect the power / thermal behavior of the system / platform. Examples of the one or more factors include current, voltage sag, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be provided in physical proximity (and / or in thermal contact / coupled) with one or more components or logic / IP blocks of the computing system. Additionally, in at least one embodiment, the sensors may be directly coupled to the PCU 2410 and / or the PMIC 2412. This is to allow the PCU 2410 and / or PMIC 2412 to manage processor core energy based, at least in part, on values ​​detected by one or more of those sensors.

[0086] An exemplary software stack for device 2400 is also shown (although not all elements of the software stack are shown). By way of example only, processor 2404 may execute application programs 2450, operating system 2452, one or more power management (PM) specific application programs (e.g., commonly referred to as PM applications 2458), and / or similar programs. PM applications 2458 may also be executed by PCU 2410 and / or PMIC 2412. OS 2452 may also include one or more PM applications 2456a, 2456b, 2456c. OS 2452 may also include various drivers 2454a, 2454b, 2454c, etc., some of which may be specific for power management purposes. In some embodiments, device 2400 may further include a basic input / output system (BIOS) 2420. The BIOS 2420 may communicate with the OS 2452 (eg, via one or more drivers 2454 ) and with the processor 2404 .

[0087] For example, one or more of PM applications 2458, 2456, drivers 2454, BIOS 2420, etc. may be used to implement power management specific tasks such as, for example, controlling the voltage and / or frequency of various components of device 2400, controlling the awake, sleep, and / or any other suitable power states of various components of device 2400, controlling battery power usage, charging of battery 2418, features related to power saving operation, etc.

[0088] References herein to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some of the embodiments, but not necessarily in all of the embodiments. The various occurrences of "an embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. When the specification states that a component, feature, structure, or characteristic "may," "can," or "can be" included, it is not necessary that the particular component, feature, structure, or characteristic be included. When the specification or claims refer to "an" element, it does not mean that there is only one of that element. When the specification or claims refer to "additional" elements, it does not preclude there being two or more of the additional elements.

[0089] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment can be combined with a second embodiment, if the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0090] While the present disclosure has been described in relation to specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. The embodiments of the present disclosure are intended to embrace all such alternatives, modifications, and variations as fall within the broad scope of the appended claims.

[0091] Moreover, for ease of illustration and discussion, and to avoid obscuring the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Furthermore, to avoid obscuring the present disclosure, configurations may be shown in block diagram form. This is also in consideration of the fact that details regarding the implementation of such block diagram configurations are highly dependent on the platform on which the present disclosure is implemented (i.e., such details should be well within the capabilities of those skilled in the art). Where specific details (e.g., circuits) are described to explain exemplary embodiments of the present disclosure, it should be apparent to those skilled in the art that the present disclosure can be practiced without these specific details or with variations thereof. Thus, this document is considered to be illustrative and not limiting.

[0092] The following examples are provided to illustrate various embodiments, and these examples may depend on each other in any suitable manner. EXAMPLES

[0093] Example 1 1. An apparatus comprising: a first circuit that selects one of a first clock or a second clock; a phase-locked loop (PLL) that receives an output of the first circuit as a reference clock for the PLL; and a second circuit coupled to the PLL, wherein the second circuit detects the presence or absence of the first clock and provides a selection signal to the first circuit that selects the first clock as an output of the first circuit when the first clock is present and selects the second clock as an output of the first circuit when the first clock is absent.

[0094] Example 2 The apparatus of Example 1 further includes a third circuit that adjusts up and down pulses from a phase detector of the PLL when the first circuit selects the second clock.

[0095] Example 3 The device of the first embodiment includes a fourth circuit that divides a third clock to generate the first clock.

[0096] Example 4 4. The apparatus of example 3, wherein the third clock is generated by a host processor.

[0097] Example 5 2. The apparatus of claim 1, wherein the second clock is generated by a crystal oscillator, and wherein a frequency of the first clock is substantially the same as a frequency of the second clock.

[0098] Example 6 2. The apparatus of claim 1, wherein the first circuit comprises a multiplexer.

[0099] Example 7 The apparatus of example 1, wherein the second circuit comprises: a first flip-flop having a clock input receiving the first clock and an output coupled to an input via an inverter; a second flip-flop having a clock input receiving the output of the PLL, an input coupled to the output of the first flip-flop, and an output; a third flip-flop having a clock input receiving the output of the PLL, an input coupled to the output of the second flip-flop, and an output; and combinational logic receiving outputs of the second and third flip-flops, the output of the combinational logic providing the selection signal.

[0100] Example 8 3. The apparatus of claim 2, wherein the third circuit comprises: a first programmable delay line for receiving the up pulse; a first inverter coupled to an output of the first programmable delay line; first combinational logic for receiving the up pulse and an output of the first inverter, the output of the first combinational logic providing the regulated up pulse; a second programmable delay for receiving the down pulse; a second inverter coupled to an output of the first programmable delay line; and second combinational logic for receiving the down pulse and an output of the second inverter, the output of the combinational logic providing the regulated down pulse.

[0101] Example 9 The apparatus of the first embodiment includes a clock distribution network coupled to an output of the PLL.

[0102] Example 10 The apparatus of Example 9, wherein the reference clock is a first reference clock, the PLL is a first PLL, and the apparatus comprises: a divider that divides an output of the first PLL to generate a second reference clock; and a second PLL that receives the second reference clock.

[0103] Example 11 The apparatus of Example 10, wherein the clock distribution network is a first clock distribution network, and the apparatus has a second clock distribution network coupled to an output of the second PLL, and an output of the second clock distribution network is received by a memory.

[0104] Example 12 11. The apparatus of embodiment 10, wherein the first and second PLLs are either analog PLLs or digital PLLs.

[0105] Example 13 An apparatus comprising: a phase-locked loop (PLL) for receiving a reference clock and generating an output clock used to directly or indirectly write data to a memory; and circuitry for detecting a valid first clock and causing a multiplexer to provide a second clock as the reference clock when the first clock is invalid.

[0106] Example 14 14. The apparatus of example embodiment 13, wherein the circuit is a first circuit, and the apparatus further comprises a second circuit that adjusts up and down pulses from the PLL when the multiplexer provides the second clock as the reference clock.

[0107] Example 15 The apparatus according to claim 14 further comprises a third circuit for dividing the first clock to generate a third clock, the third clock and the second clock being input to the multiplexer.

[0108] Example 16 14. The apparatus of example 13, wherein the first clock is generated by a host processor.

[0109] Example 17 16. The apparatus of embodiment 15, wherein the second clock is generated by a crystal oscillator, and the frequency of the third clock is substantially the same as the frequency of the second clock.

[0110] Example 18 1. A system comprising: a processor; a memory module coupled to the processor, the processor transmitting a first clock to the memory module, the memory module having: a first circuit for selecting one of the first clock or a second clock; a phase-locked loop (PLL) receiving an output of the first circuit as a reference clock for the PLL; and a second circuit coupled to the PLL, the second circuit detecting the presence or absence of the first clock and providing a selection signal to the first circuit that selects the first clock as an output of the first circuit if the first clock is present and selects the second clock as an output of the first circuit if the first clock is absent; and a wireless interface that allows the processor to communicate with another device.

[0111] Example 19 19. The system of embodiment 18, wherein the memory module has: a third circuit that adjusts up and down pulses from a phase detector of the PLL when the first circuit selects the second clock; and a fourth circuit that divides the third clock to generate the first clock.

[0112] Example 20 19. The system of embodiment 18, wherein the second clock is generated by a crystal oscillator, and the frequency of the first clock is substantially the same as the frequency of the second clock.

[0113] An Abstract is provided to enable the reader to ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. 1. An apparatus for generating a clock used directly or indirectly to write data to a memory module, the apparatus comprising: a first circuit for selecting one of a first clock generated by dividing a third clock generated by a host processor or a second clock generated by a crystal oscillator, the first clock having a frequency substantially the same as a frequency of the second clock; a phase locked loop (PLL) receiving an output of the first circuit as a reference clock for the PLL; a second circuit coupled to the PLL, the second circuit configured to detect the presence or absence of the first clock; selecting the first clock as an output of the first circuit if the first clock is present; and selecting the second clock as an output of the first circuit when the first clock is not present. a second circuit that provides a selection signal to the first circuit; a third circuit for adjusting an up pulse and a down pulse from a phase detector of the PLL when the first circuit selects the second clock; The third circuit comprises: a first programmable delay line for receiving the up pulse; a first inverter coupled to an output of the first programmable delay line; a first combinational logic receiving the up pulse and an output of the first inverter, an output of the first combinational logic providing the regulated up pulse; a second programmable delay line receiving the down pulse; a second inverter coupled to an output of the second programmable delay line; and second combinational logic for receiving the down pulse and an output of the second inverter, the output of the second combinational logic providing the regulated down pulse. Device.

2. The apparatus of claim 1 , wherein the first circuit comprises a multiplexer.

3. The second circuit comprises: a first flip-flop having a clock input for receiving the first clock, an output coupled to the input through an inverter; a second flip-flop having a clock input that receives the output of the PLL, an input coupled to the output of the first flip-flop, and an output; a third flip-flop having a clock input that receives the output of the PLL, an input coupled to the output of the second flip-flop, and an output; and combinational logic receiving outputs of the second and third flip-flops, the output of the combinational logic providing the selection signal.

3. Apparatus according to claim 1 or 2.

4. 4. The apparatus of claim 1, further comprising a clock distribution network coupled to an output of the PLL.

5. The reference clock is a first reference clock, the PLL is a first PLL, and the apparatus comprises: a frequency divider that divides an output of the first PLL to generate a second reference clock; a second PLL receiving the second reference clock; 5. The apparatus of claim 4.

6. 6. The apparatus of claim 5, wherein the clock distribution network is a first clock distribution network, the apparatus having a second clock distribution network coupled to an output of the second PLL, the output of the second clock distribution network being received by a memory.

7. 7. The apparatus of claim 5 or 6, wherein the first and second PLLs are either analog PLLs or digital PLLs.

8. A processor; a memory module coupled to the processor, the processor transmitting a first clock to the memory module, the memory module comprising the device of any one of claims 1 to 7; and a wireless interface that allows the processor to communicate with another device. system.

9. selecting, by a first circuit, one of a first clock generated by dividing a third clock generated by a host processor or a second clock generated by a crystal oscillator, wherein the frequency of the first clock is substantially the same as the frequency of the second clock; receiving, by a phase locked loop (PLL), an output of the first circuit as a reference clock for the PLL; Detecting the presence or absence of the first clock by a second circuit coupled to the PLL: selecting the first clock as an output of the first circuit if the first clock is present; and selecting the second clock as an output of the first circuit when the first clock is not present. providing a selection signal to the first circuit; and adjusting, by a third circuit, up and down pulses from a phase detector of the PLL when the first circuit selects the second clock; The adjusting step comprises: receiving the up pulse through a first programmable delay line; inverting the output of the first programmable delay line with a first inverter; receiving, by a first combinational logic, the up pulse and an output of the first inverter and providing as an output of the first combinational logic the regulated up pulse; receiving the down pulse through a second programmable delay line; inverting the output of the second programmable delay line by a second inverter; a second combinational logic receiving the down pulse and an output of the second inverter and providing the regulated down pulse as an output of the second combinational logic; an output of said PLL is used directly or indirectly to write data to a memory module; method.

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