Semiconductor wafer test device, semiconductor wafer test system, flatness measurement device, and method for adjusting flatness of wiring board

Abstract

A semiconductor wafer testing device 10 is electrically connectable to a probe card 80, which has probes 81 that are in contact with a DUT formed on a semiconductor wafer 200. The semiconductor wafer testing device comprises: a motherboard 40 having a plurality of connectors 41; a plurality of daughterboards 50 having respective connectors 51 which are engaged with the connectors 41; and a plurality of adjusting mechanisms 60 that adjust the flatness of the motherboard 40 by changing the positions of the daughterboards 50 in the height direction while the connectors 41 and the connectors 51 are engaged with each other.

Description

[Technical field]

[0001] The present invention relates to a semiconductor wafer testing apparatus that tests electronic devices under test (DUTs: Devices Under Test) such as integrated circuit elements formed on semiconductor wafers, a semiconductor wafer testing system that includes the semiconductor wafer testing apparatus, a flatness measuring apparatus that measures the flatness of a wiring board included in the semiconductor wafer testing apparatus, and a method for adjusting the flatness of the wiring board. [Background technology]

[0002] A conventional probe card assembly includes a spatial transformer having an elastic contact structure on its bottom surface that contacts pads of a semiconductor device formed on a semiconductor wafer, a printed wiring board, an interposer disposed between the spatial transformer and the printed wiring board, and a dedicated planarizing device for adjusting the planarization of the spatial transformer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2003-528459 Summary of the Invention [Problem to be solved by the invention]

[0004] If the printed wiring board is deformed, such as flexed, poor contact may occur between the printed wiring board and the interposer, or the elastic contact structure may be misaligned with respect to the pads of the semiconductor device, which may affect the testing of the semiconductor wafer. On the other hand, if a dedicated device specialized for flattening as described above is provided in the probe card assembly, there is a problem that the space available for mounting connectors, etc. on the printed wiring board is limited.

[0005] The problem to be solved by the present invention is to provide a semiconductor wafer testing device capable of adjusting the flatness of a wiring board without restricting the space on the wiring board. Also, the problem to be solved by the present invention is to provide a semiconductor wafer testing system including the semiconductor wafer testing device, a flatness measuring device for measuring the flatness of the wiring board included in the semiconductor wafer testing device, and a method for adjusting the flatness of the wiring board. [Means for solving the problem]

[0006] [1] A semiconductor wafer testing apparatus according to the present invention is a semiconductor wafer testing apparatus for testing a DUT formed on a semiconductor wafer, the semiconductor wafer testing apparatus comprising: a first wiring board electrically connectable to a probe card having a probe that contacts the DUT, the first wiring board having a plurality of first connectors, a plurality of second wiring boards each having a second connector that engages with the first connector, and a plurality of adjustment mechanisms that adjust the flatness of the first wiring board by changing the position of the second wiring board along a first direction that is a normal direction of the first wiring board when the first connector and the second connector are engaged.

[0007] [2] In the above invention, the first direction may be a direction substantially parallel to a vertical direction.

[0008] [3] In the above invention, the first wiring board may extend along a second direction substantially perpendicular to the first direction, the second wiring board may extend along a direction substantially parallel to the first direction, and a mating direction between the first connector and the second connector may be a direction substantially parallel to the first direction.

[0009] [4] In the above invention, the multiple second wiring boards may be arranged at intervals along a second direction which is the extension direction of the first wiring board, and may be arranged parallel to one another.

[0010] [5] In the above invention, each of the second wiring boards may have a plurality of the second connectors.

[0011] [6] In the above invention, the first connector may be a straight type connector mounted on a second main surface of the first wiring board opposite the first main surface on the probe card side, and the second connector may be a right-angle type connector mounted on a third main surface or a fourth main surface of the second wiring board.

[0012] [7] In the above invention, the adjustment mechanism may include a support to which the first wiring board is fixed, a holding member arranged along a second edge of the second wiring board opposite to the first edge on the first wiring board side and supported by the support, a fixing member fixed to the second wiring board and having a female threaded portion, and an adjustment screw having a male threaded portion screwed into the female threaded portion of the fixing member, inserted into a through hole of the holding member and held by the holding member, and the relative position of the second wiring board in the first direction with respect to the holding member may be changed by rotating the adjustment screw.

[0013] [8] In the above invention, the semiconductor wafer testing apparatus may include a drive device that drives the adjustment mechanism, and a control device that controls the drive device.

[0014] [9] In the above invention, the semiconductor wafer testing apparatus may include a flatness measuring device that measures the flatness of a first main surface of the first wiring board facing the probe card, and the control device may control the driving device based on the flatness measured by the flatness measuring device.

[0015]

[10] In the above invention, the flatness measuring device may include a coordinate measuring unit that measures coordinate values ​​along the first direction of a plurality of points on the first main surface of the first wiring board, and a calculation unit that calculates the difference of the coordinate values ​​with respect to a reference plane as the flatness.

[0016]

[11] A semiconductor wafer testing system according to the present invention includes the above-mentioned semiconductor wafer testing apparatus, a probe card having probes that contact DUTs formed on a semiconductor wafer and electrically connected to a first wiring board of the semiconductor wafer testing apparatus, and a prober that faces the semiconductor wafer to the probe card and presses the semiconductor wafer against the probe card.

[0017]

[12] A flatness measuring device according to the present invention is a flatness measuring device that measures the flatness of a first wiring board electrically connected to a probe card having a probe that contacts a DUT formed on a semiconductor wafer, wherein the first wiring board has a plurality of first connectors into which second connectors respectively possessed by a plurality of second wiring boards are engaged, and the flatness measuring device is a flatness measuring device that measures the flatness of a first main surface of the first wiring board on the probe card side while the first connectors and the second connectors are engaged.

[0018]

[13] In the above invention, the flatness measuring device includes a coordinate measuring unit that measures coordinate values ​​along a first direction of a plurality of points on the first main surface of the first wiring board, and a calculation unit that calculates a difference of the coordinate values ​​with respect to a reference plane as the flatness, and the first direction may be a normal direction of the first wiring board.

[0019]

[14] In the above invention, the first direction may be a direction substantially parallel to a vertical direction.

[0020]

[15] A semiconductor wafer testing system according to the present invention includes the above-mentioned semiconductor wafer testing apparatus, the above-mentioned flatness measuring apparatus, a probe card having a probe that contacts a DUT formed on a semiconductor wafer and is electrically connected to a first wiring board of the semiconductor wafer testing apparatus, and a prober that faces the semiconductor wafer to the probe card and presses the semiconductor wafer against the probe card.

[0021]

[16] A flatness adjustment method according to the present invention is a method for adjusting the flatness of a first wiring board electrically connected to a probe card having a probe that contacts a DUT formed on a semiconductor wafer, comprising: a preparation step of preparing the first wiring board having a plurality of first connectors and a plurality of second wiring boards, each having a second connector engaged with the first connector; and an adjustment step of adjusting the flatness of the first wiring board by changing the position of the second wiring board along a first direction that is a normal direction of the first wiring board while the first connectors and the second connectors are engaged.

[0022]

[17] In the above invention, the adjustment method may include a measurement step of measuring the flatness of a first main surface of the first wiring board facing the probe card, and the adjustment step may include changing a position of the second wiring board along the first direction based on a measurement result in the measurement step.

[0023]

[18] A flatness adjustment method according to the present invention is a method for adjusting the flatness of a first wiring board in the above-mentioned semiconductor wafer testing apparatus, comprising: a preparation step of preparing a first wiring board having a plurality of first connectors and a plurality of second wiring boards, each having the second connector engaged with the first connector; and an adjustment step of adjusting the flatness of the first wiring board by changing a position of the second wiring board along the first direction while the first connector and the second connector are engaged, wherein the adjustment step includes changing a relative position of the second wiring board with respect to the holding member along the first direction by rotating the adjustment screw.

[0024]

[19] In the above invention, the adjustment step may include rotating the adjustment screw until the fixed member abuts against the retaining member or an intervening member interposed between the retaining member and the fixed member.

[0025]

[20] In the above invention, the first direction may be a direction substantially parallel to a vertical direction. Effect of the Invention

[0026] According to the present invention, the semiconductor wafer testing device includes a plurality of adjustment mechanisms that change the position of the second wiring board along the first direction when the first and second connectors are engaged, and the flatness of the first wiring board can be adjusted by using the first connector mounted on the first wiring board. Therefore, the flatness of the first wiring board can be adjusted without restricting the space on the first wiring board. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a schematic diagram showing a semiconductor wafer test system according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing a connection portion between a test head and a prober in the first embodiment of the present invention. [Diagram 3] FIG. 3 is a cross-sectional view showing the internal structure of the test head in the first embodiment of the present invention, as viewed along the direction A in FIG. [Figure 4A] FIG. 4A is a plan view showing the motherboard in the first embodiment of the present invention. [Figure 4B] FIG. 4B is a bottom view showing the motherboard in the first embodiment of the present invention, illustrating measurement points on the motherboard. [Figure 5A] FIG. 5A is a cross-sectional view showing connectors mounted on a mother board and a daughter board in the first embodiment of the present invention, illustrating the state before the connectors are mated. [Figure 5B] FIG. 5B is a cross-sectional view showing the connectors mounted on the mother board and the daughter board in the first embodiment of the present invention, showing the connectors in a mated state. [Figure 6] FIG. 6 is an enlarged cross-sectional view corresponding to a portion VI in FIG. 3, taken along the longitudinal direction of the daughter board. [Figure 7] FIG. 7 is a cross-sectional view showing a first modified example of the adjustment mechanism in the first embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view showing a second modified example of the adjustment mechanism in the first embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing a flatness measuring device in the first embodiment of the present invention. [Figure 10] FIG. 10 is a flowchart showing the flatness adjustment method in the first embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing a flatness measuring device provided in a semiconductor wafer test apparatus in the second embodiment of the present invention. [Figure 12A] FIG. 12A is a cross-sectional view showing an adjustment mechanism of a semiconductor wafer test system in a second embodiment of the present invention. [Figure 12B] FIG. 12B is a plan view showing the adjustment mechanism of the semiconductor wafer test system in the second embodiment of the present invention. [Figure 13] FIG. 13 is a bottom view showing a motherboard according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0029] <<First embodiment>> FIG. 1 is a schematic diagram showing a semiconductor wafer test system according to a first embodiment of the present invention.

[0030] As shown in FIG. 1, a semiconductor wafer test system 1 in this embodiment is a system for testing DUTs such as IC devices formed on a semiconductor wafer 200 (see FIG. 2). The semiconductor wafer testing system 1 includes:The semiconductor wafer testing apparatus 10 includes a probe card 80 and a prober 90. The semiconductor wafer testing apparatus 10 includes a tester 20 and a test head 30, and the tester 20 is electrically connected to the test head 30 via a cable 21. When testing a DUT formed on a semiconductor wafer 200, the test head 30 is inverted from a maintenance position (a position indicated by a dashed line in FIG. 1) by a manipulator 96 and placed above the prober 90.

[0031] Fig. 2 is a cross-sectional view showing a connection between a test head and a prober in this embodiment, Fig. 3 is a cross-sectional view showing the internal structure of the test head in this embodiment, Fig. 4A and Fig. 4B are a plan view and a bottom view showing a motherboard in this embodiment, Fig. 5A and Fig. 5B are cross-sectional views showing connectors mounted on the motherboard and daughterboard in this embodiment, and Fig. 6 is an enlarged cross-sectional view corresponding to part VI in Fig. 3.

[0032] 2 and 3, the test head 30 includes a motherboard 40 and a plurality of (ten in this embodiment) daughterboards 50 in order to transmit and receive test signals to and from the DUT of the semiconductor wafer 200. The motherboard 40 is fixed to a frame 31 of the test head 30 by bolts (not shown) or the like. The plurality of daughterboards 50 are connected to the motherboard 40 via connectors 41, 51.

[0033] The motherboard 40 in this embodiment corresponds to an example of the "first wiring board" in the present invention, and the connector 41 in this embodiment corresponds to an example of the "first connector" in the present invention. The daughterboard 50 in this embodiment corresponds to an example of the "second wiring board" in the present invention, and the connector 51 in this embodiment corresponds to an example of the "second connector" in the present invention.

[0034] The motherboard 40 is a printed wiring board having a base material made of, for example, glass epoxy resin, etc. The motherboard 40 is disposed below the test head 30 with the upper and lower main surfaces 401, 402 extending along the horizontal direction (the XY direction in the figure).

[0035] The Z direction in the drawings of this embodiment corresponds to an example of the "first direction" in the present invention, and the X direction in the drawings of this embodiment corresponds to an example of the "second direction" in the present invention.

[0036] A plurality of connectors 41 are mounted in a matrix on the upper surface 401 of the motherboard 40. Specifically, in this embodiment, 320 connectors 41 are arranged in 16 rows and 20 columns on the upper surface 401 of the motherboard 40 so as to correspond to the connectors 51 of the daughterboard 50, as shown in FIG.

[0037] 5A and 5B, each connector 41 is a receptacle type connector including a female terminal 411 and a housing 412 that holds the female terminal 411. Moreover, this connector 41 is a straight type connector in which the mating direction (insertion / removal direction) with the mating connector 51 is substantially parallel to the normal direction (Z direction in the figure) of the mounting surface 401 of the motherboard 40 (Z direction in the figure).

[0038] 4B, a large number of pads are formed in pad formation region 42 on lower surface 402 of motherboard 40. These pads are arranged to correspond to contacts 851 of interposer 85 (described later) that electrically connects motherboard 40 and probe card 80. Although not shown, other pads such as grounds may be formed in regions other than pad formation region 42 on lower surface 402 of motherboard 40. Connector 41 mounted on upper surface 401 of motherboard 40 and pads formed on lower surface 402 of motherboard 40 are electrically connected via conductive paths such as wiring patterns and through holes formed on motherboard 40.

[0039] Each daughter board 50 is a printed wiring board having a base material made of, for example, glass epoxy resin. As shown in Figures 2 and 3, this daughter board 50 is arranged above the mother board 40 in the test head 30 with main surfaces 501, 502 extending along the vertical direction (Z direction in the figures). The multiple daughter boards 50 are arranged at substantially equal intervals along the X direction in the figures and are arranged parallel to each other.

[0040] A plurality of connectors 51 are mounted on both sides 501, 502 of the daughter board 50. Specifically, 16 connectors 51 are mounted on one main surface 501 of the daughter board 50 at substantially equal intervals along an edge 503 on the lower side (the side facing the motherboard 40) of the daughter board 50. Similarly, 16 connectors 51 are mounted on the other main surface 502 of the daughter board 50 at substantially equal intervals along an edge 503 on the lower side of the daughter board 50.

[0041] As shown in Figures 5A and 5B, each connector 51 is a plug-type connector including a male terminal 511 and a housing 512 that holds the male terminal 511. The connector 51 is a right-angle type connector in which the mating direction (insertion / removal direction) with the mating connector 41 is a direction (Z direction in the figure) that is substantially perpendicular to the normal direction (X direction in the figure) of the mounting surfaces 501, 502 of the daughter board 50. For convenience, only the connector 51 mounted on one main surface 501 of the daughter board 50 is shown in Figures 5A and 5B, and the connector 51 mounted on the other main surface 502 of the daughter board 50 is not shown.

[0042] The connector 51 mounted on the daughter board 50 may be a connector having a female terminal. In this case, the connector 41 mounted on the mother board 40 is a connector having a male terminal.

[0043] The motherboard 40 and the multiple daughterboards 50 are electrically connected by fitting the connectors 41, 51. Specifically, the male terminal 411 of one connector 41 is inserted into the female terminal 511 of the other connector 51, and the terminals 411, 511 come into contact with each other, thereby electrically connecting the connectors 41, 51 to each other. As long as the terminals 411, 511 are in contact with each other within the range of an effective fitting length ML (see FIG. 5B), the electrical connection between the connectors 41, 51 is maintained. The connectors 41, 51 of this embodiment are LIF (Low Insertion Force) connectors, but are not particularly limited thereto, and ZIF (Zero Insertion Force) connectors may be used as the connectors 41, 51.

[0044] The number of daughter boards 50 connected to the motherboard 40 is not limited to the above and can be set arbitrarily as long as there are more than one. The number of connectors 51 on the daughterboard 50 is also not limited to the above and can be set arbitrarily. The connectors 51 may be mounted on only one of the main surfaces 501, 502 of the daughterboard 50. The number and arrangement of the connectors 41 mounted on the motherboard 40 are also not limited to the above and can be set according to the number and arrangement of the connectors 51 on the daughterboard 50.

[0045] As shown in FIG. 2, the probe card 80 includes a plurality of probes 81 that are in electrical contact with pads of a DUT formed on a semiconductor wafer 200, and a wiring board 82 on which the probes 81 are mounted.

[0046] Probes 81 are probe needles formed from a semiconductor substrate such as a silicon substrate using MEMS (Micro Electro Mechanical Systems) technology. Each probe 81 is mounted on the lower surface of wiring board 82 so that the tip of probe 81 faces a pad of semiconductor wafer 200.

[0047] Wiring board 82 is a printed wiring board having a base material made of a material having a relatively small coefficient of thermal expansion, such as ceramics. Although not shown in the figure, a wiring pattern is formed on the lower surface of wiring board 82, and probes 81 are mounted on wiring board 82 by being connected to the wiring pattern by soldering or the like. Meanwhile, a large number of pads are formed on the upper surface of wiring board 82, arranged to correspond to contacts 851 of interposer 85. The pads formed on the upper surface of wiring board 82 and the wiring pattern formed on the lower surface of wiring board 82 are electrically connected via conductive paths such as wiring patterns and through holes formed on wiring board 82.

[0048] The above-mentioned configuration of probe card 80 is merely an example, and the configuration of the probe card is not particularly limited to the above, as long as it is a structure having a probe (a contactor that contacts a pad of a DUT formed on a semiconductor wafer). For example, the probe card may include a wiring board or relay member other than wiring board 82. The configuration of the probe is also not particularly limited to the above. For example, a vertical type such as a pogo pin or a membrane type having a bump formed on an insulating film may be used as probe 81.

[0049] The interposer 85 includes a large number of conductive contacts 851 and an insulating holder 852 that holds the contacts 851. Each contact 851 is a pin that is bent at the center. Due to the elastic force of the contacts 851, the upper end of the contact 851 contacts a pad on the lower surface 402 of the motherboard 40, and the lower end of the contact 851 contacts a pad on the upper surface of the wiring board 82 of the probe card 80. The pads of the motherboard 40 and the pads of the wiring board 82 are electrically connected via the contacts 851.

[0050] The configuration of the interposer is not particularly limited to the above, so long as it has a function of electrically relaying between the motherboard 40 and the probe card 80. For example, the interposer 85 may have a so-called pogo pin instead of the above-mentioned contactor 851. Alternatively, the interposer 85 may be an anisotropic conductive rubber sheet that becomes electrically conductive in the vertical direction at the applied portion when pressure is applied in the thickness direction. Also, the interposer 85 may be divided into a plurality of parts.

[0051] Furthermore, as long as the probe card 80 and the motherboard 40 are electrically connected, in addition to the interposer 85 or instead of the interposer 85, other components such as a wiring board may be interposed between the motherboard 40 and the probe card 80. Alternatively, the probe card 80 may be directly connected to the motherboard 40 without the interposer 85.

[0052] The probe card 80 is held by an annular holder 92 with the probes 81 facing downward. The holder 92 is held by an annular adapter 93, which is held in an opening 911 of a top plate 91 of a prober 90. The adapter 93 is for fitting a probe card 80 of a different size to the opening 911 of the prober 90. The probe card 80 and the motherboard 40 are mechanically connected by engaging a hook 43 provided on the lower part of the motherboard 40 with a hook 931 provided on the adapter 93. An interposer 85 is interposed between the probe card 80 and the motherboard 40, and the probe card 80 and the motherboard 40 are electrically connected via the interposer 85.

[0053] The prober 90 has a transport arm 95 that can move the semiconductor wafer 200, which is suction-held by a suction stage 94, in the X, Y, and Z directions and rotate it by θ around the Z axis. During testing, the transport arm 95 places the semiconductor wafer 200 facing the probe card 80 facing the inside of the prober 90 through an opening 911, presses the semiconductor wafer 200 against the probe card 80, and brings the probes 81 into contact with the pads of a plurality of DUTs formed on the semiconductor wafer 200. In this state, the tester 20 inputs a test signal to the DUT via the test head 30, receives a response signal from the DUT, and compares the response signal with a predetermined expected value to evaluate the electrical characteristics of the DUT.

[0054] Furthermore, the test head 30 of this embodiment includes a plurality of adjustment mechanisms 60, as shown in FIGS.

[0055] Here, the motherboard 40 to which multiple daughterboards 50 are connected via the connectors 41, 51 may be bent downward due to pressure from the daughterboards 50. In this embodiment, by changing the height position of the daughterboards 50 with the adjustment mechanism 60 while the connectors 41, 51 are engaged, it is possible to correct deformation such as bending that has occurred in the motherboard 40.

[0056] One adjustment mechanism 60 is assigned to one daughter board 50. Therefore, the test head 30 of this embodiment has ten adjustment mechanisms 60. Each adjustment mechanism 60 has a holding member 61, a pair of fixing members 63, and a pair of adjustment screws 64, as shown in Figs. 3 and 6.

[0057] The holding member 61 is a flat bar-shaped member that is hung across the frame 31 of the test head 30 so as to face the upper surface 401 of the motherboard 40 via the daughterboard 50. The holding member 61 has a flat rectangular cross-sectional shape, but is not particularly limited to this. For example, the holding member 61 may have a substantially U-shaped cross-sectional shape with ribs erected on both sides.

[0058] The holding member 61 extends substantially parallel to the daughter board 50 and is disposed along the upper edge 504 of the daughter board 50. Thus, the daughter board 50 is interposed between the mother board 40 and the holding member 61 in the vertical direction.

[0059] Fixing holes 611 that pass through the holding member 61 in the vertical direction are formed on both ends of the holding member 61. The holding member 61 is fixed to the frame 31 by fixing screws 62 that are inserted into the fixing holes 611.

[0060] As long as the holding member 61 is fixed relatively (directly or indirectly) to the frame 31, another member may be interposed between the holding member 61 and the frame 31. In this embodiment, the frame 31 of the test head 30 is used as a support for fixing the holding member 61, but instead of the frame 31, another member to which the motherboard 40 is fixed relatively (directly or indirectly) may be used as the support.

[0061] Further, the holding member 61 has a holding hole 612 that passes through the holding member 61 in the up-down direction. The holding hole 612 is formed at a position corresponding to a fixing member 63 fixed to the daughter board 50.

[0062] The fixing members 63 are members fixed to the daughter board 50 using rivets or the like, and are disposed near both left and right ends (both ends in the Y direction in the figure) of the upper edge 504 on one main surface 501 of the daughter board 50. Each fixing member 63 has a fixing hole 631 that opens at the top and is formed along the vertical direction (the Z direction in the figure), and a female screw portion 632 is formed on the inner circumferential surface of this fixing hole 631.

[0063] The adjustment screw 64 is a so-called hexagon socket head bolt (cap bolt). The adjustment screw 64 is inserted into the holding hole 612 of the holding member 61 and is screwed into the fixing member 63.

[0064] Specifically, each adjustment screw 64 includes a head 641 and a shaft 643. The head 641 of the adjustment screw 64 has an outer diameter larger than the inner diameter of the holding hole 612 of the holding member 61. On the other hand, the shaft 643 of the adjustment screw 64 has an outer diameter smaller than the inner diameter of the holding hole 612. Therefore, while the shaft 643 of the adjustment screw 64 is inserted into the holding hole 612 of the holding member 61, the seat surface 642 of the head 641 of the adjustment screw 64 abuts against the holding member 61, and the adjustment screw 64 is held by the holding member 61. Then, the male screw portion 644 of the shaft 643 of the adjustment screw 64 is inserted into the fixing hole 631 of the fixing member 63 and is screwed into the female screw portion 632.

[0065] When the adjustment screw 64 is rotated in the tightening direction (clockwise), the fixing member 63 approaches the holding member 61 that holds the adjustment screw 64, and the daughter board 50 rises relative to the holding member 61. At this time, since the connector 41 of the mother board 40 and the connector 51 of the daughter board 50 are engaged with each other, the mother board 40 is also raised via the daughter board 50 by the rotation of the adjustment screw 64. This makes it possible to correct any deformation, such as bending, that has occurred in the mother board 40.

[0066] In this embodiment, the mating of the connectors 41, 51 is maintained during the rotation of the adjustment screw 64, but the force of lifting the daughter board 50 by the rotation of the adjustment screw 64 is set to exceed the force of pulling out the connectors 41, 51 (the force required to pull out the connector 41 from the connector 51). Therefore, the rotation of the adjustment screw 64 can lift the connector 51 of the daughter board 50 relative to the connector 41 of the mother board 40 while also lifting the mother board 40 via the daughter board 50. This allows the weight of the daughter board 50 to be released to the frame 31 via the holding member 61, so that the flatness of the mother board 40 can be further improved. At this time, in order to ensure the electrical connection of the connectors 41, 51, it is preferable that the amount of lift of the daughter board 50 by the rotation of the adjustment screw 64 is smaller than the effective mating length ML of the connectors 41, 51.

[0067] The force required to pull out the connectors 41 and 51 may be equal to or greater than the force required to pull up the daughter board 50 by rotating the adjustment screw 64 .

[0068] The configuration of the adjustment mechanism 60 described above is not particularly limited as long as it is a mechanism capable of raising and / or lowering the daughter board 50. Although not particularly limited, for example, the adjustment mechanism may have a configuration as shown in Fig. 7 or Fig. 8. Fig. 7 is a cross-sectional view showing a first modified example of the adjustment mechanism in this embodiment, and Fig. 8 is a cross-sectional view showing a second modified example of the adjustment mechanism in this embodiment.

[0069] The above-described adjustment mechanism 60 has only the function of lifting the daughter board 50, whereas the adjustment mechanism 60B shown in FIG.

[0070] In this adjustment mechanism 60B, no female thread portion is formed in the fixed member 63, but a female thread portion 613 is formed on the inner circumferential surface of a holding hole 612 of the holding member 61, and the tip of the adjustment screw 64 abuts against the fixed member 63. In this first modified example, when the adjustment screw 64 is rotated in the tightening direction (clockwise), the tip of the adjustment screw 64 presses down the daughter board 50 via the fixed member 63. With such an adjustment mechanism 60B, if upward deformation such as warping occurs in the motherboard 40, the deformation can be corrected.

[0071] 8 has the function of both raising and lowering the daughter board 50. Specifically, this adjustment mechanism 60C has a coil spring 65 interposed between the holding member 61 and the fixed member 63. Note that, instead of the coil spring 65, other elastic members such as a spring washer, a wave washer, a disc spring washer, or the like may be interposed between the holding member 61 and the fixed member 63.

[0072] In this second modified example, when the adjustment screw 64 is rotated in a tightening direction (clockwise), the fixing member 63 rises against the elastic force of the coil spring 65, and the daughter board 50 is pulled up. On the other hand, when the adjustment screw 64 is rotated in a loosening direction (counterclockwise), the fixing member 63 descends and the daughter board 50 is pushed down by the elastic force of the coil spring 65 while the head 641 of the adjustment screw 64 is kept in contact with the holding member 61. Such an adjustment mechanism 60C can deal with both the case where the mother board 40 is bent downward due to pressure from the daughter board 50, and the case where the mother board 40 is deformed upward, such as by warping.

[0073] Although not specifically shown, the arrangement of the male thread portion and the female thread portion in the adjustment mechanism 60 may be reversed from that described above. In this case, the adjustment mechanism 60 includes an adjustment nut instead of the adjustment screw 64, and a shaft on which a male thread portion is formed protrudes upward from the fixed member 63 and is inserted into the holding hole 612 of the holding member 61, and the adjustment nut is screwed onto the shaft.

[0074] FIG. 9 is a cross-sectional view showing the flatness measuring device in this embodiment.

[0075] The semiconductor wafer test system 1 of this embodiment includes a flatness measurement device 100 that is independent of the semiconductor wafer test device 10 and the prober 90. This flatness measurement device 100 is a device that measures the flatness of the motherboard 40 in a state in which the motherboard 40 is mounted on the test head 30. Note that this flatness measurement device 100 is not included in the semiconductor wafer test system 1, and for example, the flatness measurement device 100 may be installed alone in a factory.

[0076] Here, as described above, in a state where the motherboard 40 is attached to the test head 30, the multiple daughterboards 50 are already connected to the motherboard 40 via the connectors 41, 51, and the motherboard 40 may be bent downward due to the pressure of the daughterboards 50. Therefore, in this embodiment, before the test head 30 is connected to the prober 90, the flatness of the motherboard 40 attached to the test head 30 is measured by the flatness measuring device 100, and the motherboard 40 is flattened using the above-mentioned adjustment mechanism 60. The specific timing for flattening the motherboard 40 is not particularly limited, but examples include when the test head 30 is shipped and when the motherboard 40 is replaced.

[0077] The flatness of the motherboard 40 refers to the degree of deviation of the lower surface 402 of the motherboard 40 from a geometrically correct reference plane. 17 is expressed as a set of differences in the Z direction of the lower surface 402 of the motherboard 40 with respect to an approximate plane (reference plane) at

[0078] As shown in FIG. 9, the flatness measuring device 100 includes a frame 110, a measuring unit 120, a moving device 130, and a calculation unit 140.

[0079] The frame 110 is capable of holding the test head 30 in a position in which the lower surface 402 of the motherboard 40 faces downward. The measurement unit 120 and the moving device 130 are disposed within this frame 110.

[0080] The measurement unit 120 measures, for example, specific points SP1 to SP2 on the lower surface 402 of the motherboard 40. 17 The specific points SP1 to SP 17 The measurement unit 120 is a laser displacement meter that acquires the coordinate values ​​in the Z direction of the specific points SP1 to SP2 on the lower surface 402 of the motherboard 40. 17 As long as the height coordinate value can be measured, the present invention is not limited to a laser displacement meter.

[0081] The moving device 130 is a device that moves the measuring unit 120 in the XY directions, and is composed of, for example, a linear guide, a ball screw mechanism, a motor, etc. The measuring unit 120 moves the measuring unit 120 to specific points SP1 to SP2 of the motherboard 40 in the XY directions by the moving device 130. 17 The moving device 130 is moved to a position facing the measuring unit 120. Note that the moving device 130 is not limited to the above as long as it is capable of moving the measuring unit 120 in the X and Y directions. For example, a robot arm may be used as the moving device 130.

[0082] The calculation unit 140 is configured by, for example, a computer. This calculation unit 140 calculates the flatness of the lower surface 402 of the motherboard 40 based on the measurement results of the measurement unit 120. A specific method of calculating the flatness by this calculation unit 140 will be described later.

[0083] A method for adjusting the flatness of a motherboard in this embodiment will be described with reference to FIG. 10. FIG. 10 is a flow chart showing the method for adjusting the flatness in this embodiment. Note that the method for calculating the flatness described below is merely an example, and is not particularly limited thereto. For example, the method described in the third embodiment described later may be used, or the flatness may be calculated by another method.

[0084] 10, the test head 30 is prepared with the motherboard 40 attached thereto. Specifically, in this test head 30, the motherboard 40 is fixed to the frame 31 of the test head 30, and the connector 51 of the daughterboard 50 is fitted into the connector 41 of the motherboard 40.

[0085] Next, in step S20 of FIG. 10, 17 specific points SP1 to SP 17 In this embodiment, the coordinate values ​​of the specific points SP1 to SP 17 Strictly speaking, there are pads at the specific points SP1 to SP 17The Z-coordinate value is the Z-coordinate value of the surface of the pad.

[0086] Specifically, first, the test head 30 prepared in step S10 described above is supported on the frame 110 of the flatness measurement device 100. Next, the moving device 130 moves the measurement unit 120 to a position facing the specific point SP1, and the measurement unit 120 acquires the Z coordinate value of this specific point SP1. Next, the moving device 130 moves the measurement unit 120 to the next specific points SP2 to SP 17 The measurement unit 120 moves the specific points SP2 to SP 17 The Z coordinate values ​​of specific points SP1 to SP 17 The Z coordinate values ​​are sequentially output from the measurement unit 120 to the calculation unit 140.

[0087] The positions of the specific points on the lower surface 402 of the motherboard 40 are the above-mentioned specific points SP1 to SP 17 The number of specific points on the lower surface 402 of the motherboard 40 is not limited to the above. For example, the positions on the lower surface 402 of the motherboard 40 corresponding to the connectors 41 may be set as the specific points measured by the measuring unit 120.

[0088] All specific points SP1~SP 17 When the measurement of the Z coordinate values ​​of the specific points SP1 to SP2 is completed (YES in step S30), in step S40 of FIG. 17 In step S50 of FIG. 10, the calculation unit 140 creates an approximation plane based on the XYZ coordinate values ​​of each of the specific points SP1 to SP 17 The deformation in the Z direction is calculated at the specific points SP1 to SP 17 The X coordinate value and the Y coordinate value are known coordinate values ​​that are set in advance.

[0089] Specifically, first, the calculation unit 140 calculates the specific points SP1 to SP2 by using the least squares method or the like. 17 Next, the calculation unit 140 calculates an approximate plane that passes through the specific points SP1 to SP 17Next, the calculation unit 140 extracts the coordinate values ​​in the Z direction of the positions corresponding to all of the specific points SP1 to SP 17 Regarding the above, the difference (amount of deformation) between the actual Z coordinate value of lower surface 402 of motherboard 40 and the Z coordinate value on the approximate plane is calculated as the flatness (step S50).

[0090] Next, in step S60 of FIG. 10, the adjustment mechanism 60 flattens the motherboard 40 based on the amount of deformation.

[0091] Specifically, the worker rotates the adjustment screw 64 of the adjustment mechanism 60 in the tightening direction (clockwise) to lift up the daughter board 50. At this time, a shim 66 (a member shown by a broken line in FIG. 6) is interposed between the holding member 61 and the fixed member 63, and the worker rotates the adjustment screw 64 until the fixed member 63 abuts against the shim 66. This narrows the gap between the holding member 61 and the fixed member 63, and the daughter board 50 is lifted up relative to the holding member 61, and the specific points SP1 to SP 17 The above-mentioned deformation amount at the specific points SP1 to SP5 is eliminated (canceled). The shim 66 is selected to have a thickness such that the amount of pulling up is an amount that eliminates the deformation amount. 17 The amount of deformation at the adjustment mechanism 60 is selected individually for each adjustment mechanism 60.

[0092] In addition, specific points SP1 to SP 17 A table showing the correspondence between the amount of deformation at the adjustment mechanism 60 and the amount of lifting of the daughter board 50 (the thickness of the shim 66) required to eliminate the amount of deformation may be created in advance through experiments or the like.

[0093] Or, specific points SP1 to SP 17 Alternatively, a table showing the correspondence between the amount of deformation at the adjustment screw 64 and the amount of rotation of the adjustment screw 64 of each adjustment mechanism 60 required to eliminate that amount of deformation may be created in advance, and the adjustment mechanism 60 may be operated without using the shim 66.

[0094] Or, specific points SP1 to SP 17While measuring the deformation amount at the specific points SP1 to SP2 with the flatness measuring device 100, the operator operates the adjustment mechanism 60 to adjust the 17 The operator may rotate the adjustment screw 64 until the deformation at is substantially zero.

[0095] Furthermore, if the amount of lifting of the adjustment mechanism 60 is insufficient, a shim may be interposed between the holding member 61 and the frame 31 to widen the gap between the holding member 61 and the fixing member 63 .

[0096] As described above, in this embodiment, the test head 30 includes a plurality of adjustment mechanisms 60 that change the height position of the daughter board 50 when the connectors 41, 51 are engaged, and it is possible to flatten the motherboard 40 by using the connectors 41 mounted on the motherboard 40. Therefore, it is possible to adjust the flatness of the motherboard 40 without restricting the space on the motherboard 40.

[0097] <<Second embodiment>> FIG. 11 is a diagram showing a flatness measuring device provided in a semiconductor wafer testing device in this embodiment, and FIGS. 12A and 12B are a cross-sectional view and a plan view showing an adjustment mechanism of a semiconductor wafer testing system in this embodiment.

[0098] This embodiment differs from the above-described first embodiment in that (1) flatness measurement device 100B is incorporated in semiconductor wafer test device 10B and (2) the operation of adjustment mechanism 60 is automated, but other configurations are similar to those of the first embodiment. Below, only the differences between the semiconductor wafer test system in the second embodiment and the first embodiment will be described, and the same reference numerals will be used to denote parts having the same configuration as the first embodiment, and their description will be omitted.

[0099] 11, the semiconductor wafer test apparatus 10B in this embodiment includes a flatness measurement apparatus 100B in addition to the tester 20 and the test head 30. The flatness measurement apparatus 100B includes a measurement unit 120, a robot arm 130B, and a calculation unit 140 (not shown in FIG. 11). The measurement unit 120 is attached to the tip of the robot arm 130B. The robot arm 130B is connected to, for example, the side of the test head 30, and is capable of moving the measurement unit 120 in the X, Y, and Z directions.

[0100] The robot arm 130B moves the measurement unit 120 to specific points SP1 to SP 17 The measurement unit 120 moves the specific points SP1 to SP 17 The Z coordinate values ​​of the specific points SP1 to SP 17 The Z coordinate values ​​of the specific points SP1 to SP 17 Calculate the deformation in the Z direction at

[0101] Note that the flatness measurement apparatus 100B may include another moving device capable of moving the measurement unit 120 at least in the X and Y directions, instead of the robot arm 130B. In this embodiment, the flatness measurement apparatus 100B is attached to the test head 30, but the flatness measurement apparatus 100B may be provided in the prober 90. In this case, the prober 90 includes the flatness measurement apparatus 100B.

[0102] As shown in FIGS. 12A and 12B, the semiconductor wafer test apparatus 10B in this embodiment includes a drive device 70 that drives the adjustment mechanism 60, and a control device 75 that controls the drive device 70.

[0103] The driving device 70 includes a worm wheel 71, a worm gear 72, and a motor 73. The worm wheel 71 is fixed to a head 641 of the adjustment screw 64. The worm gear 72 meshes with the worm wheel 71, and is connected to the drive shaft of the motor 73 via a shaft 74.

[0104] The driving device 70 may be provided individually for each adjustment mechanism 60. Alternatively, the multiple adjustment mechanisms 60 may be driven by the same driving device 70. For example, the multiple adjustment screws 64 arranged at one end (the +Y direction side in the figure) of the multiple daughter boards 50 may be driven by one driving device 70, and the multiple adjustment screws 64 arranged at the other end (the -Y direction side in the figure) of the daughter boards 50 may be driven by another single driving device 70.

[0105] The configuration of the drive device 70 is not limited to the above, so long as it automatically operates the adjustment screw 64. The configurations of the adjustment mechanism and drive device are also not limited to the above, so long as they can automatically raise and / or lower the daughter board 50. For example, the adjustment mechanism and drive device may be configured by a ball screw mechanism and a motor connected to the daughter board 50.

[0106] The control device 75 is composed of, for example, a computer. The control device 75 calculates the amount of lifting of the daughter board 50 (the amount of rotation of the adjustment screw 64) for each adjustment mechanism 60 that eliminates the amount of deformation calculated by the calculation unit 140 of the flatness measurement device 100B, and controls the drive device 70 so that the adjustment mechanism 60 is driven by the amount of lifting.

[0107] As described above, in this embodiment, as in the first embodiment, the test head 30 includes a plurality of adjustment mechanisms 60 that change the height position of the daughter board 50 when the connectors 41, 51 are engaged, and it is possible to flatten the motherboard 40 by using the connectors 41 mounted on the motherboard 40. Therefore, the flatness of the motherboard 40 can be adjusted without restricting the space on the motherboard 40.

[0108] In this embodiment, the planarization work of the motherboard 40 is entirely automated, but the present invention is not limited to this. The semiconductor wafer test apparatus 10B includes the flatness measurement apparatus 100B, but does not include the driving device 70 and the control device 75, and the adjustment mechanism 60 may be mainly operated manually. Alternatively, the semiconductor wafer test apparatus 10B includes the driving device 70 and the control device 75, but does not include the flatness measurement apparatus 100B.

[0109] Further, although the semiconductor wafer test apparatus 10B of this embodiment is equipped with the adjustment mechanism 60 shown in FIG. 6, the present invention is not limited to this, and the semiconductor wafer test apparatus 10B may be equipped with an adjustment mechanism 60B shown in FIG. 7 or an adjustment mechanism 60C shown in FIG. 8 instead of the adjustment mechanism 60.

[0110] <<Third embodiment>> FIG. 13 is a bottom view showing the motherboard in this embodiment.

[0111] In this embodiment, the method of calculating the flatness of the motherboard 40 is different from that of the first embodiment described above, but the other configurations are the same as those of the first embodiment. Below, only the differences between the semiconductor wafer test system in the third embodiment and the first embodiment will be described, and the same reference numerals will be used to denote parts that are the same as those in the first embodiment, and the description thereof will be omitted.

[0112] In this embodiment, specific points SP1 to SP 17 Instead of the coordinate value in the Z direction, the flatness of the motherboard 40 is measured using strain gauges 120a to 120j.

[0113] 13, strain gauges 120a-120j are attached to specific points on the lower surface 402 of the motherboard 40 mounted on the test head 30. Although not particularly limited, in this embodiment, the strain gauges 120a-120j include a plurality of pairs arranged point-symmetrically with respect to the center of the pad formation region 42 of the motherboard 40. Then, the resistance value of each of the strain gauges 120a-120j is measured, the difference between this resistance value and a reference value is calculated, and the flatness of the lower surface 402 of the motherboard 40 is calculated from the difference and the direction of each strain. Note that the strain gauges 120a-120j themselves may be formed on the motherboard 40 in advance.

[0114] The reference values ​​to be compared with the resistance values ​​of the strain gauges 120a-120j are resistance values ​​measured by the strain gauges 120a-120j attached to the motherboard 40 before the motherboard 40 is mounted on the test head 30. Therefore, the flatness of the motherboard 40 in this embodiment is expressed as a set of differences between the flat strain (reference resistance value) and the actual strain (measured resistance value) at a specific point.

[0115] It should be noted that this reference value is not limited to the above, and if the motherboard 40 is sufficiently flattened when attached to the test head 30, the resistance value obtained by measuring the motherboard 40 may be used as the reference value.

[0116] Then, the worker operates the adjustment mechanism 60 based on the flatness calculated using the strain gauges 120a to 120j. At this time, a shim is interposed between the holding member 61 and the fixed member 63, and the worker rotates the adjustment screw 64 until the fixed member 63 abuts against the shim.

[0117] In addition, a table showing the correspondence between the difference in resistance value of strain gauges 120a to 120j and the amount of lifting of daughter board 50 (shim thickness) by each adjustment mechanism 60 required to eliminate the difference may be created in advance through experiments, etc.

[0118] Alternatively, a table showing the correspondence between the difference in resistance value of strain gauges 120a to 120j and the amount of rotation of adjustment screw 64 of each adjustment mechanism 60 required to eliminate the difference may be created in advance, and adjustment mechanism 60 may be operated without using a shim.

[0119] Alternatively, an operator may operate the adjustment mechanism 60 while measuring the resistance values ​​of the strain gauges 120a to 120j, and rotate the adjustment screw 64 until the difference between the resistance values ​​of the strain gauges 120a to 120j becomes substantially zero.

[0120] As described above, in this embodiment, as in the first embodiment, the test head 30 includes a plurality of adjustment mechanisms 60 that change the height position of the daughter board 50 when the connectors 41, 51 are engaged, and it is possible to flatten the motherboard 40 by using the connectors 41 mounted on the motherboard 40. Therefore, the flatness of the motherboard 40 can be adjusted without restricting the space on the motherboard 40.

[0121] The method of calculating the flatness described in this embodiment may be applied to the semiconductor wafer test system of the second embodiment.

[0122] The above-described embodiments are described to facilitate understanding of the present invention, and are not described to limit the present invention. Therefore, each element disclosed in the above embodiments is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0123] For example, in the above embodiment, the test head 30 is held in a position in which the main surface 402 of the motherboard 40 faces downward during planarization, but the position of the test head 30 is not particularly limited to this. For example, the test head 30 may be held in a position in which the main surface 402 of the motherboard 40 faces horizontally during planarization.

[0124] The above-described configuration of the semiconductor wafer test system 1 is merely an example, and is not particularly limited to this. For example, the above-described mechanical connection structure between the test head 30 and the prober 90 is merely an example, and is not particularly limited to this.

[0125] Similarly, the configuration of the semiconductor wafer test apparatus 10 described above is merely an example, and is not particularly limited to this. For example, the function of the tester 20 may be incorporated into the test head 30, that is, the tester 20 and the test head 30 may be integrated. [Explanation of symbols]

[0126] 1. Semiconductor wafer test system 10...Semiconductor wafer testing equipment 20…Tester 30…Test head 31...Frame 40…Motherboard 41…Connector SP1~SP 17 …Specific point 50…Daughter board 51…Connector 60...Adjustment mechanism 61... Retaining member 62…Fixing screw 63...Fixing member 632…Female thread 64…Adjustment screw 644…Male thread 70...Drive unit 71…Worm wheel 72…Worm gear 73…Motor 75...Control device 80...Probe card 81…Probe 82...Wiring board 85…Interposer 90…Prober 100...Flatness measuring device 120...Measuring part 130...Moving device 140...Arithmetic section 200...Semiconductor wafers

Claims

1. A semiconductor wafer testing apparatus for testing a DUT formed on a semiconductor wafer, comprising: a first wiring board that is electrically connectable to a probe card having a probe that contacts the DUT and that has a plurality of first connectors; a plurality of second wiring boards each having a second connector mated with the first connector; a plurality of adjustment mechanisms that adjust the flatness of the first wiring board by changing the position of the second wiring board along a first direction that is a normal direction of the first wiring board while the first connector and the second connector are engaged.

2. 2. The semiconductor wafer testing apparatus according to claim 1, The semiconductor wafer testing apparatus, wherein the first direction is parallel to a vertical direction.

3. 3. The semiconductor wafer testing apparatus according to claim 1, the first wiring board extends along a second direction perpendicular to the first direction; the second wiring board extends along a direction parallel to the first direction, A semiconductor wafer testing device, wherein a mating direction between the first connector and the second connector is parallel to the first direction.

4. The semiconductor wafer test apparatus according to any one of claims 1 to 3, The plurality of second wiring boards are arranged at intervals along a second direction which is the extension direction of the first wiring board, and are arranged parallel to one another in a semiconductor wafer testing device.

5. The semiconductor wafer test apparatus according to any one of claims 1 to 4, A semiconductor wafer testing device, wherein each of the second wiring boards has a plurality of the second connectors.

6. The semiconductor wafer test apparatus according to any one of claims 1 to 5, the first connector is a straight type connector mounted on a second main surface of the first wiring board opposite to a first main surface on the probe card side, The second connector is a right-angle type connector mounted on a third main surface or a fourth main surface of the second wiring board.

7. The semiconductor wafer test apparatus according to any one of claims 1 to 6, The adjustment mechanism includes: a support to which the first wiring board is fixed; a holding member disposed along a second edge of the second wiring board opposite to a first edge of the second wiring board and supported by the support; a fixing member fixed to the second wiring board and having a female screw portion; an adjustment screw having a male screw portion screwed into the female screw portion of the fixing member, the adjustment screw being inserted into a through hole of the holding member and held by the holding member, A semiconductor wafer testing apparatus in which the relative position of the second wiring board with respect to the holding member along the first direction is changed by rotating the adjustment screw.

8. The semiconductor wafer test apparatus according to any one of claims 1 to 7, The semiconductor wafer testing apparatus includes: A drive device that drives the adjustment mechanism; A control device that controls the driving device.

9. 9. The semiconductor wafer testing apparatus according to claim 8, the semiconductor wafer testing apparatus includes a flatness measuring device that measures flatness of a first main surface of the first wiring board that faces the probe card; The control device controls the drive device based on the flatness measured by the flatness measurement device.

10. A semiconductor wafer test device according to any one of claims 1 to 9, a probe card having a probe that contacts a DUT formed on a semiconductor wafer and electrically connected to a first wiring board of the semiconductor wafer testing device; a prober that places the semiconductor wafer against the probe card and presses the semiconductor wafer against the probe card.

11. A semiconductor wafer test device according to any one of claims 1 to 7, a probe card having a probe that contacts a DUT formed on a semiconductor wafer and electrically connected to a first wiring board of the semiconductor wafer testing device; a prober that faces the semiconductor wafer to the probe card and presses the semiconductor wafer against the probe card; a flatness measuring device for measuring the flatness of the first wiring board; the first wiring board has a plurality of first connectors into which second connectors respectively provided on a plurality of second wiring boards are fitted; The flatness measuring device is a semiconductor wafer testing system that measures the flatness of a first main surface of the first wiring board that faces the probe card while the first connector and the second connector are engaged with each other.

12. The semiconductor wafer testing system of claim 11, comprising: The flatness measuring device is a coordinate measuring unit that measures coordinate values ​​along a first direction of a plurality of points on the first main surface of the first wiring board; a calculation unit that calculates a difference of the coordinate value with respect to a reference plane as the flatness, A semiconductor wafer testing system, wherein the first direction is a normal direction of the first wiring board.

13. 1. A method for adjusting flatness of a first wiring board electrically connected to a probe card having a probe that contacts a DUT formed on a semiconductor wafer, comprising: a preparation step of preparing a first wiring board having a plurality of first connectors and a plurality of second wiring boards each having a second connector mated with the first connector; and an adjustment step of adjusting the flatness of the first wiring board by changing the position of the second wiring board along a first direction that is a normal direction of the first wiring board while the first connector and the second connector are engaged.

14. The adjustment method according to claim 13, The adjustment method includes a measuring step of measuring flatness of a first main surface of the first wiring board that faces the probe card, The adjusting method includes changing a position of the second wiring board along the first direction based on a measurement result in the measuring step.

15. A method for adjusting flatness of a first wiring board in a semiconductor wafer test apparatus according to claim 7, comprising the steps of: a preparation step of preparing the first wiring board having a plurality of first connectors and a plurality of second wiring boards each having the second connector mated with the first connector; and an adjustment step of adjusting flatness of the first wiring board by changing a position of the second wiring board along the first direction in a state in which the first connector and the second connector are fitted together, The adjusting method includes: changing a relative position of the second wiring board with respect to the holding member along the first direction by rotating the adjusting screw.

Images