Semiconductor Device

Abstract

To provide a semiconductor device capable of accelerating operation of a differential amplifier circuit.SOLUTION: According to one embodiment, there is provided the semiconductor device including a first differential amplifier circuit. The first differential amplifier circuit comprises a first input transistor, a second input transistor, a first current source, a first transistor, and a second transistor. The first input transistor receives a first signal at a gate. The second input transistor receives a second signal at the gate. The first current source is connected to a source of the first input transistor and a source of the second input transistor. The first transistor is connected in parallel to the first current source with respect to the source of the first input transistor and the source of the second input transistor. The first transistor receives the first signal at the gate. The second transistor is connected in series to the first transistor. The second transistor receives a control signal at the gate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device including a differential amplifier circuit in which a pair of transistors forming a differential pair receive an input signal and a reference signal, respectively, a power supply voltage is used to amplify the difference between the input signal and the reference signal to generate an output signal. In this case, it is desirable to increase the speed of the operation of the differential amplifier circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5993174 [Patent Document 2] U.S. Patent No. 7,271,659 [Patent Document 3] U.S. Patent No. 8,536,944 [Patent Document 4] Patent No. 5971366 [Non-patent literature]

[0004] [Non-Patent Document 1] Kyu-Dong Hwang,Boram Kim,Sang-Yeon Byeon,Kyu-Young Kim,“A 16Gb / s / pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications”,2018 IEEE International Solid - State Circuits Conference - (ISSCC),February 2018 [Non-Patent Document 2] Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Sang-Hyup Kwak, Woo Seong Kim, Dae-Hyun Kim, Y.I Kim, Yoo-Seok Yang, Su-Yeon Doo, Jin-Il Lee, Sam-Young Bang, Sun-Young Park, Ki-Woong Yeom, Jae-Young Lee, Hwanwook Park, Woo-Seop Kim, Hyang-Ja Yang, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun, “A 40nm 7Gb / s / pin Single-ended Transceiver with Jitter and ISI Reduction Techniques for High-Speed DRAM Interface”, 2010 Symposium on VLSI Circuits, July 2010 Non-Patent Document 3 Seung-Jun Bae,Young-Soo Sohn,Tae-Young Oh,Si-Hong Kim,Yun-Seok Yang,Dae-Hyun Kim, Sang-Hyup Kwak,Ho-Seok Seol,Chang-Ho Shin,Min-Sang Park,Gong-Heom Han,Byeong-Cheol Kim,Yong-Ki Cho,Hye-Ran Kim,Su-Yeon Doo,YI Kim, Dong-Seok Kang,Young-Ryeol Choi,Sam-Young Bang,Sun-Young Park,Yong-Jae Shin,Gil-Shin Moon,Cheol-Goo Park,Woo-Seop Kim,Hyang-Ja Yang,Jeong-Don Lim,Kwang-Il Park,JH Choi, Young-Hyun Jun,” A 40 nm 2 Gb 7 Gb / s / p GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW”, 2011 IEEE International Solid-State Circuits Conference,February 2011 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor device capable of increasing the speed of operation of a differential amplifier circuit. [Means for solving the problem]

[0006] According to one embodiment, there is provided a semiconductor device having a first differential amplifier circuit. The first differential amplifier circuit includes: Load circuit and a first input transistor, a second input transistor, and a first current source; The load circuit includes a pre-emphasis circuit, a current mirror circuit, and a control circuit. The load circuit includes a first load transistor and a second load transistor, the gates and drains of which are cross-coupled. The first input transistor has a drain connected to the drain of the first load transistor. The first input transistor receives a first signal at its gate. The second input transistor has a drain connected to the drain of the second load transistor.The second input transistor receives a second signal at its gate. The first current source is connected to the source of the first input transistor and the source of the second input transistor. and ground potential is connected to The pre-emphasis circuit is connected in parallel to the first current source. The current mirror circuit transfers the output of the load circuit. The control circuit inverts the output of the current mirror circuit to generate the control signal. The pre-emphasis circuit has a first transistor and a second transistor. The first transistor is connected in parallel with the first current source to the source of the first input transistor and the source of the second input transistor. input The second transistor receives a signal at its gate. and ground potential The second transistor receives a control signal at its gate. The current mirror circuit includes a third transistor, a fourth transistor, and a fifth transistor. The third transistor is connected in series to the first input transistor. The fourth transistor forms a current mirror circuit with the third transistor. The fifth transistor is connected in series to the third transistor. The fifth transistor receives a control signal at its gate. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a waveform diagram showing the operation of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration of a semiconductor device according to the second embodiment. [Figure 4] FIG. 4 is a waveform diagram showing the operation of the semiconductor device according to the second embodiment. [Diagram 5] FIG. 5 is a circuit diagram showing a configuration of a semiconductor device according to the third embodiment. [Figure 6] FIG. 6 is a circuit diagram showing a configuration of an inverter according to the third embodiment. [Figure 7] FIG. 7 is a waveform diagram showing the operation of the semiconductor device according to the third embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a configuration of a semiconductor device according to the fourth embodiment. [Figure 9] FIG. 9 is a circuit diagram showing a configuration of a semiconductor device according to the fifth embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a configuration of a semiconductor device according to the sixth embodiment. [Figure 11]FIG. 11 is a circuit diagram showing a configuration of a semiconductor device according to the seventh embodiment. [Figure 12] FIG. 12 is a circuit diagram showing a configuration of a semiconductor device according to the eighth embodiment. [Figure 13] FIG. 13 is a circuit diagram showing a configuration of a semiconductor device according to the ninth embodiment. [Figure 14] FIG. 14 is a circuit diagram showing a configuration of a semiconductor device according to the tenth embodiment. [Figure 15] FIG. 15 is a circuit diagram showing a configuration of a semiconductor device according to the eleventh embodiment. [Figure 16] FIG. 16 is a circuit diagram showing a configuration of a semiconductor device according to the twelfth embodiment. [Figure 17] FIG. 17 is a circuit diagram showing a configuration of a semiconductor device according to the thirteenth embodiment. [Figure 18] FIG. 18 is a circuit diagram showing a configuration of a semiconductor device according to the fourteenth embodiment. [Figure 19] FIG. 19 is a circuit diagram showing a configuration of a semiconductor device according to the fifteenth embodiment. [Figure 20] FIG. 20 is a circuit diagram showing a configuration of a semiconductor device according to the sixteenth embodiment. [Figure 21] FIG. 21 is a circuit diagram showing a configuration of a semiconductor device according to the seventeenth embodiment. [Figure 22] FIG. 22 is a circuit diagram showing a configuration of a semiconductor device according to the eighteenth embodiment. [Diagram 23] FIG. 23 is a circuit diagram showing a configuration of a semiconductor device according to the nineteenth embodiment. [Figure 24] FIG. 24 is a circuit diagram showing a configuration of a memory system to which the semiconductor device according to the first to nineteenth embodiments can be applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

[0009] (First embodiment) A semiconductor device according to a first embodiment includes a differential amplifier circuit. The differential amplifier circuit receives an input signal and a reference signal by a pair of transistors forming a differential pair. The differential amplifier circuit amplifies the difference between the input signal and the reference signal using a power supply voltage to generate an output signal. A semiconductor device including the differential amplifier circuit may be used as a receiver in a high-speed interface of a semiconductor memory. In this case, it is desirable to increase the speed of the operation of the differential amplifier circuit.

[0010] However, with the current circuit configuration, in order to increase speed, the current will need to be significantly increased overall to improve the driving force of each transistor, which could lead to increased power consumption due to increased heat generation from the parasitic resistance components of the wiring.

[0011] Therefore, in this embodiment, a pre-emphasis circuit that shapes a signal waveform into an undershoot waveform and an overshoot waveform is added to the differential amplifier circuit of the semiconductor device, thereby achieving both reduced power consumption and increased speed.

[0012] Specifically, the semiconductor device 1 can be configured as shown in Fig. 1. Fig. 1 is a circuit diagram showing the configuration of the semiconductor device 1.

[0013] The semiconductor device 1 realizes a single-input, single-output circuit by using two differential amplifier circuits in which the polarities of the included elements are inverted from each other. The semiconductor device 1 receives an input signal VIN as a single input, converts the input signal VIN to a differential signal, performs amplification processing, generates an output signal OUT from the processed differential signal, and outputs it as a single output.

[0014] The semiconductor device 1 includes a differential amplifier circuit 10, a differential amplifier circuit 20, an output circuit 30, and a control circuit 40. The differential amplifier circuit 10 and the differential amplifier circuit 20 are arranged in parallel with each other on the input side of the output circuit 30. The differential amplifier circuit 10 is a differential amplifier circuit (a differential amplifier circuit receiving an N-type transistor) that receives an input signal VIN with an N-type transistor. The differential amplifier circuit 20 is a differential amplifier circuit (a differential amplifier circuit receiving a P-type transistor) that receives an input signal VIN with a P-type transistor. The control circuit 40 is arranged between the differential amplifier circuit 10 and the output circuit 30 and between the differential amplifier circuit 10 and the differential amplifier circuit 20 and the output circuit 30. The differential amplifier circuit 10 includes a pre-emphasis circuit PE1, and the differential amplifier circuit 20 includes a pre-emphasis circuit PE2.

[0015] The differential amplifier circuit 10 receives an input signal VIN and a reference signal VREF by a pair of input transistors Trin1 and Trin2 that form a differential pair, respectively, and amplifies the difference between the input signal VIN and the reference signal VREF using a power supply voltage VCCQ to generate a signal HVO in cooperation with the differential amplifier circuit 20. The input transistors Trin1 and Trin2 are N-type transistors. The reference signal VREF may be preset according to the level of the power supply voltage VCCQ. The reference signal VREF may have a level that is, for example, approximately half that of the power supply voltage VCCQ. At this time, the pre-emphasis circuit PE1 shapes the waveform of the internal signal of the differential amplifier circuit 10 into an undershoot waveform. This allows the slope of the signal HVO during the level transition to be steep.

[0016] The differential amplifier circuit 20 receives the input signal IN and the reference signal VREF by a pair of input transistors Trin3 and Trin4 that form a differential pair, respectively, and amplifies the difference between the input signal VIN and the reference signal VREF using a power supply voltage VCCQ to generate a signal HVO in cooperation with the differential amplifier circuit 10. The input transistors Trin3 and Trin4 are both P-type transistors. At this time, the pre-emphasis circuit PE2 shapes the waveform of the internal signal of the differential amplifier circuit 20 into an overshoot waveform. This allows the slope of the signal HVO during the level transition to be made steeper.

[0017] The output circuit 30 receives the signal HVO from the differential amplifier circuit 10 and the differential amplifier circuit 20. At this time, the pre-emphasis circuit PE1 and the pre-emphasis circuit PE2 can make the slope of the level transition of the signal HVO steeper.

[0018] The output circuit 30 generates and outputs an output signal OUT according to the signal HVO. At this time, since the slope of the level transition of the signal HVO can be made steep, the slope of the level transition of the output signal OUT can also be made steep. The output circuit 30 may generate and output the output signal OUT by logically inverting the signal HVO an even number of times (twice in FIG. 1). The output signal OUT may have the same logical level as the signal HVO.

[0019] The control circuit 40 receives the signal HVO from the differential amplifier circuit 10 and the differential amplifier circuit 20. The control circuit 40 uses the power supply voltage VCCQ to generate a signal HVON according to the signal HVO and feeds it back to the pre-emphasis circuit PE1 of the differential amplifier circuit 10 and the pre-emphasis circuit PE2 of the differential amplifier circuit 20. The control circuit 40 may generate and output the signal HVON by logically inverting the signal HVO an odd number of times (once in FIG. 1). The signal HVON is a control signal for controlling the pre-emphasis circuits PE1 and PE2.

[0020] The differential amplifier circuit 10 includes a differential circuit DIFF1, a pre-emphasis circuit PE1, a load circuit LD1, auxiliary circuits AS11 and AS12, and a transfer circuit TR1. The differential circuit DIFF1 is disposed between the load circuit LD1 and a ground potential. The pre-emphasis circuit PE1 is disposed between the differential circuit DIFF1 and a ground potential. The load circuit LD1 is disposed between the differential circuit DIFF1 and a power supply potential VCCQ. The load circuit LD1 is configured as a circuit (cross-coupled circuit) in which the gates and drains of two transistors are cross-coupled.

[0021] The transfer circuit TR1 has a transistor Tr4 as a fourth transistor. The transistor Tr4 may be a PMOS transistor. The gate of the transistor Tr4 is connected to the auxiliary circuit AS11 via a bias line NN. The drain of the transistor Tr4 is connected to the output circuit 30, and the source is connected to the power supply potential VCCQ.

[0022] The differential circuit DIFF1 has an input transistor Trin1 as a first input transistor, an input transistor Trin2 as a second input transistor, and a current source CS1. The input transistor Trin1 and the input transistor Trin2 form a differential pair. The input transistor Trin1 and the input transistor Trin2 may each be configured as an NMOS transistor. The input transistor Trin1 receives an input signal VIN at its gate, has a drain electrically connected to a node N1, and has a source electrically connected to one end of the current source CS1. The input transistor Trin2 receives a reference signal VREF at its gate, has a drain electrically connected to a node N2, and has a source electrically connected to one end of the current source CS1. The other end of the current source CS1 is electrically connected to the ground potential.

[0023] The pre-emphasis circuit PE1 has a transistor Tr1 as a first transistor and a transistor Tr2 as a second transistor. The transistor Tr1 is connected in parallel with a current source CS1 to a source of the input transistor Trin1 and a source of the input transistor Trin2. The transistor Tr2 is connected in series with the transistor Tr1. The transistors Tr1 and Tr2 may each be configured as an NMOS transistor. The transistor Tr1 receives an input signal VIN at its gate, has a drain electrically connected to the source of the input transistor Trin1 and the source of the input transistor Trin2, and has a source electrically connected to the transistor Tr2. The transistor Tr2 receives a signal HVON at its gate, has a source electrically connected to a ground potential, and has a drain electrically connected to the transistor Tr1.

[0024] The load circuit LD1 has a transistor Tr8 as an eighth transistor and a transistor Tr10 as a tenth transistor. The gates and drains of the transistors Tr8 and Tr10 are cross-coupled. The transistors Tr8 and Tr10 may each be configured as a PMOS transistor. The transistor Tr8 has a gate connected to the gate and drain of the transistor Tr10, a drain electrically connected to a node N1, and a source electrically connected to a power supply potential VCCQ. The transistor Tr10 has a gate connected to the drain and the gate of the transistor Tr8, a drain electrically connected to a node N2, and a source electrically connected to a power supply potential VCCQ.

[0025] The auxiliary circuit AS11 has a transistor Tr6 as a sixth transistor. The transistor Tr6 may be a PMOS transistor. The transistor Tr6 is disposed between the input transistor Trin1 and the power supply potential VCCQ. The transistor Tr6 is connected in series with the input transistor Trin1. The transistor Tr6 forms a current mirror circuit with the transistor Tr4. The gate of the transistor Tr6 is connected to the bias line NN and the drain of the transistor Tr6. The drain of the transistor Tr6 is connected to the node N1. As a result, a drain current corresponding to a mirror ratio determined by the ratio between the dimensions of the transistor Tr6 and the transistor Tr4 appears at the drain side of the transistor Tr4 with respect to the drain current of the transistor Tr6 (i.e., the current flowing to the node N1).

[0026] The auxiliary circuit AS12 includes a transistor Tr18. The transistor Tr18 may be a PMOS transistor. The transistor Tr18 is disposed between the input transistor Trin2 and a power supply potential VCCQ. The transistor Tr18 is connected in series with the input transistor Trin2. The gate of the transistor Tr18 is connected to the drain. The drain of the transistor Tr18 is connected to the node N2.

[0027] The differential amplifier circuit 20 includes a differential circuit DIFF2, a pre-emphasis circuit PE2, a load circuit LD2, an auxiliary circuit AS21, an auxiliary circuit AS22, and a transfer circuit TR2. The differential circuit DIFF2 is disposed between the load circuit LD2 and a power supply potential VCCQ. The pre-emphasis circuit PE2 is disposed between the differential circuit DIFF2 and a power supply potential VCCQ. The load circuit LD2 is disposed between the differential circuit DIFF2 and a ground potential. The load circuit LD2 is configured as a circuit in which the gates and drains of two transistors are cross-coupled (a cross-coupled circuit).

[0028] The transfer circuit TR2 has a transistor Tr15 as a fifteenth transistor. The transistor Tr15 may be an NMOS transistor. The gate of the transistor Tr15 is connected to the auxiliary circuit AS21 via the bias line NP. The drain of the transistor Tr15 is connected to the output circuit 30, and the source is connected to the ground potential.

[0029] The differential circuit DIFF2 has an input transistor Trin3 as a third input transistor, an input transistor Trin4 as a fourth input transistor, and a current source CS2. The input transistor Trin3 and the input transistor Trin4 form a differential pair. The input transistor Trin3 and the input transistor Trin4 may each be configured as a PMOS transistor. The input transistor Trin3 receives an input signal VIN at its gate, has a drain electrically connected to a node N3, and has a source electrically connected to one end of the current source CS2. The input transistor Trin4 receives a reference signal VREF at its gate, has a drain electrically connected to a node N4, and has a source electrically connected to one end of the current source CS2. The other end of the current source CS2 is electrically connected to a power supply potential VCCQ.

[0030] The pre-emphasis circuit PE2 has a transistor Tr12 as a twelfth transistor and a transistor Tr13 as a thirteenth transistor. The transistor Tr12 is connected in parallel with a current source CS2 to the source of the input transistor Trin3 and the source of the input transistor Trin4. The transistor Tr13 is connected in series with the transistor Tr12. The transistors Tr12 and Tr13 may each be configured as a PMOS transistor. The transistor Tr12 receives an input signal VIN at its gate, has a drain electrically connected to the source of the input transistor Trin3 and the source of the input transistor Trin4, and has a source electrically connected to the transistor Tr13. The transistor Tr13 receives a signal HVON at its gate, has a source electrically connected to a power supply potential VCCQ, and has a drain electrically connected to the transistor Tr12.

[0031] The load circuit LD2 includes a transistor Tr20 and a transistor Tr21. The gates and drains of the transistors Tr20 and Tr21 are cross-coupled. The transistors Tr20 and Tr21 may each be configured as a PMOS transistor. The transistor Tr20 has a gate connected to the gate and drain of the transistor Tr21, a drain electrically connected to a node N3, and a source electrically connected to a ground potential. The transistor Tr21 has a gate connected to the drain and the gate of the transistor Tr20, a drain electrically connected to a node N4, and a source electrically connected to a ground potential.

[0032] The auxiliary circuit AS21 has a transistor Tr17 as a 17th transistor. The transistor Tr17 may be an NMOS transistor. The transistor Tr17 is disposed between the input transistor Trin3 and the ground potential. The transistor Tr17 is connected in series with the input transistor Trin3. The transistor Tr17 forms a current mirror circuit with the transistor Tr15. The gate of the transistor Tr17 is connected to the bias line NP and the drain of the transistor Tr17. The drain of the transistor Tr17 is connected to the node N3. As a result, a drain current corresponding to a mirror ratio determined by the ratio between the dimensions of the transistor Tr17 and the transistor Tr15 appears at the drain side of the transistor Tr15 with respect to the drain current of the transistor Tr17 (i.e., the current flowing to the node N3).

[0033] The auxiliary circuit AS22 includes a transistor Tr23. The transistor Tr23 may be an NMOS transistor. The transistor Tr23 is disposed between the input transistor Trin4 and the ground potential. The transistor Tr18 is connected in series with the input transistor Trin4. The gate of the transistor Tr23 is connected to the drain. The drain of the transistor Tr23 is connected to the node N4.

[0034] The output circuit 30 has a plurality of inverters INV1-1 and INV1-2. The plurality of inverters INV1-1 and INV1-2 are arranged on an output line Lout. The output line Lout extends from the drains of the transistors Tr4 and Tr15 to an output node Nout. The input node of the inverter INV1-1 is connected to the drains of the transistors Tr4 and Tr15, and the output node is connected to the inverter INV1-2. The inverter INV1-1 receives a signal HVO at an input node. The input node of the inverter INV1-2 is connected to the inverter INV1-1, and the output node is connected to the output node Nout of the semiconductor device 1. The inverters INV1-1 and INV1-2 logically invert the signal HVO an even number of times (for example, twice) to generate and output an output signal OUT.

[0035] The control circuit 40 includes an inverter INV3. The input node of the inverter INV3 is connected to the drains of the transistors Tr4 and Tr15, and the output node is connected to the gates of the transistors Tr2 and Tr13. The inverter INV3 receives a signal HVO at its input node. The inverter INV3 logically inverts the level of the signal HVO to generate a signal HVON, which is then supplied to the gates of the transistors Tr2 and Tr13.

[0036] In the semiconductor device 1, the waveforms of the internal signals N_VINB and P_VINB are shaped into an undershoot waveform and an overshoot waveform by the pre-emphasis circuits PE1 and PE2 as shown in Fig. 2. The internal signals N_VINB and P_VINB are signals of the bias lines NN and NP in the differential amplifier circuits 10 and 20. Fig. 2 is a waveform diagram showing the operation of the semiconductor device 1.

[0037] Immediately before timing t1, the signal HVON is at H level, and the input signal VIN is at L level.

[0038] In response to this, in the differential amplifier circuit 10, the transistor Tr1 is turned off, the pre-emphasis circuit PE1 is inactive, and a current of the amount I1 flows through the common source node COMN of the input transistors Trin1 and Trin2. I1 is the amount of current from the current source CS1.

[0039] In the differential amplifier circuit 20, the transistor Tr13 is turned off, the pre-emphasis circuit PE2 is inactive, and a current of the amount I2 flows through the common source node COMP of the input transistors Trin3 and Trin4. I2 is the amount of current from the current source CS2.

[0040] At timing t1, the input signal VIN changes from the L level to the H level while the signal HVON is maintained at the H level.

[0041] In response to this, in the differential amplifier circuit 10, the transistors Tr1 and Tr2 are turned on, the pre-emphasis circuit PE1 is activated, and a current of I1+ΔIpe1 (>I1) flows through the common source node COMN. ΔIpe1 is the current amount due to the pre-emphasis circuit PE1. As a result, the pre-emphasis circuit PE1 emphasizes the L-level amplitude of the internal signal N_VINB when the internal signal N_VINB transitions from H-level to L-level.

[0042] That is, the internal signal N_VINB is at the H level V Hn Amplitude-emphasized L level V LLn Transition to H level V Hn and L level V Ln The intermediate value is the reference value V Rn Then, the amplitude-emphasized L level V LLn The reference value V Rn The difference from H level V Hn The reference value V Rn 2, the period during which the L level amplitude of the internal signal N_VINB of the differential amplifier circuit 10 is emphasized is indicated as "strong," and the period during which the L level amplitude of the internal signal N_VINB is not emphasized is indicated as "weak."

[0043] In the differential amplifier circuit 20, the transistors Tr11 and Tr12 are turned off, the pre-emphasis circuit PE2 remains in an inactive state, and a current of the amount I2 flows through the common source node COMP. As a result, the internal signal P_VINB becomes high level V Hp From L level V Lp , but the L level amplitude is not emphasized.

[0044] At timing t2, while the input signal VIN is maintained at the H level, the signal HVON changes from the H level to the L level.

[0045] In response to this, in the differential amplifier circuit 10, the transistor Tr2 is turned off, the pre-emphasis circuit PE1 returns to an inactive state, and a current of the amount I1 flows to the common source node COMN. As a result, the pre-emphasis circuit PE1 cancels the emphasis on the L-level amplitude of the internal signal N_VINB.

[0046] In other words, the internal signal N_VINB is an L level V LLn De-emphasized L level V Ln The de-emphasized L level becomes V Ln The reference value V Cn The difference from H level V Hn The reference value V Cn is approximately equal to the difference from the output of the differential amplifier 10. Therefore, the pre-emphasis circuit PE1 shapes the waveform of the internal signal N_VINB into an undershoot waveform. This temporarily increases the driving force of the transistor Tr4 in the transfer circuit TR1 during a level transition, making the slope of the signal HVO output from the differential amplifier circuit 10 to the output circuit 30 during the level transition steeper.

[0047] In the differential amplifier circuit 20, the transistors Tr11 and Tr12 are off, the pre-emphasis circuit PE2 remains in an inactive state, and a current of the amount I2 flows through the common source node COMP. As a result, the waveform of the internal signal P_VINB is not shaped, and the slope of the level transition of the signal HVO output from the differential amplifier circuit 20 to the output circuit 30 is not made steep.

[0048] In the period from timing t1 to t2, the slope of the level transition of the signal HVO output from the differential amplifier circuit 10 to the output circuit 30 is made steeper. This causes the slope of the level transition of the output signal OUT generated by the output circuit 30 in response to the signal HVO to also be steeper.

[0049] Immediately before timing t3, the signal HVON is at the L level, and the input signal VIN is at the H level.

[0050] In response to this, in the differential amplifier circuit 10, the transistor Tr2 is turned off, the pre-emphasis circuit PE1 is in an inactive state, and a current of the amount I1 flows to the common source node COMN of the input transistors Trin1 and Trin2.

[0051] In the differential amplifier circuit 20, the transistor Tr12 is turned off, the pre-emphasis circuit PE2 is in an inactive state, and a current of the amount I2 flows through the common source node COMP of the input transistors Trin3 and Trin4.

[0052] At timing t3, while the signal HVON is maintained at the L level, the input signal VIN changes from the H level to the L level.

[0053] In response to this, in the differential amplifier circuit 20, the transistors Tr12 and Tr13 are turned on, the pre-emphasis circuit PE2 is activated, and a current of I2+ΔIpe2 (>I2) flows through the common source node COMP. ΔIpe2 is the amount of current caused by the pre-emphasis circuit PE2. As a result, the pre-emphasis circuit PE2 emphasizes the H-level amplitude of the internal signal P_VINB when the internal signal P_VINB transitions from an L level to an H level.

[0054] That is, the internal signal P_VINB is at the L level V Lp Amplitude-emphasized H level V HHp Transition to H level V Hp and L level V Lp The intermediate value is the reference value V Cp Then, the amplitude-emphasized H level V HHp The reference value V Cp The difference from L level V Lp The reference value V Cp 2, the period during which the H-level amplitude of the internal signal P_VINB of the differential amplifier circuit 20 is emphasized is indicated as "strong," and the period during which the H-level amplitude of the internal signal P_VINB is not emphasized is indicated as "weak."

[0055] In the differential amplifier circuit 10, the transistors Tr1 and Tr2 are turned off, the pre-emphasis circuit PE1 remains in an inactive state, and a current of I1 flows through the common source node COMN. As a result, the internal signal N_VINB goes low (V Ln From H level V Hn , but the H level amplitude is not emphasized.

[0056] At timing t4, while the input signal VIN is maintained at the L level, the signal HVON changes from the L level to the H level.

[0057] In response to this, in the differential amplifier circuit 20, the transistor Tr13 is turned off, the pre-emphasis circuit PE2 returns to an inactive state, and a current of the amount I2 flows to the common source node COMP. As a result, the pre-emphasis circuit PE2 cancels the emphasis on the H-level side of the H-level amplitude of the internal signal P_VINB.

[0058] That is, the internal signal P_VINB is a high-level V HHp De-emphasized H level V Hp The de-emphasized H level becomes V Hp The reference value V Cp The difference from L level V Lp The reference value V Cp is approximately equal to the difference from the output of the differential amplifier 20. Therefore, the waveform of the internal signal P_VINB is shaped into an overshoot waveform. As a result, the driving force of the transistor Tr15 of the transfer circuit TR2 is temporarily increased at the time of the level transition, and the slope of the signal HVO output from the differential amplifier circuit 20 to the output circuit 30 at the time of the level transition is made steeper.

[0059] In the differential amplifier circuit 10, the transistor Tr1 is off, the pre-emphasis circuit PE1 remains in an inactive state, and a current of the amount I1 flows through the common source node COMN. Therefore, the waveform of the internal signal N_VINB is not shaped.

[0060] In the period from timing t3 to t4, the slope of the level transition of the signal HVO output from the differential amplifier circuit 20 to the output circuit 30 is made steeper. This causes the slope of the level transition of the output signal OUT generated by the output circuit 30 in response to the signal HVO to also be steeper.

[0061] At times t5 and t6, the same operations as those at times t1 and t2 are performed.

[0062] As shown in Fig. 1, the signal HVO is reversed in polarity and fed back to the pre-emphasis circuits PE1 and PE2 as the signal HVON. As a result, as shown in Fig. 2, the pre-emphasis circuits PE1 and PE2 temporarily increase the drive current corresponding to the amplitude of the internal signal of the differential amplifier circuit 10 when the input signal VIN transitions from L level to H level, thereby increasing the drive power of the transfer circuit TR1. When the input signal VIN transitions from H level to L level, the pre-emphasis circuits PE1 and PE2 temporarily increase the drive current corresponding to the amplitude of the internal signal of the differential amplifier circuit 20, thereby increasing the drive power of the transfer circuit TR2. This makes it possible to current-efficiently strengthen the drive power of the differential amplifier circuits 10 and 20 during the level transition.

[0063] As described above, in the first embodiment, in the semiconductor device 1, the pre-emphasis circuits PE1 and PE2 are added to the differential amplifier circuits 10 and 20, respectively. The pre-emphasis circuits PE1 and PE2 shape the waveforms of the internal signals of the differential amplifier circuits 10 and 20 into undershoot and overshoot waveforms by emphasizing the amplitude at the time of level transition. This makes it possible to speed up the transition of the signal level while suppressing the time-averaged amplitude, and to raise the operating frequency of the semiconductor device 1 with current efficiency. As a result, it is possible to achieve both suppression of power consumption and high speed.

[0064] Second embodiment Next, a semiconductor device according to a second embodiment will be described, focusing on the differences from the first embodiment.

[0065] In the first embodiment, the waveforms of the internal signals of the differential amplifier circuits 10 and 20 are shaped into undershoot and overshoot waveforms by emphasizing the amplitude at the time of the level transition, whereas in the second embodiment, the waveforms of the internal signals of the differential amplifier circuits 110 and 120 are shaped into undershoot and overshoot waveforms by attenuating the amplitude after the level transition.

[0066] Specifically, the semiconductor device 101 may be configured as shown in Fig. 3. Fig. 3 is a diagram showing the configuration of the semiconductor device 101. The semiconductor device 101 has a differential amplifier circuit 110 and a differential amplifier circuit 120 instead of the differential amplifier circuit 10 and the differential amplifier circuit 20 (see Fig. 1). The differential amplifier circuit 110 has a de-emphasis circuit DE101 instead of the pre-emphasis circuit PE1 (see Fig. 1), and the differential amplifier circuit 120 has a de-emphasis circuit DE102 instead of the pre-emphasis circuit PE2 (see Fig. 1).

[0067] The differential amplifier circuit 110 amplifies the difference between the input signal VIN and the reference signal VREF using the power supply voltage VCCQ, and generates the signal HVO in cooperation with the differential amplifier circuit 120. At this time, the de-emphasis circuit DE101 shapes the waveform of the internal signal of the differential amplifier circuit 110 into an undershoot waveform. This allows the slope of the signal HVO during the level transition to be made steeper.

[0068] The differential amplifier circuit 120 amplifies the difference between the input signal VIN and the reference signal VREF using the power supply voltage VCCQ, and generates the signal HVO in cooperation with the differential amplifier circuit 110. At this time, the de-emphasis circuit DE102 shapes the waveform of the internal signal of the differential amplifier circuit 120 into an overshoot waveform. This allows the slope of the signal HVO during the level transition to be made steeper.

[0069] The output circuit 30 receives the signal HVO from the differential amplifier circuit 110 and the differential amplifier circuit 120, and generates and outputs an output signal OUT according to the signal HVO. At this time, the slope of the level transition of the signal HVO can be made steep. In addition, since the slope of the level transition of the signal HVO can be made steep, the slope of the level transition of the output signal OUT can also be made steep.

[0070] The de-emphasis circuit DE101 includes a transistor Tr3 and a transistor Tr5. The transistor Tr3 is connected in parallel with the transistors Tr6 and Tr8 to the drain of the input transistor Trin1. The transistor Tr5 is connected between the transistor Tr3 and a power supply potential VCCQ. The transistor Tr5 is connected in series with the transistor Tr3. The transistors Tr3 and Tr5 may each be configured as a PMOS transistor.

[0071] The transistor Tr5 receives the signal HVON at its gate, has a drain electrically connected to the source of the transistor Tr3, and has a source electrically connected to the power supply potential VCCQ.

[0072] The transistor Tr3 forms a current mirror circuit with the transistor Tr4. The gate of the transistor Tr3 is connected to the bias line NN and the drain of the transistor Tr3. The drain of the transistor Tr3 is connected to the node N1.

[0073] The de-emphasis circuit DE101 makes a drain current corresponding to a mirror ratio determined by the ratio between the dimensions of the transistors Tr3 and Tr4 appear additionally on the drain side of the transistor Tr4 with respect to the drain current of the transistor Tr3 during a period when the signal HVON is at the L level. For example, the de-emphasis circuit DE101 makes a drain current that attenuates the L level amplitude of the signal appear additionally on the drain side of the transistor Tr4.

[0074] The de-emphasis circuit DE102 has a transistor Tr14 as a 14th transistor and a transistor Tr16 as a 16th transistor. The transistor Tr14 is connected in parallel with the transistors Tr17 and Tr20 to the drain of the input transistor Trin3. The transistor Tr16 is connected between the transistor Tr14 and the ground potential. The transistor Tr16 is connected in series with the transistor Tr14. The transistors Tr14 and Tr16 may each be configured as an NMOS transistor.

[0075] The transistor Tr16 receives the signal HVON at its gate, has a drain electrically connected to the source of the transistor Tr14, and has a source electrically connected to the ground potential.

[0076] The transistor Tr14 forms a current mirror circuit with the transistor Tr15. The gate of the transistor Tr14 is connected to the bias line NP and the drain of the transistor Tr14. The drain of the transistor Tr14 is connected to the node N1.

[0077] During a period when the signal HVON is at H level, the de-emphasis circuit DE102 causes a drain current corresponding to a mirror ratio determined by the ratio between the dimensions of the transistor Tr14 and the transistor Tr15 to additionally appear on the drain side of the transistor Tr15 with respect to the drain current of the transistor Tr14. For example, the de-emphasis circuit DE102 causes a drain current that attenuates the H level amplitude of the signal to additionally appear on the drain side of the transistor Tr15.

[0078] In the semiconductor device 101, the waveforms of the internal signals N_VINB and P_VINB are shaped into an undershoot waveform and an overshoot waveform by the de-emphasis circuits DE101 and DE102, as shown in Fig. 4. The internal signals N_VINB and P_VINB are signals of the bias lines NN and NP in the differential amplifier circuits 110 and 120. Fig. 4 is a waveform diagram showing the operation of the semiconductor device 101.

[0079] At timing t11, while the signal HVON is maintained at the H level, the input signal VIN changes from the L level to the H level.

[0080] In response to this, in the differential amplifier circuit 110, the transistor Tr5 is turned off and the de-emphasis circuit DE101 is in an inactive state. In response to the transition of the input signal VIN from the L level to the H level, the internal signal N_VINB goes to the H level V Hn From L level V Ln Transition to.

[0081] In the differential amplifier circuit 120, the transistor Tr16 is turned on and the de-emphasis circuit DE102 is in an active state. In response to the transition of the input signal VIN from the L level to the H level, the internal signal P_VINB goes to the H level V HpL From L level V Lp Transition to.

[0082] At timing t12 after the input signal VIN transitions from the L level to the H level, the signal HVON changes from the H level to the L level while the input signal VIN is maintained at the H level.

[0083] In response to this, in the differential amplifier circuit 110, the transistor Tr5 is turned on, the de-emphasis circuit DE101 is activated, the potential of the bias line NN is raised to the H level side, and the L level amplitude of the internal signal N_VINB is attenuated.

[0084] That is, the internal signal N_VINB is at the L level V Ln The attenuated L level V LnHThe amplitude attenuated L level V LnH , L level V Ln Compared to the above, the L level amplitude is raised toward the H level. Hn and L level V Ln The intermediate value is the reference value V Rn When the amplitude is attenuated, the L level V LnH The reference value V Rn The difference from H level V Hn The reference value V Rn is smaller than the difference from . Therefore, the waveform of the internal signal N_VINB is shaped into an undershoot waveform by the de-emphasis circuit DE101. As a result, in relative terms, the driving force of the transistor Tr4 of the transfer circuit TR1 is temporarily increased during the level transition compared to after the level transition, and the slope of the level transition of the differential signal VO10 output from the differential amplifier circuit 110 to the output circuit 30 is made steeper.

[0085] In the differential amplifier circuit 120, the transistor Tr16 is turned off, the de-emphasis circuit DE102 is in an inactive state, and the potential of the bias line NP is not lowered. As a result, the internal signal P_VINB is at the L level V Lp Therefore, the waveform of the internal signal P_VINB is not shaped.

[0086] In the period from timing t11 to t12, the slope of the level transition of the signal HVO output from the differential amplifier circuit 110 to the output circuit 30 is made steeper. This causes the slope of the level transition of the output signal OUT generated by the output circuit 30 in response to the signal HVO to also be steeper.

[0087] At timing t13, while the signal HVON is maintained at the L level, the input signal VIN changes from the H level to the L level.

[0088] In response to this, in the differential amplifier circuit 120, the transistor Tr16 is turned off and the de-emphasis circuit DE102 is in an inactive state. In response to the transition of the input signal VIN from H level to L level, the internal signal P_VINB goes to the L level VLp From H level V Hp Transition to.

[0089] In the differential amplifier circuit 110, the transistor Tr5 is turned on and the de-emphasis circuit DE101 is in an active state. In response to the transition of the input signal VIN from the H level to the L level, the internal signal N_VINB goes to the L level V LnL From H level V Hn Transition to.

[0090] At timing t14 after the input signal VIN transitions from H level to L level, the signal HVON changes from L level to H level while the input signal VIN is maintained at L level.

[0091] In response to this, in the differential amplifier circuit 120, the transistor Tr16 is turned on, the de-emphasis circuit DE102 is activated, the potential of the bias line NP is pulled down to the L level, and the H level amplitude of the internal signal P_VINB is attenuated.

[0092] That is, the internal signal P_VINB is at the H level V Hp Attenuated H level V HpL H level V HpL is H level V Hp Compared to the above, the H level amplitude is lowered toward the L level. Lp and H level V Hp The intermediate value is the reference value V Rp When the amplitude is attenuated, the H level V HpL The reference value V Rp The difference from L level V Lp The reference value V Rp is smaller than the difference from . Therefore, the waveform of the internal signal P_VINB is shaped into an overshoot waveform by the de-emphasis circuit DE102. As a result, in relative terms, the driving force of the transistor Tr15 of the transfer circuit TR2 is temporarily increased during the level transition compared to after the level transition, and the slope of the level transition of the signal HVO output from the differential amplifier circuit 120 to the output circuit 30 is made steeper.

[0093] In the differential amplifier circuit 110, the transistor Tr5 is turned off, the de-emphasis circuit DE101 is in an inactive state, and the potential of the bias line NN is not lowered. As a result, the internal signal N_VINB is at the H level V Hn Therefore, the waveform of the internal signal N_VINB is not shaped.

[0094] In the period from timing t13 to t14, the slope of the level transition of the signal HVO output from the differential amplifier circuit 120 to the output circuit 30 is made steeper. This causes the slope of the level transition of the output signal OUT generated by the output circuit 30 in response to the signal HVO to also be steeper.

[0095] At timings t15 and t16, the same operations as those at timings t11 and t12 are performed.

[0096] At timings t17 and t18, the same operations as those at timings t13 and t14 are performed.

[0097] As shown in Fig. 3, the signal HVO is reversed in polarity and fed back to the de-emphasis circuits DE101 and DE102 as the signal HVON. As a result, the de-emphasis circuits DE101 and DE102 temporarily reduce the drive current corresponding to the amplitude of the internal signal of the differential amplifier circuit 110 to reduce the drive power of the transfer circuit TR1 after the input signal VIN transitions from L level to H level, as shown in Fig. 4. After the input signal VIN transitions from H level to L level, the de-emphasis circuits temporarily reduce the drive current corresponding to the amplitude of the internal signal of the differential amplifier circuit 120 to reduce the drive power of the transfer circuit TR2. As a result, the drive power of the differential amplifier circuits 110 and 120 at the time of the level transition can be relatively strengthened.

[0098] As described above, in the second embodiment, in the semiconductor device 101, the de-emphasis circuits DE101 and DE102 are added to the differential amplifier circuits 110 and 120, respectively. The de-emphasis circuits DE101 and DE102 attenuate the amplitude after the level transition to shape the waveforms of the internal signals of the differential amplifier circuits 110 and 120 into undershoot and overshoot waveforms. This makes it possible to speed up the transition of the signal level while suppressing the time-averaged amplitude, and to raise the operating frequency of the semiconductor device 101 with current efficiency. As a result, it is possible to achieve both suppression of power consumption and high speed.

[0099] (Third embodiment) Next, a semiconductor device according to a third embodiment will be described, focusing on the differences from the first and second embodiments.

[0100] In the second embodiment, the waveforms of the internal signals of the differential amplifier circuits 110 and 120 are shaped into an undershoot waveform and an overshoot waveform, whereas in the third embodiment, the waveform of the signal HVO synthesized from the difference signals VO10 and VO20 of the differential amplifier circuits 210 and 220 is shaped into an undershoot waveform and an overshoot waveform.

[0101] Specifically, the semiconductor device 201 may be configured as shown in Fig. 5. Fig. 5 is a diagram showing the configuration of the semiconductor device 201. The semiconductor device 201 has differential amplifier circuits 210 and 220 instead of the differential amplifier circuits 110 and 120 (see Fig. 3), and further has a de-emphasis circuit DE203. The differential amplifier circuits 210 and 220 are configured by omitting the de-emphasis circuits DE101 and DE102 from the differential amplifier circuits 110 and 120, respectively.

[0102] The output circuit 30 receives the signal HVO from the differential amplifier circuit 210 and the differential amplifier circuit 220, and generates and outputs an output signal OUT according to the signal HVO. At this time, the de-emphasis circuit DE203 generates a signal FB according to the output signal OUT, feeds it back to the input node of the output circuit 30, and attenuates the amplitude of the signal HVO after the level transition. As a result, the de-emphasis circuit DE203 shapes the waveform of the signal HVO into an undershoot waveform and an overshoot waveform. As a result, the slope of the signal HVO during the level transition can be made steep. In addition, since the slope of the signal HVO during the level transition can be made steep, the slope of the output signal OUT during the level transition can also be made steep.

[0103] The de-emphasis circuit DE203 is disposed between the output circuit 30 and the differential amplifier circuit 210 and the differential amplifier circuit 220. The de-emphasis circuit DE203 has one or more inverters INV2. The inverter INV2 is connected to a feedback line L FB The feedback line L FB extends from node N5 on the output line Lout to the drains of the transistors Tr4 and Tr15. The de-emphasis circuit DE203 includes inverters INV2 such that the total number of inverters INV1 and INV2 through which the feedback loop passes is an odd number. The feedback loop is formed by a portion of the output line Lout from one end to node N5 and a portion of the feedback line L FB The inverter INV2 has an input node connected to the node N5 and an output node connected to the drains of the transistors Tr4 and Tr15.

[0104] The driving force of the inverter INV2 is smaller than the driving force of the transistors Tr4 and Tr15 of the transfer circuits TR1 and TR2. This makes it possible to prevent excessive attenuation of the amplitude of the signal HVO when the de-emphasis circuit DE203 attenuates the amplitude of the signal HVO by feeding back the logically inverted signal FB to the signal HVO, thereby preventing oscillation due to feedback.

[0105] For example, when the inverter INV1 is configured as shown in Fig. 6(a), the inverter INV2 may be configured as shown in Fig. 6(b) or Fig. 6(c). Fig. 6(a) is a circuit diagram showing the configuration of the inverter INV1, and Fig. 6(b) and Fig. 6(c) are circuit diagrams showing the configuration of the inverter INV2, respectively.

[0106] The inverter INV1 shown in Fig. 6(a) has an N-type transistor NM and a P-type transistor PM. The transistor NM is connected between the transistor PM and a ground potential, and the transistor PM is connected between a power supply potential VCCQ and the transistor NM. The transistor NM is, for example, an NMOS transistor, with a source connected to a ground potential, a drain connected to an output node of the inverter INV1, and a gate connected to an input node of the inverter INV1. The transistor PM is, for example, a PMOS transistor, with a source connected to a power supply potential VCCQ, a drain connected to the output node of the inverter INV1, and a gate connected to the input node of the inverter INV1.

[0107] The inverter INV2 shown in FIG. 6(b) has a plurality of N-type transistors NM1 to NM3 and a plurality of P-type transistors PM1 to PM3. The plurality of transistors NM1 to NM3 are connected in series between the transistors PM1 to PM3 and the ground potential, and the plurality of transistors PM1 to PM3 are connected in series between the power supply potential VCCQ and the transistors NM1 to NM3. Each of the transistors NM1 to NM3 is, for example, an NMOS transistor, and the dimensions (=L / W, L: gate length, W: gate width) of each of the transistors NM1 to NM3 may be equal to the dimensions of the transistor NM. The transistor NM1 has a source connected to the transistor NM2, a drain connected to the output node of the inverter INV1, and a gate connected to the input node of the inverter INV1. The transistor NM2 has a source connected to the transistor NM3, a drain connected to the transistor NM1, and a gate connected to the input node of the inverter INV1. The transistor NM3 has a source connected to the ground potential, a drain connected to the transistor NM2, and a gate connected to the input node of the inverter INV1. Each of the transistors PM1 to PM3 may be, for example, a PMOS transistor, and the dimensions of each of the transistors PM1 to PM3 may be equal to the dimensions of the transistor PM. The transistor PM1 has a source connected to the transistor PM2, a drain connected to the output node of the inverter INV1, and a gate connected to the input node of the inverter INV1. The transistor PM2 has a source connected to the transistor PM3, a drain connected to the transistor PM1, and a gate connected to the input node of the inverter INV1. The transistor PM3 has a source connected to the power supply potential VCCQ, a drain connected to the transistor PM2, and a gate connected to the input node of the inverter INV1.

[0108] The inverter INV2 shown in Fig. 6(b) has a larger number of N-type transistors connected between the output node and the ground potential than the inverter INV1 shown in Fig. 6(a), and a larger number of P-type transistors connected between the output node and the power supply potential VCCQ than the inverter INV1 shown in Fig. 6(a). As a result, the driving load of each N-type transistor and each P-type transistor in Fig. 6(b) is larger than the driving load of the N-type transistor and P-type transistor in Fig. 6(a), and the driving power of the inverter INV2 is smaller than the driving power of the inverter INV1.

[0109] The inverter INV2 shown in FIG. 6(c) has an N-type transistor NM11, a P-type transistor PM11, a current source CS11, and a current source CS12. The transistor NM11 is connected between the transistor PM11 and the current source CS11, and the transistor PM11 is connected between the current source CS12 and the transistor NM11. The current source CS11 is connected between the transistor NM11 and a ground potential, and the current source CS12 is connected between a power supply potential VCCQ and the transistor PM11. The transistor NM11 is, for example, an NMOS transistor, and the dimensions of the transistor NM11 may be equal to the dimensions of the transistor NM. The source of the transistor NM11 is connected to the current source CS11, the drain is connected to the output node of the inverter INV1, and the gate is connected to the input node of the inverter INV1. One end of the current source CS11 is connected to the transistor NM11, and the other end is connected to the ground potential. The transistor PM11 is, for example, a PMOS transistor, with a source connected to the current source CS12, a drain connected to the output node of the inverter INV1, and a gate connected to the input node of the inverter INV1. One end of the current source CS12 is connected to the transistor PM11, and the other end is connected to the power supply potential VCCQ.

[0110] In the inverter INV2 shown in Fig. 6(c), a current source CS11 is connected between the output node and the ground potential in addition to an N-type transistor, and a current source CS12 is connected between the output node and the power supply potential VCCQ in addition to a P-type transistor. As a result, the driving load of the N-type transistor and the P-type transistor in Fig. 6(c) is larger than the driving load of the N-type transistor and the P-type transistor in Fig. 6(a), and the driving power of the inverter INV2 is smaller than the driving power of the inverter INV1.

[0111] In the semiconductor device 201, the waveform of the signal HVO is shaped into an undershoot waveform or an overshoot waveform by the de-emphasis circuit DE203, as shown in Fig. 7. Fig. 7 is a waveform diagram showing the operation of the semiconductor device 201.

[0112] Immediately before timing t21, the input signal VIN is at the L level, and the output signal OUT is at the L level.

[0113] In response to this, the de-emphasis circuit DE203 outputs a positive amplitude absolute value ΔV L The output circuit 30 generates a signal FB, which is a low level V, and feeds it back to the input node of the output circuit 30. At this time, the signal HVO before the feedback is at a low level V, which is indicated by a dotted line in FIG. L1 As shown by the solid line in FIG. 7, the output circuit 30 adds the fed back signal FB to the signal HVO before feedback, and adjusts the L level amplitude of the signal HVO to V L1 +ΔV L =V L1H The amplitude is attenuated to the L level V L1H , L level V L1 Compared to the above, the L level amplitude is raised toward the H level. H1 and L level V L1 The intermediate value is the reference value V R1 When the amplitude is attenuated, the L level V L1H The reference value V R1 The difference from H level V H1 The reference value V R1 The output circuit 30 outputs a low level V L1HThe output signal OUT is generated in response to the signal HVO.

[0114] At timing t21, the input signal VIN changes from the L level to the H level while the output signal OUT is maintained at the L level.

[0115] In response to this, in the differential amplifier circuit 210, the internal signal N_VINB becomes the H level V Hn From L level V Ln In the differential amplifier circuit 220, the internal signal P_VINB transitions to the H level V Hp From L level V Lp In response to these transitions, the signal HVO changes to the L level V L1H From H level V H1 Transition to.

[0116] At timing t22, while the input signal VIN is maintained at the H level, the output signal OUT transitions from the L level to the H level.

[0117] In response to this, the de-emphasis circuit DE203 outputs a negative amplitude absolute value ΔV H The output circuit 30 generates a signal FB, which is a high level V, and feeds it back to the input node of the output circuit 30. At this time, the signal HVO before the feedback is a high level V H1 As shown by the solid line in FIG. 7, the output circuit 30 adds the fed back signal FB to the signal HVO before feedback, and adjusts the H level amplitude of the signal HVO to V H1 -ΔV H =V H1L The amplitude is attenuated to H level V H1L is H level V H1 Compared to the H level, the H level amplitude is lowered toward the L level. H1 and L level V L1 The intermediate value is the reference value V R1 When the amplitude is attenuated, the H level V H1L The reference value V R1 The difference from H level V H1 The reference value V R1is smaller than the difference from . Therefore, the waveform of the signal HVO is shaped into an overshoot waveform by the de-emphasis circuit DE203. As a result, in relative terms, the slope of the signal HVO is made steeper during the level transition compared to after the level transition, and the slope of the output signal OUT generated by the output circuit 30 in response to the signal HVO during the level transition is also made steeper.

[0118] At timing t23, the input signal VIN changes from H level to L level while the output signal OUT is maintained at H level.

[0119] In response to this, in the differential amplifier circuit 210, the internal signal N_VINB becomes the L level V Ln From H level V Hn , and in the differential amplifier circuit 220, the internal signal P_VINB transitions to the L level V Lp From H level V Hp In response to these transitions, the signal HVO changes to the H level V H1L From L level V L1 Transition to.

[0120] At timing t24, while the input signal VIN is maintained at the L level, the output signal OUT transitions from the H level to the L level.

[0121] In response to this, the de-emphasis circuit DE203 outputs a positive amplitude absolute value ΔV L The output circuit 30 generates a signal FB, which is a low level V, and feeds it back to the input node of the output circuit 30. At this time, the signal HVO before the feedback is at a low level V, which is indicated by a dotted line in FIG. L1 As shown by the solid line in FIG. 7, the output circuit 30 adds the fed back signal FB to the signal HVO before feedback, and adjusts the L level amplitude of the signal HVO to V L1 +ΔV L =V L1H The amplitude is attenuated to the L level V L1H , L level V L1 Compared to the L level, the L level amplitude is raised toward the H level. L1 and H level V H1The intermediate value is the reference value V R1 When the amplitude is attenuated, the L level V L1H The reference value V R1 The difference from L level V L1 The reference value V R1 is smaller than the difference from . Therefore, the waveform of the signal HVO is shaped into an undershoot waveform by the de-emphasis circuit DE203. As a result, in relative terms, the slope of the signal HVO is made steeper during the level transition compared to after the level transition, and the slope of the output signal OUT generated by the output circuit 30 in response to the signal HVO during the level transition is also made steeper.

[0122] At timings t25 and t26, the same operations as those at timings t21 and t22 are performed.

[0123] At timings t27 and t28, the same operations as those at timings t23 and t24 are performed.

[0124] As shown in FIG. 5, the de-emphasis circuit DE203 reverses the polarity of the output signal OUT and feeds it back to the input node of the output circuit 30 as a signal FB. As a result, as shown in FIG. 7, the de-emphasis circuit DE203 can temporarily attenuate the H-level amplitude of the signal HVO generated by the transistors Tr4 and Tr15 of the transfer circuits TR1 and TR2 after the input signal VIN transitions from the L level to the H level. In addition, when the input signal VIN transitions from the H level to the L level thereafter, the driving force for transitioning the signal HVO from the H level to the L level can be temporarily increased. After the input signal VIN transitions from the H level to the L level, the de-emphasis circuit DE203 can temporarily attenuate the L-level amplitude of the signal HVO generated by the transistors Tr4 and Tr15 of the transfer circuits TR1 and TR2. In addition, when the input signal VIN transitions from the L level to the H level thereafter, the driving force for transitioning the signal HVO from the L level to the H level can be temporarily increased. As a result, the level transition of the signal HVO can be performed at high speed.

[0125] As described above, in the third embodiment, the de-emphasis circuit DE203 is added to the semiconductor device 201. The de-emphasis circuit DE203 attenuates the amplitude after a level transition, thereby shaping the waveform of the signal HVO, which is the source of generating the output signal OUT in the output circuit 30, into an undershoot waveform and an overshoot waveform. This makes it possible to speed up the transition of the signal level while suppressing the time-averaged amplitude, and to raise the operating frequency of the semiconductor device 201 with current efficiency. As a result, it is possible to achieve both suppression of power consumption and high speed.

[0126] (Fourth embodiment) Next, a semiconductor device according to a fourth embodiment will be described, focusing on the differences from the first to third embodiments.

[0127] In the fourth embodiment, the pre-emphasis circuits PE1 and PE2 of the first embodiment, the de-emphasis circuits DE101 and DE102 of the second embodiment, and the de-emphasis circuit DE203 of the third embodiment are combined.

[0128] Specifically, the semiconductor device 301 may be configured as shown in Fig. 8. Fig. 8 is a diagram showing the configuration of the semiconductor device 301. The semiconductor device 301 has a differential amplifier circuit 310, a differential amplifier circuit 320, and an output circuit 330 instead of the differential amplifier circuit 10, the differential amplifier circuit 20, and the output circuit 30 (see Fig. 1), and further has a de-emphasis circuit DE203. The differential amplifier circuit 310 has a de-emphasis circuit DE101 in addition to the pre-emphasis circuit PE1, and the differential amplifier circuit 320 has a de-emphasis circuit DE102 in addition to the pre-emphasis circuit PE2. The functions of the pre-emphasis circuits PE1 and PE2 are the same as those in the first embodiment, and the functions of the de-emphasis circuits DE101 and DE102 are the same as those in the second embodiment.

[0129] The de-emphasis circuit DE203 has an input node connected to node N8 instead of node N5 (see FIG. 5). Node N8 is a node between inverters INV1-1 and INV1-2 in output circuit 330. The de-emphasis circuit DE203 differs from the third embodiment in the number of inverters INV2-1 and INV2-2 it includes, but is similar to the third embodiment in that the total number of inverters INV1 and INV2 through which the feedback loop passes is an odd number. Therefore, the function of the de-emphasis circuit DE203 is similar to that of the third embodiment.

[0130] The inverter INV2-2 has an input node connected to the inverter INV2-1, and an output node connected to the drains of the transistors Tr4 and T15. The inverter INV2-1 has an input node connected to the node N8 between the inverters INV1-1 and INV1-2, and an output node connected to the inverter INV2-2.

[0131] The differential amplifier circuit 310 has a load circuit LD301 and an auxiliary circuit AS311 instead of the load circuit LD1 and the auxiliary circuit AS11 (see FIG. 1), and further has a voltage adjustment circuit VA301, a correction circuit CR301, a capacitance element C11, and a capacitance element C12.

[0132] The load circuit LD301 further includes a transistor Tr9 as a ninth transistor and a transistor Tr11 as an eleventh transistor in addition to the load circuit LD1 (see FIG. 1). The transistor Tr9 is connected in series to the transistor Tr8 and is diode-connected via the transistor Tr8. The transistor Tr11 is connected in series to the transistor Tr10 and is diode-connected via the transistor Tr10. The transistors Tr9 and Tr11 may each be configured as a PMOS transistor.

[0133] The transistor Tr9 has a gate connected to the gate of the transistor Tr10 and the drain of the transistor Tr8, a source connected to the power supply potential VCCQ, and a drain connected to the source of the transistor Tr8. The transistor Tr9 has a gate connected to the drain of the transistor Tr9 via the transistor Tr8 and is connected to the bias line NN via the node N1, and forms a current mirror circuit with the transistor Tr4.

[0134] The transistor Tr11 has a gate connected to the gate of the transistor Tr8 and the drain of the transistor Tr10, a source connected to the power supply potential VCCQ, and a drain connected to the source of the transistor Tr10. The transistor Tr11 has a gate connected to the drain of the transistor Tr11 via the transistor Tr10 and is connected to the bias line NNB via the node N2, and forms a current mirror circuit with the transistor Tr25.

[0135] The auxiliary circuit AS311 further includes a transistor Tr7 as a seventh transistor in addition to the auxiliary circuit AS11 (see FIG. 1). The transistors Tr6 and Tr7 are connected in series between the node N1 and the power supply potential VCCQ and in parallel with the transistors Tr8 and Tr9. The transistor Tr7 receives the input signal VIN at its gate, has a drain connected to the source of the transistor Tr6, and has a source connected to the power supply potential VCCQ.

[0136] That is, the transistor Tr9 is diode-connected itself and is diode-connected in parallel with the transistor Tr6. This allows the mirror ratio of the drain current of the transistor Tr4 to the drain current of the transistor Tr9 (current flowing from the load circuit LD301 side to the node N1) to be changed according to the level of the input signal VIN received by the gate of the transistor Tr7. This allows the amplification degree of the differential amplifier circuit 310 to be increased.

[0137] The potential adjustment circuit VA301 is connected to the node N6 and is configured to be able to adjust the potential of the node N6. The potential adjustment circuit VA301 has a control node connected to the bias line NN, an input node connected to the power supply potential VCCQ, and an output node connected to the node N6. This allows the potential adjustment circuit VA301 to adjust the potential of the node N6 according to the signal level of the bias line NN. The node N6 is an intermediate node in the auxiliary circuit AS311, and is connected to the drain of the transistor Tr7 and the source of the transistor Tr6.

[0138] The potential adjustment circuit VA301 includes a transistor Tr24. The transistor Tr24 is connected in parallel with the transistor Tr7 with respect to the source of the transistor Tr6. The transistor Tr24 is diode-connected via the transistor Tr6. The transistor Tr24 has a gate connected to the bias line NN, a source connected to the power supply potential VCCQ, and a drain connected to a node N6.

[0139] That is, the transistor Tr24 is diode-connected via the bias line NN and the transistor Tr6. As a result, the signal amplitude of the bias line NN is suppressed indirectly via the potential adjustment of the intermediate node N6 of the auxiliary circuit AS311. Therefore, the signal amplitude of the bias line NN can be suppressed more gently than when a diode-connected transistor (diode load) is directly connected to the bias line NN.

[0140] The correction circuit CR301 is connected to the non-inverting bias line NN and the inverting bias line NNB of the differential amplifier circuit 310, and shares the transfer circuit TR1 with the differential amplifier circuit 310, and is configured as a differential amplifier. The correction circuit CR301 has transistors Tr4, Tr25, Tr26, and Tr27. The gate of the transistor Tr25 is connected to the bias line NNB, the source is connected to the power supply potential VCCQ, and the drain is connected to the transistor Tr26. The gate of the transistor Tr26 is connected to the drain and is connected to the gate of the transistor Tr27, and forms a current mirror circuit with the transistor Tr27. The source of the transistor Tr26 is connected to the power supply potential. The source of the transistor Tr27 is connected to the power supply potential, and the drain is connected to the transistor Tr4.

[0141] In the correction circuit CR301, the noise components included in the signal transferred from the non-inverting bias line NN to the inverting input node and the noise components included in the signal transferred from the inverting bias line NNB to the non-inverting input node can have the same polarity and similar amplitude. As a result, the correction circuit CR301 takes the difference between the signal on the bias line NN and the signal on the bias line NNB, and supplies the differential signal VO1 with reduced noise components to the output circuit 330 and the control circuit 40.

[0142] One end of the capacitance element C11 is connected to the output node of the inverter INV3, and the other end is connected to the gate of the transistor Tr4 of the transfer circuit TR1 via the bias line NN. The loop including the transfer circuit TR1 → inverter INV3 → capacitance element C11 → bias line NN → transfer circuit TR1 constitutes a first feedback loop for performing feedback control on the differential amplifier circuit 310. The first feedback loop is DC-blocked by the capacitance element C11, that is, a DC-cut loop. Therefore, the first feedback control can be selectively performed when the level of the differential signal VO10 transferred from the transfer circuit TR1 transitions. This allows the potential level of the bias line NN to transition from H level to L level or from L level to H level at high speed while suppressing the influence on the potential amplitude of the bias line NN.

[0143] One end of the capacitance element C12 is connected to the output node of the inverter INV3, and the other end is connected to the gate of the transistor Tr27 of the correction circuit CR301. The loop including the transfer circuit TR1 → inverter INV3 → capacitance element C12 → transistor Tr27 → transfer circuit TR1 constitutes a second feedback loop for performing feedback control on the correction circuit CR301. The second feedback loop is DC-blocked by the capacitance element C12, that is, a DC-cut loop. Therefore, the second feedback control can be selectively performed when the level of the difference signal VO10 transferred from the transfer circuit TR1 transitions. This allows the potential level for reducing the noise component of the correction circuit CR301 to transition from H level to L level or from L level to H level at high speed.

[0144] The differential amplifier circuit 320 has a load circuit LD302 and an auxiliary circuit AS321 instead of the load circuit LD2 and the auxiliary circuit AS21 (see FIG. 1), and further has a voltage adjustment circuit VA302, a correction circuit CR302, a capacitance element C21, and a capacitance element C22.

[0145] The load circuit LD302 further includes a transistor Tr28 and a transistor Tr29 in addition to the load circuit LD2 (see FIG. 1). The transistor Tr28 is connected in series to the transistor Tr20 and is diode-connected via the transistor Tr20. The transistor Tr29 is connected in series to the transistor Tr21 and is diode-connected via the transistor Tr21. The transistors Tr28 and Tr29 may each be configured as an NMOS transistor.

[0146] The transistor Tr28 has a gate connected to the gate of the transistor Tr21 and the drain of the transistor Tr20, a source connected to the ground potential, and a drain connected to the source of the transistor Tr20. The transistor Tr28 has a gate connected to the drain of the transistor Tr28 via the transistor Tr20 and is connected to the bias line NP via the node N3, and forms a current mirror circuit with the transistor Tr15.

[0147] The transistor Tr29 has a gate connected to the gate of the transistor Tr20 and the drain of the transistor Tr21, a source connected to the ground potential, and a drain connected to the source of the transistor Tr21. The transistor Tr29 has a gate connected to the drain of the transistor Tr29 via the transistor Tr21 and is connected to the bias line NPB via the node N4, and forms a current mirror circuit with the transistor Tr31.

[0148] The auxiliary circuit AS321 further includes a transistor Tr22 in addition to the auxiliary circuit AS21 (see FIG. 1). The transistors Tr17 and Tr22 are connected in series between the node N3 and the ground potential and in parallel with the transistors Tr20 and Tr28. The transistor Tr22 receives the input signal VIN at its gate, has a drain connected to the source of the transistor Tr17, and has a source connected to the ground potential.

[0149] That is, the transistor Tr28 is diode-connected itself and is diode-connected in parallel with the transistor Tr17. This allows the mirror ratio of the drain current of the transistor Tr15 to the drain current of the transistor Tr28 (the current flowing from the node N3 to the load circuit LD302 side) to be changed according to the level of the input signal VIN received by the gate of the transistor Tr22. This allows the amplification degree of the differential amplifier circuit 320 to be increased.

[0150] The voltage adjustment circuit VA302 is connected to the node N7 and is configured to be able to adjust the potential of the node N7. The potential adjustment circuit VA302 has a control node connected to the bias line NP, an input node connected to the ground potential, and an output node connected to the node N7. This allows the potential adjustment circuit VA302 to adjust the potential of the node N7 according to the signal level of the bias line NP. The node N7 is an intermediate node in the auxiliary circuit AS321, and is connected to the drain of the transistor Tr22 and the source of the transistor Tr17.

[0151] The potential adjustment circuit VA302 includes a transistor Tr30. The transistor Tr30 is connected in parallel with the transistor Tr22 with respect to the source of the transistor Tr17. The transistor Tr30 is diode-connected via the transistor Tr17. The transistor Tr30 has a gate connected to the bias line NP, a source connected to the ground potential, and a drain connected to a node N7.

[0152] That is, the transistor Tr30 is diode-connected via the bias line NP and the transistor Tr17. As a result, the signal amplitude of the bias line NP is suppressed indirectly via the potential adjustment of the intermediate node N7 of the auxiliary circuit AS321. Therefore, the signal amplitude of the bias line NP can be suppressed more gently than when a diode-connected transistor (diode load) is directly connected to the bias line NP.

[0153] The correction circuit CR302 is connected to the non-inverting bias line NP and the inverting bias line NPB of the differential amplifier circuit 320, and shares the transfer circuit TR2 with the differential amplifier circuit 320, and is configured as a differential amplifier. The correction circuit CR302 has transistors Tr15, Tr31, Tr32, and Tr33. The transistor Tr31 has a gate connected to the bias line NPB, a source connected to the ground potential, and a drain connected to the transistor Tr32. The transistor Tr32 has a gate connected to the drain and is connected to the gate of the transistor Tr33, and forms a current mirror circuit with the transistor Tr33. The transistor Tr32 has a source connected to the power supply potential. The transistor Tr33 has a source connected to the power supply potential, and a drain connected to the transistor Tr15.

[0154] In the correction circuit CR302, the noise components included in the signal transferred from the non-inverting bias line NP to the inverting input node and the noise components included in the signal transferred from the inverting bias line NPB to the non-inverting input node can have the same polarity and similar amplitude. As a result, the correction circuit CR302 takes the difference between the signal on the bias line NP and the signal on the bias line NPB, and supplies the differential signal VO2 with reduced noise components to the output circuit 330 and the control circuit 40.

[0155] One end of the capacitance element C21 is connected to the output node of the inverter INV3, and the other end is connected to the gate of the transistor Tr15 of the transfer circuit TR2 via the bias line NP. The loop including the transfer circuit TR2 → inverter INV3 → capacitance element C21 → bias line NP → transfer circuit TR2 constitutes a third feedback loop for performing feedback control on the differential amplifier circuit 320. The third feedback loop is DC-blocked by the capacitance element C21, that is, a DC-cut loop. Therefore, the third feedback control can be selectively performed when the level of the differential signal VO20 transferred from the transfer circuit TR2 transitions. This allows the potential level of the bias line NP to transition from H level to L level or from L level to H level at high speed while suppressing the influence on the potential amplitude of the bias line NP.

[0156] One end of the capacitance element C22 is connected to the output node of the inverter INV3, and the other end is connected to the gate of the transistor Tr33 of the correction circuit CR302. The loop including the transfer circuit TR2 → inverter INV3 → capacitance element C22 → transistor Tr33 → transfer circuit TR2 constitutes a fourth feedback loop for performing feedback control on the correction circuit CR302. The fourth feedback loop is DC-blocked by the capacitance element C22, that is, a DC-cut loop. Therefore, the fourth feedback control can be selectively performed when the level of the difference signal VO20 transferred from the transfer circuit TR2 transitions. This allows the potential level for reducing the noise component of the correction circuit CR302 to transition from H level to L level or from L level to H level at high speed.

[0157] The output circuit 330 receives the signal HVO from the differential amplifier circuit 310 and the differential amplifier circuit 320. The output circuit 330 generates and outputs an output signal OUT in response to the signal HVO using a power supply voltage VCCQ and a power supply voltage VDDC. The level of the power supply voltage VDDC is different from the level of the power supply voltage VCCQ, and can be set to be lower than the level of the power supply voltage VCCQ, for example.

[0158] The output circuit 330 has a processing circuit 331, a level shifter 332, and a processing circuit 333. The processing circuit 331 receives the signal HVO from the differential amplifier circuit 310 and the differential amplifier circuit 320, and supplies it to the level shifter 332. The level shifter 332 shifts the level of the signal HVO and supplies it to the processing circuit 333. The processing circuit 333 generates and outputs an output signal OUT that corresponds to the level-shifted signal HVO.

[0159] The processing circuit 331 has a plurality of inverters INV1-1 and INV1-2. The plurality of inverters INV1-1 and INV1-2 are similar to the plurality of inverters INV1-1 and INV1-2 of the first embodiment. The level shifter 332 has an inverter INV1-3 and inverters INV4-1 to INV4-3. The series connection of the inverter INV1-3 and inverter INV4-1 and the series connection of the inverter INV4-2 and inverter INV4-3 are connected in parallel to each other between the processing circuit 331 and the processing circuit 333. The processing circuit 333 has a plurality of inverters INV4-4 and INV4-5. The INV1-1 to INV1-3 operate using a power supply voltage VCCQ, and the INV4-1 to INV4-5 operate using a power supply voltage VDDC.

[0160] As described above, in the fourth embodiment, in the semiconductor device 301, the pre-emphasis circuits PE1 and PE2 and the de-emphasis circuits DE101 and DE102 shape the waveforms of the internal signals of the differential amplifier circuits 310 and 320 into undershoot and overshoot waveforms. The de-emphasis circuit DE203 shapes the waveform of the signal HVO, which is synthesized from the difference signals VO10 and VO20 of the differential amplifier circuits 310 and 320, into an undershoot and overshoot waveform. This makes it possible to speed up the transition of the signal level while suppressing the time-averaged amplitude, and to raise the operating frequency of the semiconductor device 301 with current efficiency. As a result, it is possible to achieve both suppression of power consumption and high speed.

[0161] Fifth embodiment Next, a semiconductor device according to a fifth embodiment will be described, focusing on the differences from the first to fourth embodiments.

[0162] In the fourth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a single-input / single-output circuit, but in the fifth embodiment, the combination thereof is realized in a single-input / differential-output circuit.

[0163] Specifically, the semiconductor device 401 receives an input signal VIN as a single input, and outputs output signals OUT and OUTB as differential outputs. The output signals OUT and OUTB form a differential pair with each other.

[0164] The semiconductor device 401 can be configured as shown in Fig. 9. Fig. 9 is a diagram showing the configuration of the semiconductor device 401. The semiconductor device 401 has a differential amplifier circuit 410 and a differential amplifier circuit 420 instead of the differential amplifier circuit 310 and the differential amplifier circuit 320 (see Fig. 8), and further has an output circuit 430, a de-emphasis circuit DE403, and a control circuit 440.

[0165] The differential amplifier circuit 410 has an auxiliary circuit AS412 instead of the auxiliary circuit AS12 (see FIG. 8), and further has a pre-emphasis circuit PE401, a de-emphasis circuit DE401, a transfer circuit TR401, a potential adjustment circuit VA401, and a correction circuit CR401. The differential amplifier circuit 420 has an auxiliary circuit AS422 instead of the auxiliary circuit AS22 (see FIG. 8), and further has a pre-emphasis circuit PE402, a de-emphasis circuit DE402, a transfer circuit TR402, a potential adjustment circuit VA402, and a correction circuit CR402.

[0166] The transfer circuit TR401 receives an internal signal via a bias line NNB, and generates and outputs a differential signal VOB10 in response to the internal signal.

[0167] The transfer circuit TR402 receives an internal signal via a bias line NPB, and generates and outputs a differential signal VOB20 in response to the internal signal.

[0168] Control circuit 440 receives signal HVOB from differential amplifier circuit 410 and differential amplifier circuit 420. Control circuit 440 uses power supply voltage VCCQ to generate signal HVOBN corresponding to signal HVOB, and feeds it back to pre-emphasis circuit PE401 and de-emphasis circuit DE401 of differential amplifier circuit 410 and to pre-emphasis circuit PE402 and de-emphasis circuit DE402 of differential amplifier circuit 20, respectively.

[0169] The pre-emphasis circuit PE401 is configured similarly to the pre-emphasis circuit PE1, except that it receives a reference signal VREF instead of the input signal VIN. The pre-emphasis circuit PE401 shapes the waveform of the internal signal of the differential amplifier circuit 410 into an undershoot waveform by emphasizing the amplitude at the time of level transition. This allows the slope of the signal HVOB at the time of level transition to be made steeper.

[0170] The de-emphasis circuit DE401 is configured similarly to the de-emphasis circuit DE1, except that it receives the signal HVOBN instead of the signal HVON. The de-emphasis circuit DE401 attenuates the amplitude after a level transition to shape the waveform of the internal signal of the differential amplifier circuit 410 into an undershoot waveform. This allows the slope of the signal HVOB during the level transition to be made steeper.

[0171] The pre-emphasis circuit PE402 is configured similarly to the pre-emphasis circuit PE2, except that it receives a reference signal VREF instead of the input signal VIN. The pre-emphasis circuit PE402 shapes the waveform of the internal signal of the differential amplifier circuit 420 into an overshoot waveform by emphasizing the amplitude at the time of level transition. This allows the slope of the signal HVOB at the time of level transition to be made steeper.

[0172] The de-emphasis circuit DE402 is configured similarly to the de-emphasis circuit DE2, except that it receives the signal HVOBN instead of the signal HVON. The de-emphasis circuit DE402 attenuates the amplitude after a level transition to shape the waveform of the internal signal of the differential amplifier circuit 420 into an overshoot waveform. This allows the slope of the signal HVOB during the level transition to be made steeper.

[0173] The auxiliary circuit AS412 is configured similarly to the auxiliary circuit AS311, except that it receives a reference signal VREF instead of the input signal VIN and is connected to a bias line NNB instead of the bias line NN. The auxiliary circuit AS412 can change the mirror ratio of the current transferred from the load circuit LD301 to the transfer circuit TR401 via the bias line NNB in ​​response to the level of the reference signal VREF.

[0174] The auxiliary circuit AS422 is configured similarly to the auxiliary circuit AS321, except that it receives a reference signal VREF instead of the input signal VIN and is connected to a bias line NPB instead of the bias line NP. The auxiliary circuit AS422 can change the mirror ratio of the current transferred from the load circuit LD302 to the transfer circuit TR402 via the bias line NPB in response to the level of the reference signal VREF.

[0175] The potential adjustment circuit VA401 is connected to the node N9 and is configured to be able to adjust the potential of the node N9, thereby enabling the potential adjustment circuit VA401 to gently suppress the signal amplitude of the bias line NNB.

[0176] The potential adjustment circuit VA402 is connected to the node N10 and is configured to be able to adjust the potential of the node N10, so that the potential adjustment circuit VA402 can gently suppress the signal amplitude of the bias line NNB.

[0177] The correction circuit CR401 is connected to the non-inverting bias line NN and the inverting bias line NNB of the differential amplifier circuit 410, and shares the transfer circuit TR401 with the differential amplifier circuit 410. The correction circuit CR401 is composed of a differential amplifier. The correction circuit CR401 takes the difference between the signal of the bias line NN and the signal of the bias line NNB, and supplies a differential signal VOB10 with reduced noise components to the output circuit 430 and the control circuit 440.

[0178] The correction circuit CR402 is connected to the non-inverting bias line NP and the inverting bias line NPB of the differential amplifier circuit 420, and is configured as a differential amplifier, sharing the transfer circuit TR402 with the differential amplifier circuit 420. The correction circuit CR402 takes the difference between the signal of the bias line NP and the signal of the bias line NPB, and supplies the differential signal VOB20, in which noise components have been reduced, to the output circuit 430 and the control circuit 440.

[0179] The output circuit 430 is configured similarly to the output circuit 330, except that the input node is connected to transfer circuits TR401 and TR402 instead of the transfer circuits TR1 and TR2 (see FIG. 8). The output circuit 430 receives the signal HVOB from the differential amplifier circuit 410 and the differential amplifier circuit 420, and generates and outputs the output signal OUTB according to the signal HVOB. The output signal OUTB forms a differential pair together with the output signal OUT.

[0180] As described above, in the fifth embodiment, in the semiconductor device 401, the combination of the pre-emphasis circuits PE1, PE401, PE2, and PE402 and the de-emphasis circuits DE101, DE401, DE102, DE402, DE203, and DE403 can be realized by a single-input, differential-output circuit.

[0181] Sixth embodiment Next, a semiconductor device according to the sixth embodiment will be described, focusing on the differences from the first to fifth embodiments.

[0182] In the fourth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a single-input / single-output circuit, but in the sixth embodiment, the combination is realized in a differential-input / single-output circuit.

[0183] Specifically, the semiconductor device 501 receives input signals VIN and VINB as differential inputs and outputs an output signal OUT as a single output. The input signals VIN and VINB form a differential pair with each other.

[0184] The semiconductor device 501 can be configured as shown in Fig. 10. Fig. 10 is a diagram showing the configuration of the semiconductor device 501. The semiconductor device 501 has a differential amplifier circuit 510 and a differential amplifier circuit 520 instead of the differential amplifier circuit 310 and the differential amplifier circuit 320 (see Fig. 8), and further has a control circuit 540.

[0185] The differential amplifier circuit 510 has an auxiliary circuit AS512 instead of the auxiliary circuit AS12 (see FIG. 8), and further has a pre-emphasis circuit PE501, a de-emphasis circuit DE401, a potential adjustment circuit VA401, and a discharge circuit DIS501. The differential amplifier circuit 520 has an auxiliary circuit AS522 instead of the auxiliary circuit AS22 (see FIG. 8), and further has a pre-emphasis circuit PE502, a de-emphasis circuit DE402, a potential adjustment circuit VA402, and a discharge circuit DIS502.

[0186] The control circuit 540 is disposed between the control circuit 40 and the differential amplifier circuit 510 and the differential amplifier circuit 520. The control circuit 540 receives the signal HVON from the control circuit 40, generates a signal HVONB by logically inverting the signal HVON, and feeds the signal HVONB back to the pre-emphasis circuit PE501 and the de-emphasis circuit DE401 of the differential amplifier circuit 510 and the pre-emphasis circuit PE502 and the de-emphasis circuit DE402 of the differential amplifier circuit 520, respectively.

[0187] The pre-emphasis circuit PE501 is configured similarly to the pre-emphasis circuit PE1, except that it receives the input signal VINB instead of the input signal VIN. The pre-emphasis circuit PE501 shapes the waveform of the internal signal of the differential amplifier circuit 510 into an undershoot waveform by emphasizing the amplitude at the time of the level transition. This allows the slope of the signal HVOB at the time of the level transition to be made steeper.

[0188] The de-emphasis circuit DE401 is configured similarly to the de-emphasis circuit DE1, except that it receives the signal HVONB instead of the signal HVON. The de-emphasis circuit DE401 attenuates the amplitude after a level transition to shape the waveform of the internal signal of the differential amplifier circuit 510 into an undershoot waveform. This allows the slope of the signal HVOB during the level transition to be made steeper.

[0189] The auxiliary circuit AS512 is configured similarly to the auxiliary circuit AS311, except that it receives an input signal VINB instead of the input signal VIN and is connected to a bias line NNB instead of the bias line NN. The auxiliary circuit AS512 can change the mirror ratio of the current transmitted from the load circuit LD301 to the correction circuit CR301 via the bias line NNB in ​​accordance with the level of the input signal VINB.

[0190] The potential adjustment circuit VA401 is connected to the node N9 and is configured to be able to adjust the potential of the node N9, thereby enabling the potential adjustment circuit VA401 to gently suppress the signal amplitude of the bias line NNB.

[0191] The discharge circuit DIS501 includes a transistor Tr101, a transistor Tr102, and a current source CS1. The transistors Tr101 and Tr102 form a differential pair. The transistors Tr101 and Tr102 may each be configured as an NMOS transistor. The drains of the transistors Tr101 and Tr102 are electrically connected to the gates and the nodes N1 and N2, respectively, and the sources are electrically connected to one end of the current source CS1. The discharge circuit DIS501 discharges the charges of the nodes N1 and N2 in accordance with the potentials of the nodes N1 and N2 (e.g., potentials higher than a threshold voltage).

[0192] The pre-emphasis circuit PE502 is configured similarly to the pre-emphasis circuit PE2, except that it receives the input signal VINB instead of the input signal VIN. The pre-emphasis circuit PE502 shapes the waveform of the internal signal of the differential amplifier circuit 520 into an overshoot waveform by emphasizing the amplitude at the time of the level transition. This allows the slope of the signal HVOB at the time of the level transition to be made steeper.

[0193] The de-emphasis circuit DE402 is configured similarly to the de-emphasis circuit DE2, except that it receives the signal HVONB instead of the signal HVON. The de-emphasis circuit DE402 attenuates the amplitude after the level transition to shape the waveform of the internal signal of the differential amplifier circuit 520 into an overshoot waveform. This allows the slope of the signal HVOB during the level transition to be made steeper.

[0194] The auxiliary circuit AS522 is configured similarly to the auxiliary circuit AS321, except that it receives an input signal VINB instead of the input signal VIN and is connected to a bias line NPB instead of the bias line NP. The auxiliary circuit AS522 can change the mirror ratio of the current transmitted from the load circuit LD302 to the correction circuit CR302 via the bias line NPB in accordance with the level of the input signal VINB.

[0195] The potential adjustment circuit VA402 is connected to the node N10 and is configured to be able to adjust the potential of the node N10, so that the potential adjustment circuit VA402 can gently suppress the signal amplitude of the bias line NNB.

[0196] The discharge circuit DIS502 has a transistor Tr103, a transistor Tr104, and a current source CS2. The transistors Tr103 and Tr104 form a differential pair. The transistors Tr103 and Tr104 may each be formed of a PMOS transistor. The drains of the transistors Tr103 and Tr104 are electrically connected to the gates and nodes N3 and N4, respectively, and the sources are electrically connected to one end of the current source CS2. The discharge circuit DIS502 discharges the charges of the nodes N3 and N4 in accordance with the potentials of the nodes N3 and N4 (for example, potentials higher than a threshold voltage).

[0197] As described above, in the sixth embodiment, in the semiconductor device 501, the combination of the pre-emphasis circuits PE1, PE501, PE2, and PE502 and the de-emphasis circuits DE101, DE401, DE102, DE402, and DE203 can be realized by a differential input / single output circuit.

[0198] Seventh embodiment Next, a semiconductor device according to the seventh embodiment will be described, focusing on the differences from the first to sixth embodiments.

[0199] In the fourth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a single-input / single-output circuit, but in the seventh embodiment, the combination thereof is realized in a differential-input / differential-output circuit.

[0200] Specifically, the semiconductor device 601 receives input signals VIN and VINB as differential inputs and outputs output signals OUT and OUTB as differential outputs. The input signals VIN and VINB form a differential pair. The output signals OUT and OUTB form a differential pair.

[0201] The semiconductor device 601 can be configured as shown in Fig. 11. Fig. 11 is a diagram showing the configuration of the semiconductor device 601. The semiconductor device 601 has a differential amplifier circuit 610 and a differential amplifier circuit 620 instead of the differential amplifier circuit 410 and the differential amplifier circuit 420 (see Fig. 9).

[0202] The differential amplifier circuit 610 has a pre-emphasis circuit PE501 and an auxiliary circuit AS512 instead of the pre-emphasis circuit PE401 and the auxiliary circuit AS412 (see FIG. 9).

[0203] The pre-emphasis circuit PE501 is configured similarly to the pre-emphasis circuit PE1, except that it receives the input signal VINB instead of the input signal VIN. The pre-emphasis circuit PE501 shapes the waveform of the internal signal of the differential amplifier circuit 510 into an undershoot waveform by emphasizing the amplitude at the time of the level transition. This allows the slope of the signal HVOB at the time of the level transition to be made steeper.

[0204] The auxiliary circuit AS512 is configured similarly to the auxiliary circuit AS311, except that it receives an input signal VINB instead of the input signal VIN and is connected to a bias line NNB instead of the bias line NN. The auxiliary circuit AS512 can change the mirror ratio of the current transmitted from the load circuit LD301 to the correction circuit CR301 via the bias line NNB in ​​accordance with the level of the input signal VINB.

[0205] The differential amplifier circuit 620 has a pre-emphasis circuit PE502 and an auxiliary circuit AS522 instead of the pre-emphasis circuit PE402 and the auxiliary circuit AS422 (see FIG. 9).

[0206] The pre-emphasis circuit PE502 is configured similarly to the pre-emphasis circuit PE2, except that it receives the input signal VINB instead of the input signal VIN. The pre-emphasis circuit PE502 shapes the waveform of the internal signal of the differential amplifier circuit 520 into an overshoot waveform by emphasizing the amplitude at the time of the level transition. This allows the slope of the signal HVOB at the time of the level transition to be made steeper.

[0207] The auxiliary circuit AS522 is configured similarly to the auxiliary circuit AS321, except that it receives an input signal VINB instead of the input signal VIN and is connected to a bias line NPB instead of the bias line NP. The auxiliary circuit AS522 can change the mirror ratio of the current transmitted from the load circuit LD302 to the correction circuit CR302 via the bias line NPB in accordance with the level of the input signal VINB.

[0208] As described above, in the seventh embodiment, in the semiconductor device 601, the combination of the pre-emphasis circuits PE1, PE501, PE2, and PE502 and the de-emphasis circuits DE101, DE401, DE102, DE402, DE203, and DE403 can be realized by a differential input / differential output circuit.

[0209] Eighth embodiment Next, a semiconductor device according to the eighth embodiment will be described, focusing on the differences from the first to seventh embodiments.

[0210] In the fourth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a single-input, single-output circuit using two differential amplifier circuits with inverted polarity, but in the eighth embodiment, this combination is realized in a single-input, single-output circuit using a differential amplifier circuit on one side (receiving an N-type transistor).

[0211] Specifically, the semiconductor device 701 can be configured as shown in Fig. 12. Fig. 12 is a diagram showing the configuration of the semiconductor device 701. The semiconductor device 701 is configured by omitting the differential amplifier circuit 320 from the semiconductor device 301 (see Fig. 8). The differential amplifier circuit 310 receives the input signal VIN via an N-type input transistor Trin1, and is an N-type transistor-receiving differential amplifier circuit.

[0212] Similar to the fourth embodiment, the pre-emphasis circuit PE1 and the de-emphasis circuit DE101 shape the waveform of the internal signal of the differential amplifier circuit 310 into an undershoot waveform, and the de-emphasis circuit DE203 shapes the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0213] As described above, in the eighth embodiment, in the semiconductor device 701, the combination of the pre-emphasis circuit PE1 and the de-emphasis circuits DE101 and DE203 can be realized by a single-input single-output circuit using a differential amplifier circuit receiving N-type transistors.

[0214] Ninth embodiment Next, a semiconductor device according to a ninth embodiment will be described, focusing on the differences from the first to eighth embodiments.

[0215] In the fourth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a single-input, single-output circuit using two differential amplifier circuits with inverted polarity, but in the ninth embodiment, the combination is realized in a single-input, single-output circuit using a differential amplifier circuit on one side (receiving a P-type transistor).

[0216] Specifically, the semiconductor device 801 can be configured as shown in Fig. 13. Fig. 13 is a diagram showing the configuration of the semiconductor device 801. The semiconductor device 801 is configured by omitting the differential amplifier circuit 310 from the semiconductor device 301 (see Fig. 8). The differential amplifier circuit 320 receives the input signal VIN via a P-type input transistor Trin3, and is a P-type transistor-receiving differential amplifier circuit.

[0217] Similar to the fourth embodiment, the pre-emphasis circuit PE2 and the de-emphasis circuit DE102 shape the waveform of the internal signal of the differential amplifier circuit 320 into an undershoot waveform, and the de-emphasis circuit DE203 shapes the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0218] As described above, in the ninth embodiment, in the semiconductor device 801, the combination of the pre-emphasis circuit PE2 and the de-emphasis circuits DE102 and DE203 can be realized by a single-input single-output circuit using a differential amplifier circuit receiving a P-type transistor.

[0219] (Tenth embodiment) Next, a semiconductor device according to a tenth embodiment will be described below, focusing on the differences from the first to ninth embodiments.

[0220] In the fifth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a single-input, differential-output circuit using two differential amplifier circuits with inverted polarity, but in the tenth embodiment, the combination is realized in a single-input, differential-output circuit using a differential amplifier circuit on one side (receiving an N-type transistor).

[0221] Specifically, the semiconductor device 901 can be configured as shown in Fig. 14. Fig. 14 is a diagram showing the configuration of the semiconductor device 901. The semiconductor device 901 is configured by omitting the differential amplifier circuit 420 from the semiconductor device 401 (see Fig. 9). The differential amplifier circuit 410 receives the input signal VIN via an N-type input transistor Trin1, and is an N-type transistor-receiving differential amplifier circuit.

[0222] Similar to the fifth embodiment, the pre-emphasis circuits PE1, PE401 and the de-emphasis circuits DE101, DE401 shape the waveform of the internal signal of the differential amplifier circuit 310 into an undershoot waveform, and the de-emphasis circuits DE203, DE403 shape the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0223] As described above, in the tenth embodiment, in the semiconductor device 901, the combination of the pre-emphasis circuits PE1 and PE401 and the de-emphasis circuits DE101, DE401, DE203 and DE403 can be realized by a single input / differential output circuit using an N-type transistor-receiving differential amplifier circuit.

[0224] (Eleventh embodiment) Next, a semiconductor device according to an eleventh embodiment will be described, focusing on the differences from the first to tenth embodiments.

[0225] In the fifth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a single-input, differential-output circuit using two differential amplifier circuits with inverted polarity, but in the eleventh embodiment, the combination is realized in a single-input, differential-output circuit using a differential amplifier circuit on one side (receiving a P-type transistor).

[0226] Specifically, the semiconductor device 1001 can be configured as shown in Fig. 15. Fig. 15 is a diagram showing the configuration of the semiconductor device 1001. The semiconductor device 1001 is configured by omitting the differential amplifier circuit 410 from the semiconductor device 401 (see Fig. 9). The differential amplifier circuit 420 receives the input signal VIN via a P-type input transistor Trin3, and is a P-type transistor-receiving differential amplifier circuit.

[0227] Similar to the fifth embodiment, the pre-emphasis circuits PE2 and PE402 and the de-emphasis circuits DE102 and DE402 shape the waveform of the internal signal of the differential amplifier circuit 420 into an undershoot waveform, and the de-emphasis circuits DE203 and DE403 shape the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0228] As described above, in the eleventh embodiment, in the semiconductor device 1001, the combination of the pre-emphasis circuits PE2 and PE402 and the de-emphasis circuits DE102, DE402, DE203 and DE403 can be realized by a single input / differential output circuit using a differential amplifier circuit receiving a P-type transistor.

[0229] (Twelfth embodiment) Next, a semiconductor device according to a twelfth embodiment will be described, focusing on the differences from the first to eleventh embodiments.

[0230] In the sixth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a differential input / single output circuit using two differential amplifier circuits with inverted polarity, but in the twelfth embodiment, this combination is realized in a differential input / single output circuit using a differential amplifier circuit on one side (receiving an N-type transistor).

[0231] Specifically, the semiconductor device 1101 can be configured as shown in Fig. 16. Fig. 16 is a diagram showing the configuration of the semiconductor device 1101. The semiconductor device 1101 is configured by omitting the differential amplifier circuit 520 from the semiconductor device 501 (see Fig. 10). The differential amplifier circuit 510 receives the input signal VIN via an N-type input transistor Trin1, and is an N-type transistor-receiving differential amplifier circuit.

[0232] Similar to the sixth embodiment, the pre-emphasis circuits PE1 and PE501 and the de-emphasis circuits DE101 and DE401 shape the waveform of the internal signal of the differential amplifier circuit 510 into an undershoot waveform, and the de-emphasis circuit DE203 shapes the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0233] As described above, in the twelfth embodiment, in the semiconductor device 1101, the combination of the pre-emphasis circuits PE1, PE501 and the de-emphasis circuits DE101, DE401, DE203 can be realized by a differential input / single output circuit using an N-type transistor-receiving differential amplifier circuit.

[0234] Thirteenth embodiment Next, a semiconductor device according to a thirteenth embodiment will be described, focusing on the differences from the first to twelfth embodiments.

[0235] In the sixth embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized in a differential input / single output circuit using two differential amplifier circuits with inverted polarity, but in the thirteenth embodiment, this combination is realized in a differential input / single output circuit using a differential amplifier circuit on one side (receiving a P-type transistor).

[0236] Specifically, the semiconductor device 1201 can be configured as shown in Fig. 17. Fig. 17 is a diagram showing the configuration of the semiconductor device 1201. The semiconductor device 1201 is configured by omitting the differential amplifier circuit 510 from the semiconductor device 501 (see Fig. 10). The differential amplifier circuit 520 receives the input signal VIN at a P-type input transistor Trin3, and is a P-type transistor-receiving differential amplifier circuit.

[0237] Similar to the sixth embodiment, the pre-emphasis circuits PE2 and PE502 and the de-emphasis circuits DE102 and DE402 shape the waveform of the internal signal of the differential amplifier circuit 520 into an undershoot waveform, and the de-emphasis circuit DE203 shapes the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0238] As described above, in the thirteenth embodiment, in the semiconductor device 1201, the combination of the pre-emphasis circuits PE2 and PE502 and the de-emphasis circuits DE102, DE402 and DE203 can be realized by a differential input / single output circuit using a differential amplifier circuit receiving P-type transistors.

[0239] (Fourteenth embodiment) Next, a semiconductor device according to a fourteenth embodiment will be described below, focusing on the differences from the first to thirteenth embodiments.

[0240] In the seventh embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized by a differential input / differential output circuit using two differential amplifier circuits with inverted polarity, but in the fourteenth embodiment, the combination is realized by a differential input / differential output circuit using a differential amplifier circuit on one side (receiving an N-type transistor).

[0241] Specifically, the semiconductor device 1301 can be configured as shown in Fig. 18. Fig. 18 is a diagram showing the configuration of the semiconductor device 1301. The semiconductor device 1301 is configured by omitting the differential amplifier circuit 620 from the semiconductor device 601 (see Fig. 11). The differential amplifier circuit 610 receives the input signal VIN via an N-type input transistor Trin1, and is an N-type transistor-receiving differential amplifier circuit.

[0242] As in the seventh embodiment, the pre-emphasis circuits PE1, PE501 and the de-emphasis circuits DE101, DE401 shape the waveform of the internal signal of the differential amplifier circuit 610 into an undershoot waveform, and the de-emphasis circuits DE203, DE403 shape the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0243] As described above, in the fourteenth embodiment, in the semiconductor device 1301, the combination of the pre-emphasis circuits PE1 and PE501 and the de-emphasis circuits DE101, DE401, DE203 and DE403 can be realized by a differential input / differential output circuit using a differential amplifier circuit receiving N-type transistors.

[0244] Fifteenth embodiment Next, a semiconductor device according to a fifteenth embodiment will be described, focusing on the differences from the first to fourteenth embodiments.

[0245] In the seventh embodiment, the combination of the pre-emphasis circuit and the de-emphasis circuit is realized by a differential input / differential output circuit using two differential amplifier circuits with inverted polarity, whereas in the fifteenth embodiment, the combination is realized by a differential input / differential output circuit using a differential amplifier circuit on one side (receiving a P-type transistor).

[0246] Specifically, the semiconductor device 1401 can be configured as shown in Fig. 19. Fig. 19 is a diagram showing the configuration of the semiconductor device 1401. The semiconductor device 1401 is configured by omitting the differential amplifier circuit 610 from the semiconductor device 601 (see Fig. 11). The differential amplifier circuit 620 receives the input signal VIN at a P-type input transistor Trin3, and is a P-type transistor-receiving differential amplifier circuit.

[0247] As in the seventh embodiment, the pre-emphasis circuits PE2 and PE502 and the de-emphasis circuits DE102 and DE402 shape the waveform of the internal signal of the differential amplifier circuit 620 into an undershoot waveform, and the de-emphasis circuits DE203 and DE403 shape the waveform of the signal HVO into an undershoot waveform and an overshoot waveform.

[0248] As described above, in the fifteenth embodiment, in the semiconductor device 1401, the combination of the pre-emphasis circuits PE2 and PE502 and the de-emphasis circuits DE102, DE402, DE203 and DE403 can be realized by a differential input / differential output circuit using a differential amplifier circuit receiving P-type transistors.

[0249] Sixteenth embodiment Next, a semiconductor device according to the sixteenth embodiment will be described, focusing on the differences from the first to fifteenth embodiments.

[0250] In the third embodiment, the operating point of the de-emphasis circuit DE203 is not particularly limited. As a result, the amplitude attenuation amount ΔV of the signal HVO after the level transition by the de-emphasis circuit DE203 is L ,ΔV H (See FIG. 7) may vary depending on environmental conditions such as power supply voltage and temperature.

[0251] Therefore, in the sixteenth embodiment, the operating point of the de-emphasis circuit DE1503 is synchronized with the differential amplifier circuits 210 and 220 to operate the de-emphasis circuit DE1503 while suppressing the influence of fluctuations due to environmental conditions, and the attenuation amount ΔVL ,ΔV H We aim to stabilize the level of

[0252] Specifically, the semiconductor device 1501 may be configured as shown in FIG. 20. FIG. 20 is a diagram showing the configuration of the semiconductor device 1501. The semiconductor device 1501 has a de-emphasis circuit DE1503 instead of the de-emphasis circuit DE203 (see FIG. 5). The de-emphasis circuit DE1503 has an inverter INV2a instead of the inverter INV2 (see FIG. 5). The inverter INV2a has an input node connected to the node N5, an output node connected to the drains of the transistors Tr4 and Tr15, a first control node connected to the node N2 of the differential amplifier circuit 210, and a second control node connected to the node N4 of the differential amplifier circuit 220.

[0253] The inverter INV2a has a plurality of N-type transistors NM21, NM22 and a plurality of P-type transistors PM21, PM22. The transistor NM21 is connected between the transistor PM21 and the transistor NM22, and the transistor PM21 is connected between the transistor PM22 and the transistor NM21. The transistor NM22 is connected between the transistor NM21 and the ground potential, and the transistor PM22 is connected between the power supply potential VCCQ and the transistor PM21. The transistors NM21 and PM21 are inverter-connected.

[0254] The transistor NM22 has a source connected to the ground potential, a drain connected to the transistor NM21, and a gate connected to a node N4 of the differential amplifier circuit 220. The transistor NM22 is turned on to activate the transistors NM21 and PM21 during a period when the internal signal P_VREFB of the differential amplifier circuit 220 is at an active level (for example, an H level), and is turned off to inactivate the transistors NM21 and PM21 during a period when the internal signal P_VREFB is at a non-active level (for example, an L level).

[0255] The transistor PM22 has a source connected to a power supply potential VCCQ, a drain connected to the transistor PM21, and a gate connected to a node N2 of the differential amplifier circuit 210. The transistor PM22 is turned on to activate the transistors NM21 and PM21 during a period when the internal signal N_VREFB of the differential amplifier circuit 210 is at an active level (for example, an L level), and is turned off to inactivate the transistors NM21 and PM21 during a period when the internal signal N_VREFB is at a non-active level (for example, an H level).

[0256] Such operation of the transistors NM22 and PM22 makes it possible to synchronize the operating point of the inverter INV2a of the de-emphasis circuit DE1503 with the differential amplifier circuits 210 and 220.

[0257] For example, when the transistor Tr15 is strongly turned on in response to the internal signal P_VINB, the transistor PM22 is strongly turned on in response to the internal signal N_VREFB, and the H-level amplitude of the signal HVO is attenuated by an amount ΔV H When the transistor Tr4 is strongly turned on in response to the internal signal N_VINB, the transistor NM22 is strongly turned on in response to the internal signal P_VREFB, and the H-level amplitude of the signal HVO is attenuated by an attenuation amount ΔV L Attenuate with.

[0258] The on-strength of each of the transistors NM22 and PM22 is determined by the driving force of the differential amplifier circuits 210 and 220. Therefore, regardless of the environmental conditions, the amplitude attenuation amount ΔV L ,ΔV H It is easy to stabilize the level.

[0259] As described above, in the sixteenth embodiment, in the semiconductor device 1501, the operating point of the de-emphasis circuit DE1503 is synchronized with the differential amplifier circuits 210 and 220. This makes it possible to operate the de-emphasis circuit DE1503 while suppressing the influence of fluctuations due to environmental conditions, and the attenuation amount ΔV L ,ΔV H The level of can be stabilized.

[0260] (Seventeenth embodiment) Next, a semiconductor device according to the seventeenth embodiment will be described, focusing on the differences from the first to sixteenth embodiments.

[0261] In the sixteenth embodiment, the transistors NM22 and PM22 of the de-emphasis circuit DE1503 are strongly turned on, but in the seventeenth embodiment, the strength at which the transistors NM22 and PM22 are turned on is further adjusted to adjust the attenuation amount ΔV L ,ΔV H We aim to achieve a high level of precision.

[0262] Specifically, the semiconductor device 1601 can be configured as shown in Fig. 21. Fig. 21 is a diagram showing the configuration of the semiconductor device 1601. The semiconductor device 1601 has a differential amplifier circuit 1610, a differential amplifier circuit 1620, and a de-emphasis circuit DE1603 instead of the differential amplifier circuit 210, the differential amplifier circuit 220, and the de-emphasis circuit DE1503 (see Fig. 20).

[0263] The differential amplifier circuit 1610 has a transfer circuit TR1601 instead of the transfer circuit TR1. The transfer circuit TR1601 further has a transistor Tr34. The transistor Tr34 may be configured as a PMOS transistor. The gate of the transistor Tr34 is connected to the auxiliary circuit AS11 via a bias line NN. The drain of the transistor Tr34 is connected to the de-emphasis circuit DE1603, and the source is connected to the power supply potential VCCQ.

[0264] The differential amplifier circuit 1620 has a transfer circuit TR1602 instead of the transfer circuit TR2. The transfer circuit TR1602 further has a transistor Tr35. The transistor Tr35 may be configured as a PMOS transistor. The transistor Tr35 has a gate connected to the auxiliary circuit AS21 via a bias line NP. The transistor Tr35 has a drain connected to the de-emphasis circuit DE1603 and a source connected to the ground potential.

[0265] The de-emphasis circuit DE1603 has an inverter INV2b instead of the inverter INV2a (see FIG. 20). The inverter INV2b has an input node connected to the node N5, an output node connected to the drains of the transistors Tr4 and Tr15, a first control node connected to the drain of the transistor Tr35, and a second control node connected to the drain of the transistor Tr34.

[0266] The inverter INV2b has a plurality of N-type transistors NM21 to NM23 and a plurality of P-type transistors PM21 to PM23.

[0267] The transistor NM23 has a source connected to the ground potential, a drain connected to the drain of the transistor Tr34, and a gate connected to the drain and the gate of the transistor NM22. The transistors NM22 and NM23 form a current mirror circuit.

[0268] This current mirror circuit supplies a current, which is a copy of the drain current of transistor Tr34 according to the mirror ratio, to the drain side of transistor NM21. That is, the amount of current supplied to the gate of transistor NM22 can be adjusted according to the driving force of differential amplifier circuit 1610 and the mirror ratio of the current mirror circuit, and the strength of transistor NM22 being turned on can be adjusted. The mirror ratio of the current mirror circuit can be adjusted by changing the ratio between the dimensions of transistor NM23 and transistor NM22.

[0269] The transistor PM23 has a source connected to the power supply potential VCCQ, a drain connected to the drain of the transistor Tr35, and a gate connected to the drain and the gate of the transistor PM22. The transistors PM22 and PM23 form a current mirror circuit.

[0270] This current mirror circuit supplies a current, which is a copy of the drain current of transistor Tr35 according to the mirror ratio, to the drain side of transistor PM21. That is, the amount of current supplied to transistor PM22 can be adjusted according to the driving force of differential amplifier circuit 1620 and the mirror ratio of the current mirror circuit, and the strength of turning on transistor PM22 can be adjusted. The mirror ratio of the current mirror circuit can be adjusted by changing the ratio between the dimensions of transistor PM23 and transistor PM22.

[0271] As in the sixteenth embodiment, the operating point of the inverter INV2b in the de-emphasis circuit DE1603 can be synchronized with the differential amplifier circuits 1610 and 1620 by the operations of the transistors NM22 and PM22.

[0272] As described above, in the seventeenth embodiment, in the semiconductor device 1601, the strength at which the transistors NM22 and PM22 are turned on is adjusted in accordance with the driving force of the differential amplifier circuits 1610 and 1620 and the mirror ratio of the current mirror circuit including the transistors NM22 and PM22. As a result, the attenuation amount ΔV L ,ΔV H The level of precision can be improved.

[0273] (Eighteenth embodiment) Next, a semiconductor device according to the eighteenth embodiment will be described, focusing on the differences from the first to seventeenth embodiments.

[0274] In the seventeenth embodiment, the operating point of the de-emphasis circuit DE 1603 is synchronized with the differential amplifier circuits 1610 and 1620 , but in the eighteenth embodiment, the operating point of the de-emphasis circuit DE 1703 is slightly delayed with respect to the differential amplifier circuits 1610 and 1620 .

[0275] Specifically, the semiconductor device 1701 can be configured as shown in Fig. 22. Fig. 22 is a diagram showing the configuration of the semiconductor device 1701. The semiconductor device 1701 has a de-emphasis circuit DE1703 instead of the de-emphasis circuit DE1603 (see Fig. 21).

[0276] The de-emphasis circuit DE1703 has an inverter INV2c instead of the inverter INV2b (see FIG. 21). The inverter INV2c further has a resistive element R1 and a resistive element R2.

[0277] One end of the resistor R1 is connected to the gate of the transistor NM23, and the other end is connected to the gate of the transistor NM22. The transistors PM22, PM23, and the resistor R1 form a current mirror circuit. This current mirror circuit supplies a current, which is a copy of the drain current of the transistor Tr34 according to the mirror ratio, to the drain side of the transistor NM21 with a timing delayed by the resistor R1.

[0278] This makes it possible to slightly delay the timing until the de-emphasis circuit DE1703 attenuates the H-level amplitude after the signal HVO transitions from L level to H level. This makes it possible to secure a longer overshoot period when the de-emphasis circuit DE1703 shapes the waveform of the signal HVO into an overshoot waveform, and makes it easy to stabilize the H-level amplitude before attenuation. This is effective in securing the amplitude when, for example, the H-level amplitude of the signal HVO is small.

[0279] One end of the resistor R2 is connected to the gate of the transistor PM23, and the other end is connected to the gate of the transistor PM22. The transistors NM22 and NM23 and the resistor R2 form a current mirror circuit. This current mirror circuit supplies a current, which is a copy of the drain current of the transistor Tr35 according to the mirror ratio, to the drain side of the transistor PM21 with a timing delayed by the resistor R2.

[0280] This makes it possible to slightly delay the timing until the de-emphasis circuit DE1703 attenuates the L-level amplitude after the signal HVO transitions from H level to L level. This makes it possible to secure a longer undershoot period when the de-emphasis circuit DE1703 shapes the waveform of the signal HVO into an undershoot waveform, and makes it easy to stabilize the L-level amplitude before attenuation. This is effective in securing the amplitude when, for example, the L-level amplitude of the signal HVO is small.

[0281] As described above, in the eighteenth embodiment, in the semiconductor device 1701, the operating point of the de-emphasis circuit DE1703 is slightly delayed with respect to the differential amplifier circuits 1610 and 1620. This makes it possible to easily stabilize the amplitude of the signal HVO when the de-emphasis circuit DE1703 shapes the waveform of the signal HVO into an overshoot waveform and an undershoot waveform.

[0282] (19th embodiment) Next, a semiconductor device according to a nineteenth embodiment will be described, focusing on the differences from the first to eighteenth embodiments.

[0283] In the eighteenth embodiment, the configuration of the de-emphasis circuit DE1703 for delaying the operating point is realized using an inverter, but in the nineteenth embodiment, it is realized without using an inverter.

[0284] Specifically, the semiconductor device 1801 can be configured as shown in Fig. 23. Fig. 23 is a diagram showing the configuration of the semiconductor device 1801. The semiconductor device 1801 has de-emphasis circuits DE1803 and DE1804 instead of the de-emphasis circuit DE1703 (see Fig. 22). The de-emphasis circuits DE1803 and DE1804 are configured by omitting the transistors NM21 and PM21 as an inverter configuration from the de-emphasis circuit DE1703 and isolating the two current mirror circuits from each other. This allows the delay amount of the operating point of the de-emphasis circuits DE1803 and DE1804 to be determined regardless of the delay time of the inverter configuration.

[0285] The de-emphasis circuit DE1803 includes transistors NM22 and NM23 and a resistor element R1. The transistors NM22 and NM23 and the resistor element R1 form a current mirror circuit. This current mirror circuit supplies a current, which is a copy of the drain current of the transistor Tr34 according to its mirror ratio, to the input node of the output circuit 30 at a timing delayed by the resistor element R1. This allows a slight delay in the timing until the de-emphasis circuit DE1803 attenuates the H-level amplitude after the signal HVO transitions from the L-level to the H-level. At this time, the delay amount of the operating point of the de-emphasis circuit DE1803 with respect to the differential amplifier circuits 1610 and 1620 is adjusted by the resistance value of the resistor element R1.

[0286] The de-emphasis circuit DE1804 includes transistors PM22 and PM23 and a resistor element R2. The transistors PM22 and PM23 and the resistor element R2 form a current mirror circuit. This current mirror circuit supplies a current, which is a copy of the drain current of the transistor Tr35 according to its mirror ratio, to the input node of the output circuit 30 at a timing delayed by the resistor element R2. This allows a slight delay in the timing until the de-emphasis circuit DE1804 attenuates the L level amplitude after the signal HVO transitions from H level to L level. At this time, the delay amount of the operating point of the de-emphasis circuit DE1804 with respect to the differential amplifier circuits 1610 and 1620 is adjusted by the resistance value of the resistor element R2.

[0287] As described above, in the 19th embodiment, in the semiconductor device 1801, the delay amount of the operating point of the de-emphasis circuits DE1803 and DE1804 relative to the differential amplifier circuits 1610 and 1620 is adjusted by the resistance values ​​of the resistive elements R1 and R2. This makes it possible to improve the accuracy of the delay amount of the operating point of the de-emphasis circuits DE1803 and DE1804.

[0288] Next, a memory system 1000 to which the semiconductor device according to the first to nineteenth embodiments is applied will be described with reference to Fig. 24. Fig. 24 is a diagram showing a configuration of the memory system 1000 to which the semiconductor device according to the first to nineteenth embodiments is applied.

[0289] The memory system 1000 can be connected to a host 2000 and can function as an external storage medium of the host 2000. The host 2000 is, for example, a personal computer, and the memory system 1000 is, for example, an SSD. The memory system 1000 has a controller 1100, a semiconductor memory 1200, and a power supply circuit 1300. The controller 1100 is a hardware circuit, and has a host interface circuit (host I / F) 1110, a signal processing circuit 1120, and a memory interface circuit (memory I / F) 1130. The power supply circuit 1300 generates a plurality of types of power supply voltages (for example, power supply voltages VCCQ, VDDC, etc.) and supplies them to each unit in the memory system 1000.

[0290] For example, the semiconductor memory 1200 has the semiconductor device 1b as a receiver. The memory I / F 1130 receives a predetermined signal from the signal processing circuit 1120 and transfers it to the semiconductor device 1b. The semiconductor device 1b operates using the power supply circuit 1300 (e.g., power supply voltages VCCQ, VDDC, etc.) received from the power supply circuit 1300, and receives the signal transferred from the memory I / F 1130. The semiconductor device 1b supplies the received signal to the semiconductor memory 1200.

[0291] Such signals may be single-ended signals such as, for example, write data, a reference potential, a chip select signal (CE), a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (WE), a write protect signal (WP), etc. In this case, the semiconductor device 1b can be any of the semiconductor devices according to the first to fifth embodiments, the eighth to eleventh embodiments, and the sixteenth to nineteenth embodiments.

[0292] Alternatively, such a signal may be, for example, a differential signal such as a data strobe signal (DQS / BDQS) during writing, a read enable signal (RE / BRE), etc. In this case, the semiconductor device 1b may be any of the semiconductor devices according to the sixth embodiment, the seventh embodiment, and the twelfth to fifteenth embodiments.

[0293] The memory I / F 1130 has the semiconductor device 1a as a receiver. The semiconductor memory 1200 transfers a predetermined signal to the semiconductor device 1a. The semiconductor device 1a operates using a power supply circuit 1300 (e.g., power supply voltages VCCQ, VDDC, etc.) received from the power supply circuit 1300, and receives the signal transferred from the semiconductor memory 1200. The semiconductor device 1a supplies the received signal to the signal processing circuit 112.

[0294] Such a signal may be, for example, a single-ended signal such as read data, a ready / busy signal (R / B), etc. In this case, the semiconductor device 1a may be any of the semiconductor devices according to the first to fifth embodiments, the eighth to eleventh embodiments, and the sixteenth to nineteenth embodiments.

[0295] Alternatively, such a signal may be a differential signal such as a data strobe signal (DQS / BDQS) during reading. In this case, the semiconductor device 1a may be any of the semiconductor devices according to the sixth embodiment, the seventh embodiment, and the twelfth to fifteenth embodiments.

[0296] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0297] 1,101,201,301,401,501,601,701,801,901,1001,1101,1201,1301,1401,1501,1601,1701,1801 Semiconductor device, 10,20,110,120,210,220,310,320,410,420,510,520,610,620,1610,1620 Differential amplifier circuit, DE101,DE102,DE203,DE401,DE402,DE403,DE1503,DE1603,DE1703,DE1803,DE1804 De-emphasis circuit, PE1,PE2,PE401,PE402,PE501,PE502, Pre-emphasis circuit.

Claims

1. A first differential amplifier circuit is provided, The first differential amplifier circuit comprises: a load circuit in which the gates and drains of a first load transistor and a second load transistor are cross-coupled; a first input transistor having a drain connected to the drain of the first load transistor and receiving a first input signal at its gate; a second input transistor having a drain connected to the drain of the second load transistor and receiving a reference signal at its gate; a first current source connected between a source of the first input transistor and a ground potential and a source of the second input transistor; a pre-emphasis circuit connected in parallel to the first current source; a current mirror circuit that transfers an output of the load circuit; a control circuit that inverts an output of the current mirror circuit to generate a control signal; an output circuit for generating an output signal corresponding to an output of the current mirror circuit; Equipped with The pre-emphasis circuit includes: a first transistor connected in parallel with the first current source to a source of the first input transistor and a source of the second input transistor, the first transistor receiving the first input signal at its gate; a second transistor connected between the first transistor and a ground potential and receiving the control signal at its gate; having The current mirror circuit includes: a third transistor connected between the first input transistor and a power supply potential; a fourth transistor connected between a power supply potential and the output circuit, forming a current mirror circuit together with the third transistor; have Semiconductor device.

2. The current mirror circuit comprises: a fifth transistor connected between the third transistor and a power supply potential and receiving the control signal at its gate; The semiconductor device according to claim 1 .

3. a third inverter connected between the drain of the fourth transistor and the gate of the second transistor to generate the control signal; The semiconductor device according to claim 1 .

4. a third inverter connected between the drain of the fourth transistor and the gate of the second transistor to generate the control signal; The first differential amplifier circuit comprises: a capacitance element having one end connected to the output node of the third inverter and the other end connected to the gate of the fourth transistor; The semiconductor device according to claim 1 .

5. The device further includes a second differential amplifier circuit having a polarity inverted from that of the first differential amplifier circuit, The second differential amplifier circuit comprises: a second load circuit in which the gates and drains of the third load transistor and the fourth load transistor are cross-coupled; a third input transistor having a drain connected to the drain of the third load transistor and receiving the first input signal at its gate; a fourth input transistor having a drain connected to the drain of the fourth load transistor and receiving a reference signal at its gate; a second current source connected between a source of the third input transistor and a ground potential and a source of the fourth input transistor; a second pre-emphasis circuit connected in parallel to the first current source; a second current mirror circuit that transfers an output of the second load circuit; a second control circuit that inverts an output of the second current mirror circuit to generate a second control signal; Equipped with The second pre-emphasis circuit includes: a twelfth transistor connected in parallel with the second current source to the source of the third input transistor and the source of the fourth input transistor, the twelfth transistor receiving the first input signal at its gate; a thirteenth transistor connected between the twelfth transistor and a ground potential, the thirteenth transistor receiving the second control signal at its gate; having The second current mirror circuit includes: a fourteenth transistor connected between the third input transistor and a ground potential; a fifteenth transistor connected between a ground potential and the output circuit and constituting a current mirror circuit together with the fourteenth transistor; having The output circuit generates the output signal according to the output of the current mirror circuit and the output of the second current mirror circuit. The semiconductor device according to claim 1 .

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