Low noise quadrature signal generation

Abstract

A quadrature clock generator is disclosed. The quadrature clock generator can include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator can generate a first plurality of clock signals from a first reference clock signal. The phase interpolator can generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator can generate the second plurality of clock signals from the second reference clock signal. The first quadrature clock signal can be selected from the first plurality of clock signals, and the second quadrature clock signal can be selected from the second plurality of reference clock signals.

Description

[Technical field]

[0001] Aspects of the present disclosure relate generally to oscillators, and more particularly, to oscillators configured to generate quadrature clock signals. [Background technology]

[0002] Many wireless and wired communication systems employ quadrature amplitude modulation (QAM) transceivers to transmit and receive data. Many QAM transceivers include a quadrature clock signal generator to provide in-phase (I) and quadrature (Q) clock signals used to modulate or encode transmitted data and to demodulate or decode received data. Phase mismatch between the I and Q clock signals can result in I / Q mismatch impairments in transmitted and received signals, which in turn can cause signal degradation and data errors. Because I / Q phase mismatch can be related to clock frequency, it becomes increasingly important to minimize I / Q phase mismatch as clock frequencies increase, for example, in multi-gigabit SERial / DESerial (SERDES)-based communications. Summary of the Invention

[0003] This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Moreover, the systems, methods, and devices of the present disclosure each have several innovative aspects, no single aspect of which is solely responsible for the desirable attributes disclosed herein.

[0004] One innovative aspect of the subject matter described in this disclosure can be used to reduce phase mismatch between an in-phase (I) clock signal and a quadrature (Q) clock signal in a quadrature clock generator. In some embodiments, the quadrature clock generator can include a first injection locked oscillator, a configured second injection locked oscillator, a first selection circuit, a second selection circuit, and a phase interpolator. The first injection locked oscillator can be configured to generate a plurality of first clock signals based at least in part on a first reference clock signal. The first selection circuit can be coupled to the first injection locked oscillator and configured to select one of the first clock signals as a transmit quadrature clock signal. The phase interpolator can be coupled to the first injection locked oscillator and configured to generate a second reference clock signal based on the plurality of first clock signals. The second injection locked oscillator can be configured to generate a plurality of second clock signals based at least in part on a second reference clock signal. A second selection circuit coupled to the second injection-locked oscillator and configured to select one of the second clock signals as the receive quadrature clock signal.

[0005] Another innovative aspect of the subject matter described in this disclosure can be implemented in a programmable logic device. In some embodiments, the programmable logic device can include a transmit data processing block, a receive data processing block, and a quadrature clock generator. The transmit data processing block can be configured to transmit data using a transmit quadrature signal, and the receive data processing block can be configured to receive data using a receive quadrature signal. The quadrature clock generator can be coupled to the transmit data processing block and to the receive data processing block and can include a first injection locked oscillator, a first selection circuit, a phase interpolator, a second injection locked oscillator, and a second selection circuit. The first injection locked oscillator can be configured to generate a plurality of first clock signals based at least in part on a first reference clock signal. The first selection circuit can be configured to select one of the first clock signals as a transmit quadrature clock signal. The phase interpolator can be coupled to the first injection locked oscillator and configured to generate a second reference clock signal based on a selected pair of the first clock signals. The second injection-locked oscillator can be configured to generate a plurality of second clock signals based at least in part on the second reference clock signal, and the second selection circuit can be configured to select one of the second clock signals as the receive quadrature clock signal.

[0006] Another innovative aspect of the subject matter described in this disclosure may be implemented as a method for operating a quadrature clock generator. In some embodiments, the method may include generating a plurality of first clock signals based at least in part on a first reference clock signal, selecting one of the plurality of first clock signals as a transmit quadrature clock signal, generating a second reference clock signal based at least in part on the plurality of first clock signals, generating a plurality of second clock signals based at least in part on the second reference clock signal, and selecting one of the plurality of second clock signals as a receive quadrature clock signal.

[0007] Other non-limiting examples of aspects of the subject matter described in this disclosure are provided below.

[0008] Example 1: A quadrature clock generator including: a first injection locked oscillator configured to generate a plurality of first clock signals based at least in part on a first reference clock signal; a first selection circuit coupled to the first injection locked oscillator and configured to select one of the first clock signals as a transmit quadrature clock signal; a phase interpolator coupled to the first injection locked oscillator and configured to generate a second reference clock signal based on a selected pair of the first clock signals; a second injection locked oscillator configured to generate a plurality of second clock signals based at least in part on the second reference clock signal; and a second selection circuit coupled to the second injection locked oscillator and configured to select one of the second clock signals as a receive quadrature clock signal.

[0009] Example 2: The quadrature clock generator of example 1, wherein the transmit quadrature clock signal includes a first in-phase (I) component and a first quadrature (Q) component, and the receive quadrature clock signal includes a second I component and a second Q component.

[0010] Example 3: The quadrature clock generator of example 1, wherein a transmit quadrature clock signal is provided to a transmit data processing block of an associated programmable device, and a receive quadrature clock signal is provided to a receive data processing block of an associated programmable device.

[0011] Example 4: The quadrature clock generator of Example 3, wherein the phase interpolator is configured to generate the second reference clock signal based at least in part on the input signal provided by the receive data processing block.

[0012] Example 5: The quadrature clock generator of example 1, wherein each of the plurality of first clock signals are offset in phase from one another by 45 degrees, and each of the plurality of second clock signals are offset in phase from one another by 45 degrees.

[0013] Example 6: The quadrature clock generator of example 1, wherein the first injection-locked oscillator, the phase interpolator, and the second injection-locked oscillator are controlled, at least in part, by a reference voltage.

[0014] Example 7: The quadrature clock generator of Example 6, further including a quadrature locked loop (QLL) configured to generate a control signal based at least in part on the plurality of second clock signals, and a voltage regulator configured to generate a reference voltage based at least in part on the control signal.

[0015] Example 8: The quadrature clock generator of Example 7, further comprising a coarse frequency tracking circuit configured to selectively disable the control signal based at least in part on detecting a wake-up condition.

[0016] Example 9: The quadrature clock generator of example 8, wherein the voltage regulator is configured to control the oscillation frequencies of the first injection locked oscillator and the second injection locked oscillator before quadrature lock is established during the sensed start-up condition.

[0017] Example 10: The quadrature clock generator of Example 1, wherein the first injection locked oscillator is controlled, at least in part, by a first reference voltage, and the phase interpolator and the second injection locked oscillator are controlled, at least in part, by a second reference voltage.

[0018] Example 11: The quadrature clock generator of example 10, further including a first quadrature locked loop (QLL) configured to generate a first control signal based at least in part on the plurality of first clock signals, a first voltage regulator configured to generate a first reference voltage based at least in part on the first control signal, a second QLL configured to generate a second control signal based at least in part on the plurality of second clock signals, and a second voltage regulator configured to generate a second reference voltage based at least in part on the second control signal.

[0019] Example 12: The quadrature clock generator of Example 11, further comprising a coarse frequency tracking circuit configured to selectively disable the first and second control signals based at least in part on detecting a wake-up condition.

[0020] Example 13: A programmable logic device including a transmit data processing block configured to transmit data using a transmit quadrature clock signal, a receive data processing block configured to receive data using a receive quadrature clock signal, and a quadrature clock generator coupled to the transmit data processing block and to the receive data processing block, wherein the quadrature clock generator includes a first injection locked oscillator configured to generate a plurality of first clock signals based at least in part on a first reference clock signal, a first selection circuit configured to select one of the first clock signals as the transmit quadrature clock signal, a phase interpolator coupled to the first injection locked oscillator and configured to generate a second reference clock signal based on a selected pair of the first clock signals, a second injection locked oscillator configured to generate a plurality of second clock signals based at least in part on the second reference clock signal, and a second selection circuit configured to select one of the second clock signals as the receive quadrature clock signal.

[0021] Example 14: The programmable logic device of example 13, wherein the first injection locked oscillator, the phase interpolator, and the second injection locked oscillator are controlled, at least in part, by a reference voltage.

[0022] Example 15: The programmable logic device of Example 14, further including a quadrature locked loop (QLL) configured to generate a control signal based at least in part on the plurality of second clock signals, and a voltage regulator configured to generate a reference voltage based at least in part on the control signal.

[0023] Example 16: The programmable logic device of Example 15, further comprising a coarse frequency tracking circuit configured to selectively disable the control signal based at least in part on detecting a wake-up condition.

[0024] Example 17: A method for operating a quadrature clock generator, the method including: generating a plurality of first clock signals based at least in part on a first reference clock signal; selecting one of the plurality of first clock signals as a transmit quadrature clock signal; generating a second reference clock signal based at least in part on the plurality of first clock signals; generating a plurality of second clock signals based at least in part on the second reference clock signal; and selecting one of the plurality of second clock signals as a receive quadrature clock signal.

[0025] Example 18: The method of example 17, wherein the second reference clock signal is generated by interpolating between a pair of the first clock signals.

[0026] Example 19: The method of example 17, wherein the second reference clock signal is generated based at least in part on an input signal from the receive data processing block.

[0027] Example 20: The method of example 17, wherein each of the plurality of first clock signals is offset by 45 degrees from a corresponding second clock signal of the plurality of second clock signals.

[0028] Exemplary embodiments described herein are illustrated by way of example and not by way of limitation in the accompanying drawing figures. Like numbers refer to like elements throughout the drawings and specification. It should be noted that the relative dimensions of the figures below may not be drawn to scale. [Brief description of the drawings]

[0029] [Figure 1] FIG. 1 is a block diagram of an example programmable device in which aspects of the present disclosure may be implemented. [Diagram 2] 1 is a simplified block diagram of a transceiver in accordance with some embodiments. [Diagram 3]1 is a block diagram of an example quadrature clock generator in accordance with some implementations. [Figure 4A] 1 is a block diagram of another example quadrature clock generator in accordance with some implementations. [Figure 4B] FIG. 13 is a block diagram of another exemplary quadrature clock generator according to other embodiments. [Figure 5A] 1 is a block diagram of another example quadrature clock generator in accordance with some implementations. [Figure 5B] FIG. 13 is a block diagram of another exemplary quadrature clock generator according to other embodiments. [Figure 6] 5 is an exemplary flowchart illustrating example operations for operating a quadrature clock generator in accordance with some implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Aspects of the present disclosure can be used to reduce or minimize I / Q mismatch and other phase errors that can degrade signal integrity in wired and wireless communications. In some embodiments, a quadrature clock generator is disclosed that utilizes two injection-locked oscillators and a single phase interpolator to generate a first set of in-phase (I) and quadrature (Q) clock signals and a second set of I and Q clock signals. The first and second sets of I and Q clock signals can be phase shifted relative to each other and used to transmit and receive data. By using a single phase interpolator rather than multiple phase interpolators, aspects of the present disclosure can reduce phase mismatch compared to conventional quadrature clock generators.

[0031] In the following description, many specific details are given, such as examples of specific components, circuits, and processes, to provide a thorough understanding of the disclosure. The term "coupled" as used herein means directly coupled or coupled through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific terminology and / or details are given to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that these specific details may not be required to practice the exemplary embodiments. In other examples, well-known circuits and devices are shown in block diagram form to avoid obscuring the disclosure. Any of the signals provided through the various buses described herein can be time-multiplexed with other signals and provided through one or more common buses. In addition, the interconnects between circuit elements or software blocks can be shown as buses or as single signal lines. Each of those buses can alternatively be single signal lines, each of those single signal lines can alternatively be buses, and the single line or bus can represent any one or more of the myriad physical or logical mechanisms for communication between components. The exemplary embodiments should not be construed as being limited to the specific examples described herein, but rather will include within their scope all embodiments defined by the appended claims.

[0032] FIG. 1 illustrates a block diagram of an exemplary programmable device 100 in which aspects of the disclosure may be implemented. In some embodiments, device 100 may be formed on a single die. In other embodiments, device 100 may be distributed across multiple dies. Additionally or alternatively, device 100 may be implemented as a system-on-a-chip (SoC) that includes several subsystems that may interact with one another. Thus, the programmable device 100 shown in FIG. 1 is an illustrative example of a programmable device in which aspects of the disclosure may be implemented, and other embodiments with additional or fewer blocks or modules in similar or different arrangements are possible.

[0033] Device 100 may include several subsystems, such as, for example, programmable logic (PL) 110, network-on-chip (NoC) interconnect system 120, dedicated circuitry 130, CCIX and PCIe module (CPM) 140, connectivity fabric 145, transceiver 150, input / output (I / O) block 160, and memory controller 170. In one or more embodiments, device 100 may include other subsystems or components not shown in FIG. 1. Additionally, although not shown for simplicity, device 100 may be coupled to several peripheral components (such as one or more high performance memory devices 195) and / or other devices or chips (such as another programmable device).

[0034] PL 110 includes circuitry that can be programmed to perform a number of different user-defined functions or operations. In some embodiments, PL 110 can include an array of programmable circuit blocks or tiles, each including programmable interconnect circuitry and programmable logic circuitry. The programmable circuit blocks can include configurable logic blocks (CLBs), random access memory blocks (BRAMs), digital signal processing blocks (DSPs), clock managers, delay-locked loops (DLLs), and / or other logic or circuitry that can be programmed or configured to implement a user-specified circuit design. Additionally or alternatively, PL 110 can include a number of input / output blocks (IOBs). In one or more embodiments, PL 110 can be implemented as an array of programmable fabric subregions (FSRs) that can be distributed throughout the programmable fabric. In some embodiments, the FSRs can be implemented within the programmable fabric as repeatable tiles.

[0035] The programmable interconnect circuitry can include multiple interconnect wires of variable length interconnected by programmable interconnect points (PIPs). The interconnect wires can be configured to provide connectivity between components within a particular programmable tile, between components within separate programmable tiles, and between components of a programmable tile and other subsystems or devices. The programmable interconnect circuitry and the programmable circuit blocks can be programmed or configured by loading configuration data into configuration registers that define how the programmable elements are configured to operate to implement a corresponding user-specified circuit design. In some aspects, the programmable interconnect circuitry within each of several programmable circuit blocks can form part of a programmable interconnect fabric that provides block-level and / or device-level signal routing resources for device 100.

[0036] Each CLB may include look-up tables (LUTs), flip-flops, combinatorial logic, and / or programmable interconnect circuitry that may be collectively programmed by configuration data to perform various logical functions (such as addition and subtraction) on input signals of varying widths. The LUTs may be of any suitable size and may include any suitable number of inputs and outputs. In some embodiments, each CLB may include 32 LUTs and 64 flip-flops. Each of the CLBs may also include arithmetic carry logic and multiplexers that may be used to implement wider logical functions. In some embodiments, the resources of the PL 110 may be implemented as repeatable tiles that are arranged in multiple columns in the programmable device 100 and may be divided into several regions of fixed height and width. With respect to the example of FIG. 1, the PL 110 is shown as occupying separate regions of the device 100. In other embodiments, the PL 110 may be implemented as a unified region of the programmable fabric.

[0037] NoC interconnect system 120, which may be fabricated as part of device 100, provides a high-speed, high-bandwidth programmable signal routing network that may selectively interconnect various resources, subsystems, circuits, and other components of device 100. In some embodiments, NoC interconnect system 120 may extend horizontally and vertically (e.g., toward the edge) across the programmable fabric of device 100, as shown in FIG. 1. Additionally or alternatively, NoC interconnect system 120 may extend in one or more diagonal directions across the programmable fabric. Moreover, while shown in the example of FIG. 1 as having a single column, in other embodiments, NoC interconnect system 120 may include multiple columns that extend vertically across the height of the programmable fabric. Thus, the particular layout, shape, size, orientation, and other physical characteristics of the exemplary NoC interconnect system 120 are merely illustrative of various implementations disclosed herein.

[0038] In some embodiments, the NoC interconnect system 120 may employ a data packet protocol and memory-mapped addresses to route information as packetized data between various resources, subsystems, circuits, and other components of the device 100. The data packets may include source addresses, destination addresses, and protocol information that may be used by the NoC interconnect system 120 to route the data packets to their indicated destinations. In one or more embodiments, the data packets may include quality of service (QoS) information that allows the transmission of the data packets through the NoC interconnect system 120 to be prioritized based on, for example, assigned priority, traffic type, and / or flow information. In such embodiments, the NoC interconnect system 120 may include priority logic that may identify a priority level or traffic class of a received data packet and use the identified priority level or traffic class when queuing the data packet for transmission.

[0039] Although not shown for simplicity, the NoC interconnect system 120 may also include a scheduler and arbitration logic. The scheduler may be used to schedule transmission of data packets from source addresses to destination addresses using one or more physical and / or virtual channels of the NoC interconnect system 120. The arbitration logic may be used to arbitrate access to the NoC interconnect system 120, for example, to minimize collisions and other contention-related latencies. For embodiments in which the device 100 is fabricated using stacked silicon interconnect (SSI) technology, the columnar portions of the NoC interconnect system 120 may provide signal connections between adjacent super logic regions (SLRs), for example, to allow configuration data to be routed between a master SLR and a slave SLR.

[0040] In some embodiments, NoC interconnect system 120 may include multiple nodes, ports, or other interfaces (not shown for simplicity) that provide selective connectivity between NoC interconnect system 120 and various resources, subsystems, circuits, and other components of device 100. For example, NoC interconnect system 120 may enable multiple subsystems of device 100 to share access to on-chip memory (OCM) resources, processing resources, and / or I / O resources. By selectively interconnecting various resources, subsystems, circuits, and other components of device 100 that may require and use large amounts of data, NoC interconnect system 120 may reduce the burden of signal routing on local interconnect resources, thereby increasing device performance and allowing greater configuration flexibility than other programmable devices. Moreover, by providing a high-performance signal routing network having higher data transmission rates and lower error rates than device-level and block-level programmable interconnects, the NoC interconnect system 120 can increase the processing power and data throughput of the device 100 (compared to other programmable devices).

[0041] The dedicated circuitry 130 may include any suitable hardwired circuitry, including, but not limited to, a processor, a serial transceiver, a digital signal processor (DSP), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), device management resources, device monitoring resources, device testing management resources, and the like. In some embodiments, the dedicated circuitry 130 may include a processing system (PS) and a platform management controller (PMC). In some embodiments, the PS may include several processor cores, cache memory, and one-way and / or two-way interfaces that may be configured to directly couple to I / O pins of the device 100. In some embodiments, each processor core may include a central processing unit (CPU) or a scalar processor that may be used for sequential data processing. The PMC may be used to boot and configure the device 100 based on configuration data (such as a configuration bitstream) provided from an external memory. The PMC may also be used to configure the PL 110, as well as to control various encryption, authentication, system monitoring, and debug functions of the device 100.

[0042] CCIX and PCIe module (CPM) 140 may include several interfaces that provide connectivity between device 100 and several peripheral components (such as external devices or chips). In some embodiments, CPM 140 may include several Peripheral Interconnect Express (PCIe) interfaces and a Cache Coherent Interconnect for Accelerators (CCIX) interface that provide connectivity to other devices or chips via transceiver 150. In some aspects, the PCIe and CCIX interfaces may be implemented as part of transceiver 150.

[0043] A programmable interconnect fabric (not shown for simplicity) can provide block-level and / or device-level signal routing resources that can selectively interconnect circuits and subsystems in nearby regions of the programmable fabric based on configuration data loaded into corresponding configuration registers. In some embodiments, the programmable interconnect fabric can include multiple fabric sub-regions (FSRs), which can be implemented as repeatable tiles and distributed throughout device 100. In some aspects, the FSRs can include portions of the programmable interconnect elements associated with various programmable logic circuits (such as CLBs, DSPs, and BRAMs) of PL 110.

[0044] The transceiver 150 may provide a signal connection to one or more other devices or chips (not shown for simplicity) connected to the device 100. The transceiver 150 may include several different data serializers and deserializers (SERDES), such as, for example, gigabit serial transceivers. In some embodiments, the transceiver 150 may be implemented as several repeatable tiles located at various locations along the right and left sides of the device 100, as shown in FIG. 1. In other embodiments, the transceiver 150 may be located in other suitable locations of the device 100.

[0045] I / O block 160 may be coupled to I / O pins (not shown for simplicity) of the device and may provide I / O functionality for device 100. For example, I / O block 160 may receive data from one or more other devices and may convey the received data to a number of destinations in device 100. I / O block 160 may also receive data from a number of sources in device 100 and may convey the received data to one or more other devices via I / O pins of the device. In some embodiments, I / O block 160 may be implemented as repeatable tiles. Device 100 may include any suitable number of I / O blocks 160, and thus, the exemplary implementation shown in FIG. 1 is merely exemplary.

[0046] I / O block 160 may include any number of suitable I / O circuits or devices. In some embodiments, I / O block 160 may include ultra-high performance I / O (XPIO) circuits, high density I / O (HDIO) circuits, and multiplexed I / O (MIO) circuits. XPIO circuits may be optimized for high performance communications, such as providing a high speed, low latency interface to memory controller 170. HDIO circuits may provide a cost-effective solution to support lower speed and higher voltage I / O functions (compared to XPIO circuits). MIO circuits may provide general purpose I / O resources that may be accessed by various subsystems, such as, for example, PL 110, dedicated circuits 130, and CPM 140.

[0047] In some embodiments, a first column of I / O blocks 160 may be implemented as repeatable tiles disposed along a bottom edge of device 100, and a second column of I / O blocks 160 may be implemented as repeatable tiles disposed along a top edge of device 100. In some aspects, the repeatable tiles implementing I / O blocks 160 may differ from one another. For example, some I / O blocks 160 may implement XPIO circuitry, other I / O blocks 160 may implement HDIO circuitry, and other I / O blocks 160 may implement MIO circuitry.

[0048] Memory controllers 170 may be used to control access to various memory resources provided within and / or outside device 100. Memory controllers 170 may include double data rate v4 (DDR4) memory controllers, double data rate v5 (DDR5) memory controllers, high bandwidth memory (HBM) controllers, and / or other suitable memory controllers. In one or more embodiments, some or all of memory controllers 170 may include a scheduler with transaction reordering capabilities, which may improve memory access efficiency.

[0049] In some embodiments, a first row of memory controllers 170 can be implemented as repeatable tiles arranged along a bottom edge of device 100, and a second row of memory controllers 170 can be implemented as repeatable tiles arranged along a top edge of device 100. In some aspects, the repeatable tiles implementing memory controllers 170 can be different from each other. For example, a first number of memory controllers 170 can implement a DDR4 memory controller, a second number of memory controllers 170 can implement an LPDDR4 memory controller, and a third number of memory controllers 170 can implement an HBM controller. The repeatable tiles implementing I / O blocks 160 and memory controllers 170 can be staggered or distributed with respect to each other, for example, as shown in the example of FIG. 1. Device 100 can include any number of I / O blocks 160 and memory controllers 170, and thus the number and location of I / O blocks 160 and memory controllers 170 shown in FIG. 1 are merely exemplary.

[0050] Although not shown in FIG. 1 for simplicity, device 100 may include a boundary logic interface (BLI) that provides connectivity between I / O blocks 160 and programmable interconnects provided within PL 110. In some aspects, the BLI may enable large, complex external devices (such as HBMs) to appear as much smaller blocks (such as CLBs) in the programmable fabric of device 100. In some implementations, the BLI may be arranged in multiple rows that are located at the upper and lower boundaries or edges of the programmable fabric. In this manner, the BLI may be used to route signals between columnar logic structures (such as CLB columns or DSP columns) and rows of I / O resources (such as I / O blocks 160).

[0051] 2 illustrates a simplified block diagram of a transceiver 200 according to some embodiments. The transceiver 200 may be an example of one or more of the transceivers 150 of FIG. 1 and is shown to include a transmit (TX) front end 210, a transmit data processing block 220, a quadrature clock generator 230, a receive (RX) data processing block 240, and a receive front end 250 coupled between an input terminal (IN) and an output terminal (OUT). In some embodiments, the transceiver 200 may be a gigabit SERDES transceiver. In other embodiments, the transceiver 200 may be of another suitable type or configuration.

[0052] A quadrature clock generator 230 is coupled to the TX data processing block 220 and to the RX data processing block 240 and provides a reference clock signal CLK REF For the example of FIG. 2, the reference clock signal CLK REF is generated by reference clock generator 201, which can be any feasible reference clock source, including but not limited to a crystal-based oscillator, a phase-locked loop, etc. In other embodiments, the reference clock signal CLK REF can be generated by another suitable circuit or oscillator.

[0053] The quadrature clock generator 230 generates the CLK REF2. In some embodiments, the first quadrature clock signal 231 may be used to transmit data, and the second quadrature clock signal 232 may be used to receive data. Although not shown in FIG. 2 for simplicity, the first quadrature clock signal 231 may include an in-phase (I) component and a quadrature (Q) component, and the second quadrature clock signal 232 may include an I component and a Q component. In some embodiments, the I and Q components (sometimes referred to as I and Q clock signals) of the first quadrature clock signal 231 may be implemented as differential signals, and the I and Q components (sometimes referred to as I and Q clock signals) of the second quadrature clock signal 232 may be implemented as differential signals.

[0054] In one or more embodiments, the first quadrature clock signal 231 may be related in frequency to the second quadrature clock signal 232, but may be offset in phase relative to the second quadrature clock signal 232. For example, the first and second quadrature clock signals 231-232 may have the same frequency and be offset in phase from each other by 45 degrees. As another example, the first and second quadrature clock signals 231-232 may have the same frequency and be offset in phase from each other by 90 degrees (or some other suitable integer multiple of 45 degrees).

[0055] The transmit data processing block 220 is coupled between the quadrature clock generator 230 and the transmit front end 210 and may receive a first quadrature clock signal 231 generated by the quadrature clock generator 230. The transmit data processing block 220 may also receive output data 221 to be transmitted by the transceiver 200. The output data 221 may be provided by the PL 110, the dedicated circuit 130, or any other possible circuit, component, or subsystem of the programmable device 100 of FIG. 1. The transmit data processing block 220 may use the first quadrature clock signal 231 to encode and / or modulate the output data 221 for transmission. In some embodiments, the transmit data processing block 220 may serialize the output data 221 based on the first quadrature clock signal 231.

[0056] The transmit front end 210 may process the encoded and / or modulated output data provided by the transmit data processing block 220 and may provide the processed output data to a wired or wireless communication medium as transmit data 211. The transmit front end 210 may include any number of circuits or components suitable for preparing the processed output data for transmission as transmit data 211. For example, in some aspects the transmit front end 210 may include amplifiers, mixers, filters, and other components configured to enhance signal integrity while minimizing noise, distortion, and timing errors.

[0057] The receive front end 250 may receive RX data 251 from one or more other devices or circuits via an input terminal IN, either via a wireless medium or a wired connection. In some embodiments, the receive front end 250 may include amplifiers, mixers, filters, and any other circuits or components suitable for maximizing data reception rates while minimizing data loss, noise, and distortion. The receive front end 250 may provide the RX data 251 to the receive data processing block 240.

[0058] The receive data processing block 240 is also coupled to the quadrature clock generator 230 and may use the second quadrature clock signal 232 to decode and / or demodulate the RX data 251 to generate the input data 241. The input data 241 may be provided to (or routed to) the PL 110, the dedicated circuit 130, or any other possible circuit, component, or subsystem of the programmable device 100 of FIG. 1. In some embodiments, the receive data processing block 240 may deserialize the RX data 251 based on the second quadrature clock signal 232.

[0059] 3 illustrates a block diagram of an exemplary quadrature clock generator 300 according to some implementations. The quadrature clock generator 300 may include an injection-locked oscillator (ILO) 310, a first phase interpolator 321, a second phase interpolator 322, a quadrature-locked loop (QLL) 340, and a voltage regulator 350. In some aspects, the quadrature clock generator 300 may be an example of the quadrature clock generator 230 of FIG.

[0060] The ILO 310 includes a first input coupled to the reference clock generator 201, a second input coupled to a voltage regulator 350, and an output coupled to the first and second phase interpolators 321-322, and outputs a reference clock signal CLKREF In some embodiments, the ILO 310 may be configured as a differential oscillator, and the reference clock generator 201 may generate a differential clock signal, CLK REF It is possible to provide:

[0061] ILO310 is CLK REF M clock signals CLK that are frequency locked to ILO where M is an integer greater than 1. A clock signal CLK ILO may be referred to as clock phases and may be equally spaced or offset in phase from one another, e.g., whereby the clock signal CLK ILO Each of the M=8 clock signals CLK has a unique phase that is an integer multiple of a reference phase offset. For example, in the embodiment of FIG. 3, the ILO 310 generates M=8 clock signals CLK that are offset in phase from each other by 45 degrees. ILO where the first clock signal CLK_0 has no phase offset, the second clock signal CLK_45 has a phase offset of 45 degrees with respect to CLK_0, the third clock signal CLK_90 has a phase offset of 90 degrees with respect to CLK_0, the fourth clock signal CLK_135 has a phase offset of 135 degrees with respect to CLK_0, the fifth clock signal CLK_180 has a phase offset of 180 degrees with respect to CLK_0, the sixth clock signal CLK_225 has a phase offset of 225 degrees with respect to CLK_0, the seventh clock signal CLK_270 has a phase offset of 270 degrees with respect to CLK_0, and the eighth clock signal CLK_315 has a phase offset of 315 degrees with respect to CLK_0.

[0062] The first phase interpolator 321 and the second phase interpolator 322 may be implemented using complementary metal oxide silicon (CMOS) technology, current mode logic (CML), or any other feasible technology. The first phase interpolator 321 receives M clock signals CLK provided by the ILO 310. ILO The first set of M clock signals CLK provided by the ILO 310 may be used to generate one or more in-phase (I) output clock signals, and the second phase interpolator 322 may use the M clock signals CLK ILO A second set of I and Q may be used to generate one or more quadrature (Q) output clock signals. In the example of FIG. 3, the first phase interpolator 321 uses I and It is possible to generate a differential in-phase (I) output clock signal represented as 9170 signals, where: TIFF0007618670000002.tif9170 is the logical complement of I. Similarly, the second phase interpolator 322 outputs Q and It is possible to generate a differential quadrature (Q) output clock signal represented as 9170 signals, where: TIFF0007618670000004.tif9170 is the logical complement of Q. In another example, the first and second phase interpolators 321-322 may generate single-ended I and Q clock signals, respectively.

[0063] In some embodiments, the first phase interpolator 321 is a clock signal CLK ILO It is possible to generate an in-phase output clock signal by interpolating between a pair of adjacent clock signals of the first set (or the second set), e.g., thereby The TIFF0007618670000005.tif9170 signals can have any desired phase. Similarly, the second phase interpolator 322 interpolates the clock signal CLK ILOIt is possible to generate a quadrature output clock signal by interpolating between a pair of adjacent clock signals of the second set (or the first set), e.g., thereby providing Q and The 9170 signals can have any desired phase.

[0064] The QLL 340 includes several inputs that are coupled to one or more outputs of the ILO 310, and an output that is coupled to a control terminal of a voltage regulator 350. In some embodiments, the QLL 340 generates M clock signals, CLK ILO (such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315) and ILO The control signal (CTRL) may be configured to generate a control signal based on one or more relationships between the reference voltage V and the reference voltage V. The CTRL signal is provided to a control input of the voltage regulator 350, which then adjusts the reference voltage V based at least in part on the CTRL signal. REF It is possible to generate

[0065] The voltage regulator 350 supplies a reference voltage V to the control terminals of the ILO 310, the first phase interpolator 321, and the second phase interpolator 322. REF It is possible to provide a reference voltage V REF may be used to control, adjust, or modify one or more operating characteristics of the ILO 310, the first phase interpolator 321, and the second phase interpolator 322.

[0066] In some embodiments, the QLL 340 may also receive one or more signals (not shown for simplicity) provided by the receive data processing block 240 of FIG. 2. These one or more signals may embody or indicate various characteristics of the incoming RX data, and the QLL 340 may be configured to generate the control signal CTRL based at least in part on these one or more signals. For example, in some aspects, these one or more signals may adjust the reference voltage V in a manner that causes the first phase interpolator 321 to maintain a particular relationship between the in-phase output clock signal and the RX data, and / or causes the second phase interpolator 322 to maintain a particular relationship between the quadrature output clock signal and the RX data. REF It is possible to adjust

[0067] Mismatches between circuit elements (such as mixers and filters) in the first and second phase interpolators 321-322 may cause timing mismatches between the in-phase and quadrature output clock signals. According to other aspects of the present disclosure, timing mismatches between the I and Q output clock signals may be avoided by using a single phase interpolator (rather than the two phase interpolators 321-322 of FIG. 3).

[0068] 4A illustrates a block diagram of another exemplary quadrature clock generator 400 according to some implementations. The quadrature clock generator 400 may be one example of the quadrature clock generator 230 of FIG. 2 and is shown to include a first ILO 411, a second ILO 412, a phase interpolator 420, a number of buffers 431, 433, and 435, a number of selection circuits 432 and 434, a quadrature locked loop (QLL) 440, a voltage regulator 450, a coarse frequency tracking circuit 460, and a switch 465.

[0069] The first ILO411 is connected to the first reference voltage V REF1a first input coupled to receive a reference clock signal CLK, a second input coupled to a voltage regulator 450, and an output coupled to a first buffer 431; REF The first reference clock signal CLK may be any suitable ILO capable of generating multiple clock signals having the same frequency but offset in phase relative to one another. REF CLK may be generated by reference clock generator 201 (not shown in FIG. 4 for simplicity) or by another suitable clock generation circuit. In some embodiments, the first ILO 411 may be configured as a differential oscillator, and reference clock generator 201 generates a differential clock signal, CLK REF It is possible to provide:

[0070] The first ILO411 is CLK REF1 P first clock signals CLK that are frequency locked to ILO1 where P is an integer greater than 1. The first clock signal CLK ILO1 may also be referred to as clock phases and may be equally spaced or offset in phase from one another, e.g., whereby the first clock signal CLK ILO1 Each of the first ILOs 411 has a unique phase that is an integer multiple of a reference phase offset. For example, in some embodiments, the first ILO 411 generates P=8 first clock signals CLK that are offset in phase from each other by 45 degrees. ILO1where a first clock signal CLK_0 has no phase offset, a second clock signal CLK_45 has a phase offset of 45 degrees relative to CLK_0, a third clock signal CLK_90 has a phase offset of 90 degrees relative to CLK_0, a fourth clock signal CLK_135 has a phase offset of 135 degrees relative to CLK_0, a fifth clock signal CLK_180 has a phase offset of 180 degrees relative to CLK_0, a sixth clock signal CLK_225 has a phase offset of 225 degrees relative to CLK_0, a seventh clock signal CLK_270 has a phase offset of 270 degrees relative to CLK_0, and an eighth clock signal CLK_315 has a phase offset of 315 degrees relative to CLK_0.

[0071] In some embodiments, the first clock signal CLK generated by the first ILO 411 ILO1 is buffered by a buffer 431 to produce a buffered first clock signal CLK ILO1’ , which may be provided to the phase interpolator 420 and to the first selection circuit 432. In other embodiments, the optional buffer 431 (shown by the dashed line) may be omitted and the first clock signal CLK ILO1 may be provided to the phase interpolator 420 and to the first selection circuit 432. In some embodiments, an optional buffer 435 (shown by a dashed line) may provide a buffered first clock signal CLK ILO1’ may be buffered for the phase interpolator 420. In other embodiments, the optional buffer 435 may be omitted.

[0072] The phase interpolator 420 is connected to the first clock signal CLK provided by the first ILO 411. ILO1 A second reference clock signal CLK is used REF2In the example of FIG. 4, the phase interpolator 420 can generate the second reference clock signal CLK REF2 In some embodiments, the phase interpolator 420 may generate a plurality of first clock signals CLK as a differential signal. ILO1 A second reference clock signal CLK is generated by interpolating between a pair of adjacent clock signals. REF2 In this manner, the phase interpolator 420 can generate the first clock signal CLK ILO1 A second reference clock signal CLK having an arbitrary phase relationship with respect to REF2 Additionally or alternatively, phase interpolator 420 may receive a signal 422 from an associated receive circuit (such as a clock data recovery circuit and / or receive data processing block), which may be used to control or adjust the interpolation.

[0073] The phase interpolator 420 may be implemented using complementary metal oxide silicon (CMOS) technology, current mode logic (CML), or any other feasible technology. In some embodiments, the phase interpolator 420 may be an example of the first phase interpolator 321 or the second phase interpolator 322 of FIG. 3. Thus, although not shown for simplicity, P first clock signals CLK ILO1 Each of the P first clock signals CLK may be provided to a corresponding input of a phase interpolator 420, which in turn generates the P first clock signals CLK ILO1 Based on the relationship between the second reference clock signal CLK REF2 It is possible to generate

[0074] The first selection circuit 432 selects the first clock signal CLK ILO1 to provide as the I / Q output clock signal 416. In some embodiments, the first selection circuit 432 selects the first clock signal CLK ILO1Any appropriate pair of may be selected to provide as the I / Q TX output clock signal 416. The I / Q output clock signal 416 may be used by a transmit circuit, such as the transmit data processing block 220 of FIG. 2, to encode or modulate data for transmission.

[0075] The second ILO 412 has a first input coupled to the phase interpolator 420 and a second input coupled to the voltage regulator 450, V REF and an output coupled to an optional buffer 433 (shown by a dashed line) for receiving a second reference clock signal CLK REF2 The second ILO 412 may be any suitable ILO capable of generating multiple clock signals having the same frequency as, but offset in phase relative to, each other. REF2 P second clock signals CLK that are frequency locked to ILO2 where P is an integer greater than 1. ILO2 may also be referred to as clock phases and may be equally spaced or offset in phase from one another, e.g., whereby the second clock signal CLK ILO2 Each of the phases has a unique phase that is an integer multiple of the reference phase offset.

[0076] In some embodiments, the second clock signal CLK ILO2 may be equally spaced or offset in phase from one another, e.g., whereby the second clock signal CLK ILO2 Each of the P=8 second clock signals CLK has a unique phase that is an integer multiple of a reference phase offset. For example, in some embodiments, the second ILO 412 generates P=8 second clock signals CLK that are offset in phase from each other by 45 degrees. ILO2where the first clock signal CLK_0 has no phase offset, the second clock signal CLK_45 has a 45 degree phase offset with respect to CLK_0, the third clock signal CLK_90 has a 90 degree phase offset with respect to CLK_0, the fourth clock signal CLK_135 has a 135 degree phase offset with respect to CLK_0, the fifth clock signal CLK_180 has a 180 degree phase offset with respect to CLK_0, the sixth clock signal CLK_225 has a 225 degree phase offset with respect to CLK_0, the seventh clock signal CLK_270 has a 270 degree phase offset with respect to CLK_0, and the eighth clock signal CLK_315 has a 315 degree phase offset with respect to CLK_0. In some aspects, the second clock signal CLK ILO2 to an optional buffer 433 to generate a plurality of buffered second clock signals CLK ILO2’ It is possible to generate

[0077] The second selection circuit 434 selects the second clock signal CLK ILO2 , and may be configured to select two (or a pair) of the I / Q RX output clock signal 436. In some embodiments, the second selection circuit 434 selects the second clock signal CLK ILO2 Any appropriate pair of the I / Q RX output clock signals 436 may be selected to provide as the I / Q RX output clock signal 436. The I / Q RX output clock signal 436 may be used by a receiver circuit, such as the receive data processing block 240 of FIG. 2, to decode or demodulate data received by the transceiver 400.

[0078] The QLL 440 includes several inputs that are coupled to one or more outputs of the second ILO 412 (via optional buffers 433) and includes an output that is coupled to a control terminal of a voltage regulator 450. In some embodiments, the QLL 440 generates P second clock signals, CLK ILO2(such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315) and ILO2 The control signal (CTRL) may be configured to generate a control signal based on one or more relationships between the reference voltage V and the reference voltage V. The CTRL signal is provided to a control input of the voltage regulator 450, which then adjusts the reference voltage V based at least in part on the CTRL signal. REF It is possible to generate

[0079] A voltage regulator 450 supplies a reference voltage V to the control terminals of the first ILO 411, the second ILO 412, the phase interpolator 420, and the optional buffers 431 and 433. REF It is possible to provide a reference voltage V REF can be used to control, adjust, or modify one or more operating characteristics of the first ILO 411, the second ILO 412, and the phase interpolator 420 (as well as the optional buffers 431 and 433). In some embodiments, the QLL 440 generates a second clock signal CLK ILO2 The voltage regulator 450 may control or adjust the value of the control signal (CTRL) based at least in part on the control signal (CTRL). REF The value of can be adjusted, thereby allowing the QLL 440 to essentially control the various operations of the first ILO 411, the second ILO 412, and the phase interpolator 420. In some embodiments, the voltage regulator 450 can also control the operation of the optional buffers 431 and 433.

[0080] The coarse frequency tracking circuit 460 may include a finite state machine (FSM) 461 and a digital-to-analog converter (DAC) 462 and may be used to control the initial start-up operation of at least the first ILO 411 and the second ILO 412. In some embodiments, the coarse frequency tracking circuit 460 generates a control voltage V CTRL and generates the control voltage V CTRL 4. More specifically, upon detecting a start-up condition, FSM 461 can assert a select signal that causes switch 465 to close (e.g., to a conducting state) and pull V through switch 465 to a level that disables the CTRL signal. CTRL to the DAC 462, for example, so that the voltage regulator 450 can control the oscillation frequencies of at least the first ILO 411 and the second ILO 512 before quadrature lock is established during the start-up state. At other times, the FSM 461 can deassert the SEL signal to open the switch 465 (such as to hold the switch 465 in a non-conducting state).

[0081] In some embodiments, I / Q mismatch may exist between the I / Q TX clock signals 416 and / or may exist between the I / Q RX clock signals 436. The mismatch between the I / Q TX clock signals 416 and the mismatch between the I / Q RX clock signals 436 may be caused by the QLL 440 controlling the second clock signal CLK ILO2 While monitoring the first clock signal CLK ILO1 This may be caused by not monitoring the

[0082] 4B illustrates a block diagram of another exemplary quadrature clock generator 401 according to another embodiment. The quadrature clock generator 401 is similar in many respects to the quadrature clock generator 400 of FIG. 4A, with the difference being that the QLL 440 generates, for example, a buffered second clock signal CLK ILO2’ Instead, the buffered first clock signal CLK ILO1’ as an input signal.

[0083] 5A illustrates a block diagram of another exemplary quadrature clock generator 500 according to some implementations. The quadrature clock generator 500 may include a first ILO 511, a second ILO 512, a phase interpolator 520, a first optional buffer 531, a first selection circuit 532, a second optional buffer 533, a second selection circuit 534, a first QLL 541, a second QLL 542, a first voltage regulator 551, a second voltage regulator 552, a coarse frequency tracking circuit 560, a first switch 561, and a second switch 562. As discussed in more detail below, the quadrature clock generator 500 may use the first QLL 541 to control the I / Q TX clock signal 516 used by the transmit data processing block and the second QLL 542 to control the I / Q RX clock signal 536 used by the receive data processing block.

[0084] The first ILO 511 generates a first reference clock signal CLK REF1 a first input coupled to receive a first reference voltage V generated by a first voltage regulator 551; REF1 and an output coupled to the first buffer 531, for receiving the first reference clock signal CLK REF1 The first reference clock signal CLK may be any suitable ILO capable of generating multiple clock signals having the same frequency but offset in phase relative to one another. REF1CLK may be generated by reference clock generator 201 (not shown in FIG. 5 for simplicity), or alternatively by another suitable clock generation circuit. In some embodiments, the first ILO 511 may be configured as a differential oscillator, and reference clock generator 201 generates CLK as a differential clock signal. REF1 It is possible to provide:

[0085] The first ILO511 is CLK REF1 N first clock signals CLK that are frequency locked to ILO1 where N is an integer greater than 1. The first clock signal CLK ILO1 may also be referred to as clock phases and may be equally spaced or offset in phase from one another, e.g., whereby the first clock signal CLK ILO1 Each of the first ILOs 511 has a unique phase that is an integer multiple of a reference phase offset. For example, in some embodiments, the first ILO 511 generates N=8 first clock signals CLK that are offset in phase from each other by 45 degrees. ILO1 where a first clock signal CLK_0 has no phase offset, a second clock signal CLK_45 has a phase offset of 45 degrees relative to CLK_0, a third clock signal CLK_90 has a phase offset of 90 degrees relative to CLK_0, a fourth clock signal CLK_135 has a phase offset of 135 degrees relative to CLK_0, a fifth clock signal CLK_180 has a phase offset of 180 degrees relative to CLK_0, a sixth clock signal CLK_225 has a phase offset of 225 degrees relative to CLK_0, a seventh clock signal CLK_270 has a phase offset of 270 degrees relative to CLK_0, and an eighth clock signal CLK_315 has a phase offset of 315 degrees relative to CLK_0.

[0086] In some embodiments, the first clock signal CLK generated by the first ILO 511 ILO1 is buffered by a buffer 531 to obtain a buffered first clock signal CLK ILO1’ may be generated, which may be provided to the phase interpolator 520, the first selection circuit 532, and the first QLL 541. In other embodiments, the optional buffer 531 (shown by the dashed line) may be omitted, and the first clock signal CLK ILO1 may be provided to the phase interpolator 520, the first selection circuit 532, and the first QLL 541. In some embodiments, an optional buffer 535 (shown by a dashed line) may provide a buffered first clock signal CLK ILO1’ may be buffered for the phase interpolator 520. In other embodiments, the optional buffer 535 may be omitted.

[0087] The first QLL 541 includes several inputs that are coupled to one or more outputs of the first ILO 511 (via optional buffers 531) and includes an output that is coupled to a control terminal of a first voltage regulator 551. In some embodiments, the first QLL 541 generates N first clock signals CLK ILO1 (such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315), of which the first of the clock signals CLK ILO1 The first voltage regulator 551 may be configured to generate a first control signal (CTRL1) based on one or more relationships between the first voltage regulator 551 and the second voltage regulator 551. The CTRL1 signal is provided to a control input of the first voltage regulator 551, which then adjusts V based at least in part on the CTRL1 signal. REF1 It is possible to generate

[0088] A first voltage regulator 551 supplies V to the control terminals of the first ILO 511 and the optional buffer 531. REF1 to, for example, control, adjust, or modify one or more operating characteristics of the first ILO 511 and the optional buffer 531. In some embodiments, the first QLL 541 provides a first clock signal CLK ILO1 The first voltage regulator 551 may control or adjust the value of the CTRL1 signal based at least in part on the relative phase of the CTRL1 signal. REF1 It is possible to adjust the value of , thereby allowing the first QLL 541 to control various operations of the first ILO 511.

[0089] The phase interpolator 520 is configured to interpolate the first clock signal CLK provided by the first ILO 511. ILO1 A second reference clock signal CLK is used REF2 In the example of FIG. 5, the phase interpolator 520 can generate the second reference clock signal CLK REF2 In some embodiments, the phase interpolator 520 may generate a plurality of first clock signals CLK as a differential signal. ILO1 A second reference clock signal CLK is generated by interpolating between a pair of adjacent clock signals. REF2 In this manner, the phase interpolator 520 can generate the first clock signal CLK ILO1 A second reference clock signal CLK having an arbitrary phase relationship with respect to REF2 Additionally or alternatively, phase interpolator 520 may receive a signal 522 from an associated receive circuit (such as a clock data recovery circuit and / or receive data processing block), which may be used to control or adjust the interpolation.

[0090] The phase interpolator 520 may be implemented using complementary metal oxide silicon (CMOS) technology, current mode logic (CML), or any other feasible technology. In some embodiments, the phase interpolator 520 may be an example of the first phase interpolator 321 or the second phase interpolator 322 of FIG. 3. Thus, N first clock signals CLK, not shown for simplicity, may be included. ILO1 Each of the N first clock signals CLK may be provided to a corresponding input of a phase interpolator 520, which in turn generates the N first clock signals CLK ILO1 The second reference clock signal CLK is based on the relationship between REF2 It is possible to generate

[0091] The first selection circuit 532 selects the first clock signal CLK ILO1 to provide as the I / Q TX output clock signal 516. In some embodiments, the first selection circuit 532 selects the first clock signal CLK ILO1 may be selected to provide as the I / Q TX output clock signal 516. The I / Q TX output clock signal 516 may be used by a transmit circuit, such as the transmit data processing block 220 of FIG. 2, to encode or modulate data for transmission.

[0092] The second ILO 512 receives the second reference clock signal CLK from the phase interpolator 520. REF2 and a first input for receiving a second reference voltage V generated by a second voltage regulator 552. REF2 and an output coupled to an optional buffer 533 (shown by a dashed line) for receiving a second reference clock signal CLK REF2 The ILO may be any suitable ILO capable of generating multiple clock signals having the same frequency as, but offset in phase with respect to one another.

[0093] In some embodiments, the second clock signal CLK ILO2 may be equally spaced or offset in phase from one another, e.g., whereby the second clock signal CLK ILO2 Each of the N=8 second clock signals CLK has a unique phase that is an integer multiple of a reference phase offset. For example, in some embodiments, the second ILO 512 generates N=8 second clock signals CLK that are offset in phase from each other by 45 degrees. ILO2 where the first clock signal CLK_0 has no phase offset, the second clock signal CLK_45 has a 45 degree phase offset with respect to CLK_0, the third clock signal CLK_90 has a 90 degree phase offset with respect to CLK_0, the fourth clock signal CLK_135 has a 135 degree phase offset with respect to CLK_0, the fifth clock signal CLK_180 has a 180 degree phase offset with respect to CLK_0, the sixth clock signal CLK_225 has a 225 degree phase offset with respect to CLK_0, the seventh clock signal CLK_270 has a 270 degree phase offset with respect to CLK_0, and the eighth clock signal CLK_315 has a 315 degree phase offset with respect to CLK_0. In some aspects, the second clock signal CLK ILO2 to an optional buffer 533 to generate a plurality of buffered second clock signals CLK ILO2’ It is possible to generate

[0094] The second selection circuit 534 selects the second clock signal CLK ILO2 to provide as the I / Q RX output clock signal 536. In some embodiments, the second selection circuit 534 may be configured to select two (or a pair) of the second clock signal CLK ILO2Any appropriate pair of the I / Q RX output clock signals 536 may be selected to provide as the I / Q RX output clock signal 536. The I / Q RX output clock signal 536 may be used by a receiver circuit, such as the receive data processing block 240 of FIG. 2, to decode or demodulate data received by the transceiver 500.

[0095] The second QLL 542 includes several inputs that are coupled to one or more outputs of the second ILO 512 (via optional buffers 533) and includes an output that is coupled to a control terminal of a second voltage regulator 552. In some embodiments, the second QLL 452 generates N second clock signals CLK ILO2 (such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315) and ILO2 The second voltage regulator 552 may be configured to generate a second control signal (CTRL2) based on one or more relationships between the first and second voltage regulators 552. The CTRL2 signal is provided to a control input of the second voltage regulator 552, which then adjusts V based at least in part on the CTRL2 signal. REF2 It is possible to generate and / or adjust the value of

[0096] A second voltage regulator 552 supplies V REF2 to, for example, control, adjust, or modify one or more operating characteristics of the phase interpolator 520 and the second ILO 512. In some embodiments, the second QLL 542 provides a second clock signal, CLK ILO2 The second voltage regulator 552 may control or adjust the value of the CTRL2 signal based at least in part on the relative phase of the CTRL2 signal. REF2The value of can be adjusted, thereby allowing the second QLL 542 to control various operations of the phase interpolator 520 and the second ILO 512.

[0097] 4 and may be used to control the initial start-up operation of at least the first ILO 511 and the second ILO 512. In some embodiments, the coarse frequency tracking circuit 560 may be an implementation of the coarse frequency tracking circuit 460 of FIG. 4 and may be used to control the initial start-up operation of at least the first ILO 511 and the second ILO 512. In some embodiments, the coarse frequency tracking circuit 560 may be configured to generate a control voltage V CTRL , asserts the select (SEL) signal, and generates its control voltage V CTRL and the SEL signal can be used to temporarily disable the CTRL1 signal via a first switch 561 and / or to temporarily disable the CTRL2 signal via a second switch 562. More specifically, upon detecting a start-up condition, the coarse frequency tracking circuit 560 can assert the SEL signal to close or turn on the switches 561-562 and increase V to a level that disables the CTRL1 signal via switch 561 and / or disables the CTRL2 signal via switch 562. CTRL In this manner, the coarse frequency tracking circuit 560 can enable the first voltage regulator 551 to control the oscillation frequency of the first ILO 511 and the second voltage regulator 552 to control the oscillation frequency of the second ILO 512 before quadrature lock is established during the start-up state.

[0098] 5B illustrates a block diagram of another exemplary quadrature clock generator 501 according to another embodiment. The quadrature clock generator 501 is similar in many respects to the quadrature clock generator 500 of FIG. 5A, with the difference being that the phase interpolator 520 is a phase interpolator that is, for example, a second reference voltage V REF2 Instead, the first reference voltage V REF1 It is possible for the signal to be controlled by

[0099] Figure 6 illustrates an exemplary flow chart showing exemplary operations 600 for operating a quadrature clock generator, according to some implementations. The operations 600 may be used to operate any suitable quadrature clock generator, including, for example, the quadrature clock generator 400 of Figure 4A, the quadrature clock generator 401 of Figure 4B, the quadrature clock generator 500 of Figure 5A, and the quadrature clock generator 501 of Figure 5B. Thus, although described hereinafter with respect to the quadrature clock generator 400 of Figure 4A, the quadrature clock generator 401 of Figure 4B, the quadrature clock generator 500 of Figure 5A, and the quadrature clock generator 501 of Figure 5B, the exemplary operations 600 may be used with other suitable quadrature clock generators.

[0100] The operations 600 may begin with generating 602 a plurality of first clock signals based at least in part on a first reference clock signal. Referring also to FIGS. 4A and 4B, the first ILO 411 generates 602 a plurality of first clock signals based at least in part on a first reference clock signal CLK. REF1 A plurality of first clock signals CLK based on ILO1 In some embodiments, the first clock signal CLK ILO1 may include an integer number of clock signals that may be selected for use as the I and Q TX clock signals.

[0101] The operation 600 may proceed with selecting (604) one of the first clock signals as the transmit quadrature clock signal. Referring also to Figures 4A and 4B, the selection circuit 432 may select the first clock signal CLK ILO1 Any suitable one of may be selected to provide as the I / Q TX output clock signal 416. The I / Q TX output clock signal 416 may be used by a transmit circuit, such as the transmit data processing block 220 of FIG. 2, to encode or modulate data for transmission.

[0102] The operations 600 may proceed with generating 606 a second reference clock signal based at least in part on the plurality of first clock signals. Referring also to FIGS. 4A and 4B, the phase interpolator 420 may generate 606 a second reference clock signal based at least in part on the plurality of first clock signals. ILO1 A second reference clock signal CLK is used REF2 In some embodiments, the phase interpolator 420 may generate a plurality of first clock signals CLK ILO1 A second reference clock signal CLK is generated by interpolating between a pair of adjacent clock signals. REF2 For example, it is possible to generate a second reference clock signal CLK REF2 is the first clock signal CLK ILO1 It is possible for the .lamda.

[0103] The operations 600 may proceed with generating (608) a plurality of second clock signals based at least in part on the second reference clock signal. Referring also to Figures 4A and 4B, the second ILO 412 generates a second reference clock signal CLK REF2 A plurality of second clock signals CLK based on ILO2 In some embodiments, the second clock signal CLK ILO2 may include an integer number of clock signals that may be selected for use as the I and Q RX clock signals.

[0104] The operation 600 may proceed with selecting (610) one of the plurality of second clock signals as the received quadrature clock signal. Referring also to Figures 4A and 4B, the second selection circuit 434 selects the second clock signal CLK ILO2Any suitable pair of the I / Q RX output clock signals 436 may be selected to provide as the I / Q RX output clock signal 436. The I / Q RX output clock signal 436 may be used by a receiver circuit, such as the receive data processing block 240 of FIG. 2, to encode or modulate data for transmission.

[0105] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0106] Moreover, those skilled in the art will appreciate that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art will appreciate that the described functionality can be implemented in various ways for each particular application, and such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0107] The methods, sequences, or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in software modules executed by a processor, or in a combination of the two. The software modules may reside in RAM latches, flash latches, ROM latches, EPROM latches, EEPROM latches, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

[0108] In the foregoing specification, exemplary embodiments have been described with reference to specific illustrative implementations thereof. It will be apparent, however, that various modifications and changes may be made thereto without departing from the broader scope of the present disclosure as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

Claims

1. a first injection-locked oscillator configured to generate a plurality of first clock signals based at least in part on a first reference clock signal; a first selection circuit coupled to the first injection-locked oscillator and configured to select one of the first clock signals as a transmit quadrature clock signal, the transmit quadrature clock signal being provided to a transmit circuit; a phase interpolator coupled to the first injection-locked oscillator and configured to generate a second reference clock signal based on a selected pair of the first clock signals; a second injection-locked oscillator configured to generate a plurality of second clock signals based at least in part on the second reference clock signal; a second selection circuit coupled to the second injection-locked oscillator and configured to select one of the second clock signals as a receive quadrature clock signal, the receive quadrature clock signal being provided to a receiver circuit; a quadrature clock generator including:

2. 2. The quadrature clock generator of claim 1, wherein the transmit quadrature clock signal includes a first in-phase (I) component and a first quadrature (Q) component, and the receive quadrature clock signal includes a second I component and a second Q component.

3. The quadrature clock generator of claim 1 , wherein the phase interpolator is configured to generate the second reference clock signal based at least in part on an input signal provided by the receiver circuit.

4. 2. The quadrature clock generator of claim 1, wherein each of the plurality of first clock signals are offset in phase from each other by 45 degrees and each of the plurality of second clock signals are offset in phase from each other by 45 degrees.

5. The quadrature clock generator of claim 1 , wherein the first injection-locked oscillator, the phase interpolator, and the second injection-locked oscillator are controlled, at least in part, by a reference voltage.

6. a quadrature locked loop (QLL) configured to generate a control signal based at least in part on the plurality of second clock signals; a voltage regulator configured to generate the reference voltage based at least in part on the control signal; The quadrature clock generator of claim 5 further comprising:

7. The quadrature clock generator of claim 6 , further comprising a coarse frequency tracking circuit configured to selectively disable the control signal based at least in part on detecting a power-up condition.

8. a first quadrature locked loop (QLL) configured to generate a first control signal based at least in part on the plurality of first clock signals; a first voltage regulator configured to generate a first reference voltage based at least in part on the first control signal; a second QLL configured to generate a second control signal based at least in part on the plurality of second clock signals; a second voltage regulator configured to generate a second reference voltage based at least in part on the second control signal; The quadrature clock generator of claim 1 further comprising:

9. The method of claim 8, wherein the first injection-locked oscillator is controlled, at least in part, by the first reference voltage; the phase interpolator and the second injection-locked oscillator are controlled, at least in part, by the second reference voltage; 9. The quadrature clock generator of claim 8.

10. 10. The quadrature clock generator of claim 8, further comprising a coarse frequency tracking circuit configured to selectively disable the first and second control signals based at least in part on detecting a power-up condition.

11. a transmit data processing block configured to transmit data using the transmit quadrature clock signal; a receive data processing block configured to receive data using a receive quadrature clock signal; a quadrature clock generator coupled to the transmit data processing block and to the receive data processing block; 1. A programmable logic device comprising: a first injection-locked oscillator configured to generate a plurality of first clock signals based at least in part on a first reference clock signal; a first selection circuit configured to select one of the first clock signals as the transmit quadrature clock signal; a phase interpolator coupled to the first injection-locked oscillator and configured to generate a second reference clock signal based on a selected pair of the first clock signals; a second injection-locked oscillator configured to generate a plurality of second clock signals based at least in part on the second reference clock signal; and a second selection circuit configured to select one of the second clock signals as the receive quadrature clock signal.

12. 12. The programmable logic device of claim 11 wherein the first injection locked oscillator, the phase interpolator, and the second injection locked oscillator are controlled, at least in part, by a reference voltage.

13. a quadrature locked loop (QLL) configured to generate a control signal based at least in part on the plurality of second clock signals; a voltage regulator configured to generate the reference voltage based at least in part on the control signal; 13. The programmable logic device of claim 12 further comprising:

14. 1. A method for operating a quadrature clock generator, comprising: generating, by a first injection-locked oscillator, a plurality of first clock signals based at least in part on a first reference clock signal; selecting, by a first selection circuit coupled to the first injection-locked oscillator, one of the plurality of first clock signals as a transmit quadrature clock signal; generating, by a phase interpolator coupled to the first injection-locked oscillator, a second reference clock signal based at least in part on the plurality of first clock signals; generating, by a second injection-locked oscillator, a plurality of second clock signals based at least in part on the second reference clock signal; selecting, by a second selection circuit coupled to the second injection-locked oscillator, one of the plurality of second clock signals as a receive quadrature clock signal; The transmit quadrature clock signal is provided to a transmit circuit. the receive quadrature clock signal is provided to a receive circuit; method.

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