SEMICONDUCTOR INSPECTION APPARATUS AND SEMICONDUCTOR WAFER INSPECTION METHOD

Abstract

To provide a semiconductor inspection device and an inspection method for a semiconductor wafer that can suppress the occurrence of failure at the inspection of the semiconductor wafer and stabilize the inspection sensitivity of the semiconductor wafer.SOLUTION: A stage 11 includes a first holding unit 11c, a plurality of gas suction holes 15, and a plurality of gas supply holes 16. The first holding unit 11c is provided protruding from a placement surface 11a of the stage 11, and holds a semiconductor wafer 13 at a position away from the placement surface 11a of the stage 11. After the semiconductor wafer 13 is placed on the placement surface 11a of the stage 11 and held by the first holding unit 11c, gas between the semiconductor wafer 13 and the stage 11 is sucked from the gas suction holes 15 and the gas is supplied from the gas supply holes 16 into a space between the semiconductor wafer 13 and the stage 11, so that the warpage of the semiconductor wafer 13 is corrected at the position away from the placement surface 11a of the stage 11. In the approximately flat state where the warpage is corrected, an inspection surface 3b of a semiconductor wafer 3 is photographed by an inspection head 12.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor inspection device and a method for inspecting a semiconductor wafer. [Background technology]

[0002] Conventionally, in power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors having an insulated gate with a three-layer structure of metal-oxide-semiconductor), which employ a vertical element structure in which the main current flows in the depth direction or thickness direction (opposite to the depth direction) of the semiconductor chip, there has been a demand for reducing the thickness of the semiconductor wafer in order to reduce the on-resistance.

[0003] Fig. 8 is a cross-sectional view that shows a schematic state of a semiconductor wafer during inspection by a conventional semiconductor inspection device. The thinning of the semiconductor wafer 113 is performed by a polishing process in which the semiconductor wafer 113 is polished from either of the main surfaces 113a, 113b to a position of a predetermined thickness, and this polishing process causes warping of the semiconductor wafer 113. The warping of the semiconductor wafer 113 refers to a cross-sectional shape of the semiconductor wafer 113 that is curved in a convex shape that protrudes toward the stage 111 (hereinafter, referred to as a downward convex shape) (Fig. 8) or a cross-sectional shape that is curved in a convex shape that protrudes away from the stage 111 (hereinafter, referred to as an upward convex shape) (not shown).

[0004] If the semiconductor wafer 113 is warped, the distance h101 between the inspection head (imaging means) 112 of the semiconductor inspection device 110 and the main surface (inspection surface) 113b of the semiconductor wafer 113 will not be constant within the inspection surface 113b of the semiconductor wafer 113. For this reason, when visual inspection of adjacent chip regions (portions that will become semiconductor chips: not shown) is continuously performed over the entire surface of the inspection surface 113b of the semiconductor wafer 113 in a single scan 114 (horizontal arrow) by the inspection head 112, the focal depth h102 cannot be kept constant. Therefore, the inspection sensitivity of the visual inspection within the inspection surface 113b of the semiconductor wafer 113 will not be stable.

[0005] In particular, as the diameter of the semiconductor wafer 113 increases (larger aperture), the warpage of the semiconductor wafer 113 also increases, and the adverse effects of the warpage of the semiconductor wafer 113 on the appearance inspection of the semiconductor wafer 113 become increasingly large. As a conventional technique for solving the problems caused by the warpage of the semiconductor wafer 113, a semiconductor inspection device has been proposed that corrects the warpage of the semiconductor wafer and flattens it by sucking air between the semiconductor wafer and the stage, or by sucking air and supplying air between the semiconductor wafer and the stage at the same time (see, for example, Patent Documents 1 to 4 below).

[0006] In Patent Document 1 below, a stage on which a semiconductor wafer is placed has a plurality of intake holes that suck in the atmosphere (air) between the semiconductor wafer and the stage, generating a negative pressure between the semiconductor wafer and the main surface of the semiconductor wafer facing the stage (hereinafter referred to as the facing surface), thereby partially adsorbing the wafer. For the plurality of intake holes of the stage, the suction force of the intake holes corresponding to the portions of the semiconductor wafer with a relatively large amount of warping within the surface of the semiconductor wafer is made greater than the suction force of the intake holes corresponding to the portions of the semiconductor wafer with a relatively small amount of warping, thereby correcting the warping of the semiconductor wafer and flattening it, and reducing the contact resistance between the semiconductor wafer and the stage.

[0007] In the following Patent Document 2, a stage on which a semiconductor wafer is placed has a plurality of intake holes that suck in the air between the semiconductor wafer and the stage and generate a negative pressure between the semiconductor wafer and the facing surface of the semiconductor wafer to partially adsorb the wafer, and an intake passage having a planar spiral shape that is connected to all of the plurality of intake holes. The suction force of a vacuum pump that sucks in the air in the intake passage is first applied to the center of the semiconductor wafer directly above the start of the spiral intake passage, and is then applied with a delay to each portion of the semiconductor wafer directly above each portion of the intake passage toward the outer periphery of the intake passage, thereby correcting warpage of the semiconductor wafer and flattening it.

[0008] In the following Patent Document 3, a stage on which a semiconductor wafer is placed is provided on a chuck stage, and the semiconductor wafer is attracted and fixed to the surface opposite to the surface in contact with the chuck stage by the negative pressure created by the chuck stage. The stage also has a plurality of grooves on the surface in contact with the chuck stage, and a plurality of intake holes penetrating from the surface on which the semiconductor wafer is placed to the bottom surface of each groove. Two or more intake holes are penetrating the same groove, and the distribution density of the intake holes is changed from the center to the edge of the semiconductor wafer, and the negative pressure within the surface of the semiconductor wafer is changed, thereby correcting the warpage of the semiconductor wafer and flattening it.

[0009] In the following Patent Document 4, a stage on which a semiconductor wafer is placed has an intake hole for drawing in air between the semiconductor wafer and the stage, and an air supply hole for supplying air between the semiconductor wafer and the stage. A plurality of intake holes and a plurality of air supply holes are arranged radially from the center of the stage. Air is supplied between the semiconductor wafer and the stage from the air supply hole, and air is sucked from the exhaust port between the semiconductor wafer and the stage, making the air layer formed between the semiconductor wafer and the stage substantially uniform (a state in which no pressure distribution occurs), thereby correcting warpage of the semiconductor wafer and flattening it.

[0010] Fig. 9 is a cross-sectional view showing a schematic diagram of another example of a state during inspection of a semiconductor wafer by a conventional semiconductor inspection device. The conventional semiconductor inspection device 120 shown in Fig. 9 is a semiconductor wafer visual inspection device having a stage 121 on which a semiconductor wafer 123 is placed, and an inspection head 122 that photographs the semiconductor wafer 123. The stage 121 is a typical flat-plate-shaped porous chuck using porous ceramics, and has a plurality of fine holes (indicated by vertically striped hatching) that serve as air intake holes over the entire surface 121a on which the semiconductor wafer 123 is placed (hereinafter referred to as the placement surface). The air intake holes penetrate the stage 121 between both surfaces (flat surfaces) 121a and 121b.

[0011] Air between the semiconductor wafer 123 and the stage 121 is sucked in 125 (downward arrow) through the air intake, so that the entire main surface (opposing surface) 123a of the semiconductor wafer 123 facing the stage 121 is pressed against the mounting surface 121a of the stage 121. As a result, even if the semiconductor wafer 123 is warped (see the semiconductor wafer 113 in FIG. 8), the warp is corrected and the semiconductor wafer 123 becomes flat. Therefore, the distance h201 between the inspection head 122 and the inspection surface 123b of the semiconductor wafer 123 becomes constant within the surface of the semiconductor wafer 123, and the focal depth h202 is kept constant during one scan 124 (horizontal arrow) by the inspection head 122. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2014-195016 A [Patent Document 2] JP 2015-026765 A [Patent Document 3] JP 2017-027974 A [Patent Document 4] JP 2007-214336 A Summary of the Invention [Problem to be solved by the invention]

[0013] However, in the above-mentioned conventional semiconductor inspection device 120 (see FIG. 9), there is a risk of defective portions occurring in the semiconductor wafer 123 due to the semiconductor wafer 123 coming into contact with the stage 121. This problem is particularly noticeable in a warped semiconductor wafer 123. The reason is that when the semiconductor wafer 123 is warped, in order to bring the portion of the semiconductor wafer 123 that is separated from the stage 121 into contact with the stage 121, it is necessary to suck 125 the semiconductor wafer 123 with a larger suction force than when the semiconductor wafer 123 is sucked simply to fix it to the stage 111 while it is in a warped state.

[0014] The suction force for sucking 125 the semiconductor wafer 123 is approximately uniform within the surface of the mounting surface 121a of the stage 121 (porous chuck). Therefore, the entire surface of the facing surface 123a of the semiconductor wafer 123 is sucked 125 by the suction force for bringing the part of the facing surface 123a of the semiconductor wafer 123 farthest from the stage 121 into contact with the stage 121, and the part of the facing surface 123a of the semiconductor wafer 123 that is relatively close to the stage 121 is strongly pressed against the stage 121. This causes the electrode pattern on the facing surface 123a of the semiconductor wafer 123 to be crushed or chipped, foreign matter to adhere, scratches, etc., during inspection of the semiconductor wafer 123.

[0015] This may result in defects such as short circuits or openings due to pattern collapse or loss, short circuits or interruptions to ion implantation due to foreign matter, and separation of a field stop (FS) layer due to scratches when the facing surface 123a of the semiconductor wafer 123 contacts the back surface of the semiconductor chip. The portion of the semiconductor wafer 123 that is relatively close to the stage 121 is the vicinity of the apex portion at approximately the center of the facing surface 123a of the semiconductor wafer 123 when the semiconductor wafer 123 is warped in a downward convex shape, and is the vicinity of the end portion of the facing surface 123a of the semiconductor wafer 123 when the semiconductor wafer 123 is warped in an upward convex shape.

[0016] In order to solve the problems associated with the conventional techniques described above, an object of the present invention is to provide a semiconductor inspection apparatus and a semiconductor wafer inspection method that can suppress the occurrence of defects during semiconductor wafer inspection and stabilize the inspection sensitivity of semiconductor wafers. [Means for solving the problem]

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor inspection device according to the present invention has the following features: A stage carries a semiconductor wafer. A first holding part is provided protruding from a first surface of the stage on which the semiconductor wafer is placed, and contacts a part of a first main surface of the semiconductor wafer that faces the stage, and holds the semiconductor wafer at a position away from the first surface of the stage. A plurality of intake holes have one opening provided at a predetermined position on the first surface of the stage and the other opening connected to an intake means, and suck in gas between the semiconductor wafer and the stage.

[0018] A plurality of air supply holes have one opening provided at a predetermined position on the first surface of the stage and the other opening connected to an air supply means, and supply gas between the semiconductor wafer and the stage. An imaging means images a second main surface of the semiconductor wafer opposite to the stage. Before the imaging means images the semiconductor wafer, the gas between the semiconductor wafer and the stage is sucked in through the air intake holes, and gas is supplied from the air supply holes between the semiconductor wafer and the stage, thereby controlling to correct warpage of the semiconductor wafer at a position away from the first surface of the stage.

[0019] In addition, in the semiconductor inspection device according to the present invention, the first holding portion holds the semiconductor wafer by contacting an outer periphery of the first main surface of the semiconductor wafer.

[0020] In addition, the semiconductor inspection apparatus of the present invention is characterized in that, in the above-mentioned invention, the first holding portion is supported on the first surface of the stage in a movable state so as to move the semiconductor wafer in a direction away from the first surface of the stage and in a direction toward the first surface of the stage.

[0021] In addition, the semiconductor inspection apparatus of the present invention is characterized in that, in the above-mentioned invention, it further comprises a second holding part that is provided opposite the first holding part, contacts a portion of the second main surface of the semiconductor wafer, and holds the semiconductor wafer between itself and the first holding part.

[0022] In the semiconductor inspection device according to the present invention, the intake holes are grouped into predetermined sections of the first surface of the stage and connected to different intake means, and control is performed to suck in gas between the semiconductor wafer and the stage with different intake amounts for each of the predetermined sections.

[0023] In the semiconductor inspection device according to the present invention, the air supply holes are grouped into predetermined sections of the first surface of the stage and connected to different air supply means, and control is performed to supply gas between the semiconductor wafer and the stage at different amounts of air for each of the predetermined sections.

[0024] In addition, the semiconductor inspection apparatus of the present invention is characterized in that, in the above-mentioned invention, the air intake hole and the air supply hole are provided on the first main surface of the stage at positions that are obtained in advance based on the warpage state of the semiconductor wafer.

[0025] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor wafer inspection method according to the present invention has the following features. A holding step is performed in which a part of a first main surface of the warped semiconductor wafer facing the stage is brought into contact with a first holding part provided so as to protrude from a first surface of the stage on which the semiconductor wafer is placed, and the semiconductor wafer is held at a position away from the first surface of the stage. An intake step is performed in which gas is sucked between the semiconductor wafer and the stage from a plurality of intake holes, one of which is provided at a predetermined position on the first surface of the stage and the other of which is connected to an intake means. An air supply step is performed in which gas is supplied between the semiconductor wafer and the stage from a plurality of air supply holes, one of which is provided at a predetermined position on the first surface of the stage and the other of which is connected to an air supply means. An imaging step is performed in which a second main surface of the semiconductor wafer opposite to the stage is imaged by an imaging means. Before the imaging step, the intake step and the air supply step are performed simultaneously to correct the warpage of the semiconductor wafer at a position away from the first surface of the stage.

[0026] The semiconductor wafer inspection method according to the present invention further includes, before the holding step, an acquisition step of acquiring positions of the air intake hole and the air supply hole on the first main surface of the stage based on a warpage state of the semiconductor wafer. The holding step uses the stage in which the air intake hole and the air supply hole are arranged on the first main surface at the positions acquired in the acquisition step. In addition, the semiconductor wafer inspection method of the present invention is characterized in that, in the holding process, a portion of a second main surface of the semiconductor wafer is brought into contact with a second holding part provided opposite the first holding part, and the semiconductor wafer is held between the first holding part and the second holding part.

[0027] According to the above-mentioned invention, the semiconductor wafer is pulled toward the stage at the portion facing the air intake hole, and is pushed up in a direction away from the stage at the portion facing the air supply hole, so that the warp of the semiconductor wafer can be corrected without the semiconductor wafer coming into contact with the stage. Also, since the semiconductor wafer is inspected in a substantially flat state after the warp is corrected, the distance between the inspection head and the inspection surface of the semiconductor wafer becomes substantially constant, and the semiconductor wafer can be inspected in a state where the focal depth is kept constant across the inspection surface of the semiconductor wafer. Effect of the Invention

[0028] The semiconductor inspection device and semiconductor wafer inspection method according to the present invention have the effect of suppressing the occurrence of defects during semiconductor wafer inspection and stabilizing the inspection sensitivity of the semiconductor wafer. [Brief description of the drawings]

[0029] [Figure 1] 1 is a cross-sectional view showing a schematic example of a state during inspection of a semiconductor wafer by a semiconductor inspection device; [Diagram 2] 1 is a cross-sectional view showing a schematic example of a state during inspection of a semiconductor wafer by a semiconductor inspection device; [Diagram 3] FIG. 13 is a perspective view showing a schematic diagram of another example of a semiconductor inspection device according to an embodiment. [Figure 4] 13 is a plan view showing another example of a semiconductor inspection device according to an embodiment as viewed from the stage mounting surface side. FIG. [Diagram 5] 5 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. 4. [Figure 6] 5 is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIG. 4. [Figure 7] 11 is a cross-sectional view showing an example of a state during inspection of another semiconductor wafer by the semiconductor inspection device according to the embodiment; FIG. [Figure 8] 1 is a cross-sectional view showing a schematic state of a semiconductor wafer during inspection by a conventional semiconductor inspection device. [Figure 9] 11 is a cross-sectional view showing a schematic diagram of another example of a state during inspection of a semiconductor wafer by a conventional semiconductor inspection device. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] A preferred embodiment of the semiconductor inspection device and semiconductor wafer inspection method according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations will be omitted.

[0031] (Embodiment) The structure of a semiconductor inspection device according to an embodiment will be described. FIGS. 1 and 2 are cross-sectional views showing an example of a state when a semiconductor wafer is inspected by the semiconductor inspection device according to an embodiment. FIG. 3 is a perspective view showing another example of the semiconductor inspection device according to an embodiment. FIG. 4 is a plan view showing another example of the semiconductor inspection device according to an embodiment as viewed from the stage mounting surface side. FIGS. 5 and 6 are cross-sectional views showing the cross-sectional structures along the cutting lines A-A' and B-B' in FIG. 4, respectively. FIG. 7 is a cross-sectional view showing an example of a state when another semiconductor wafer is inspected by the semiconductor inspection device according to an embodiment.

[0032] The semiconductor inspection devices 10a and 10b according to the embodiment shown in Figures 1 and 2 are semiconductor wafer visual inspection devices having a stage 11 on which a semiconductor wafer 13 (3) is placed, an inspection head (imaging means) 12 that images the inspection surface 3b of the semiconductor wafer 3 in a state in which the warpage has been corrected, and a transport means (not shown) that transports the inspection head 12. The semiconductor inspection devices 10a and 10b according to the embodiment differ from a general semiconductor wafer visual inspection device in that the stage 11 is provided with a mechanism for correcting the warpage of the semiconductor wafer 13. In Figures 1 and 2, the semiconductor wafer 13 before the warpage is corrected (the curvature direction of the warpage is different in Figures 1 and 2) is shown by a dashed line, and the semiconductor wafer 3 in a state in which the warpage has been corrected is shown by a solid line.

[0033] 8, which has a stage 111 equipped with suction means for simply fixing a semiconductor wafer 113 in a warped state, and an image of the entire inspection surface 113b of the semiconductor wafer 113 is captured by a single scan 114 using an inspection head (imaging means) 112 that keeps a predetermined focal depth h102 constant within the plane of the inspection surface 113b of the semiconductor wafer 113 on the stage 111. Specifically, an example of a typical semiconductor wafer visual inspection device is ZI-2000 (trademark) by SCREEN Holdings Co., Ltd. (registered trademark).

[0034] In the semiconductor wafer 13 to be inspected in the embodiment, a predetermined amount of warpage and a predetermined direction of curvature are generated according to the element structure of the semiconductor wafer 13 by a process of thinning the semiconductor wafer 13 by polishing (or grinding, or both) from either of the main surfaces (first and second main surfaces) 13a and 13b to a predetermined thickness in the manufacturing process of the semiconductor device. The warpage of the semiconductor wafer 13 refers to a cross-sectional shape of the semiconductor wafer 13 that is curved in a convex shape (convex downward) protruding in a direction toward the stage 11 (curving direction) (FIG. 1), or a cross-sectional shape that is curved in a convex shape (convex upward) protruding in a direction away from the stage 11 (FIG. 2).

[0035] The center of the semiconductor wafer 13 is a chip effective area (not shown) in which an area (hereinafter referred to as a chip area: not shown) that will become a semiconductor chip after the semiconductor wafer 13 is diced (cut) is arranged. The chip effective area has dicing lines arranged in a lattice pattern and a plurality of chip areas of approximately rectangular planar shape arranged in a matrix pattern surrounded by the dicing lines. Between the chip effective area and the end (side surface) of the semiconductor wafer 13 is an invalid area 13c in which no chip area is arranged. The invalid area 13c of the semiconductor wafer 13 is provided along the outer periphery of the semiconductor wafer 13 and surrounds the periphery of the chip effective area.

[0036] In the semiconductor wafer 13, semiconductor devices such as IGBTs, MOSFETs, and diodes that employ a vertical element structure in which a main current flows in the depth direction or thickness direction (opposite to the depth direction) are formed in each chip region. Metal electrodes are formed on both sides of the semiconductor wafer 13. A portion of one main surface (either main surface 13a or 13b) that is the front surface of the semiconductor wafer 13, except for the metal electrodes, is covered with a protective film formed of a resin material, and the other main surface that is the back surface is entirely covered with the metal electrodes. The thickness of the semiconductor wafer 13 is reduced to a thickness according to the on-resistance and withstand voltage of the power semiconductor device.

[0037] The stage 11 is, for example, a pedestal having flat both surfaces (first and second surfaces) 11a and 11b of a substantially circular planar shape with a diameter equal to or larger than the diameter of the semiconductor wafer 13. The stage 11 has a first holding portion 11c for holding the semiconductor wafer 13 on the outer periphery of the surface (mounting surface) 11a on which the semiconductor wafer 13 is placed. The first holding portion 11c is a protruding portion that protrudes in a direction away from the mounting surface 11a of the stage 11, and contacts at its apex portion an ineffective region 13c of the main surface (opposing surface: here, the case where the main surface 13a faces) of the semiconductor wafer 13 facing the stage 11, and holds the semiconductor wafer 13 at a height position where the semiconductor wafer 13 does not contact the mounting surface 11a of the stage 11.

[0038] The first holding portion 11c may be supported by the stage 11 in a movable state so that the height position of its apex from the mounting surface 11a of the stage 11 in the vertical direction (raised in a direction away from the mounting surface 11a of the stage 11, and lowered in a direction towards the mounting surface 11a of the stage 11) can be changed. The first holding portion 11c may be configured to move up and down so long as the height position of the apex of the first holding portion 11c from the mounting surface 11a of the stage 11 is changed, and the first holding portion 11c may be configured to raise or lower the entirety, or the length (height) of the first holding portion 11c may be configured to expand and contract in the vertical direction.

[0039] The height position of the semiconductor wafer 13 from the mounting surface 11a of the stage 11 can be changed by moving the first holding part 11c. For this reason, for example, the height position of the apex of the first holding part 11c is raised to a position where the semiconductor wafer 13 does not contact the mounting surface 11a of the stage 11, and then the semiconductor wafer 13 is placed on the mounting surface 11a of the stage 11 and held by the first holding part 11c. Thereafter, before correcting the warpage of the semiconductor wafer 13, the height position of the apex of the first holding part 11c may be lowered to a level where the semiconductor wafer 13 does not contact the mounting surface 11a of the stage 11, thereby narrowing the gap between the semiconductor wafer 13 and the stage 11.

[0040] By raising the height position of the apex of first holding portion 11c and then contacting first holding portion 11c with opposing surface 13a of semiconductor wafer 13, for example, when semiconductor wafer 13 is warped in a downward convex shape, it is possible to prevent the apex at approximately the center of opposing surface 13a of semiconductor wafer 13 from contacting mounting surface 11a of stage 11. In addition, by narrowing the gap between semiconductor wafer 13 and stage 11 and then correcting the warp of semiconductor wafer 13 as described below, it is possible to adjust the pressure (air pressure) between semiconductor wafer 13 and stage 11 with good controllability in a short time.

[0041] The first holding parts 11c may be, for example, scattered along the outer periphery of the mounting surface 11a of the stage 11 (see FIG. 3), or may have a circular planar shape extending along the outer periphery of the mounting surface 11a of the stage 11 (not shown). A second holding part 17a may be provided in contact with the invalid area 13c of the inspection surface (the main surface opposite to the facing surface 13a) 13b of the semiconductor wafer 13 at a position farther from the mounting surface 11a of the stage 11 than the first holding part 11c. The cross-sectional shape and arrangement of the second holding part 17a are, for example, plane-symmetrical to the first holding part 11c with respect to the semiconductor wafer 13 mounted on the first holding part 11c (see FIG. 3).

[0042] The second holding portion 17a is, for example, a protrusion protruding toward the stage 11 from a fixing jig 17 having a substantially circular frame-like planar shape disposed opposite the mounting surface 11a of the stage 11. The fixing jig 17 has, for example, substantially the same outer dimensions as the stage 11, and is supported by a columnar support portion 18 in a state in which its own height position from the mounting surface 11a of the stage 11 can be changed in the up-down direction 19 (vertical double arrow) (raised in a direction away from the mounting surface 11a of the stage 11, and lowered in a direction approaching the mounting surface 11a of the stage 11). "Substantially the same outer dimensions" means that the fixing jig 17 has substantially the same outer circumference within a range including the allowable error due to variations in the molding process.

[0043] For example, the length of the support portion 18 expands or contracts in the vertical direction 19, thereby changing the height position of the fixing jig 17 from the mounting surface 11a of the stage 11, and determining the height position of the second holding portion 17a arranged on the fixing jig 17 from the mounting surface 11a of the stage 11. The second holding portion 17a contacts the invalid area 13c of the inspection surface 13b of the semiconductor wafer 13 at its apex, and holds the semiconductor wafer 13 at a height position where the semiconductor wafer 13 does not contact the mounting surface 11a of the stage 11. The invalid area 13c of the semiconductor wafer 13 is sandwiched between the apexes of the first and second holding portions 11c and 17a, thereby fixing the semiconductor wafer 13 on the stage 11.

[0044] By providing the second holding part 17a, it is possible to suppress the positional deviation of the semiconductor wafer 13 compared to the case where the semiconductor wafer 13 is held only by the first holding part 11c. For example, after the semiconductor wafer 13 having a downwardly convex warp is placed on the apex part of the first holding part 11c, the invalid area 13c of the semiconductor wafer 13 is pressed downward against the first holding part 11c from the inspection surface 13b side by the second holding part 17a. This makes it possible to correct the warp of the semiconductor wafer 13 slightly and prevent the apex part at the approximate center of the facing surface 13a of the semiconductor wafer 13 from contacting the mounting surface 11a of the stage 11.

[0045] The first and second holding parts 11c, 17a are formed of a resin material that does not easily adhere to the semiconductor wafer 13. If the first and second holding parts 11c, 17a were formed of a resin material that easily adheres to the semiconductor wafer 13, such as Teflon (registered trademark), the semiconductor wafer 13 would be adversely affected by the matter adhering to the first and second holding parts 11c, 17a. Also, if a part of the first and second holding parts 11c, 17a comes off at the contact point with the semiconductor wafer 13, the semiconductor wafer 13 would be misaligned. Specifically, the first and second holding parts 11c, 17a are preferably formed of, for example, PEEK (polyether ether ketone) resin.

[0046] A plurality of air intake holes 15 and air supply holes 16 are arranged at a distance from each other on the mounting surface 11a of the stage 11. The air intake holes 15 and air supply holes 16 may penetrate the stage 11 between both surfaces (flat surfaces) 11a and 11b, or may penetrate the stage 11 from the mounting surface 11a to a side surface. The semiconductor wafer 13 placed on the stage 11 is pulled toward the stage 11 at a portion facing the air intake holes 15, and is pushed away from the stage 11 at a portion facing the air supply holes 16. For this reason, the arrangement, number and diameter of the air intake holes 15 and the air supply holes 16 are set so that the warpage of the semiconductor wafer 13 is corrected.

[0047] The arrangement, number and diameter of the intake holes 15 and the supply holes 16 are obtained in advance based on the diameter and thickness of the semiconductor wafer 13, the amount of warping (the distance between the stage 11 and the semiconductor wafer 13 in the plane), the direction of curvature (the direction of convex curvature), etc. As described above, the amount of warping and the direction of curvature of the semiconductor wafer 13 are determined according to the element structure formed in the chip region. Therefore, these conditions may be obtained, for example, by empirical rules or simulations based on experiments and actual inspections. By using the stage 11 manufactured under these previously obtained conditions, the warping of the semiconductor wafer 13 can be corrected, and the semiconductor wafer 13 can be made closer to flat.

[0048] For example, a semiconductor wafer 13 that is warped in a downward convex shape will be farthest from the stage 11 near the periphery and closest to the stage 11 near the center (see FIG. 1). For this reason, a stage 11 is prepared in which an intake hole 15 is arranged at a position on the mounting surface 11a facing the periphery of the semiconductor wafer 13, and an air supply hole 16 (16a) is arranged at a position facing the vicinity of the center of the semiconductor wafer 13. This stage 11 pulls the vicinity of the periphery of the semiconductor wafer 13 toward the stage 11, and pushes the vicinity of the center of the semiconductor wafer 13 away from the stage 11, so that the warpage of the semiconductor wafer 13 is corrected.

[0049] On the other hand, a semiconductor wafer 13 that has a warp that is convex upward is closest to the stage 11 near the periphery and farthest from the stage 11 near the center (see FIG. 2). For this reason, a stage 11 is prepared in which an intake hole 15 is arranged at a position on the mounting surface 11a facing the vicinity of the center of the semiconductor wafer 13, and an air supply hole 16 (16b) is arranged at a position facing the periphery of the semiconductor wafer 13. This stage 11 pushes the vicinity of the periphery of the semiconductor wafer 13 away from the stage 11, and pulls the vicinity of the center of the semiconductor wafer 13 toward the stage 11, so that the warp of the semiconductor wafer 13 is corrected.

[0050] Specifically, the intake holes 15 are preferably arranged substantially uniformly over the entire surface of the mounting surface 11a of the stage 11, like the pores of porous ceramic. For example, the intake holes 15 may be arranged radially from the center of the stage 11 at predetermined intervals (see FIG. 4). The intake holes 15 have an opening on the mounting surface 11a side of the stage 11 facing the semiconductor wafer 13, and the other opening is connected to an external suction device (e.g., a vacuum pump: suction means) via a pipe 33 (see FIGS. 4 to 6). The intake holes 15 are preferably grouped into predetermined sections 31a to 31c of the mounting surface 11a of the stage 11, and each section is connected to a different suction device via a different pipe 33.

[0051] As a result, the intake holes 15 for each of the predetermined sections 31a to 31c can be connected to different suction devices via different pipes 33, and the air between the opposing surface 13a of the semiconductor wafer 13 and the intake holes 15 can be sucked in at different intake volumes for each of the predetermined sections 31a to 31c. The arrangement, number and diameter of the intake holes 15 may be changed for each of the predetermined sections 31a to 31c. Figures 5 and 6 show a case where the intake holes 15 in the predetermined section 31c of the mounting surface 11a of the stage 11 (hatched portion) are connected to a suction device via a pipe 33c. The intake holes 15 in the predetermined sections 31a and 31b may also be connected to different suction devices in the same manner as the intake holes 15 in the predetermined section 31c shown in Figures 5 and 6.

[0052] By operating the suction device, the atmosphere (air) between the semiconductor wafer 13 and the stage 11 is sucked through the suction hole 15 via the pipe 33 (downward arrow in Figs. 1 and 2). This reduces the pressure between the opposing surface 13a of the semiconductor wafer 13 and the suction hole 15, generating a negative pressure, which pulls the semiconductor wafer 13 toward the stage 11 at the portion facing the suction hole 15. A general pressure controller (vacuum pump) can be used as the suction device. Specifically, the suction device may be, for example, a pressure switch PS6 (trademark) from Nidec Copal Electronics Corporation (trademark).

[0053] The air supply holes 16 may be arranged at positions where the distance between the semiconductor wafer 13 and the stage 11 is relatively small (see FIGS. 1 and 2), or may be arranged at predetermined intervals on the mounting surface 11a of the stage 11 (for example, arranged scattered radially from the center of the stage 11) (see FIG. 4). The opening of the air supply holes 16 on the mounting surface 11a side of the stage 11 faces the semiconductor wafer 13, and the other opening is connected to an external air supply device (for example, an air supply pump or compressed gas cylinder: air supply means) via a pipe 32 (see FIGS. 4 and 5). The air supply holes 16 are preferably grouped into predetermined sections 31a to 31c of the mounting surface 11a of the stage 11, and each section is connected to a different suction device via a different pipe 32.

[0054] As a result, the air supply holes 16 for each of the predetermined sections 31a to 31c can be connected to different suction devices via different pipes 32, and air can be supplied between the opposing surface 13a of the semiconductor wafer 13 and the air supply holes 16 at different supply rates for each of the predetermined sections 31a to 31c. The arrangement, number and diameter of the air supply holes 16 may be changed for each of the predetermined sections 31a to 31c. FIG. 5 shows a case where the air supply holes 16 in the predetermined section 31c of the mounting surface 11a of the stage 11 (hatched portion) are connected to an air supply device via a pipe 32c. The air supply holes 16 in the predetermined sections 31a and 31b may also be connected to different air supply devices, similar to the air supply hole 16 in the predetermined section 31c shown in FIG. 5.

[0055] By operating the air supply device, gas (air) is supplied from the air supply hole 16 through the pipe 32 between the semiconductor wafer 13 and the stage 11 (upward arrow in Figs. 1 and 2). This increases the pressure (air pressure) between the opposing surface 13a of the semiconductor wafer 13 and the air supply hole 16, and the semiconductor wafer 13 is pushed up in a direction away from the stage 11 at the portion facing the air supply hole 16. A general pressure control meter (pump) can be used as the air supply device. Specifically, the air supply device may be, for example, a pressure switch PS6 (trademark) from Nidec Copal Electronics Corporation (trademark), similar to the suction device connected to the air intake hole 15.

[0056] 4 shows a case where the number of air supply holes 16 is greater than the number of air intake holes 15 and the diameter of air supply holes 16 is greater than the diameter of air intake holes 15, but as described above, the arrangement, number and diameter of each of air intake holes 15 and air supply holes 16 are set in advance based on the state of semiconductor wafer 13 (diameter, thickness, amount of warping, curvature direction). Furthermore, by adjusting the amount of air intake at air intake hole 15 and the amount of air supply at air supply hole 16, the same stage 11 can be used for any warping state (amount of warping and curvature direction) of semiconductor wafer 13. The amount of air intake at air intake hole 15 and the amount of air supply at air supply hole 16 may be obtained in advance based on the state of semiconductor wafer 13.

[0057] When both main surfaces 13a, 13b of semiconductor wafer 13 are inspected, semiconductor wafer 13 is curved in a downward convex shape when one main surface faces stage 11, and is curved in an upward convex shape when the other main surface faces stage 11. In this case, stages 11 corresponding to both main surfaces 13a, 13b of semiconductor wafer 13 may be prepared. Alternatively, a single stage 11 in which the arrangement, number and diameter of intake holes 15 and air supply holes 16 are set so as to be applicable to any warpage state of semiconductor wafer 13 may be used to adjust the intake air amount at intake hole 15 and the supply air amount at air supply hole 16.

[0058] The configuration of the inspection head 12 is similar to that of the inspection head 122 of a general semiconductor wafer visual inspection device (see FIG. 9). The inspection head 12 has an optical lens that forms an image of an object at a predetermined focal depth (imaging range), and an imaging means that images (or observes) the object. The inspection head 12 is disposed facing the semiconductor wafer 3 (object) placed on the mounting surface 11a of the stage 11. The inspection head 12 images a main surface (inspection surface) 3b of the semiconductor wafer 3 facing the inspection head 12 while being moved (scanned) parallel to the mounting surface 11a of the stage 11 by a moving means (not shown).

[0059] When photographing with the inspection head 12, the semiconductor wafer 3 on the stage 11 is in a substantially flat state with warpage corrected. The substantially flat state of the semiconductor wafer 3 means that the absolute value of the amount of change in the distance h1 between the inspection head 12 and the inspection surface 3b of the semiconductor wafer 3 is approximately 0 mm or more and 0.1 mm or less within the plane of the inspection surface 3b of the semiconductor wafer 3. Since the semiconductor wafer 3 on the stage 11 is in a substantially flat state, the focal depth h2 of the inspection head 12 is kept constant within the plane of the inspection surface 3b of the semiconductor wafer 3, and photographing can be performed in focus at both the center side and the outer periphery of the semiconductor wafer 3.

[0060] A method for inspecting a semiconductor wafer 3 using semiconductor inspection equipment 10a, 10b (see FIGS. 1 to 6) according to the embodiment will be described. A predetermined vertical element structure is formed on semiconductor wafer 13 by a general semiconductor device manufacturing method. When this element structure is formed, semiconductor wafer 13 is thinned, causing warping of semiconductor wafer 13. Therefore, after semiconductor wafer 13 is placed on first holder 11c of stage 11 of semiconductor inspection equipment 10a, 10b according to the embodiment, warping of semiconductor wafer 13 is corrected on stage 11 before inspection surface 13b of semiconductor wafer 13 is photographed by inspection head 12.

[0061] To correct the warpage of the semiconductor wafer 13, first, the arrangement, number and diameter of each of the intake holes 15 and the air supply holes 16 of the stage 11 are acquired based on the state of the semiconductor wafer 13 (diameter, thickness, amount of warpage, curvature direction) as described above (acquisition step). The amount of intake air at the intake hole 15 and the amount of supply air at the air supply hole 16 may also be acquired based on the state of the semiconductor wafer 13 and the conditions of the intake hole 15 and the air supply hole 16. In this case, a predetermined number of intake holes 15 may be connected to different suction devices for each of predetermined sections 31a to 31c of the mounting surface 11a of the stage 11, and a predetermined number of air supply holes 16 may be connected to different air supply devices.

[0062] Next, a stage 11 that satisfies the acquired conditions for the intake holes 15 and the supply holes 16 is prepared and attached to the semiconductor inspection devices 10a and 10b according to the embodiment. Next, the semiconductor wafer 13 is placed on the placement surface 11a of the stage 11 with the main surface (opposing surface 13a) opposite to the inspection surface (main surface 13b in Figs. 1 and 2) facing the stage 11, and is held by the first holding part 11c (holding step). At this time, if a fixing jig 17 (see Fig. 3) is provided, the semiconductor wafer 13 may be further held by the second holding part 17a from the inspection surface 13b side of the semiconductor wafer 13 so that the semiconductor wafer 13 is sandwiched between the first and second holding parts 11c and 17a.

[0063] Next, the suction device and the air supply device are operated simultaneously to suck the air between the semiconductor wafer 13 and the stage 11 through the air intake holes 15 at a previously acquired air intake volume (air intake process), and to supply gas between the semiconductor wafer 13 and the stage 11 through the air supply holes 16 at a previously acquired air supply volume (air supply process). As a result, the semiconductor wafer 13 is pulled toward the stage 11 at the portion facing the air intake holes 15, and is pushed up in a direction away from the stage 11 at the portion facing the air supply holes 16, so that the warp can be corrected without the opposing surface 3a of the semiconductor wafer 3 coming into contact with the stage 11. This makes it possible to suppress the occurrence of new defects in the semiconductor wafer 3.

[0064] Next, the inspection head 12 takes an image of the entire inspection surface 3b of the semiconductor wafer 3 in one scan 14 (horizontal arrow) (imaging step), and the captured image is stored in a storage means (not shown), and a calculation means (not shown) judges whether each chip area of ​​the semiconductor wafer 3 is good or bad based on the captured image and previously acquired information. Since the semiconductor wafer 3 is in a substantially flat state with warpage corrected, the distance h1 from the inspection head 12 is substantially constant over the entire surface of the inspection surface 3b. Therefore, it is possible to perform a visual inspection of the entire inspection surface 3b of the semiconductor wafer 3 while maintaining a constant focal depth h2.

[0065] It is advisable to set the conditions of the intake hole 15 and the supply hole 16 and the intake and supply amounts of the gas by considering the balance of the gas flow between the semiconductor wafer 13 and the stage 11 within the surface of the semiconductor wafer 3. The stage 11, the inspection head 12, the transport means, the calculation means, the suction device, the supply device, etc. are controlled by the control means (not shown) of the semiconductor inspection devices 10a, 10b. The method for inspecting the semiconductor wafer 13 according to this embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation, a database server, or a web server.

[0066] Furthermore, a program for implementing the method for inspecting semiconductor wafer 13 according to this embodiment is recorded on a computer-readable recording medium such as a solid state drive (SSD), a hard disk, a Blu-ray (registered trademark) disc (BD), a flexible disk, a USB flash memory, a CD-ROM, an MO, or a DVD, and is executed by being read from the recording medium by a computer or a server. Furthermore, this program may be a transmission medium that can be distributed via a network such as the Internet.

[0067] 7, the warpage occurring in the thin central portion can be corrected while the wafer is placed on the stage 11 in the same manner as the normal semiconductor wafer 13. The rib-shaped semiconductor wafer 43 is produced by thinning the central portion of a semiconductor wafer having a substantially uniform thickness by polishing (or grinding, or both) from one main surface 43a side, and leaving the peripheral portion, which becomes the invalid region 43c, thicker than the central portion by a predetermined width along the periphery. The substantially uniform thickness means that the thickness is the same within a range including the allowable error due to process variations.

[0068] In the rib-shaped semiconductor wafer 43, a warp occurs in the central portion where the thickness is reduced, which curves upward or downward in a convex shape. FIG. 7 shows a rib-shaped semiconductor wafer 43 in which the central portions of both main surfaces 43a, 43b are curved so as to protrude in a convex shape toward the main surface 43a side where a step occurs due to the thickness difference between the central portion and the outer periphery. The rib-shaped semiconductor wafer 43 is placed on the placement surface 11a of the stage 11 with the main surface (opposing surface) 43a where a step occurs due to the thickness difference between the central portion and the outer periphery facing the stage 11, for example, and is held by the first holding part 11c. A portion (rib) 43d where the outer periphery of the rib-shaped semiconductor wafer 43 remains thick contacts the first holding part 11c.

[0069] As described above, according to the embodiment, the stage of the semiconductor inspection device has, on a mounting surface on which the semiconductor wafer is placed, a holder for holding the semiconductor wafer, an intake hole for sucking gas between the semiconductor wafer and the stage, an intake hole for supplying gas between the semiconductor wafer and the stage, and an inspection head for inspecting the appearance of the semiconductor wafer. The mounting surface of the stage has a plurality of intake holes and an intake hole with a position, number and diameter that are obtained and determined in advance based on the state of the semiconductor wafer. The semiconductor wafer is held by the holder on the mounting surface of the stage so as not to come into contact with the mounting surface of the stage.

[0070] In this state, gas is sucked from the space between the semiconductor wafer and the stage through the intake holes, and gas is supplied between the semiconductor wafer and the stage through the intake holes. As a result, the semiconductor wafer is pulled toward the stage at the portion facing the intake holes, and is pushed up in a direction away from the stage at the portion facing the intake holes, so that warping of the semiconductor wafer can be corrected without the semiconductor wafer coming into contact with the stage. This makes it possible to suppress the occurrence of defects in the semiconductor wafer during inspection of the semiconductor wafer, and to reliably detect defects that occur during the formation of element structures on the semiconductor wafer (defects that occur other than during inspection of the semiconductor wafer).

[0071] According to the embodiment, the semiconductor wafer is inspected in a substantially flat state after the warpage is corrected, so that the distance between the inspection head and the inspection surface of the semiconductor wafer is substantially constant, and the semiconductor wafer can be inspected in a state in which the focal depth is kept constant across the inspection surface of the semiconductor wafer. This makes it possible to suppress the occurrence of defects during the inspection of the semiconductor wafer, and to continuously inspect the adjacent chip regions of the semiconductor wafer with stable inspection sensitivity. Moreover, by correcting the warpage of the semiconductor wafer on the stage, the focal depth is kept constant, so that the semiconductor wafer can be inspected automatically.

[0072] The present invention is not limited to the above-mentioned embodiment, and various modifications are possible within the scope of the present invention. For example, in the above-mentioned embodiment, the external inspection of the semiconductor wafer is performed in an air atmosphere, but the present invention is not limited to this, and the external inspection of the semiconductor wafer may be performed in an atmosphere of a gas other than the air. The ... [Industrial Applicability]

[0073] As described above, the semiconductor inspection apparatus and semiconductor wafer inspection method according to the present invention are useful for semiconductor wafers having vertical element structures, and are particularly suitable for large-diameter semiconductor wafers. [Explanation of symbols]

[0074] 3. Semiconductor wafer with warpage corrected 3a, 3b Main surface of semiconductor wafer after warpage has been corrected 10a, 10b Semiconductor inspection equipment 11 Stage 11a, 11b Stage surface (flat surface) 11c Stage holder 12 Inspection Head 13 Semiconductor wafer before warping is corrected 13a, 13b Main surface of semiconductor wafer before warpage is corrected 13c Ineffective area of ​​semiconductor wafer before warpage correction 14 Inspection head scanning direction 15 Stage Air Intake 16 Stage air intake 17 Fixture 17a Fixture holder 18 Fixture support 19 Fixture movement direction (up and down) 31a~31c Classification of stage mounting surface 32,32c,33,33c Pipe 43 Rib-shaped semiconductor wafer 43a, 43b Rib-shaped semiconductor wafer main surface 43c Ineffective area of ​​rib-shaped semiconductor wafer 43d Rib-shaped semiconductor wafer rib h1 Distance between the inspection head and the inspection surface of the semiconductor wafer h2 depth of focus

Claims

1. a stage on which a semiconductor wafer is placed; a first holding portion provided to protrude from a first surface of the stage on which the semiconductor wafer is placed, the first holding portion being in contact with a portion of a first main surface of the semiconductor wafer facing the stage and holding the semiconductor wafer at a position away from the first surface of the stage; a plurality of intake holes, each having an opening on one side and connected to an intake means at a predetermined position on a first surface of the stage, for sucking in gas between the semiconductor wafer and the stage; a plurality of air supply holes, each having an opening on one side and connected to an air supply means at a predetermined position on a first surface of the stage, for supplying gas between the semiconductor wafer and the stage; an imaging means for imaging a second main surface of the semiconductor wafer opposite to the stage; Equipped with the air intake hole and the air supply hole are provided on a first main surface of the stage at positions that are acquired in advance based on a warpage state of the semiconductor wafer, a first surface of the stage that is disposed adjacent to the first surface of the stage and that faces the stage and that faces the stage, and that faces the stage and ...

2. 2. The semiconductor inspection device according to claim 1, wherein the first holding portion holds the semiconductor wafer by contacting an outer periphery of the first main surface of the semiconductor wafer.

3. 3. The semiconductor inspection apparatus according to claim 1, wherein the first holding portion is supported on the first surface of the stage in a movable state so as to move the semiconductor wafer in a direction away from the first surface of the stage and in a direction toward the first surface of the stage.

4. The semiconductor inspection device according to any one of claims 1 to 3, further comprising a second holding part provided opposite the first holding part, contacting a portion of the second main surface of the semiconductor wafer, and holding the semiconductor wafer between the first holding part and the second holding part.

5. The air intake holes are grouped into predetermined sections of the first surface of the stage and are connected to different air intake means, 5. The semiconductor inspection device according to claim 1, wherein control is performed to suck in gas between the semiconductor wafer and the stage with a different intake amount for each of the predetermined sections.

6. The air supply holes are grouped into predetermined sections of the first surface of the stage and are connected to different air supply means, 5. The semiconductor inspection device according to claim 1, wherein control is performed to supply gas between the semiconductor wafer and the stage at different amounts of gas for each of the predetermined sections.

7. A stage for placing a semiconductor wafer thereon; a first holding portion provided to protrude from a first surface of the stage on which the semiconductor wafer is placed, the first holding portion being in contact with a portion of a first main surface of the semiconductor wafer facing the stage and holding the semiconductor wafer at a position away from the first surface of the stage; a second holding part provided opposite to the first holding part, contacting a portion of a second main surface of the semiconductor wafer and holding the semiconductor wafer between the first holding part and the second holding part; a plurality of intake holes, each having an opening on one side and connected to an intake means at a predetermined position on a first surface of the stage, for sucking in gas between the semiconductor wafer and the stage; a plurality of air supply holes, each having an opening on one side and connected to an air supply means at a predetermined position on a first surface of the stage, for supplying gas between the semiconductor wafer and the stage; an imaging means for imaging a second main surface of the semiconductor wafer opposite to the stage; Equipped with a first surface of the stage that is disposed adjacent to the first surface of the stage and that faces the stage and that faces the stage, and that faces the stage and ...

8. a holding step of holding the semiconductor wafer at a position away from the first surface of the stage by bringing a part of a first main surface of the semiconductor wafer facing the stage in a warped state into contact with a first holding portion provided so as to protrude from a first surface of the stage on which the semiconductor wafer is placed; a suction step of sucking gas between the semiconductor wafer and the stage through a plurality of suction holes, the suction holes having openings on one side at predetermined positions on a first surface of the stage and connected to a suction means on the other side; an air supply step of supplying gas between the semiconductor wafer and the stage from a plurality of air supply holes, each having an opening on one side thereof provided at a predetermined position on a first surface of the stage and the other opening thereof connected to an air supply means; an imaging step of imaging a second main surface of the semiconductor wafer opposite to the stage side with an imaging means; Including, The method further includes, before the holding step, acquiring positions of the air intake hole and the air supply hole of the first main surface of the stage based on a warpage state of the semiconductor wafer, In the holding step, the stage is used, in which the air intake hole and the air supply hole are arranged on the first main surface at the positions acquired in the acquiring step, a first surface of the stage that is disposed on the first surface of the stage and that is parallel to the first surface of the stage;

9. A holding process comprising: bringing a part of a first main surface of the semiconductor wafer in a warped state that faces the stage into contact with a first holding portion provided protruding from a first surface of the stage on which the semiconductor wafer is placed, thereby holding the semiconductor wafer at a position away from the first surface of the stage; and further bringing a part of a second main surface of the semiconductor wafer into contact with a second holding portion provided opposite the first holding portion, thereby holding the semiconductor wafer between the first holding portion and the semiconductor wafer; a suction step of sucking gas between the semiconductor wafer and the stage through a plurality of suction holes, the suction holes having openings on one side at predetermined positions on a first surface of the stage and connected to a suction means on the other side; an air supply step of supplying gas between the semiconductor wafer and the stage from a plurality of air supply holes, each having an opening on one side thereof provided at a predetermined position on a first surface of the stage and the other opening thereof connected to an air supply means; an imaging step of imaging a second main surface of the semiconductor wafer opposite to the stage side with an imaging means; Including, a first surface of the stage that is disposed on the first surface of the stage and that is parallel to the first surface of the stage;

Images