Analog-to-digital conversion circuit using output signal feedback, operation method thereof, and image sensor

Abstract

To provide an analog-to-digital conversion circuit with power consumption reduced by using output signal feedback and an operation method thereof, and an image sensor including the same.SOLUTION: An analog-to-digital conversion circuit of the present invention comprises: a first amplifier that compares a reset signal of a pixel signal output from a pixel array with a ramp signal in a first operation section and compares an image signal of the pixel signal with the ramp signal in a second operation section to generate one output signal; a second amplifier that generates a second output signal based on a first output signal; and a counter that counts the pulse of the second output signal and outputs a result of the counting as a digital signal. During at least one operation section of the first operation section and the second operation section, the first output signal controls a first power current of the first amplifier, or the second output signal controls the first power current of the first amplifier or a second power current of the second amplifier.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an analog-to-digital conversion circuit, and more particularly to an analog-to-digital conversion circuit using feedback of an output signal, a method of operating the same, and an image sensor. [Background technology]

[0002] There are several types of image sensors, including CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide Semiconductor) image sensors (CIS). CMOS image sensors contain pixels made of CMOS transistors, and convert light energy into electrical signals using the photoelectric conversion elements contained in each pixel. CMOS image sensors obtain information about the captured image using the electrical signals generated from each pixel.

[0003] An analog-to-digital converter (ADC) receives an analog input voltage generated by a pixel and converts it into a digital signal. The converted digital signal is then transferred to another device. ADCs are used in a variety of signal processing devices. As the performance of modern signal processing devices improves, improved resolution for analog signals is required. Therefore, ADCs that process many signals in the same time and provide improved resolution for each signal are used, but they have the problem of increased power consumption. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 10,616,518 [Patent Document 2] U.S. Pat. No. 7,304,599 [Patent Document 3] U.S. Pat. No. 8,035,066 [Patent Document 4] U.S. Patent No. 10,230,915 [Patent Document 5] U.S. Pat. No. 10,021,329 [Patent Document 6] U.S. Pat. No. 10,694,131 [Patent Document 7] U.S. Patent No. 7,227,488 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems in the conventional technology, and an object of the present invention is to provide an analog-to-digital conversion circuit having reduced power consumption using feedback of an output signal, an operating method thereof, and an image sensor including the same. [Means for solving the problem]

[0006] In order to achieve the above object, an analog-to-digital conversion circuit according to one aspect of the present invention includes a first amplifier that compares a reset signal of a pixel signal output from a pixel array with a ramp signal in a first operating interval and compares an image signal of the pixel signal with the ramp signal in a second operating interval to generate a first output signal, a second amplifier that generates a second output signal based on the first output signal, and a counter that counts pulses of the second output signal and outputs the counting result as a digital signal, wherein the first output signal controls a first power supply current of the first amplifier, or the second output signal controls the first power supply current of the first amplifier or the second power supply current of the second amplifier during at least one operating interval of the first operating interval and the second operating interval.

[0007] In order to achieve the above object, an image sensor according to one aspect of the present invention includes a pixel array that converts light into an electrical signal to generate a pixel signal, a ramp signal generator that generates a ramp signal, and an analog-to-digital conversion circuit that converts the pixel signal into a digital signal, wherein the analog-to-digital conversion circuit includes a first amplifier that compares a reset signal of the pixel signal with the ramp signal in a first operating interval and compares an image signal of the pixel signal with the ramp signal in a second operating interval to generate a first output signal, a second amplifier that generates a second output signal based on the first output signal, and a counter that counts pulses of the second output signal and outputs the counting result as a digital signal, and during at least one operating interval of the first operating interval and the second operating interval, the first output signal controls a first power supply current of the first amplifier, or the second output signal controls the first power supply current of the first amplifier or the second power supply current of the second amplifier.

[0008] In order to achieve the above-mentioned object, an operating method of an analog-to-digital conversion circuit according to one aspect of the present invention includes a step of comparing a pixel signal output from a pixel array with a ramp signal to generate a first output signal, a step of generating a second output signal based on the first output signal, and a step of controlling a power supply current of the analog-to-digital conversion circuit using the first output signal or the second output signal. Effect of the Invention

[0009] According to the present invention, it is possible to reduce the power consumption of an analog-to-digital conversion circuit, and in particular, it is possible to improve the performance degradation of an image sensor by reducing the power consumption of the analog-to-digital conversion circuit included in an image sensor. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram showing an example of a configuration of an image processing block according to an embodiment of the present invention. [Diagram 2]FIG. 2 is a diagram illustrating an example of the configuration of an image sensor in FIG. [Diagram 3] FIG. 3 is a circuit diagram illustrating an example of one of the pixel groups in the pixel array of FIG. 2. [Figure 4] 3 is a diagram illustrating an example of the configuration of an analog-to-digital conversion ADC circuit in FIG. 2. [Diagram 5] 5 is a timing diagram illustrating an example of the operation of the analog-to-digital conversion ADC circuit of FIG. [Figure 6] 5 is a circuit diagram showing an example of a first amplifier of FIG. 4. [Figure 7] 5 is a circuit diagram showing an example of a second amplifier of FIG. 4. [Figure 8A] 8 is a timing diagram showing an example of the operation of the analog-to-digital conversion ADC circuit of FIG. 4 due to the operation of the feedback circuit of FIG. 7. [Figure 8B] 8 is a timing diagram showing an example of the operation of the analog-to-digital conversion ADC circuit of FIG. 4 by the operation of the control circuit of FIG. 7. [Figure 9] 5 is a circuit diagram showing another example of the second amplifier of FIG. 4. [Figure 10] 5 is a circuit diagram showing another example of the second amplifier of FIG. 4. [Figure 11] 5 is a circuit diagram showing another example of the second amplifier of FIG. 4. [Figure 12] 5 is a circuit diagram showing another example of the second amplifier of FIG. 4. [Figure 13] 3 is a diagram illustrating another example of the configuration of the analog-to-digital conversion ADC circuit of FIG. 2. [Figure 14] 14 is a circuit diagram showing an example of a first amplifier of FIG. 13. [Figure 15] 4 is a flow chart illustrating a method of operating an analog-to-digital conversion circuit using output feedback in accordance with one embodiment of the present invention. [Figure 16] FIG. 1 is a diagram showing an example of the configuration of an electronic device including an analog-to-digital conversion circuit using output feedback according to an embodiment of the present invention. [Figure 17] FIG. 17 is a diagram illustrating an example of the configuration of the camera module of FIG. 16. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings.

[0012] All of the embodiments described herein are exemplary and not limiting, and may be implemented in various forms. Each of the embodiments provided in the following description is not excluded from being related to other embodiments or one or more features of other embodiments that may or may not be provided herein but are consistent with the concept of the present invention.

[0013] As used herein, phrases such as "at least one of," when preceding a list of elements, do not modify the entire list of elements or the individual elements of the list. For example, the phrase "at least one of a, b, and c" should be understood to include a only, b only, c only, both a and b, both a and c, both b and c, or all of a, b, and c.

[0014] The components described with reference to terms such as part or unit, module, block, device (or, er) and the functional blocks illustrated in the drawings may be implemented in the form of software, hardware, or a combination thereof. For example, software is machine code, firmware, embedded code, and application software. For example, hardware includes an electric circuit, an electronic circuit, a processor, a computer, an integrated circuit, an integrated circuit core, a pressure sensor, an inertial sensor, a MEMS (Micro Electro Mechanical Systems), a passive element, or a combination thereof.

[0015] 1 is a diagram showing an example of the configuration of an image processing block 10 according to an embodiment of the present invention. The image processing block 10 can be implemented as part of a variety of electronic devices such as a smartphone, a digital camera, a laptop, or a desktop. The image processing block 10 includes a lens 12, an image sensor 14, an ISP front end block 16, and an image signal processor 18.

[0016] Light is reflected by an object, a scene, etc. to be photographed, and the lens 12 receives the reflected light. The image sensor 14 generates an electrical signal based on the optical signal received through the lens 12. For example, the image sensor 14 is realized by a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like. For example, the image sensor 14 is a multi-pixel image sensor having a dual pixel structure or a tetracell structure.

[0017] The image sensor 14 includes a pixel array. The pixels of the pixel array convert optical signals into electrical signals to generate pixel values. In addition, the image sensor 14 includes an Analog-to-Digital Converting (ADC) Circuit (ADC) for performing Correlation Double Sampling (CDS) on the pixel values. The configuration of the image sensor 14 will be described in more detail with reference to FIG. 2.

[0018] The ISP front-end block 16 performs pre-processing on the electrical signal output from the image sensor 14 to convert it into a form suitable for processing by the image signal processor 18 .

[0019] The image signal processor 18 appropriately processes the electrical signals processed by the ISP front end block 16 to generate image data related to the photographed object, scene, etc. To this end, the image signal processor 18 performs various processes such as color correction, auto white balance, gamma correction, color saturation correction, bad pixel correction, hue correction, etc.

[0020] 1 shows one lens 12 and one image sensor 14. However, in another embodiment, the image processing block 10 includes multiple lenses, multiple image sensors, and multiple ISP front-end blocks, where the multiple lenses have different angles of view, and the multiple image sensors have different functions, performance, and / or characteristics and include pixel arrays with different configurations.

[0021] Fig. 2 is a diagram showing an example of the configuration of the image sensor 14 in Fig. 1. The image sensor 100 includes a pixel array 110, a row driver 120, a ramp signal generator 130, a voltage buffer 140, an ADC circuit 150, a timing controller 160, and a buffer 170.

[0022] The pixel array 110 includes a plurality of pixels arranged in a matrix along rows and columns, each of which includes a photoelectric conversion element, such as a photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0023] The pixel array 110 includes a number of pixel groups PG. Each pixel group PG includes two or more pixels. The pixels that make up a pixel group share a floating diffusion region or multiple floating diffusion regions. Although the pixel array 110 of FIG. 2 is shown to include four rows and four columns (i.e., 4×4) of pixel groups PG, the present invention is not so limited.

[0024] The pixel groups PG include pixels of the same color, for example, red pixels that convert optical signals in the red spectral region into electrical signals, green pixels that convert optical signals in the green spectral region into electrical signals, or blue pixels that convert optical signals in the blue spectral region into electrical signals, for example, the pixels that make up the pixel array 110 are arranged in the form of a Tetra-Bayer Pattern.

[0025] Each of the pixels of the pixel array 110 outputs a pixel signal along the column lines (CL1 to CL4) in response to the intensity or amount of light received from the outside. For example, the pixel signal is an analog signal corresponding to the intensity or amount of light received from the outside. The pixel signal passes through a voltage buffer (for example, a source follower) and is provided to the ADC circuit 150 via the column lines (CL1 to CL4).

[0026] The row driver 120 selects and drives rows of the pixel array 110. The row driver 120 decodes addresses and / or control signals generated by the timing controller 160 to generate control signals for selecting and driving rows of the pixel array 110. For example, the control signals include signals for selecting pixels, signals for resetting floating diffusion regions, etc.

[0027] The ramp signal generator 130 generates the ramp signal RAMP under the control of the timing controller 160. For example, the ramp signal generator 130 operates under a control signal such as a ramp enable signal. When the ramp enable signal is activated, the ramp signal generator 130 generates the ramp signal RAMP according to a predetermined value (e.g., a start level, an end level, a slope, etc.). In other words, the ramp signal RAMP is a signal that increases or decreases according to a predetermined slope for a specific time. The ramp signal RAMP is provided to the ADC circuit 150 through the voltage buffer 140.

[0028] The ADC circuit 150 receives pixel signals from a plurality of pixels of the pixel array 110 via column lines (CL1-CL4) and receives a ramp signal RAMP from the ramp signal generator 130 via a voltage buffer 140. The ADC circuit 150 operates based on a correlated double sampling CDS technique that obtains a reset signal and an image signal for the received pixel signal and extracts the difference into a useful signal component. The ADC circuit 150 includes a plurality of comparators COMP and a counter CNT.

[0029] Specifically, the comparator COMP compares the reset signal of the pixel signal with the ramp signal RAMP, and compares the image signal of the pixel signal with the ramp signal RAMP to perform correlated double sampling CDS. The counter CNT counts pulses of the correlated double sampled signal and outputs it as a digital signal. Note that the ADC circuit 150 of the present invention is implemented to reduce power consumption using output feedback. Although the ADC circuit 150 of FIG. 2 is shown to include four comparators COMP and four counters CNT, the present invention is not limited thereto.

[0030] The timing controller 160 generates control signals and / or clocks for controlling the operation and / or timing of each of the row driver 120, the ramp signal generator 130, and the ADC circuit 150.

[0031] The buffer 170 includes a memory MEM and a sense amplifier SA. The memory MEM stores a digital signal output from a corresponding counter CNT of the ADC circuit 150. The sense amplifier SA senses and amplifies the stored digital signal. The sense amplifier SA outputs the amplified digital signal as image data IDAT, which is transferred to the ISP front-end block 16 of FIG. 1.

[0032] Fig. 3 is a circuit diagram showing an example of any one of the pixel groups PG of the pixel array 110 of Fig. 2. For example, the pixel group 111 includes pixels (111a to 111d), photoelectric conversion elements (PD1 to PD4), transfer transistors (Tx1 to Tx4), a reset transistor RST, a dual conversion transistor DC, a drive transistor Dx, and a selection transistor SEL. Although the pixel group 111 of Fig. 3 is shown to have a tetracell structure in which four pixels (111a to 111d) each include a photoelectric conversion element (PD1 to PD4), the present invention is not limited thereto, and the pixel group 111 may be implemented to have various other structures.

[0033] The first pixel 111a includes a first photoelectric conversion element PD1 and a first transfer transistor Tx1, and the other pixels (111b, 111c, and 111d) include similar components. Each of the pixels (111a to 111d) shares a reset transistor RST, a dual conversion transistor DC, a drive transistor Dx, and a selection transistor SEL. In addition, each of the pixels (111a to 111d) shares a floating diffusion region FD.

[0034] The dual conversion transistor DC is driven by a dual conversion signal VDC. When the dual conversion transistor DC is turned off, the floating diffusion region FD is coupled to the first floating diffusion capacitor CFD1. The capacitance of the floating diffusion region FD corresponds to the capacitance of the first floating diffusion capacitor CFD1.

[0035] When the dual conversion transistor DC is turned on, the floating diffusion region FD is coupled not only to the first floating diffusion capacitor CFD1 but also to the second floating diffusion capacitor CFD2. The extended floating diffusion region FD' represents the floating diffusion region when the dual conversion transistor DC is turned on. The second floating diffusion capacitor CFD2 is provided to prevent saturation. For example, the floating diffusion capacitors (CFD1, CFD2) are parasitic capacitors and / or capacitor elements.

[0036] The transfer transistors (Tx1 to Tx4) are driven by transfer signals (VT1 to VT4), respectively, and transfer the charges generated by the photoelectric conversion elements (PD1 to PD4) to the floating diffusion region FD or the extended floating diffusion region FD'. For example, one end of each of the transfer transistors (Tx1 to Tx4) is connected to the photoelectric conversion elements (PD1 to PD4), respectively, and the other end is connected to the floating diffusion region FD.

[0037] The floating diffusion region FD or the expanded floating diffusion region FD' accumulates charges corresponding to the amount of incident light. While the transfer transistors (Tx1 to Tx4) are turned on by the transfer signals (VT1 to VT4), the floating diffusion region FD or the expanded floating diffusion region FD' accumulates charges provided from the photoelectric conversion elements (PD1 to PD4). The floating diffusion region FD is connected to the gate terminal of the drive transistor Dx operated as a source follower amplifier, so that a voltage corresponding to the charges accumulated in the floating diffusion region FD is formed.

[0038] The reset transistor RST is driven by a reset signal VRST and provides the power supply voltage VDD to the floating diffusion region FD or the extended floating diffusion region FD', so that the charge stored in the floating diffusion region FD or the extended floating diffusion region FD' moves to the power supply voltage VDD terminal and the voltage of the floating diffusion region FD or the extended floating diffusion region FD' is reset.

[0039] The driving transistor Dx amplifies the voltage of the floating diffusion region FD or the extended floating diffusion region FD' to generate a pixel signal PIX. The selection transistor SEL is driven by a selection signal VSEL to select the pixel to be read out row by row. When the selection transistor SEL is turned on, the pixel signal PIX is output to the ADC circuit 150 of FIG. 2 via the column line CL.

[0040] Fig. 4 is a diagram showing an example of the configuration of the analog-to-digital conversion ADC circuit 150 of Fig. 2. The ADC circuit 150 includes a comparator 151 and a counter 152. The ADC circuit 150 converts a pixel signal PIX, which is an analog signal output from the pixel array 110, into a digital signal DS and outputs the digital signal DS. For clear explanation and simplicity of the drawings, the pixel array 110 of Fig. 4 shows only one pixel, and the configuration and function of the pixel array 110 are the same as those described with reference to Fig. 3.

[0041] Specifically, as described with reference to FIG 2, the comparator 151 performs correlated double sampling (CDS) by comparing a reset signal of the pixel signal with the ramp signal RAMP and comparing an image signal of the pixel signal with the ramp signal RAMP. The counter 152 counts pulses of the correlated double sampled signal and outputs the counted signal as a digital signal. Hereinafter, the description will be made with reference to FIG 2 and FIG 3 as well as FIG 4.

[0042] For example, the comparator 151 has a two-stage structure including two amplifiers (a first amplifier (first amplifier) ​​151_1 and a second amplifier (second amplifier) ​​151_2), and the first amplifier 151_1 and the second amplifier 151_2 are implemented as operational transconductance amplifiers (OTAs), but the present invention is not limited thereto. For example, the comparator 151 may have a structure including more amplifiers. Note that the ADC circuit 150 may include multiple comparators and counters, but for the sake of clarity, FIG. 4 shows one comparator 151 and one counter 152.

[0043] The first amplifier 151_1 receives the pixel signal PIX from the pixel array 110 through the column line CL, and receives the ramp signal RAMP from the ramp signal generator 130 through the voltage buffer 140. The first amplifier 151_1 outputs a first output signal OTA1_OUT based on the received signal. For example, the first amplifier 151_1 outputs a first output signal OTA1_OUT having a high level during a period in which the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, and outputs a first output signal OTA1_OUT having a low level during a period in which the level of the ramp signal (RAMP) is lower than the level of the pixel signal PIX. The comparison operation of the first amplifier 151_1 described above is performed both between the reset signal of the pixel signal PIX and the ramp signal RAMP, and between the image signal of the pixel signal PIX and the ramp signal RAMP.

[0044] The second amplifier 151_2 amplifies the first output signal OTA1_OUT and outputs the second output signal OTA2_OUT, which is a comparison signal. For example, the second output signal OTA2_OUT is an inverted signal of the first output signal OTA1_OUT. In other words, the second amplifier 151_2 is implemented to output the second output signal OTA2_OUT having a low level while the first output signal OTA1_OUT has a high level, and to output the second output signal OTA2_OUT having a high level while the first output signal OTA1_OUT has a low level.

[0045] Furthermore, the second output signal OTA2_OUT is fed back to the second amplifier 151_2. The second output signal OTA2_OUT fed back to the second amplifier 151_2 controls the power supply (eg, a current source) of the second amplifier 151_2, thereby reducing the power consumption of the ADC circuit 150.

[0046] The above-mentioned output feedback operation of the second amplifier 151_2 is performed both when the first amplifier 151_1 performs a comparison operation between the reset signal of the pixel signal PIX and the ramp signal RAMP and when it performs a comparison operation between the image signal of the pixel signal PIX and the ramp signal RAMP.

[0047] In the following description, the comparison operation of the comparator 151 and the change in the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT from high level to low level or from low level to high level will be referred to as the determination of the ADC circuit 150.

[0048] In other words, "after the determination of the ADC circuit 150 is completed" means "after the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT changes from a high level to a low level, or from a low level to a high level." The comparator 151 is initialized in response to the auto-zero signal AZ in the auto-zero section before the comparison operation is performed, and performs the comparison operation again.

[0049] The counter 152 operates under the control of the timing controller 160, counts the pulses of the corresponding second output signal OTA2_OUT, and outputs the counted pulses as a digital signal DS. For example, the counter 152 operates under control signals such as a count clock signal CNT_CLK and an inversion signal CONV that inverts an internal bit of the counter 152.

[0050] For example, the counter 152 includes an up / down counter and a bit-wise inversion counter. The bit-wise counter performs the same operation as the up / down counter. For example, the bit-wise counter performs only an up-counting function and a function of inverting all bits in the counter to create 1's complement when a specific signal is input. The bit-wise counter performs a reset count, and then inverts the result to convert it to a 1's complement (i.e., a negative number).

[0051] FIG 5 is a timing diagram showing an example of the operation of the analog-to-digital conversion ADC circuit 150 of FIG 4. Referring to FIG 5, an auto-zero section is defined from time t0 to time t1, and a comparison operation section is defined from time t1 to time t10. Before time t0, a selection signal VSEL is activated, and pixel signals PIX are output from a plurality of pixel groups (e.g., pixel groups as shown in FIG 3) of the pixel array of FIG 2. In addition, a power supply voltage is provided by a reset signal VRST activated before time t0. The following description will be made with reference to FIG 4 together with FIG 5.

[0052] The auto-zero signal AZ is activated from time t0 to time t1, and the comparator 151 is initialized in response to the auto-zero signal AZ. For example, the voltage levels of the input node and / or output node of the first amplifier 151_1 and the second amplifier 151_2 become the same. For digital conversion of the reset signal of the pixel signal PIX, an offset is added to the ramp signal RAMP at time t2, and the ramp signal RAMP is decreased from time t3. The counter 152 counts the count clock signal CNT_CLK from time t3 to time t4 when the polarity of the second output signal OTA2_OUT, which is the output of the second amplifier 151_2, changes.

[0053] After the digital conversion of the reset signal is completed, an offset is again added to the ramp signal RAMP at time t5 to convert the image signal of the pixel signal PIX into a digital signal at time t5, and the bit of the counter 152 is inverted in response to the inversion signal CONV at time t6. At time t7, the transfer signal VT is activated, and the voltage level of the input node of the first amplifier 151_1 that receives the pixel signal PIX changes due to the charge accumulated by the photoelectric conversion element PD during that time.

[0054] At time t8, the level of the ramp signal RAMP decreases in order to digitally convert the image signal. The counter 152 counts the count clock signal CNT_CLK from time t8 to time t9 when the polarity of the second output signal OTA2_OUT, which is the output of the second amplifier 151_2, changes. When the digital conversion of the image signal is completed, the ADC circuit 150 is initialized for the next comparison operation (i.e., correlated double sampling).

[0055] Although the operation timing of the ADC circuit 150 has been described with reference to FIG. 5, the present invention is not limited to this, and the signal timing can be changed depending on the implementation method of the ADC circuit 150 (e.g., the structures of the first amplifier 151_1 and the second amplifier 151_2, etc.).

[0056] Fig. 6 is a circuit diagram showing an example of the first amplifier 151_1 of Fig. 4. The first amplifier 200 includes a plurality of transistors (TR11 to TR15) and a first current source 210. For example, the first transistor TR11, the second transistor TR12, and the fifth transistor TR15 are NMOS transistors, and the third transistor TR13 and the fourth transistor TR14 are PMOS transistors. However, the present invention is not limited thereto, and the first to fifth transistors (TR11 to TR15) may be transistors of different types from those shown in Fig. 6.

[0057] 6, a pixel signal PIX is input to the gate terminal of a first transistor TR11, and a ramp signal RAMP is input to the gate terminal of a second transistor TR12. Source terminals of the first and second transistors TR11 and TR12 are commonly connected to a first current source 210. For example, the third and fourth transistors TR13 and TR14 are connected in the form of a current mirror. The sum of the currents flowing through the first and second transistors TR11 and TR12 is equal to a first power supply current ISS1.

[0058] The gate terminal and the drain terminal of the third transistor TR13 and the drain terminal of the first transistor TR11 are commonly connected to the second output node OUT12, and the drain terminal of the fourth transistor TR14 and the drain terminal of the second transistor TR12 are commonly connected to the first output node OUT11. The fifth transistor TR15 is connected between the first output node OUT11 and the second output node OUT12. For example, the fifth transistor TR15 limits the voltage level of the signal output from the first output node OUT11.

[0059] A first output signal OTA1_OUT is output from the first output node OUT11. For example, the first output signal OTA1_OUT has a high level during a period in which the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, and has a low level during a period in which the level of the ramp signal RAMP is lower than the level of the pixel signal PIX. The first output signal OTA1_OUT is provided to the second amplifier 151_2 of FIG.

[0060] Fig. 7 is a circuit diagram showing an example of the second amplifier 151_2 of Fig. 4. The second amplifier 300 includes a plurality of transistors (TR21 to TR26), a capacitor C1, a switching circuit 310, a second current source 320, a feedback circuit 330, and a control circuit 340. For example, the sixth transistor TR21 is a PMOS transistor, and the seventh to eleventh transistors (TR22 to TR26) are NMOS transistors. However, the present invention is not limited thereto, and the sixth to eleventh transistors (TR21 to TR26) may be transistors of a different type from those shown in Fig. 6.

[0061] The sixth transistor TR21 receives the first output signal OTA1_OUT from the first amplifier 151_1 of FIG. 4 as an input and operates in response to the first output signal OTA1_OUT. For example, when the voltage level of the first output signal OTA1_OUT is high, the sixth transistor TR21 is turned off and no current flows to the third output node OUT21, so that the voltage level of the second output signal OTA2_OUT is low. Conversely, when the voltage level of the first output signal OTA1_OUT is low, the sixth transistor TR21 is turned on and a current flows to the third output node OUT21, so that the voltage level of the second output signal OTA2_OUT is high.

[0062] In other words, the second amplifier 300 operates as an inverting amplifier. That is, when the voltage level of the first output signal OTA1_OUT increases, the voltage level of the second output signal OTA2_OUT decreases. In addition, when the sixth transistor TR21 turns on, a current also flows through the seventh transistor TR22. The second output signal OTA2_OUT is transferred to the feedback circuit 330.

[0063] The seventh transistor TR22 is connected between the third output node OUT21 and the fourth output node OUT22. The seventh transistor TR22 operates in response to the output of the feedback circuit 330 that controls the output feedback operation. For example, when the seventh transistor TR22 is turned off, the second power supply current ISS2 does not flow through the seventh transistor TR22, so that the power consumption of the second amplifier 300 is reduced.

[0064] However, the invention is not so limited and the seventh transistor TR22 may be implemented to be coupled in ways other than that shown in Figure 7. Additionally, although the seventh transistor TR22 is shown as being an NMOS transistor, it may be implemented as a combination of a PMOS transistor and a logic gate (e.g., an AND gate).

[0065] The switching circuit 310 includes an eighth transistor TR23 coupled between the third output node OUT21 and a bias node BN. During the auto-zero period, the eighth transistor TR23 operates in response to the auto-zero signal AZ and is turned on in response to the activated auto-zero signal AZ. When the eighth transistor TR23 is turned on, the voltage level of the bias node BN becomes equal to the voltage level of the third output node OUT21.

[0066] On the other hand, when the auto-zero signal AZ is inactivated and the eighth transistor TR23 is turned off while the ADC circuit 150 of FIG. 4 is performing a comparison operation, the voltage level of the bias node BN, which becomes equal to the voltage level of the third output node OUT21, is maintained by the capacitor C1, thereby operating the second current source 320.

[0067] 7 is shown as being connected between the third output node OUT21 and the bias node BN, the present invention is not limited thereto, and the eighth transistor TR23 may be connected between the fourth output node OUT22 and the bias node BN. In this case, when the eighth transistor TR23 is turned on in response to an activated auto-zero signal AZ, the voltage level of the bias node BN becomes equal to the voltage level of the fourth output node OUT22.

[0068] The second current source 320 includes a ninth transistor TR24 coupled to the fourth output node OUT22. The ninth transistor TR24 generates a power supply current ISS based on the voltage of the bias node BN, that is, the voltage of one end of the capacitor C1.

[0069] The feedback circuit 330 controls the second current source 320 based on the second output signal OTA2_OUT and the feedback enable signal FB_EN. To perform such an output feedback operation, the feedback circuit 330 includes a logic gate 331. For example, the logic gate 331 is a NAND gate.

[0070] The logic gate 331 outputs a feedback signal FB in response to the second output signal OTA2_OUT and the feedback activation signal FB_EN. For example, the logic gate 331 is implemented such that when the voltage level of the feedback activation signal FB_EN and the voltage level of the second output signal OTA2_OUT are both high levels, the voltage level of the feedback signal FB is low.

[0071] When the voltage level of the feedback signal FB is high, the seventh transistor TR22 is turned on and the second power supply current ISS2 flows through the seventh transistor TR22. However, when the voltage level of the feedback signal FB is low, the seventh transistor TR22 is turned off and the second power supply current ISS2 cannot flow through the seventh transistor TR22.

[0072] Specifically, after the comparison between the ramp signal RAMP and the pixel signal PIX is completed, the voltage level of the first output signal OTA1_OUT is low and the voltage level of the second output signal OTA2_OUT is high. At this time, before the feedback enable signal FB_EN is activated, the feedback signal FB is high, the seventh transistor TR22 is turned on, and the second power supply current ISS2 flows through the seventh transistor TR22.

[0073] On the other hand, when the feedback activation signal FB_EN is activated (i.e., the voltage level of the feedback activation signal FB_EN becomes high), the feedback signal FB becomes low and the seventh transistor TR22 is turned off, so that the second power supply current ISS2 does not flow through the seventh transistor TR22. As a result, by utilizing the output feedback after the comparison operation is completed, the power consumption of the second amplifier 300 is reduced, and the power consumption of the ADC circuit 150 is also reduced.

[0074] If the difference in power consumption before and after the comparison operation continues, the performance of the image sensor (e.g., the performance of the ADC circuit that converts pixel signals into digital signals) may deteriorate. After the comparison operation is performed by the operation of the feedback circuit 330 described above, when the second power supply current ISS2 stops flowing through the output nodes (OUT21, OUT22), the difference in power consumption before and after the comparison operation decreases. Therefore, the problem of performance deterioration of the image sensor can be improved by the operation of the feedback circuit 330.

[0075] On the other hand, although the logic gate 331 in FIG. 7 is shown as a NAND gate, the present invention is not so limited and the feedback circuit 330 may be implemented as any other configuration (e.g., as a NOR gate and an inverting amplifier) ​​that results in the voltage level of the feedback signal FB being low when the voltage level of the second output signal OTA2_OUT is high.

[0076] Although the feedback circuit 330 in FIG. 7 is shown as being directly input with the second output signal OTA2_OUT, the present invention is not limited thereto. For example, the feedback circuit 330 in FIG. 7 may receive another signal based on the second output signal OTA2_OUT. For example, the second amplifier 300 may further include a transistor, a switch, an inverter, or a logic gate coupled between the sixth transistor TR21 and the third output node OUT21. In this case, the logic gate 331 of the feedback circuit 330 receives a signal obtained by passing the second output signal OTA2_OUT through the transistor, the switch, the inverter, or the logic gate, and performs the comparison operation as described above.

[0077] In other words, the feedback circuit 330 may receive the second output signal OTA2_OUT as is, or the second output signal OTA2_OUT may be input as a signal that has passed through a transistor, switch, inverter, or logic gate between the sixth transistor TR21 and the third output node OUT21.

[0078] The control circuit 340 adjusts the output of the control current ICN to reduce the difference in power consumption of the second amplifier 300 before and after the comparison operation. The control circuit 340 is connected between the power supply voltage VDD and the third output node OUT21 and includes tenth and eleventh transistors TR25 and TR26 connected in parallel to the sixth transistor TR21. The tenth transistor TR25 operates in response to a control signal CN, and the eleventh transistor TR26 operates in response to a bias signal BIAS.

[0079] When the control signal CN is deactivated, the tenth transistor TR25 is turned off and the control current ICN does not flow through the eleventh transistor TR26. On the other hand, when the control signal CN is activated and the tenth transistor TR25 is turned on, and the bias signal BIAS is applied and the eleventh transistor TR26 is also turned on, the control current ICN flows to the output nodes (OUT21, OUT22) through the tenth transistor TR25 and the eleventh transistor TR26.

[0080] After the level of the ramp signal RAMP and the level of the pixel signal PIX are compared, the level of the second power supply current ISS2 becomes high, and power continues to be consumed even after the comparison operation is performed. If the difference in power consumption before and after the comparison operation is sustained as described above, the performance of the image sensor may be degraded.

[0081] The control circuit 340 operates to prevent such degradation of the image sensor performance. After the ramp signal RAMP starts to ramp, as the control signal CN and the bias signal BIAS are activated, the control current ICN flows through the tenth and eleventh transistors TR25 and TR26 to the output nodes OUT21 and OUT22 as described above, and the level of the second power supply current ISS2 increases by the level of the control current ICN.

[0082] For example, the level of the second power supply current ISS2 (hereinafter referred to as the second level), which has increased by the level of the control current ICN after the ramp signal RAMP begins to ramp, is higher than the level of the second power supply current ISS2 (hereinafter referred to as the first level) before the comparison operation is performed, and is lower than the level of the second power supply current ISS2 (hereinafter referred to as the third level) after the comparison operation is performed (i.e., after the determination of the magnitude relationship between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX is completed).

[0083] By such an operation of the control circuit 340, the difference between the first level and the second level and the difference between the second level and the third level are both smaller than the difference between the first level and the third level, thereby reducing the difference in power consumption before and after the comparison operation of the second amplifier 300 and improving the performance degradation of the image sensor.

[0084] Therefore, the performance degradation of the image sensor caused by the difference in power consumption before and after the comparison operation is improved by the operation of the feedback circuit 330 or the operation of the control circuit 340. For example, when the second current source 320 is controlled using the output feedback of the feedback circuit 330, the operation of the control circuit 340 is not required. In such a case, the second amplifier 300 does not include the control circuit 340. An example of the second amplifier 300 not including the control circuit 340 will be described with reference to FIG. 9.

[0085] Fig. 8A is a timing diagram showing an example of the operation of ADC circuit 150 in Fig. 4 due to the operation of feedback circuit 330 in Fig. 7, and Fig. 8B is a timing diagram showing an example of the operation of ADC circuit 150 in Fig. 4 due to the operation of control circuit 340 in Fig. 7. Below, a description will be given with reference to Figs. 4 to 7 as well as Figs. 8A to 8B, but the operation of ADC circuit 150 that overlaps with that described in Fig. 5 will be omitted.

[0086] 8A and 8B, the period before section T1 corresponds to the auto-zero section, sections T1 to T3 correspond to sections in which the comparator 151 compares the reset signal of the pixel signal PIX with the ramp signal RAMP, and sections T4 to T6 correspond to sections in which the comparator 151 compares the image signal of the pixel signal PIX with the ramp signal RAMP.

[0087] 8A, the feedback active signal FB_EN is activated when the determination of the ADC circuit 150 ends (i.e., when the period T2 ends and when the period T5 ends). For example, the voltage level of the feedback active signal FB_EN is maintained at a high level during the period (T2 to T3) and / or the period (T5 to T6) in which the ramp signal RAMP is ramped.

[0088] Based on the feedback enable signal FB_EN and the second output signal OTA2_OUT, the feedback circuit 330 outputs a feedback signal FB. In response to the low level feedback signal FB, a transistor (e.g., the seventh transistor TR22 in FIG. 7) between the current source 320 and the output node is turned off, and the second power supply current ISS2 does not flow.

[0089] Therefore, the level of the second power supply current ISS2 is maintained approximately the same throughout the sections (T1 to T3) and (T4 to T6) by the operation of the feedback circuit 330. For example, the level of the second power supply current ISS2 is close to zero throughout the sections (T1 to T3) and (T4 to T6). This reduces the power consumption of the ADC circuit 150.

[0090] 8B, the voltage level of the control signal CN is activated during the period from section T2 to section T3 and from section T5 to section T6 in which the ramp signal RAMP is ramped. In response to the activated control signal CN, the control circuit 340 outputs a control current ICN to the output nodes (OUT21, OUT22). As a result, the level of the second power supply current ISS2 in sections T2 and T5 is increased by the level of the control current ICN compared to the level of the second power supply current ISS2 in sections T1 and T4, respectively. Therefore, the operation of the control circuit 340 reduces the difference in the level of the second power supply current ISS2 between sections T1 and T3 and between sections T4 and T6 (i.e., the difference in power consumption).

[0091] In the above-described embodiment, the comparison operation of the comparator 151 is performed based on the ramp signal RAMP, which is a ramping-up signal generated by the ramp signal generator 130. However, according to an embodiment, the comparison operation may also be performed based on a ramp signal RAMP, which is a ramping-down signal.

[0092] Fig. 9 is a circuit diagram showing another example of the second amplifier 151_2 of Fig. 4. As described with reference to Fig. 7, when the second current source 320 is controlled using the output feedback of the feedback circuit 330, the second amplifier 300 may not include the control circuit 340. The configuration and function of the second amplifier 300a shown in Fig. 9 are the same as those of the second amplifier 300 of Fig. 7, except that the control circuit 340 of Fig. 7 is not included, and therefore a duplicated description will be omitted.

[0093] Fig. 10 is a circuit diagram showing another example of the second amplifier 151_2 of Fig. 4. The feedback circuit 330 of the second amplifier 300b includes a plurality of logic gates (331, 332). The second amplifier 300b includes transistors (TR22, TR23) corresponding to the logic gates (331, 332), respectively. Furthermore, the second current source 320 of the second amplifier 300b is implemented to output a first sub-power supply current ISS2_1 and a second sub-power supply current ISS2_2.

[0094] Although the second current source 320 in FIG. 10 is shown to output two sub-power supply currents (ISS2_1, ISS2_2), the present invention is not limited thereto, and the current source 320 may be implemented to output more sub-power supply currents. Similarly, although the feedback circuit 330 in FIG. 10 is shown to include two logic gates (331, 332), the present invention is not limited thereto, and the feedback circuit 330 may include more logic gates, and the second amplifier 300b may include more transistors corresponding to each of the logic gates. In the following, a description that overlaps with the configuration and function of the second amplifier 300 in FIG. 7 will be omitted.

[0095] The first logic gate 331 outputs a first feedback signal FB1 in response to the second output signal OTA2_OUT and the first feedback activation signal FB_EN1, and the second logic gate 332 outputs a second feedback signal FB2 in response to the second output signal OTA2_OUT and the second feedback activation signal FB_EN2.

[0096] Even if the same second output signal OTA2_OUT is input to the feedback circuit 330, the seventh transistor TR22 or the eighth transistor TR23 is selectively turned on or off in response to the first feedback activation signal FB_EN1 and the second feedback activation signal FB_EN2. When the seventh transistor TR22 or the eighth transistor TR23 is selectively turned on or off, the sub power supply currents (ISS2_1, ISS2_2) also selectively flow.

[0097] By selectively controlling the sub-power supply currents (ISS2_1, ISS2_2) in this manner, the level of current consumed by the second amplifier 300b is gradually controlled, and the power consumption of the second amplifier 300b is gradually reduced. Although the logic gates (331, 332) in Figure 10 are shown as NAND gates, the invention is not so limited and feedback circuit 330 may be embodied in other configurations.

[0098] 4, 7, and 10, the second amplifier 151_2 of the ADC circuit 150 of the present invention can reduce the power consumption of the ADC circuit 150 by gradually reducing the current consumed by the second amplifier 151_2 by turning off the second power supply current ISS2 as shown in FIG. 7, or by selectively controlling the sub-power supply currents (ISS2_1, ISS2_2) as shown in FIG. 10.

[0099] Fig. 11 is a circuit diagram showing another example of the second amplifier 151_2 of Fig. 4. The second current source 320 of the second amplifier 300c is implemented to output the first sub-power supply current ISS_1 and the second sub-power supply current ISS_2, similar to the second current source 320 of Fig. 10. However, the feedback circuit 330 of the second amplifier 300c includes one logic gate 331, and the second amplifier 300c includes a seventh transistor TR22 corresponding to the logic gate 331. In the following, a description overlapping with the configuration and function of the second amplifier (second amplifier) ​​300 of Fig. 7 will be omitted.

[0100] Depending on the turn-on or turn-off state of the seventh transistor TR22 operating in response to the first feedback signal FB1, the first sub-power supply current ISS2_1 flows selectively, but the second sub-power supply current ISS2_2 is not controlled by the feedback circuit 330. In other words, even if the second amplifier 151_2 of the ADC circuit 150 of the present invention is implemented to flow a plurality of sub-power supply currents, only some of the sub-power supply currents are selectively controlled, and the remaining sub-power supply currents are not controlled.

[0101] FIG. 12 is a circuit diagram showing another example of the second amplifier 151_2 of FIG. 4. As described with reference to FIG. 7 and FIG. 9, when the second current source 320 is controlled using the output feedback of the feedback circuit 330, the second amplifier 300 may not include the control circuit 340. The configuration and function of the second amplifier 300d shown in FIG. 12 are similar to those of the second amplifier 300b of FIG. 10 except that the control circuit 340 is not included, so that the overlapping description will be omitted. FIG. 13 is a diagram showing another example of the configuration of the analog-to-digital conversion circuit ADC circuit 150 of FIG. 2. As described with reference to FIG. 4, the second output signal OTA2_OUT is fed back to the second amplifier 151_2 to control the power supply (e.g., the current source) of the second amplifier 151_2. Note that, referring to FIG. 13, the second output signal OTA2_OUT is fed back to the voltage buffer 140 or the first amplifier 151_1 to control the power supply of the first amplifier 151_1.

[0102] Furthermore, the first output signal OTA1_OUT may also be fed back to the voltage buffer 140 or the first amplifier 151_1. The first output signal OTA1_OUT fed back to the first amplifier 151_1 controls the power supply of the first amplifier 151_1. The feedback operation of the first output signal OTA1_OUT and the second output signal OTA2_OUT can reduce the power consumption of the ADC circuit 150.

[0103] The ADC circuit 150 in FIG. 13 performs the same functions as those described with reference to FIG. 4 except for the output feedback operation described above, and therefore a duplicated description will be omitted.

[0104] Fig. 14 is a circuit diagram showing an example of the first amplifier 151_1 of Fig. 13. The first amplifier 200a of Fig. 14 includes a feedback circuit 220 that controls the first current source 210 based on the first output signal OTA1_OUT and the feedback activation signal FB_EN. The first amplifier 200a further includes a sixth transistor TR16 that operates in response to the output of the feedback circuit 220. For example, the sixth transistor TR16 is an NMOS transistor, but the present invention is not limited thereto.

[0105] The feedback circuit 220 controls the first current source 210 based on the first output signal OTA1_OUT and the feedback enable signal FB_EN. To perform such an output feedback operation, the feedback circuit 220 includes a logic gate 221. For example, the logic gate 221 is a NAND gate, but the present invention is not limited thereto.

[0106] When the sixth transistor TR16 is turned off in response to the feedback signal FB, the first power supply current ISS1 cannot flow through the sixth transistor TR16, thereby reducing the power consumption of the first amplifier 200b, and therefore the power consumption of the ADC circuit 150 also reduces.

[0107] In addition, the first output signal OTA1_OUT may be fed back to the voltage buffer 140 of FIG. 2, and the second output signal OTA2_OUT output from the second amplifier 151_2 may also be fed back to the first current source 210 via the feedback circuit 220, as described above with reference to FIG. 13.

[0108] Except for the output feedback operation described above, the functions and operations of the first amplifier 200a in FIG. 14 are the same as those of the first amplifier 200 in FIG. 6, and therefore a duplicated description will be omitted.

[0109] 15 is a flow chart illustrating a method of operating an analog-to-digital conversion circuit using output feedback according to an embodiment of the present invention, which will now be described with reference to FIGS. 2, 4 and 7 in conjunction with FIG.

[0110] In step S110, the first amplifier 151_1 generates a first output signal OTA1_OUT by comparing a pixel signal PIX output from the pixel array 110 with a ramp signal RAMP. Specifically, in step S110, the first amplifier 151_1 compares a reset signal of the pixel signal PIX with the ramp signal RAMP, and compares an image signal of the pixel signal PIX with the ramp signal RAMP to perform correlated double sampling CDS.

[0111] For example, in step S110, the first amplifier 151_1 outputs the first output signal OTA1_OUT having a high level during a period in which the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, and outputs the first output signal OTA1_OUT having a low level during a period in which the level of the ramp signal RAMP is lower than the level of the pixel signal PIX.

[0112] In step S120, the second amplifier 151_2 generates a second output signal OTA2_OUT based on the first output signal OTA1_OUT. For example, the second output signal OTA2_OUT is an inverted signal of the first output signal OTA1_OUT.

[0113] In step S130, the ADC circuit 150 controls the power supply current using the first output signal OTA1_OUT or the second output signal OTA2_OUT. Specifically, in step S130, the feedback circuit 330 controls the second current source 320 according to the second output signal OTA2_OUT and the feedback active signal FB_EN.

[0114] 16 is a diagram showing an example of the configuration of an electronic device including an analog-to-digital conversion circuit ADC using output feedback according to an embodiment of the present invention. FIG. 17 is a diagram showing an example of the configuration of the camera module of FIG.

[0115] Referring to FIG. 16 , an electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC (power management IC) 1300, and an external memory 1400.

[0116] The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). Although the figure shows an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, the embodiment is not limited thereto. In an embodiment, the camera module group 1100 may be modified to include only two camera modules. It is noted that in an embodiment, the camera module group 1100 may be modified to include n camera modules (n is a natural number equal to or greater than 4).

[0117] The detailed configuration of camera module 1100b will be described in more detail below with reference to FIG. 17, but the following description also applies to other camera modules (1100a, 1100c) depending on the embodiment.

[0118] Referring to FIG. 17, a camera module 1100b includes a prism 1105, an optical path folding element (hereinafter referred to as OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage device 1150.

[0119] The prism 1105 changes the path of a light ray L incident from the outside, including the reflecting surface 1107 of a light reflecting material.

[0120] In one embodiment, the prism 1105 changes the path of the light ray L incident in a first direction X to a second direction Y perpendicular to the first direction X. The prism 1105 changes the path of the light L incident in the first direction X to the perpendicular second direction Y by rotating a reflective surface 1107 of a light-reflecting material around a central axis 1106 in a direction A or by rotating the central axis 1106 in a direction B. At this time, the OPFE 1110 also moves in a third direction Z perpendicular to the first direction X and the second direction Y.

[0121] In one embodiment, as shown, the maximum rotation angle of prism 1105 in the A direction is less than or equal to 15 degrees in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, although the embodiment is not limited thereto.

[0122] In one embodiment, the prism 1105 moves in the plus (+) or minus (-) direction B by 20 degrees, between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees, where the angle of movement is the same angle in the plus (+) or minus (-) direction B, or to a substantially similar angle within a range of 1 degree.

[0123] In one embodiment, the prism 1105 moves the reflective surface 1107 of the light-reflective material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106 .

[0124] The OPFE 1110 includes, for example, optical lenses consisting of m groups (where m is a natural number). The m lenses move in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, if the basic optical zoom ratio of the camera module 1100b is Z, moving the m optical lenses included in the OPFE 1110 changes the optical zoom ratio of the camera module 1100b to an optical zoom ratio of 3Z, 5Z, or more than 5Z. The OPFE 1110 further includes optical lenses consisting of n groups (where n is a natural number) in front of the above-mentioned m lenses.

[0125] The actuator 1130 moves the OPFE 1110 or an optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0126] The image sensing device 1140 includes an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 senses an image of a sensing target using a light beam L provided through an optical lens. For example, an ADC circuit of the image sensor 1142 uses output feedback to reduce power consumption and improve performance degradation of the image sensor 1142. The control logic 1144 controls the overall operation of the camera module 1100b. For example, the control logic 1144 controls the operation of the camera module 1100b according to a control signal provided via a control signal line CSLb.

[0127] The memory 1146 stores information necessary for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 includes information necessary for the camera module 1100b to generate image data using a light beam L provided from the outside. The calibration data 1147 includes, for example, information on the degree of rotation, information on the focal length, information on the optical axis, etc. When the camera module 1100b is implemented in the form of a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 includes a focal length value for each position (or state) of the optical lens and information related to auto focusing.

[0128] The storage device 1150 stores image data sensed through the image sensor 1142. The storage device 1150 is disposed outside the image sensing device 1140 and is implemented in a form stacked on a sensor chip constituting the image sensing device 1140. In one embodiment, the storage device 1150 is implemented as an Electrically Erasable Programmable Read-Only Memory (EEPROM), but the embodiment is not limited thereto.

[0129] 16 and 17 together, in one embodiment, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. Accordingly, each of the multiple camera modules (1100a, 1100b, 1100c) includes the same or different calibration data 1147 due to the operation of the actuator 1130 included therein.

[0130] In one embodiment, one camera module (e.g., 1100b) of the multiple camera modules (1100a, 1100b, 1100c) is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a, 1100b) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiment is not limited thereto.

[0131] In one embodiment, one of the camera modules (1100a, 1100b, 1100c) is a vertical depth camera that extracts depth information using infrared rays (IR). In this case, the application processor 1200 can merge image data provided from the vertical depth camera with image data provided from the other camera modules (1100a or 1100b) to generate a 3D depth image.

[0132] In one embodiment, at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules (1100a, 1100b, 1100c) have different fields of view (field of view angles), for example, but not limited to, optical lenses of at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules (1100a, 1100b, 1100c) are different from each other.

[0133] In one embodiment, the viewing angles of the camera modules (1100a, 1100b, 1100c) are different from each other. In this case, the optical lenses included in the camera modules (1100a, 1100b, 1100c) are also different from each other, but this is not limited thereto.

[0134] In one embodiment, each of the multiple camera modules (1100a, 1100b, 1100c) is arranged to be physically separated from each other. That is, instead of the multiple camera modules (1100a, 1100b, 1100c) sharing the sensing area of ​​one image sensor 1142, an independent image sensor 1142 may be arranged inside each of the multiple camera modules (1100a, 1100b, 1100c).

[0135] 16 again, the application processor 1200 includes an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 is implemented separately from the multiple camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and the multiple camera modules (1100a, 1100b, 1100c) are implemented separately on separate semiconductor chips.

[0136] The image processing device 1210 includes multiple sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216.

[0137] The image processing device 1210 includes a number of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of the camera modules (1100a, 1100b, 1100c).

[0138] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding sub-image processor (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such image data transfer is performed using, for example, a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiment is not limited thereto.

[0139] Meanwhile, in one embodiment, one sub-image processor may be arranged to correspond to a plurality of camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may be integrated into one sub-image processor instead of being implemented separately from each other as shown in the figure, and image data provided from camera module 1100a and camera module 1100c may be selected via a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0140] The image data provided to each of the sub-image processors (1212a, 1212b, 1212c) is provided to an image generator 1214. The image generator 1214 generates an output image using the image data provided from each of the sub-image processors (1212a, 1212b, 1212c) according to image generation information or a mode signal.

[0141] Specifically, the image generator 1214 generates an output image by merging at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal. The image generator 1214 may select one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal to generate the output image.

[0142] In one embodiment, the image generation information includes a zoom signal or zoom factor, and in one embodiment, the mode signal is based on a mode selected by, for example, a user.

[0143] When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different viewing field (viewing angle), the image generator 1214 performs different operations according to the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 merges the image data output from the camera module 1100a with the image data output from the camera module 1100c, and generates an output image using the merged image signal and the image data output from the camera module 1100b that was not used in the merging. When the zoom signal is a second signal different from the first signal, the image generator 1214 does not merge the image data, but selects one of the image data output from each camera module (1100a, 1100b, 1100c) to generate an output image. However, the embodiment is not limited thereto, and the method of processing the image data may be variously modified as necessary.

[0144] In one embodiment, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c) and performs HDR (High Dynamic Range) processing on the multiple image data to generate merged image data with an increased dynamic range.

[0145] The camera module controller 1216 provides control signals to each of the camera modules (1100a, 1100b, 1100c). The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc).

[0146] Any one of the multiple camera modules (1100a, 1100b, 1100c) is designated as a master camera (e.g., 1100b) according to image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a, 1100c) are designated as slave cameras. Such information is included in a control signal and provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc).

[0147] The camera module operating as the master and the slave is changed according to the zoom factor or the operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor is low, the camera module 1100b operates as the master and the camera module 1100a operates as the slave. Conversely, when the zoom factor is high, the camera module 1100a operates as the master and the camera module 1100b operates as the slave.

[0148] In one embodiment, the control signals provided from the camera module controller 1216 to each of the camera modules (1100a, 1100b, 1100c) include a sync enable signal. For example, if the camera module 1100b is a master camera and the camera modules (1100a, 1100c) are slave cameras, the camera module controller 1216 sends a sync enable signal to the camera module 1100b. The camera module 1100b that has received such a sync enable signal generates a sync signal based on the provided sync enable signal and provides the generated sync signal to the camera modules (1100a, 1100c) via a sync signal line SSL. The camera module 1100b and the camera modules (1100a, 1100c) send image data to the application processor 1200 in synchronization with such a sync signal.

[0149] In one embodiment, the control signal provided from the camera module controller 1216 to the camera modules (1100a, 1100b, 1100c) includes mode information corresponding to the mode signal, and based on such mode information, the camera modules (1100a, 1100b, 1100c) operate in a first operation mode and a second operation mode associated with a sensing speed.

[0150] In a first operation mode, the multiple camera modules (1100a, 1100b, 1100c) generate image signals at a first rate (e.g., generate image signals at a first frame rate), encode the image signals at a second rate higher than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and send the encoded image signals to the application processor 1200. In this case, the second rate is 30 times or less than the first rate.

[0151] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in an internal memory 1230 or an external memory 1400 of the application processor 1200, and then reads and decodes the encoded image signal from the internal memory 1230 or the external memory 1400, and displays image data generated based on the decoded image signal. For example, a corresponding sub-image processor among a plurality of sub-image processors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding, and the application processor 1200 performs image processing on the decoded image signal.

[0152] In the second operation mode, the multiple camera modules (1100a, 1100b, 1100c) generate image signals at a third rate lower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate) and transfer the image signals to the application processor 1200. The image signals provided to the application processor 1200 are unencoded signals. The application processor 1200 performs image processing on the received image signals or stores the image signals in the internal memory 1230 or the external memory 1400.

[0153] The PMIC 1300 supplies power, for example, a power supply voltage, to each of the multiple camera modules (1100a, 1100b, 1100c). For example, under the control of the application processor 1200, the PMIC 1300 supplies a first power to the camera module 1100a via a power signal line PSLa, supplies a second power to the camera module 1100b via a power signal line PSLb, and supplies a third power to the camera module 1100c via a power signal line PSLc.

[0154] In response to a power control signal PCON from the application processor 1200, the PMIC 1300 generates power corresponding to each of the multiple camera modules (1100a, 1100b, 1100c) and further adjusts the power level. The power control signal PCON includes a power adjustment signal for each operation mode of the multiple camera modules (1100a, 1100b, 1100c). For example, the operation mode includes a low power mode, and at this time, the power control signal PCON includes information on the camera module operating in the low power mode and the power level to be set. The levels of power provided to each of the multiple camera modules (1100a, 1100b, 1100c) may be the same or different. The power levels are dynamically changed.

[0155] At least one of the components, elements, modules, or units (collectively, "components" in this paragraph) represented by blocks in diagrams such as FIG. 4, FIG. 13, FIG. 16, and FIG. 17 may be implemented in any number of hardware, software, and / or firmware structures that perform the respective functions described above according to embodiments of the present invention. Such components include, but are not limited to, the first amplifier 151_1, the second amplifier 151_2, and the counter 152 shown in FIG. 14. According to embodiments of the present invention, at least one of these components may perform the respective functions through the control of one or more microprocessors or other control devices using direct circuit structures such as memories, processors, logic circuits, and look-up tables. It should be noted that at least one of these components may be specifically implemented by a module, program, or part of a code that includes one or more executable instructions for performing a particular logical function and is executed by one or more microprocessors or other control devices. It should be noted that at least one of these components may include or be implemented by a processor, microprocessor, or the like, such as a CPU (Central Processing Unit), that performs the respective function. Two or more of these components are combined into one single component that performs the operations or functions of both of the two or more combined components. However, at least a portion of the functions of at least one of such components may be performed by other of such components. Functional aspects of the above-described embodiments are implemented in algorithms executed on one or more processors. However, components represented as blocks or processing steps may use various related technologies for electronic components, signal processing, and / or control, data processing, etc.

[0156] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0157] 10 Image Processing Block 12 Lenses 14, 100, 1142 Image Sensor 16 ISP Front End Blocks 18 Image Signal Processor 110 pixel array 111 Pixel Group 111a~111d 1st~4th pixels 120 Line Driver 130 Ramp Signal Generator 140 Voltage Buffer 150 ADC circuit 151 Comparator 151_1 First amplifier (first amplifier) ​​(OTA1) 151_2 Second amplifier (OTA2) 152 Counter 160 Timing Controller 170 buffers 200, 200a First amplifier 210, 320 1st, 2nd current source 220, 330 Feedback circuit 221, 331, 332 logic gates 300, 300a, 300b, 300c, 300d Second amplifier 310 Switching Circuits 340 Control circuit 1000 electronic devices 1100 Camera Module Group 1100a~1100c Camera module 1105 Prism 1106 Center axis 1107 Reflective surface 1110 OPFE (Optical Path Folding Element) 1130 Actuator 1140 Image sensing device 1144 Control Logic 1146 Memory 1147 Calibration Data 1150 Storage Device 1200 Application Processor 1210 Image Processing Device 1212a~1212c Sub-image processor 1214 Image Generator 1216 Camera Module Controller 1220 Memory Controller 1230 Internal Memory 1300 PMIC (power management IC) 1400 External Memory AZ Autozero signal BN Bias Node BIAS Bias signal C1 Capacitor CDS Correlated Double Sampling CFD1, CFD2 1st and 2nd floating diffusion capacitors CL, CL1~CL4 column lines CN Control Signal CNT Counter CNT_CLK Count clock signal COMP Comparator CONV Inverted signal CSLa~CSLc Control signal lines DC Dual Conversion Transistor DS Digital signal Dx drive transistor FB Feedback signal FB1, FB2 First and second feedback signals FB_EN Feedback active signal FB_EN1, FB_EN2 First and second feedback enable signals FD Floating diffusion region FD' Extended floating diffusion region IDAT Image data ICN Control current ISLa~ISLc Image signal line ISS1, ISS2 1st, 2nd power supply current ISS2_1, ISS2_2 1st and 2nd sub power supply current MEM Memory OTA1_OUT, OTA2_OUT First and second output signals OUT11, OUT12 First and second output nodes OUT21, OUT22, OUT23 3rd to 5th output nodes PCON Power Control Signal PD photoelectric conversion element PG Pixel Group PD1~PD4 Photoelectric conversion elements PIX Pixel signal PSLa~PSLc Power signal line RAMP Ramp signal RST Reset transistor SA Sense Amplifier SEL Select transistor SSL Sync Signal Line TR11~TR16 1st~6th transistors TR21~TR28 6th~13th transistors Tx1 to Tx4: 1st to 4th transfer transistors VDC Dual Conversion Signal VDD Power supply voltage VRST Reset signal VSEL ​​Select signal VT, VT1~VT4 transmission signal

Claims

1. An analog-to-digital conversion circuit, comprising: a first amplifier for comparing a reset signal of a pixel signal output from a pixel array with a ramp signal during a first operating period, and for comparing an image signal of the pixel signal with the ramp signal during a second operating period to generate a first output signal; a second amplifier that generates a second output signal based on the first output signal; a counter that counts the count clock signal until the polarity of the second output signal changes and outputs the count result as a digital signal; During at least one of the first and second operating intervals, the first output signal controls a first power supply current of the first amplifier, or the second output signal controls the first power supply current of the first amplifier or the second power supply current of the second amplifier; The second amplifier is a feedback circuit that outputs a feedback signal for controlling a power supply current of the analog-to-digital conversion circuit based on the second output signal and a feedback activation signal; a first transistor for providing a power supply voltage to a first output node at which the second output signal is output in response to the first output signal; a second transistor responsive to the feedback signal to couple the first output node to a second output node; a current source coupled to the second transistor through the second output node for generating the second power supply current.

2. the second amplifier further includes a control circuit that outputs a control current in response to a control signal; The control circuit includes: a third transistor for generating the control current based on the power supply voltage in response to the control signal; a fourth transistor responsive to a bias signal to provide said control current to said first output node.

3. 3. The circuit of claim 2, wherein the control circuit outputs the control current to the current source via the first output node and the second output node when the ramp signal begins to ramp during the first operating interval or the second operating interval.

4. the feedback signal includes a first feedback signal and a second feedback signal; The second amplifier is a second transistor responsive to the first feedback signal to couple the first output node to a second output node; a third transistor responsive to the second feedback signal to couple the first output node to a third output node; the current source is coupled to the second transistor through the second output node and to the third transistor through the third output node to generate the second power supply current; 2. The circuit of claim 1, wherein the second power supply current comprises a first sub-power supply current flowing through the second transistor and a second sub-power supply current flowing through the third transistor.

5. The feedback circuit includes: a first logic gate that outputs the first feedback signal based on the second output signal and a first feedback activation signal; a second logic gate configured to output the second feedback signal based on the second output signal and a second feedback activation signal; the second transistor is turned off in response to the first feedback signal; 5. The circuit of claim 4, wherein the third transistor is turned off in response to the second feedback signal.

6. the current source is coupled to the second transistor via the second output node and to a third transistor via the first output node to generate the second power supply current; 2. The circuit of claim 1, wherein the second power supply current comprises a first sub-power supply current flowing through the second transistor and a second sub-power supply current flowing through the third transistor.

7. the feedback circuit includes a first logic gate that outputs the first feedback signal based on the second output signal and a first feedback activation signal; 5. The circuit of claim 4, wherein the second transistor is turned off in response to the first feedback signal.

8. a pixel array that converts light into an electrical signal to generate a pixel signal; a ramp signal generator for generating a ramp signal; an analog-to-digital conversion circuit for converting the pixel signal into a digital signal; The analog-to-digital conversion circuit includes: a first amplifier for comparing a reset signal of the pixel signal with a ramp signal during a first operating period and for comparing an image signal of the pixel signal with the ramp signal during a second operating period to generate a first output signal; a second amplifier that generates a second output signal based on the first output signal; a counter that counts the count clock signal until the polarity of the second output signal changes and outputs the counted result as a digital signal, During at least one of the first and second operating intervals, the first output signal controls a first power supply current of the first amplifier, or the second output signal controls the first power supply current of the first amplifier or the second power supply current of the second amplifier; The second amplifier is a feedback circuit that outputs a feedback signal for controlling a power supply current of the analog-to-digital conversion circuit based on the second output signal and a feedback activation signal; a first transistor for providing a power supply voltage to a first output node at which the second output signal is output in response to the first output signal; a second transistor responsive to the feedback signal to couple the first output node to a second output node; a current source coupled to the second transistor through the second output node and configured to generate the second power supply current.

9. the feedback circuit includes a logic gate that outputs the feedback signal based on the second output signal and a feedback activation signal; 9. The image sensor of claim 8, wherein the second transistor is turned off in response to the feedback signal.

10. the feedback signal includes a first feedback signal and a second feedback signal; The second amplifier is a second transistor responsive to the first feedback signal to couple the first output node to a second output node; a third transistor responsive to the second feedback signal to couple the first output node to a third output node; the current source is coupled to the second transistor through the second output node and to the third transistor through the third output node to generate the second power supply current; 9. The image sensor of claim 8, wherein the second power supply current comprises a first sub-power supply current flowing through the second transistor and a second sub-power supply current flowing through the third transistor.

11. The feedback circuit includes: a first logic gate that outputs the first feedback signal based on the second output signal and a first feedback activation signal; a second logic gate configured to output the second feedback signal based on the second output signal and a second feedback activation signal; the second transistor is turned off in response to the first feedback signal; 11. The image sensor of claim 10, wherein the third transistor is turned off in response to the second feedback signal.

12. The current source is coupled to the second transistor via the second output node and to a third transistor via the first output node to generate the second power supply current; 9. The image sensor of claim 8, wherein the second power supply current comprises a first sub-power supply current flowing through the second transistor and a second sub-power supply current flowing through the third transistor.

13. the feedback circuit includes a first logic gate that outputs the first feedback signal based on the second output signal and a first feedback activation signal; 11. The image sensor of claim 10, wherein the second transistor is turned off in response to the first feedback signal.

14. the first transistor is a PMOS transistor, the second transistor and the third transistor are NMOS transistors, 14. The image sensor of claim 13, wherein the first logic gate is a NAND gate.

15. 1. A method of operating an analog-to-digital conversion circuit, comprising: comparing a pixel signal output from the pixel array with a ramp signal to generate a first output signal; generating a second output signal based on the first output signal; and controlling a power supply current of the analog-to-digital conversion circuit using the first output signal or the second output signal; the power supply current includes a first sub-power supply current and a second sub-power supply current; The step of controlling the power supply current includes: outputting a first feedback signal based on the second output signal and a first feedback activity signal; outputting a second feedback signal based on the second output signal and a second feedback activity signal; controlling the first sub-power supply current in response to the first feedback signal, and controlling the second sub-power supply current in response to the second feedback signal.

16. The step of generating the first output signal comprises: comparing a reset signal of the pixel signal to the ramp signal during a first operating interval; comparing an image signal of the pixel signal with the ramp signal during a second operating interval; 16. The method of claim 15, wherein controlling the power supply current is performed during at least one of the first and second operating intervals.

17. The step of controlling the power supply current includes: outputting a feedback signal based on the second output signal and a feedback activation signal; 16. The method of claim 15, further comprising the step of: controlling said power supply current to not flow in response to said feedback signal.

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