Power Conversion Equipment

Abstract

A power conversion apparatus (1) comprises: a neutral point clamp-type multilevel power converter (10); and a control device (20). The control device (20) comprises: a modulation voltage generator (21) that generates modulation phase voltage commands (Vua*, Vva*, Vwa*) on the basis of phase voltage commands and phase voltage currents; and a PWM modulator (22) that generates gate signals (Gu, Gv, Gw) for driving the power converter (10), on the basis of the modulation phase voltage commands (Vua*, Vva*, Vwa*). The modulation voltage generator (21) calculates an offset voltage (VX) with respect to a center phase, which is at the center in the order of the phase voltage commands of the phases, so that the polarities of the phase voltage commands are not reversed with the polarities of the phase currents, and superposes the offset voltage (VX), as a first common voltage, on the phase voltage commands of the phases, thereby generating the modulation phase voltage commands (Vua*, Vva*, Vwa*).

Description

[Technical field]

[0001] The present application relates to a power conversion device. [Background technology]

[0002] A neutral point clamp type multilevel inverter is a circuit that converts high-output DC power into AC power. In a conventional power conversion device, a control device uses PWM (Pulse Width Modulation) control to compare voltage command values ​​for each of the three phases of a three-phase N-level inverter (N is an odd number equal to or greater than 3) that is the main circuit with (N-1) carrier signals to generate switching signals for each switching element of the N-level inverter.

[0003] The control device for a multilevel inverter described in Patent Document 1 includes a maximum current phase selection unit that selects a maximum current phase having the largest current amplitude based on the absolute value of a current detection value or a current command value for each of three phases, a subtraction unit that subtracts a voltage command value of the selected maximum current phase from a voltage command value for each of the three phases of the N-level inverter, and a carrier comparator 55 that compares the subtracted voltage command value for each of the three phases with (N-1) carrier signals to generate switching signals for each switching element of the N-level inverter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-30070 A Summary of the Invention [Problem to be solved by the invention]

[0005] It is known that in a three-level NPC (Neutral Point Clamped) inverter, loss and heat generation are large in the switching elements connected to the AC terminal side. The conventional technology described in the above Patent Document 1 aims to reduce the switching loss of the maximum current phase to reduce the loss of the entire power conversion device, but it cannot effectively reduce the loss in the switching elements connected to the AC terminal side. For this reason, it is not possible to suppress the bias in loss among the multiple switching elements in each phase of the power conversion device, and there is a limit to improving the conversion efficiency and output.

[0006] The present application discloses technology for solving the problems described above, and aims to provide a neutral point clamped power conversion device that effectively reduces losses in semiconductor switching elements connected to the AC terminal side and suppresses imbalances in losses among multiple switching elements in each phase, thereby providing a high-output, high-efficiency power conversion device. [Means for solving the problem]

[0007] The power conversion device disclosed in the present application includes a neutral-point clamped multilevel power converter that converts power between DC power and AC power, and a control device that controls the output of the power converter by PWM control. The power converter has a multiphase configuration, and each phase of the power converter includes an upper arm and a lower arm formed by connecting in series a first switching element on the DC terminal side and a second switching element on the AC terminal side, and a clamp diode connected between a connection point of the first and second switching elements and a neutral point. The control device includes a modulation voltage generator that generates a modulation phase voltage command based on a phase voltage command and a phase current, and a PWM modulator that generates gate signals for driving the first and second switching elements of the power converter based on the modulation phase voltage command. Then, for a central phase in which the high-low ranking of the phase voltage commands of each phase is in the middle, the modulation voltage generator calculates an offset voltage so that the polarity of the phase voltage command is not inverted with the polarity of the phase current, and superimposes the offset voltage as a first common voltage on the phase voltage commands of each phase to generate the modulation phase voltage command. Effect of the Invention

[0008] According to the power conversion device disclosed in the present application, the loss in the second switching element connected to the AC terminal side can be effectively reduced, and the bias in loss among the multiple switching elements in each phase can be suppressed, resulting in a high-output, highly efficient power conversion device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a configuration diagram showing a power conversion device according to a first embodiment. [Diagram 2] FIG. 2 is a current path diagram illustrating a basic operation of the power conversion device according to the first embodiment. [Diagram 3] FIG. 2 is a current path diagram illustrating a basic operation of the power conversion device according to the first embodiment. [Figure 4] 4 is a flowchart illustrating an operation of the modulated voltage generator according to the first embodiment. [Diagram 5] 5 is a waveform diagram illustrating the operation of the PWM modulator according to the first embodiment. FIG. [Figure 6] 5 is a waveform diagram illustrating the operation of the PWM modulator according to the first embodiment. FIG. [Figure 7] FIG. 4 is a waveform diagram illustrating the operation of a power conversion device according to a comparative example of the first embodiment. [Figure 8] FIG. 4 is a waveform diagram illustrating the operation of the power conversion device according to the first embodiment. [Figure 9] FIG. 11 is a configuration diagram showing a power conversion device according to a second embodiment. [Figure 10] 10 is a flowchart illustrating an operation of the modulation voltage corrector according to the second embodiment. [Figure 11] FIG. 11 is a waveform diagram illustrating the operation of the power conversion device according to the second embodiment. [Figure 12] FIG. 11 is a configuration diagram showing a power conversion device according to a third embodiment. [Figure 13] FIG. 2 is a configuration diagram showing an example of hardware for implementing each function of the control device according to the first to third embodiments. [Figure 14]FIG. 4 is a configuration diagram showing another example of hardware for realizing each function of the control device according to the first to third embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Embodiment 1 Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a power conversion device according to a first embodiment. As shown in FIG. 1, a power conversion device 1 is connected between, for example, a DC power source 2 and a load 3, which is a motor, and converts DC power from the DC power source 2 into AC power to supply the power to the load 3. The power conversion device 1 may be capable of bidirectional operation, and may convert regenerative power from the load 3 into DC power to charge the DC power source 2.

[0011] The power conversion device 1 includes an NPC inverter 10 as a three-phase, three-level power converter, and a control device 20 that controls the output of the NPC inverter 10 by PWM control. The NPC inverter 10 includes two capacitors C1 and C2 connected in series between DC buses, upper and lower arms (UA, UB), (VA, VB), and (WA, WB) of each phase (U-phase, V-phase, and W-phase) connected in series, and clamp diodes (D1u, D2u), (D1v, D2v), and (D1w, D2w) of each phase. The connection point of the two capacitors C1 and C2 is the neutral point N, and the connection points of the upper and lower arms (UA, UB), (VA, VB), and (WA, WB) of each phase are the AC terminals of each phase.

[0012] The U-phase upper arm UA is formed by connecting in series a switching element Q1u as a first switching element on the DC terminal side and a switching element Q2u as a second switching element on the AC terminal side. The U-phase lower arm UB is formed by connecting in series a switching element Q4u as a first switching element on the DC terminal side and a switching element Q3u as a second switching element on the AC terminal side. A clamp diode D1u is connected between a connection point between the switching element Q1u and the switching element Q2u and a neutral point N. A clamp diode D2u is connected between a connection point between the switching element Q4u and the switching element Q3u and a neutral point N.

[0013] The V-phase upper arm VA is formed by connecting in series a switching element Q1v as a first switching element on the DC terminal side and a switching element Q2v as a second switching element on the AC terminal side. The V-phase lower arm VB is formed by connecting in series a switching element Q4v as a first switching element on the DC terminal side and a switching element Q3v as a second switching element on the AC terminal side. A clamp diode D1v is connected between a connection point between the switching elements Q1v and Q2v and a neutral point N. A clamp diode D2v is connected between a connection point between the switching elements Q4v and Q3v and a neutral point N.

[0014] The W-phase upper arm WA is formed by connecting in series a switching element Q1w as a first switching element on the DC terminal side and a switching element Q2w as a second switching element on the AC terminal side. The W-phase lower arm WB is formed by connecting in series a switching element Q4w as a first switching element on the DC terminal side and a switching element Q3w as a second switching element on the AC terminal side. A clamp diode D1w is connected between a connection point between the switching elements Q1w and Q2w and a neutral point N. A clamp diode D2w is connected between a connection point between the switching elements Q4w and Q3w and a neutral point N.

[0015] The first switching elements (switching elements Q1u, Q1v, Q1w) in the upper arms UA, VA, WA of each phase are connected to the DC terminals on the high voltage side, and the second switching elements (switching elements Q2u, Q2v, Q2w) are connected to the AC terminals of each phase. The first switching elements (switching elements Q4u, Q4v, Q4w) in the lower arms UB, VB, WB of each phase are connected to the DC terminals on the low voltage side, and the second switching elements (switching elements Q3u, Q3v, Q3w) are connected to the AC terminals of each phase. The anodes of the clamp diodes D1u, D1v, D1w connected to the upper arms UA, VA, WA are connected to the neutral point N. The cathodes of the clamp diodes D2u, D2v, D2w connected to the lower arms UB, VB, WB are connected to the neutral point N.

[0016] The switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w are semiconductor switching elements made of silicon, for example, and may be IGBTs (Insulated Gate Bipolar Transistors) with diodes connected inversely in parallel, or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with diodes connected between the source and drain. In addition, in the case of MOSFETs or RC (Reverse Conducting) IGBTs, diodes built into the switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w may be used.

[0017] The control device 20 includes a modulation voltage generator 21 that generates modulation phase voltage commands Vua*, Vva*, Vwa* for each phase, and a PWM modulator 22 that generates gate signals Gu, Gv, Gw that drive the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w for each phase based on the modulation phase voltage commands Vua*, Vva*, Vwa*. The phase voltage commands Vu*, Vv*, Vw* and phase current commands iu*, iv*, iw* of each phase are input to the modulation voltage generator 21, which generates the phase voltage commands Vua*, Vva*, Vwa* for modulation by a calculation described later. In this case, the phase voltage commands Vu*, Vv*, Vw* of each phase have sinusoidal voltage waveforms.

[0018] In addition, when the voltages of given phase voltage commands Vu*, Vv*, Vw* are supplied to the load 3, the current flowing through the load 3 may be calculated from a model of the load 3, and used as the phase current commands iu*, iv*, iw*. Also, the phase voltage commands Vu*, Vv*, Vw* may be obtained by performing control or calculation so that the current flowing through the load 3 becomes equal to the given phase current command values ​​iu*, iv*, iw*.

[0019] 2 and 3 are current path diagrams illustrating the basic operation of the power conversion device 1. FIG. The relationship between the output voltage and the current path of each phase of the NPC inverter 10 will be described below with reference to the drawings. In this case, the U phase will be described as an example, but the same applies to the V phase and the W phase. In this case, the phase voltage Vu is a voltage based on the neutral point N, and the phase current iu is positive in the direction from the NPC inverter 10 to the load 3. Fig. 2 shows the case where the phase current iu is positive, and Fig. 3 shows the case where the phase current iu is negative. The U phase of the NPC inverter 10 outputs a phase voltage Vu having three levels, positive, negative, and 0, which is half the magnitude of the voltage Vdc of the DC power supply 2 with respect to the neutral point N as the reference.

[0020] As shown in Fig. 2, when the phase current iu is positive, the switching elements Q1u and Q2u of the upper arm QA conduct to output the phase voltage Vu = (Vdc / 2), and when the phase voltage Vu = 0, only the switching element Q2u of the upper arm QA conducts. When the phase current iu is positive, the switching elements Q4u and Q3u (anti-parallel diodes in Fig. 2) of the lower arm QB conduct to output the phase voltage Vu = -(Vdc / 2).

[0021] In PWM control, the phase voltage Vu is alternately switched between two switching states, (Vdc / 2) and 0, so that a positive phase voltage Vu is output as an average voltage. Therefore, when the polarity of the phase current iu is positive, if the polarity of the phase voltage Vu is positive or 0, the second switching element Q2u continues to be conductive, and only the first switching element Q1u needs to be switched on and off. In other words, the second switching element Q2u can be maintained in the on state, and switching can be omitted.

[0022] As shown in Fig. 3, when the phase current iu is negative, the switching elements Q1u and Q2u (anti-parallel diodes in Fig. 3) of the upper arm QA conduct to output the phase voltage Vu = (Vdc / 2). When the phase current iu is negative and the phase voltage Vu = 0, only the switching element Q3u of the lower arm QB conducts, and when the phase voltage Vu = -(Vdc / 2) is output, the switching elements Q4u and Q3u of the lower arm QB conduct.

[0023] In PWM control, the phase voltage Vu is alternately switched between two switching states, −(Vdc / 2) and 0, so that a negative phase voltage Vu is output as an average voltage. Therefore, when the polarity of the phase current iu is negative, if the polarity of the phase voltage Vu is negative or 0, the second switching element Q3u continues to be conductive, and only the first switching element Q4u needs to be switched on and off. In other words, the second switching element Q3u can be maintained in the on state, and switching can be omitted.

[0024] As described above, if the polarity of the phase voltage Vu matches the polarity of the phase current iu or is 0, that is, if the polarities of both are not reversed, the second switching element (switching element Q2u or Q3u) can be held in the on state and switching can be omitted.

[0025] Next, the operation of the modulation voltage generator 21 will be described. The modulation voltage generator 21 receives the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw* of each phase, and generates the modulation phase voltage commands Vua*, Vva*, Vwa*. FIG. 4 is a flowchart for explaining the operation of the modulation voltage generator 21. The modulation voltage generator 21 generates the modulation phase voltage commands Vua*, Vva*, Vwa* based on the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw* of each phase at every predetermined calculation cycle.

[0026] First, the modulation voltage generator 21 searches for the central phase where the high-low order of the phase voltage commands Vu*, Vv*, Vw* of each phase is in the middle (step S1), sets the phase voltage command of the central phase as VA* and the phase current command of the central phase as iA* (step S2). For example, during the period when Vw* < Vu* < Vv*, the U phase is the central phase, the phase voltage command Vu* of the U phase is set as VA*, and the phase current command iu* of the U phase is set as iA*.

[0027] Next, the modulation voltage generator 21 determines whether VA* is positive and iA* is negative (step S3). If Yes, it sets the offset voltage VX as VX = -VA* - α (step S4). α is 0 or a positive constant voltage value. Next, the modulation voltage generator 21 superimposes the offset voltage VX as the first common voltage on the phase voltage commands Vu*, Vv*, Vw* of each phase to generate the modulation phase voltage commands Vua*, Vva*, Vwa*. That is, Vua* = Vu* + VX, Vva* = Vv* + VX, Vwa* = Vw* + VX (step S5).

[0028] In step S3, if No, the modulation voltage generator 21 determines whether VA* is negative and iA* is positive (step S6). If this determination is Yes, it sets the offset voltage VX as VX = -VA* + α (step S7) and then proceeds to step S5. If the result of step S6 is No, the modulation voltage generator 21 sets the offset voltage VX as VX=0 (step S8), and the process proceeds to step S5.

[0029] In this way, the modulation voltage generator 21 calculates the offset voltage VX for the center phase, which is the center of the high-low ranking of the phase voltage commands Vu*, Vv*, and Vw* of the phases, so that the polarity of the phase voltage command VA* is not inverted with the polarity of the phase current command iA*. Specifically, the modulation voltage generator 21 calculates the offset voltage VX for the center phase, so that the value of the phase voltage command VA* does not exceed 0 during a period when the polarity of the phase voltage command VA* is positive and the polarity of the phase current command iA* is negative. Also, the modulation voltage generator 21 calculates the offset voltage VX for the center phase, so that the value of the phase voltage command VA* does not become less than 0 during a period when the polarity of the phase voltage command VA* is negative and the polarity of the phase current command iA* is positive.

[0030] Incidentally, the offset voltage VX is not made unnecessarily large, and α is set to 0 or a relatively small positive voltage value taking a margin into consideration. Then, the modulation voltage generator 21 superimposes the offset voltage VX as a first common voltage on the phase voltage commands Vu*, Vv*, Vw* of each phase to generate the phase voltage commands Vua*, Vva*, Vwa* for modulation.

[0031] Next, a description will be given of the operation of the PWM modulator 22. The PWM modulator 22 generates gate signals Gu, Gv, and Gw that drive the switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w of each phase, based on modulation phase voltage commands Vua*, Vva*, and Vwa*. 5 and 6 are waveform diagrams illustrating the operation of the PWM modulator 22. FIG. In this case, the U phase will be described as an example, but the same applies to the V phase and the W phase. Fig. 5 shows a case where the modulation phase voltage command Vua* is Vua*≧0, and Fig. 6 shows a case where the modulation phase voltage command Vua* is Vua*<0. Also, the gate signal Gu is a collective description of the gate signals G1u, G2u, G3u, and G4u to the respective switching elements Q1u, Q2u, Q3u, and Q4u of the U phase.

[0032] The PWM modulator 22 compares the modulating phase voltage command Vua* with two carrier waves, that is, triangular waves Cr1 and Cr2, to generate a gate signal Gu. The triangular wave Cr1 varies in the range from zero to (Vdc / 2), and the triangular wave Cr2 varies from -(Vdc / 2) to zero. In the NPC inverter 10, the switching elements Q1u and Q3u are driven by gate signals G1u and G3u whose H and L are inverted relative to each other. Moreover, the switching elements Q2u and Q4u are driven by gate signals G2u and G4u whose H and L are inverted relative to each other.

[0033] As shown in Fig. 5, when the modulation phase voltage command Vua* is equal to or greater than 0, the gate signal G2u remains at H and the gate signal G4u remains at L. In the region where the modulation phase voltage command Vua* exceeds the triangular wave Cr1, the gate signal G1u becomes H and the gate signal G3u becomes L. At this time, the output phase voltage Vu is (Vdc / 2). In the region where the modulation phase voltage command Vua* is equal to or less than the triangular wave Cr1, the gate signal G1u becomes L and the gate signal G3u becomes H. At this time, the output phase voltage Vu is 0. The average value of the phase voltage Vu realizes the phase voltage command Vua* for modulation through PWM control.

[0034] As shown in Figure 6, when the modulation phase voltage command Vua*<0, the gate signal G1u remains L and the gate signal G3u remains H. In the region where the modulation phase voltage command Vua* exceeds the triangular wave Cr1, the gate signal G2u becomes H and the gate signal G4u becomes L. At this time, the output phase voltage Vu is 0. In the region where the modulation phase voltage command Vua* is equal to or less than the triangular wave Cr2, the gate signal G2u becomes L and the gate signal G4u becomes H. At this time, the output phase voltage Vu is -(Vdc / 2). The average value of the phase voltage Vu realizes the phase voltage command Vua* for modulation through PWM control.

[0035] FIG. 7 is a waveform diagram illustrating the operation of a power conversion device according to a comparative example of this embodiment. This comparative example is a case where there is no modulation voltage generator 21, that is, where the gate signal Gu is generated using the phase voltage commands Vu*, Vv*, Vw* of each phase as they are. Here, the phase voltage commands Vu*, Vv*, Vw* of each phase, the phase current commands iu*, iv*, iw*, and further, the waveform Up indicating whether the polarity of the phase voltage command Vu* and the phase current command iu* for the U phase coincides or is inverted are shown. Note that when the phase voltage command Vu*=0, Up=1 indicating the polarity coincides. As shown by the waveform Up, in the region in which the U phase is the central phase, there is a section t1 in which the polarities of the phase voltage command Vu* and the phase current command iu* do not match and are inverted.

[0036] FIG. 8 is a waveform diagram illustrating the operation of the power conversion device according to the first embodiment. In this embodiment, as described above, the modulation voltage generator 21 calculates the offset voltage VX for the center phase so that the polarity of the phase voltage command VA* is not inverted from the polarity of the phase current command iA*. In this case, the offset voltage VX is calculated with α=0. Then, the offset voltage VX is superimposed as a first common voltage on the phase voltage commands Vu*, Vv*, Vw* of each phase to generate phase voltage commands Vua*, Vva*, Vwa* for modulation.

[0037] Here, the modulation phase voltage commands Vua*, Vva*, Vwa* for each phase, the phase current commands iu*, iv*, iw*, and also the waveform Upa which indicates whether the polarity of the modulation phase voltage command Vua* and the phase current command iu* for the U phase coincides. In addition, when the modulation phase voltage command Vua*=0, Upa=1, which indicates polarity agreement, is set. In other words, Upa=1 is set unless the polarity of the modulation phase voltage command Vua* is inverted from the polarity of the phase current command iu*.

[0038] The modulation phase voltage commands Vua*, Vva*, Vwa* of each phase are generated by superimposing a common first common voltage (offset voltage VX) on the phase voltage commands Vu*, Vv*, Vw*, which are sinusoidal voltage waveforms. Therefore, the line voltages of the modulation phase voltage commands Vua*, Vva*, Vwa* of each phase are maintained as sinusoidal voltages, and there is no effect on the load 3.

[0039] As shown in Fig. 8, in a period in which the modulation phase voltage command Vua* is the central phase, an offset voltage VX, which is a first common voltage, is superimposed so that the polarity of the modulation phase voltage command Vua* is not inverted from the polarity of the phase current command iu*. That is, by superimposing the offset voltage VX in the section corresponding to the section t1 in Fig. 7, when the phase current command iu*>0, the modulation phase voltage command Vua*=α, and when the phase current command iu*<0, the modulation phase voltage command Vua*=-α. In this case, since α=0, the modulation phase voltage command Vua* is 0 in the section corresponding to the section t1 in Fig. 7.

[0040] For this reason, as shown by the waveform Upa, the polarity of the modulation phase voltage command Vua* is never inverted with respect to the polarity of the phase current command iu*, but is the same as or 0. This characteristic is similar for the V-phase and W-phase, that is, the polarity of the modulation phase voltage commands Vua*, Vva*, Vwa* of each phase is never inverted with respect to the phase current commands iu*, iv*, iw* of each phase, but is the same as or 0.

[0041] As described above, for example, in the U phase, if the polarity of the phase voltage Vu matches the polarity of the phase current iu or is 0, that is, if the polarities of both are not reversed, the second switching element (switching element Q2u or Q3u) can be held in the on state and switching can be omitted. In this embodiment, the phase voltage commands Vua*, Vva*, Vwa* for modulation of each phase do not have polarity inversion with respect to the phase current commands iu*, iv*, iw* of each phase. This allows the number of switching operations of the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) connected to the AC terminals of each phase to be significantly reduced, and the switching loss can be significantly reduced.

[0042] As described above, in a three-level NPC inverter, the loss and heat generation in the switching elements connected to the AC terminal side is large. However, in this embodiment, the loss in the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) connected to the AC terminals can be effectively reduced.

[0043] As described above, in this embodiment, the power conversion device 1 includes the NPC inverter 10 and the control device 20 that uses PWM control to control the output of the NPC inverter 10. The control device 20 includes a modulation voltage generator 21 that generates modulation phase voltage commands Vua*, Vva*, Vwa* based on the phase voltage commands Vu*, Vv*, Vw* and phase current commands iu*, iv*, iw*, and a PWM modulator 22 that generates gate signals Gu, Gv, Gw that drive the first and second switching elements Q1u-Q4u, Q1v-Q4v, Q1w-Q4w of the NPC inverter 10 based on the modulation phase voltage commands Vua*, Vva*, Vwa*. Then, for the central phase, which has the phase voltage commands Vu*, Vv*, Vw* of each phase in the middle in terms of high-low ranking, the modulation voltage generator 21 calculates an offset voltage VX so that the polarity of the phase voltage command VA* is not inverted with the polarity of the phase current command iA*, and superimposes the offset voltage VX as a first common voltage on the phase voltage commands Vu*, Vv*, Vw* of each phase to generate modulation phase voltage commands Vua*, Vva*, Vwa*.

[0044] This effectively reduces the losses in the second switching elements (Q2u, Q3u), (Q2v, Q3v), and (Q2w, Q3w) connected to the AC terminals, thereby suppressing the bias in losses among the multiple switching elements in each phase of the NPC inverter 10, and thus a high-output, high-efficiency power conversion device 1 can be obtained.

[0045] In addition, in this embodiment, the phase voltage commands Vu*, Vv*, Vw* are sinusoidal voltage commands, and the modulated voltage generator 21 calculates the offset voltage VX for the central phase so that the value of the phase voltage command VA* does not exceed 0 during a period when the polarity of the phase voltage command VA* is positive and the polarity of the phase current command iA* is negative, and so that the value of the phase voltage command VA* does not become less than 0 during a period when the polarity of the phase voltage command VA* is negative and the polarity of the phase current command iA* is positive. As a result, the modulating phase voltage commands Vua*, Vva*, Vwa* for each phase can be reliably generated without always inverting polarity with the phase current commands iu*, iv*, iw*, and the loss reduction effect of the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) can be reliably obtained.

[0046] In the above embodiment, the modulation phase voltage commands Vua*, Vva*, Vwa* are generated based on the phase voltage commands Vu*, Vv*, Vw* and the phase current commands iu*, iv*, iw*. However, instead of the phase current commands iu*, iv*, iw*, the phase currents iu, iv, iw of each phase may be detected and used, with the same effect being obtained.

[0047] Embodiment 2 In the above-mentioned embodiment 1, the magnitudes of the modulation phase voltage commands Vua*, Vva*, Vwa* may exceed (Vdc / 2), which is half the voltage Vdc of the DC power supply 2. In this embodiment 2, however, the magnitudes of the modulation phase voltage commands Vua*, Vva*, Vwa* are always kept below (Vdc / 2).

[0048] FIG. 9 is a configuration diagram showing a power conversion device according to the second embodiment. 9, the power conversion device 1A includes an NPC inverter 10 as a three-phase, three-level power converter, and a control device 20A that controls the output of the NPC inverter 10 by PWM control, and is connected, for example, between a DC power source 2 and a motor that is a load 3, converts the DC power of the DC power source 2 into AC power and supplies it to the load 3. In this case, the NPC inverter 10 has the same configuration as in the above-mentioned first embodiment, but the power conversion device 1A includes a current detector 5 that detects phase currents iu, iv, and iw of each phase output from the NPC inverter 10 to the load 3. Here, the current detector 5 is shown to detect each of the three phase currents, but it is also possible to detect two of the three phases and calculate the current of the remaining phase by utilizing the fact that the sum of the currents of the three phases is zero.

[0049] The control device 20A includes a modulation voltage generator 24 (hereinafter referred to as the second modulation voltage generator 24) that generates modulation phase voltage commands Vub*, Vvb*, Vwb* for each phase, and a PWM modulator 22 that generates gate signals Gu, Gv, Gw that drive the switching elements Q1u to Q4u, Q1v to Q4v, Q1w to Q4w for each phase based on the modulation phase voltage commands Vub*, Vvb*, Vwb*.

[0050] The second modulation voltage generator 24 generates modulation phase voltage commands Vub*, Vvb*, Vwb* for each phase at each predetermined calculation period, based on the phase voltage commands Vu*, Vv*, Vw* of each phase and the detected phase currents iu, iv, iw. The second modulation voltage generator 24 includes a modulation voltage generator 21 similar to that of the first embodiment, and a modulation voltage corrector 23 that corrects the modulation phase voltage commands Vua*, Vva*, Vwa* generated by the modulation voltage generator 21 to generate modulation phase voltage commands Vub*, Vvb*, Vwb*.

[0051] The corrected modulation phase voltage commands Vub*, Vvb*, and Vwb* are input to the PWM modulator 22, which generates gate signals Gu, Gv, and Gw by the same process as in the first embodiment. In this case, the modulation voltage generator 21 receives the phase voltage commands Vu*, Vv*, Vw* for each phase and the detected phase currents iu, iv, iw, and generates the modulation phase voltage commands Vua*, Vva*, Vwa* by calculations similar to those in the first embodiment above.

[0052] The modulation voltage generator 21 calculates an offset voltage VX for a center phase in which the high-low ranking of the phase voltage commands Vu*, Vv*, and Vw* of the phases is the middle, so that the polarity of the phase voltage command VA* is not inverted with the polarity of the phase current iA. Specifically, the modulation voltage generator 21 calculates an offset voltage VX for the center phase so that the value of the phase voltage command VA* does not exceed 0 during a period in which the polarity of the phase voltage command VA* is positive and the polarity of the phase current iA is negative. Also, the modulation voltage generator 21 calculates an offset voltage VX so that the value of the phase voltage command VA* does not become less than 0 during a period in which the polarity of the phase voltage command VA* is negative and the polarity of the phase current iA is positive.

[0053] Then, the modulation voltage generator 21 generates modulation-phase voltage commands Vua*, Vva*, and Vwa* by superimposing the offset voltage VX as the first common voltage on the phase voltage commands Vu*, Vv*, and Vw* of each phase. The generated modulation-phase voltage commands Vua*, Vva*, and Vwa* may exceed (Vdc / 2), which is half of the voltage Vdc of the DC power supply 2 (see Fig. 8).

[0054] Next, the operation of the modulation voltage corrector 23 will be described. Fig. 10 is a flowchart for explaining the operation of the modulation voltage corrector 23. First, the modulation voltage corrector 23 searches for the maximum phase and the minimum phase with the highest and lowest ranks of the modulation-phase voltage commands Vua*, Vva*, and Vwa* of each phase (step SS1), sets the modulation-phase voltage command of the maximum phase as Vmax*, and sets the modulation-phase voltage command of the minimum phase as Vmin* (step SS2). For example, during a period when Vwa* < Vua* < Vva*, the V phase is the maximum phase and Vva* is set as Vmax*, and the W phase is the minimum phase and Vwa* is set as Vmin*.

[0055] Next, the modulation voltage corrector 23 determines whether Vmax* > (Vdc / 2) - β (step SS3). If Yes, it sets the offset voltage VY, which is the correction voltage, as VY = ((Vdc / 2) - β) - Vmax* (step SS4). β is 0 or a positive constant voltage value, and ((Vdc / 2) - β) is a set voltage based on the voltage Vdc of the DC power supply 2. Next, the modulation voltage corrector 23 generates corrected modulation-phase voltage commands Vub*, Vvb*, and Vwb* by superimposing the offset voltage VY as the second common voltage on the modulation-phase voltage commands Vua*, Vva*, and Vwa* of each phase. That is, Vub* = Vua* + VY, Vvb* = Vva* + VY, and Vwb* = Vwa* + VY (step SS5).

[0056] If the answer is No in step SS3, the modulation voltage corrector 23 determines whether Vmin*<-((Vdc / 2)-β) (step SS6), and if the answer is Yes, sets the offset voltage VY, which is the correction voltage, as VY=-((Vdc / 2)-β)-Vmin* (step SS7), and proceeds to step S5. If the result in step SS6 is No, the modulation voltage corrector 23 sets the offset voltage VY as VY=0 (step SS8), and the process proceeds to step SS5.

[0057] In this way, the modulation voltage compensator 23 calculates the offset voltage (correction voltage) VY so that the modulation phase voltage command Vmax* of the maximum phase, which has the highest high-low ranking of the modulation phase voltage commands Vua*, Vva*, Vwa* of each phase, does not exceed the set voltage ((Vdc / 2)-β), and so that the magnitude (absolute value) of the modulation phase voltage command Vmin* of the minimum phase, which has the lowest high-low ranking, does not exceed the set voltage ((Vdc / 2)-β). The offset voltage VY is not made unnecessarily large, and β is set to 0 or a relatively small positive voltage value taking a margin into consideration. Then, the modulation voltage compensator 23 superimposes the offset voltage VY as a second common voltage on the modulation phase voltage commands Vua*, Vva*, Vwa* of each phase to generate corrected modulation phase voltage commands Vub*, Vvb*, Vwb*.

[0058] FIG. 11 is a waveform diagram illustrating the operation of the power conversion device according to the second embodiment. In this embodiment, the modulation voltage generator 21 generates the modulation phase voltage commands Vua*, Vva*, Vwa* as in the above-mentioned embodiment 1, and further, the modulation voltage compensator 23 corrects the modulation phase voltage commands Vua*, Vva*, Vwa* to generate corrected modulation phase voltage commands Vub*, Vvb*, Vwb*. In this case, a correction voltage (offset voltage VY) is calculated with β=0, and is superimposed as a second common voltage on the modulation phase voltage commands Vua*, Vva*, Vwa* of each phase for correction.

[0059] Here, the corrected modulation phase voltage commands Vub*, Vvb*, Vwb* for each phase, the phase currents iu, iv, iw, and also the waveform Upb which indicates whether the polarity of the modulation phase voltage command Vub* and the phase current iu for the U phase coincides are shown. In addition, when the modulation phase voltage command Vub* = 0, Upb = 1, which indicates polarity agreement, is set. In other words, if the polarity of the modulation phase voltage command Vub* is not inverted from the polarity of the phase current iu, Upb = 1 is set.

[0060] In this embodiment as well, the modulation phase voltage commands Vub*, Vvb*, Vwb* of each phase are generated by superimposing the first common voltage (offset voltage VX) and the second common voltage (offset voltage VY) common to each phase on the phase voltage commands Vu*, Vv*, Vw*, which are sinusoidal voltage waveforms. Therefore, the line voltages of the modulation phase voltage commands Vub*, Vvb*, Vwb* of each phase are maintained as sinusoidal voltages, and there is no effect on the load 3.

[0061] As shown in Fig. 11, the magnitude (absolute value) of the modulation phase voltage commands Vub*, Vvb*, and Vwb* of each phase is limited by the set voltage ((Vdc / 2)-β). In this case, since β=0, it is limited by the set voltage (Vdc / 2). As shown by the waveform Upb, there is a section t2 in which the polarity of the modulation phase voltage command Vub* and the polarity of the phase current iu are inverted during the period in which the U phase is the central phase, and in this section t2, the modulation phase voltage commands Vvb* and Vwb* of the V phase or W phase are limited to a set voltage (Vdc / 2). This section t2 can be significantly shorter than the section t1 shown in Figure 7. This characteristic is similar for the V phase and the W phase.

[0062] In this manner, in this embodiment, the period during which the modulation phase voltage commands Vub*, Vvb*, Vwb* of each phase invert polarity with the phase currents iu, iv, iw of each phase can be significantly shortened, and the magnitude of the modulation phase voltage commands Vub*, Vvb*, Vwb* can always be kept below (Vdc / 2). Therefore, as in the first embodiment, the number of switching operations of the second switching elements (Q2u, Q3u), (Q2v, Q3v), (Q2w, Q3w) connected to the AC terminals of each phase can be significantly reduced, and the switching loss can be significantly reduced. Therefore, the bias in loss between the multiple switching elements in each phase of the NPC inverter 10 can be suppressed, and a high-output and high-efficiency power conversion device 1 can be obtained.

[0063] Furthermore, since the magnitudes of the modulation phase voltage commands Vua*, Vva*, and Vwa* can always be kept below (Vdc / 2), overmodulation can be prevented from occurring in PWM control, distortion of the output voltage and current is suppressed, and the reliability of control is improved.

[0064] In the above-mentioned second embodiment, the modulation voltage compensator 23 calculates the offset voltage VY by searching two phases, the maximum phase and the minimum phase, but it may search for one phase in which the magnitude (absolute value) of the modulation phase voltage commands Vua*, Vva*, Vwa* of each phase is maximum. In that case, the offset voltage VY is calculated so that the magnitude (absolute value) of the modulation phase voltage command of the searched one phase does not exceed the set voltage ((Vdc / 2)-β), thereby obtaining the same results as in the above-mentioned second embodiment.

[0065] Embodiment 3 FIG. 12 is a configuration diagram showing a power conversion device according to the third embodiment. 12, power conversion device 1B includes an NPC inverter 11 as a three-phase three-level power converter, and a control device 20 that controls the output of the NPC inverter 11 by PWM control, and is connected, for example, between a DC power source 2 and a motor that is a load 3, converts DC power from the DC power source 2 into AC power and supplies it to the load 3. In this case, the NPC inverter 11 is similar to that of the above-mentioned embodiment 1 except for the element configuration of switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w, and the control device 20 is also similar to that of the above-mentioned embodiment 1.

[0066] The first switching elements (switching elements Q1u, Q1v, Q1w) in the upper arms UA, VA, WA of each phase of the NPC inverter 11 are connected to the DC terminals on the high voltage side, and the second switching elements (switching elements Q2u, Q2v, Q2w) are connected to the AC terminals of each phase. The first switching elements (switching elements Q4u, Q4v, Q4w) in the lower arms UB, VB, WB of each phase are connected to the DC terminals on the low voltage side, and the second switching elements (switching elements Q3u, Q3v, Q3w) are connected to the AC terminals of each phase. The anodes of the clamp diodes D1u, D1v, D1w connected to the upper arms UA, VA, WA are connected to the neutral point N. The cathodes of the clamp diodes D2u, D2v, D2w connected to the lower arms UB, VB, WB are connected to the neutral point N.

[0067] In this embodiment, different switching elements are used for the first switching elements (Q1u, Q1v, Q1w), (Q4u, Q4v, Q4w) and the second switching elements (Q2u, Q2v, Q2w), (Q3u, Q4v, Q4w) of each upper and lower arm of the NPC inverter 11. Hereinafter, the first switching elements (Q1u, Q1v, Q1w) will be referred to as the first switching elements Q1, and the first switching elements (Q4u, Q4v, Q4w) will be referred to as the first switching elements Q4. Similarly, the second switching elements (Q2u, Q2v, Q2) will be referred to as the second switching elements Q2, and the second switching elements (Q3u, Q3v, Q3w) will be referred to as the second switching elements Q3.

[0068] The first switching elements Q1 and Q4 are elements having smaller switching losses than the second switching elements Q2 and Q3, and the second switching elements Q2 and Q3 are elements having smaller conduction losses due to on-resistance than the first switching elements Q1 and Q4. In this case, the first switching elements Q1 and Q4 are MOSFETs made of SiC (silicon carbide), which can achieve small switching losses, and the second switching elements Q2 and Q3 are IGBTs made of silicon, which can achieve small conduction losses even in the case of large currents.

[0069] As described in the above embodiment 1, the control device 20 generates the modulation phase voltage commands Vua*, Vva*, Vwa* so that the polarities are not inverted with the polarities of the phase current commands iu*, iv*, iw*, and PWM controls the NPC inverter 11. Therefore, the number of switching operations of the second switching elements Q2, Q3 can be significantly reduced, but the energization period becomes longer. The power loss of each of the first and second switching elements (Q1, Q4), (Q2, Q3) can be expressed as the sum of the switching loss and the conduction loss.

[0070] In this embodiment, elements with small switching loss are used for the first switching elements Q1, Q4, which have a large number of switching times, and elements with small conduction loss due to on-resistance are used for the second switching elements Q2, Q3, which have a significantly reduced number of switching times but a long current-carrying period. This makes it possible to effectively reduce the power loss of each of the first and second switching elements (Q1, Q4), (Q2, Q3), and to reduce the loss of the entire NPC inverter 11, resulting in a highly efficient power conversion device 1B.

[0071] The first switching elements Q1 and Q4 are not limited to MOSFETs made of SiC, but may be MOSFETs made of semiconductor materials with a wider band gap than silicon, and may be elements with relatively small switching losses.The second switching elements Q2 and Q3 are not limited to IGBTs made of silicon, but may be elements with relatively small conduction losses even in the case of large currents.

[0072] In this embodiment, as described above, it is possible to configure each of the switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w of the NPC inverter 11 to have low loss. When the main control of the NPC inverter 11 is to supply power to the load 3 in power running operation, it is possible to reduce both the conduction loss and switching loss of each of the switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w, thereby achieving highly efficient power conversion operation. This is particularly effective when the load 3 is a motor that drives the propulsion fan of an aircraft, which is mostly in power running mode. Furthermore, because a surface magnet type permanent magnet motor with a high power factor is used for the motor of the load 3, the period during which the polarity of the phase voltage and the polarity of the phase current match is long. This makes it possible to more effectively reduce both the conduction loss and the switching loss of each of the switching elements Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w.

[0073] In this embodiment, the control according to the above-mentioned embodiment 1 is applied, but the control according to the above-mentioned embodiment 2 can be applied in the same manner, and similarly, both the conduction loss and the switching loss of each switching element Q1u to Q4u, Q1v to Q4v, and Q1w to Q4w are reduced to obtain a highly efficient power conversion device 1B.

[0074] In addition, in each of the above embodiments, the NPC inverters 10 and 11, which are three-phase, three-level power converters, are used as neutral point clamped multilevel power converters. However, a multiphase configuration having more than three phases may also be used, and the present invention can also be applied to a multilevel power converter having more than three levels.

[0075] Incidentally, the functions of the control devices 20 and 20A in the above-described embodiments are realized by a processing circuit. 13 is a configuration diagram showing an example of hardware for implementing each function of the control devices 20 and 20A. In this case, the control devices 20 and 20A are configured by a dedicated processing circuit 30, which is dedicated hardware. In addition, the dedicated processing circuit 30 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination of these.

[0076] 14 is a configuration diagram showing another example of hardware for implementing each function of the control devices 20 and 20A. In this case, the processing circuit 30A includes a processor 31 and a storage device 32. In the processing circuit 30A, the functions of the control devices 20, 20A are realized by software, firmware, or a combination of software and firmware. The software and firmware are written as programs and stored in the storage device 32. The processor 31 realizes each function by reading and executing the programs stored in the storage device 32.

[0077] It can be said that the programs stored in the storage device 32 cause the computer to execute the procedures or methods of each of the above-mentioned parts. Here, the storage device 32 is, for example, a non-volatile or volatile semiconductor memory such as a random access memory (RAM), a read only memory (ROM), a flash memory, an erasable programmable read only memory (EPROM), an electrically erasable and programmable read only memory (EEPROM), etc. In addition, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD, etc. also fall under the category of the storage device 32.

[0078] It should be noted that the functions of the control devices 20 and 20A described above may be partially realized by dedicated hardware and partially realized by software or firmware. In this manner, the processing circuitry can realize the functions of the control devices 20, 20A described above by hardware, software, firmware, or a combination of these.

[0079] Although the present application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in this application, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0080] 1, 1A, 1B power conversion device, 10, 11 NPC inverter, 20, 20A control device, 21 modulation voltage generator, 22 PWM modulator, 23 modulation voltage compensator, 24 second modulation voltage generator, Gu, Gv, Gw gate signal, N neutral point, UA, VA, WA upper arm, UB, VB, WB lower arm, Q1u, Q1v, Q1w first switching element, Q2u, Q2v, Q2w second switching element, Q3u, Q3v, Q3w second switching element, Q4u, Q4v, Q4w first switching element, Vu*, Vv*, Vw*, VA* phase voltage commands, iu*, iv*, iw*, iA* phase current commands, iu, iv, iw, iA phase currents, Vua*, Vva*, Vwa* phase voltage commands for modulation, Vub*, Vvb*, Vwb* phase voltage commands for modulation, VX offset voltage, VY offset voltage which is the correction voltage.

Claims

1. A neutral point clamped multilevel power converter that converts power between DC power and AC power; a control device that controls an output of the power converter by PWM control, the power converter has a multi-phase configuration, and each phase of the power converter includes an upper arm and a lower arm formed by connecting in series a first switching element on a DC terminal side and a second switching element on an AC terminal side, and a clamp diode connected between a connection point of the first and second switching elements and a neutral point; the control device includes a modulation voltage generator that generates a modulation phase voltage command based on a phase voltage command and a phase current, and a PWM modulator that generates gate signals for driving the first and second switching elements of the power converter based on the modulation phase voltage command, the modulation voltage generator calculates an offset voltage for a central phase in which the high-low ranking of the phase voltage commands of the phases is in the middle, so that the polarity of the phase voltage command is not inverted with the polarity of the phase current, and generates the phase voltage command for modulation by superimposing the offset voltage as a first common voltage on the phase voltage commands of the phases. Power conversion equipment.

2. the phase voltage command is a sinusoidal voltage command, the modulation voltage generator calculates the offset voltage such that, for the central phase, a value of the phase voltage command does not exceed 0 in a period in which the polarity of the phase voltage command is positive and the polarity of the phase current is negative, and a value of the phase voltage command does not become less than 0 in a period in which the polarity of the phase voltage command is negative and the polarity of the phase current is positive. The power conversion device according to claim 1 .

3. the modulation voltage generator corrects the generated modulation phase voltage command for each phase by superimposing a second common voltage on the modulation phase voltage command for each phase so that the magnitude of the generated modulation phase voltage command for each phase does not exceed a set voltage based on the DC voltage on the DC terminal side; The power conversion device according to claim 1 or 2.

4. The modulation voltage generator calculates a correction voltage for the phase in which the magnitude of the modulation phase voltage command is maximum among the generated phases, so that the value of the modulation phase voltage command becomes the set voltage, and superimposes the correction voltage as the second common voltage on the modulation phase voltage command of each phase for correction. The power conversion device according to claim 3 .

5. The power conversion device according to claim 1 , wherein the control device generates the modulating phase voltage command by using a phase current command as the phase current.

6. The power converter is a three-phase three-level power converter. The power conversion device according to any one of claims 1 to 5.

7. A conduction loss due to an on-resistance of the second switching element is smaller than a conduction loss due to an on-resistance of the first switching element. The power conversion device according to any one of claims 1 to 6.

8. A switching loss of the first switching element is smaller than a switching loss of the second switching element. The power conversion device according to any one of claims 1 to 7.

9. an IGBT made of silicon is used as the second switching element; The power conversion device according to any one of claims 1 to 8.

10. A MOSFET made of a semiconductor material having a band gap wider than that of silicon is used for the first switching element. The power conversion device according to any one of claims 1 to 9.

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