Surge suppression circuits for thyristors

Abstract

To provide a surge suppression circuit capable of absorbing a surge current to prevent a component from malfunctioning.SOLUTION: A thyristor 300 is connected between a first AC voltage terminal AC1 and a second AC voltage terminal AC2. A surge suppression circuit 100 comprises a metal oxide film semiconductor field-effect transistor (MOSFET) 110, a resistance 130, a Zener diode 150, and a capacitor structure 170. The MOSFET is electrically connected between the base of the thyristor and a second AC voltage terminal. The resistance is electrically connected between the gate of the MOSFET and the second AC voltage terminal. The Zener diode is electrically connected between the gate of the MOSFET and the second AC voltage terminal. The capacitor structure is located between the gate of the MOSFET and a substrate terminal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a surge suppression circuit for a thyristor, and more particularly to a surge suppression circuit capable of absorbing a surge current to prevent malfunction of components. [Background technology]

[0002] A typical bidirectional Photo Triac controls the power density of a high voltage AC load with an IR-LED light signal driven by the low voltage side of a microcontroller. When a surge occurs, the dv / dt tolerance of the bidirectional Photo Triac may be exceeded, causing damage or failure of the chip and other connected components. The current dv / dt protection circuit shown in Figure 1 was proposed by Siemens and is described in U.S. Patent No. 4,578,5 96 This is disclosed in the specification of

[0003] 1 is a dv / dt suppression circuit that combines a depletion-mode metal oxide semiconductor field effect transistor 510, an enhancement-mode metal oxide semiconductor field effect transistor 520, a Zener diode 530, and a capacitor 540. However, when using a depletion-mode metal oxide semiconductor field effect transistor, a photomask needs to be added to the manufacturing process, which increases the manufacturing cost of the entire circuit.

[0004] In view of the above circumstances, the present invention proposes a surge suppression circuit that can improve the structure of a capacitor instead of a depletion-type metal oxide semiconductor field effect transistor. Summary of the Invention

[0005] An object of the present invention is to provide a surge suppression circuit that uses resistors instead of depletion-type metal oxide semiconductor field effect transistors used in existing dv / dt suppression circuits, thereby reducing the number of photomasks and simplifying the manufacturing process. In addition, in the present invention, a P-type metal oxide semiconductor field effect transistor is used instead of a capacitor, so the area of ​​the capacitor can be reduced and the chip size can be reduced. As a result, the surge suppression circuit of the present invention can simplify the manufacturing process, reduce the area of ​​the capacitor, and reduce the overall manufacturing cost.

[0006] In order to achieve the above object, the present invention discloses a surge suppression circuit for a thyristor. The thyristor is connected between a first AC voltage terminal and a second AC voltage terminal, and includes a first bipolar junction transistor (BJT) and a second bipolar transistor. The surge suppression circuit includes a metal oxide semiconductor field effect transistor (MOSFET), a resistor, a Zener diode, and a capacitor structure. The metal oxide semiconductor field effect transistor is electrically connected between a base of the second bipolar transistor and the second AC voltage terminal. The resistor is electrically connected between a gate of the metal oxide semiconductor field effect transistor and the second AC voltage terminal. The Zener diode is electrically connected between the gate of the metal oxide semiconductor field effect transistor and the second AC voltage terminal. The capacitor structure is located between the gate of the metal oxide semiconductor field effect transistor and a substrate terminal.

[0007] In an embodiment of the present invention, the metal oxide semiconductor field effect transistor has a drain and a source, the drain is electrically connected to the base of the second bipolar transistor, and the source is electrically connected to the second AC voltage terminal.

[0008] In an embodiment of the present invention, the resistor is connected in parallel with the Zener diode.

[0009] In an embodiment of the present invention, the metal oxide semiconductor field effect transistor is an enhancement type metal oxide semiconductor field effect transistor.

[0010] In an embodiment of the present invention, the metal oxide semiconductor field effect transistor is an N-type metal oxide semiconductor field effect transistor (NMOSFET).

[0011] In an embodiment of the present invention, the capacitor structure is a parasitic capacitor, and the parasitic capacitor is formed in the surge suppression circuit by a circuit layout.

[0012] In an embodiment of the present invention, the capacitor structure is formed by the circuit layout with a P-type metal oxide semiconductor field effect transistor (PMOSFET) structure.

[0013] In an embodiment of the present invention, the capacitor structure comprises a metal layer, a first oxide layer, a second oxide layer, and an N-type substrate.

[0014] In an embodiment of the present invention, the capacitor structure is composed of a metal layer, an oxide layer, and an N-type doped region.

[0015] In an embodiment of the present invention, the resistor drives the metal oxide semiconductor field effect transistor in response to an induced current generated by the capacitor structure.

[0016] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below. [Brief description of the drawings]

[0017] [Figure 1] Schematic diagram of a prior art dv / dt protection circuit [Diagram 2]FIG. 1 is a schematic diagram showing a surge suppression circuit according to the present invention; [Diagram 3] 1 is a cross-sectional view showing a surge suppression circuit according to the present invention; [Figure 4] 1 is a cross-sectional view showing a surge suppression circuit according to the present invention; [Diagram 5] 1 is a cross-sectional view showing a surge suppression circuit according to the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The contents of the present invention will be described below through examples. The examples of the present invention are not intended to be limited to the environments, applications, or specific aspects described in the examples. Therefore, the explanation of the examples is for explaining the present invention, but does not limit the present invention. In the embodiments and drawings, components that are not directly related to the present invention are omitted and not shown. The dimensional relationship of each component in the drawings is for ease of understanding, and does not limit the actual dimensions.

[0019] A first embodiment of the present invention is shown in Figures 2 and 3. Figure 2 is a schematic diagram showing a surge suppression circuit 100 according to the present invention. The surge suppression circuit 100 is used to protect a thyristor 300, such as a photo triac, from malfunction of the component due to a base current generated by a surge. The thyristor 300 is connected between a first AC voltage terminal AC1 and a second AC voltage terminal AC2, and has a first bipolar junction transistor (BJT) 310 and a second bipolar transistor 330.

[0020] Specifically, the thyristor 300 has a first pin T1 and a second pin T2. ​​The first pin T1 is connected to a first AC voltage terminal AC1. The second pin T2 is connected to a second AC voltage terminal AC2. The thyristor 300 is equivalent to the circuit shown in FIG. 2. The base of the first bipolar transistor 310 is connected to the collector of the second bipolar transistor 330. The collector of the first bipolar transistor 310 is connected to the base of the second bipolar transistor 330.

[0021] The surge suppression circuit 100 includes a metal oxide semiconductor field effect transistor (MOSFET) 110, a resistor 130, a Zener diode 150, and a capacitor structure 170. The metal oxide semiconductor field effect transistor 110 is electrically connected between the base of a second bipolar transistor 330 and a second alternating current voltage terminal AC2.

[0022] In detail, the metal oxide semiconductor field effect transistor 110 has a drain and a source. The drain is electrically connected to the base of the second bipolar transistor 330. The source is electrically connected to the second AC voltage terminal AC2. The metal oxide semiconductor field effect transistor 110 is an N-type metal oxide semiconductor field effect transistor (NMOSFET). In the present invention, the metal oxide semiconductor field effect transistor 110 is an enhancement type metal oxide semiconductor field effect transistor (enhancement type MOSFET).

[0023] The Zener diode 150 is electrically connected between the gate of the metal oxide semiconductor field effect transistor 110 and the second AC voltage terminal AC2. Since the Zener diode 150 is connected in parallel with the resistor 130, it is possible to prevent a dielectric breakdown of the gate of the metal oxide semiconductor field effect transistor 110.

[0024] The capacitor structure 170 is located between the gate and substrate terminal of the metal-oxide-semiconductor field-effect transistor 110, senses changes in dv / dt, and generates a corresponding sense current. As shown in Fig. 2, one end of the capacitor structure 170 is connected to the base of the first bipolar transistor 310. The potential of the base of the first bipolar transistor 310 is the same as the potential of the N-type substrate 190 of the metal-oxide-semiconductor field-effect transistor 110, and therefore can be considered to be connected to the N-type substrate 190 (i.e., the substrate terminal).

[0025] The resistor 130 is electrically connected between the gate of the metal oxide semiconductor field effect transistor 110 and the second alternating voltage terminal AC2, so that the resistor 130 can provide a voltage to the metal oxide semiconductor field effect transistor 110 in response to the induced current generated by the capacitor structure 170, thereby driving the metal oxide semiconductor field effect transistor 110.

[0026] In the present invention, the capacitor structure 170 is not an external capacitor, i.e., the capacitor structure 170 of the present invention is a parasitic capacitor, which is formed within the surge suppression circuit 100 by the circuit layout.

[0027] In this embodiment, the capacitor structure 170 is formed by the circuit layout with a P-type metal oxide semiconductor field effect transistor (PMOSFET) structure. In detail, as shown in FIG. 3, it can be seen that the cross section of the circuit layout within the dotted line area is similar to the NMOSFET on the right. The capacitor structure 170 is formed between two P-wells 191. The upper part of the capacitor structure 170 is similar to a PMOSFET, and the gate, drain, and source are connected to each other, so that the gate will not break down due to a high potential difference. The depletion region (not shown) is the region located between the N-type substrate 190 and the two P-wells 191.

[0028] A second embodiment of the present invention is shown in FIG. 4. Different from the capacitor structure 170 of the first embodiment, which is laid out in a structure similar to that of a PMOSFET, in this embodiment, the capacitor structure 170 is composed of a metal layer 192, a first oxide layer 193, a second oxide layer 194, and an N-type substrate 190. The metal layer 192 is the upper electrode, and the N-type substrate 190 is the lower electrode. The first oxide layer 193 and the second oxide layer 194 are located between the metal layer 192 and the N-type substrate 190. In the capacitor structure 170 of this embodiment, the first oxide layer 193 and the second oxide layer 194 are mainly parts that absorb surges.

[0029] A third embodiment of the present invention is shown in FIG. 5. The capacitor structure 170 is composed of a metal layer 192, a first oxide layer 193, and an N-type doped region 195. Unlike the capacitor structure 170 of the second embodiment having two oxide layers, in this embodiment, the capacitor structure 170 has an N-type doped region 195, and the second oxide layer 194 is removed. Therefore, compared with the capacitor structure 170 of the second embodiment, the thickness of the capacitor structure 170 of this embodiment is thinner. In this case, there is only one oxide layer (the first oxide layer 193), and the thickness of the oxide layer can be specified, so that the capacitance value of the capacitor structure 170 can be specified. Note that the N-type doped region 195 can be used as the bottom electrode of the capacitor structure 170 to eliminate the depletion region and avoid interference.

[0030] Looking at the capacitor structures 170 of the first, second and third embodiments, the surge suppression circuit 100 uses three different capacitor structures 170 but can withstand the same breakdown voltage.

[0031] Regarding the size of the entire integrated circuit, the area of ​​the surge suppression circuit 100 of the third embodiment is larger than that of the surge suppression circuit 100 of the second embodiment. The area of ​​the surge suppression circuit 100 of the second embodiment is larger than that of the surge suppression circuit 100 of the first embodiment.

[0032] Regarding the accuracy of the capacitance values ​​of the three capacitor structures 170, the accuracy of the capacitance value of the capacitor structure 170 of the third embodiment is higher than that of the capacitor structure 170 of the second embodiment. The accuracy of the capacitance value of the capacitor structure 170 of the second embodiment is higher than that of the capacitor structure 170 of the first embodiment.

[0033] As described above, the surge suppression circuit of the present invention uses resistors instead of the depletion-type metal oxide semiconductor field effect transistors used in existing dv / dt suppression circuits, making it possible to reduce the number of photomasks and simplify the manufacturing process. In addition, in the present invention, a P-type metal oxide semiconductor field effect transistor is used instead of a capacitor, making it possible to reduce the area of ​​the capacitor and the chip size. As a result, the surge suppression circuit of the present invention can simplify the manufacturing process, reduce the area of ​​the capacitor, and reduce the overall manufacturing cost.

[0034] The above examples are for explaining the embodiments of the present invention and for explaining the characteristic configuration of the present invention. The present invention is not limited to the above examples. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention is based on the claims. [Explanation of symbols]

[0035] 100 Surge Suppression Circuit 110 Metal Oxide Semiconductor Field Effect Transistor 130 Resistance 150 Zener Diode 170 Capacitor Structure 190 N-type substrate 191 P-well 192 Metal layer 193 First oxide layer 194 Second oxide layer 195 N-type doped region 300 Thyristor 310 First bipolar transistor 330 Second bipolar transistor 510 Depletion-type metal oxide semiconductor field effect transistor 520 Enhancement-type metal oxide semiconductor field effect transistor 530 Zener Diode 540 Capacitor T1 1st pin T2 2nd pin AC1 First AC voltage terminal AC2 Second AC voltage terminal

Claims

1. A surge suppression circuit for a thyristor, the thyristor being connected between a first AC voltage terminal and a second AC voltage terminal, the circuit comprising a first bipolar junction transistor (BJT) and a second bipolar transistor, the base of the first bipolar transistor being connected to the collector of the second bipolar transistor, and the collector of the first bipolar transistor being connected to the base of the second bipolar transistor; The surge suppression circuit comprises: a metal oxide semiconductor field effect transistor (MOSFET) formed on an N-type substrate having the same potential as that of the base of the first bipolar transistor and electrically connected between the base of the second bipolar transistor and the second AC voltage terminal; a resistor electrically connected between the gate of the metal oxide semiconductor field effect transistor and the second AC voltage terminal; a Zener diode electrically connected between the gate of the metal-oxide-semiconductor field effect transistor and the second AC voltage terminal; a capacitor structure located between the gate of the metal oxide semiconductor field effect transistor and the N-type substrate; The surge suppression circuit, characterized in that the capacitor structure is composed of a metal layer, a first oxide layer, a second oxide layer and a portion of the N-type substrate, the first oxide layer and the second oxide layer being sandwiched between the metal layer and the portion of the N-type substrate.

2. 2. The surge suppression circuit of claim 1, wherein the metal-oxide-semiconductor field effect transistor has a drain and a source, the drain electrically connected to the base of the second bipolar transistor and the source electrically connected to the second AC voltage terminal.

3. 2. The surge suppression circuit of claim 1, wherein the resistor is connected in parallel with the Zener diode.

4. 2. The surge suppression circuit of claim 1, wherein the metal oxide semiconductor field effect transistor is an enhancement type metal oxide semiconductor field effect transistor.

5. 2. The surge suppression circuit of claim 1, wherein the metal oxide semiconductor field effect transistor is an N-type metal oxide semiconductor field effect transistor (NMOSFET).

6. 2. The surge suppression circuit of claim 1, wherein the resistor drives the metal-oxide-semiconductor field-effect transistor in response to an induced current generated by the capacitor structure.

7. A surge suppression circuit for a thyristor, the thyristor being connected between a first AC voltage terminal and a second AC voltage terminal, the thyristor having a first bipolar transistor and a second bipolar transistor, the base of the first bipolar transistor being connected to a collector of the second bipolar transistor, the collector of the first bipolar transistor being connected to the base of the second bipolar transistor, The surge suppression circuit comprises: a metal oxide semiconductor field effect transistor (MOSFET) formed on an N-type substrate having the same potential as that of the base of the first bipolar transistor and electrically connected between the base of the second bipolar transistor and the second AC voltage terminal; a resistor electrically connected between the gate of the metal oxide semiconductor field effect transistor and the second AC voltage terminal; a Zener diode electrically connected between the gate of the metal-oxide-semiconductor field effect transistor and the second AC voltage terminal; a capacitor structure located between the gate of the metal oxide semiconductor field effect transistor and the N-type substrate; 11. A surge suppression circuit comprising: a capacitor structure comprising a metal layer, an oxide layer, and an N-type doped region, the oxide layer being sandwiched between the metal layer and the N-type doped region.

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