Driving circuit for semiconductor device, method thereof, power conversion device and manufacturing method thereof

Abstract

To provide a drive circuit for a semiconductor device capable of reducing power loss by simply and easily equalizing turn-on surge current between switching elements connected in parallel.SOLUTION: In a power conversion device 500, a main circuit (drive circuit 35) has a control function that can turn on the main circuit by applying voltage of a threshold voltage or more to at least one gate terminal of a first gate terminal 3 that can control timing of conductive or non-conductive installed on each of a plurality numbers of multi-gate type IGBTs 1 and 2 and a second gate terminal 4 that can control internal carrier concentration. The main circuit comprises: a first output unit having a common time constant to equalize a required time for charging with respect to each of first gate terminals between the multi-gate type IGBTs connected in parallel; and a second output unit that independently controls required time for charging of each of second gate terminals to equalize the maximum value of each of turn-on surge currents between the multi-gate type IGBTs connected in parallel.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a semiconductor device drive circuit, a semiconductor device drive method, a power conversion device to which these are applied, and a method for manufacturing the power conversion device. [Background technology]

[0002] Global warming has become an important and urgent issue shared by the world. There are growing expectations that power electronics technology will contribute as one of the countermeasures. In particular, in order to increase the efficiency of inverters, which control the power conversion function, there is a demand to reduce the power consumption of the power semiconductor devices that make up the inverters, mainly IGBTs (Insulated Gate Bipolar Transistors) that perform the power switching function and diodes that perform the rectification function.

[0003] However, when the operating characteristics of switching elements connected in parallel to increase current capacity are not uniform, the simultaneity of control of conduction or non-conduction (ON⇔OFF control) is not guaranteed, which causes a decrease in power conversion efficiency. As a method for balancing the turn-on surge current between parallel-connected IGBTs, there is a known technique for adjusting the bias applied to the gates of parallel-connected IGBT elements described in Patent Document 1. Furthermore, Patent Document 2 describes a means for selecting elements in the IGBT manufacturing stage so as to equalize the turn-on surge currents of parallel-connected IGBTs.

[0004] The turn-on surge current of an IGBT is correlated with the threshold voltage of the IGBT. This phenomenon occurs when a gate bias is applied to the IGBT and a turn-on surge current occurs when the threshold voltage is exceeded. The threshold voltage of an IGBT is not constant, and this is due to variations in its manufacturing and structure. By setting a standard based on the turn-on surge current for this threshold voltage and selecting IGBTs to be connected in parallel, it is possible to balance the turn-on surge current between the parallel-connected IGBTs. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Application No. 2017-115900 Summary of the Invention [Problem to be solved by the invention]

[0006] The technology described in Patent Document 1 has realized a power conversion device that can make the transient current (turn-on surge current) at turn-on between the parallel-connected IGBTs (hereinafter referred to as "parallel elements 1 and 2") constituting the main circuit uniform, and can pass a large current through the main circuit without biasing the current between the parallel elements 1 and 2. However, there is a problem that a separate power supply capable of applying various gate biases is required for the drive circuit (gate circuit) of each parallel-connected IGBT. If a highly reliable power conversion device is realized in response to this, there are side effects such as an increase in the volume of the power conversion device and an increase in the burden of labor and resources required to select IGBTs according to standards established to improve the current balance between the parallel elements 1 and 2.

[0007] Thus, it was difficult to simply and easily improve the current balance of parallel-connected IGBTs in the technology shown in Patent Document 1. The present invention has been made to solve the above problem, and an object of the present invention is to provide a semiconductor device driver circuit that can simply and easily equalize turn-on surge currents between parallel-connected switching elements to reduce power loss. [Means for solving the problem]

[0008] The present invention, which solves the above-mentioned problems, provides a semiconductor device drive circuit for controlling a semiconductor device in which a main circuit is formed by connecting switching elements in parallel, the main circuit comprising a plurality of multi-gate IGBTs as switching elements, each of the plurality of multi-gate IGBTs comprising a first gate terminal capable of controlling the timing of conduction or non-conduction, and a second gate terminal capable of controlling the internal carrier concentration, and configured to be turned on by applying a voltage equal to or greater than a threshold voltage to at least one of the first gate terminal and the second gate terminal, the semiconductor device drive circuit comprising a first output section which outputs a gate voltage so that the required charging time of the first gate terminal of each of the plurality of multi-gate IGBTs is equal, and a second output section which outputs a gate voltage so that the required charging time of the second gate terminal of each of the plurality of multi-gate IGBTs can be individually controlled. Effect of the Invention

[0009] According to the present invention, it is possible to provide a semiconductor device driver circuit capable of simply and easily equalizing turn-on surge currents between switching elements connected in parallel to reduce power loss. Problems, configurations, and effects other than those described above will become apparent from the description of the following embodiments. [Brief description of the drawings]

[0010] [Figure 1] 1 is a circuit diagram showing a semiconductor device driver circuit according to a first embodiment of the present invention (hereinafter also referred to as "the present driver circuits 10, 11") and a power converter to which the driver circuit is applied (hereinafter also referred to as "the present power converter 200"). [Diagram 2] FIG. 1 is a diagram illustrating the saturation current performance of a multi-gate IGBT. [Diagram 3] 4 is a timing chart showing a turn-on operation in a parallel element of the power conversion device of FIG. [Figure 4] FIG. 13 is a diagram for explaining the saturation current performance of a multi-gate IGBT by setting the Gc gate bias to a variable value. [Diagram 5]1 is a drive circuit diagram of a multi-gate IGBT and a timing chart showing a turn-on operation. [Figure 6A] FIG. 6A is a correlation graph showing the Gc gate resistance to be set on the vertical axis and the saturation performance of the IGBT on the horizontal axis. [Figure 6B] This is a correlation diagram in which the horizontal axis of FIG. 6A is changed from the saturation performance of the IGBT to the threshold voltage of the IGBT. [Figure 7] 2 is a circuit diagram of a drive circuit and a power conversion device showing a modified example of the drive circuit and the power conversion device shown in FIG. 1. [Figure 8] FIG. 1 is a diagram showing a semiconductor device driver circuit according to a second embodiment of the present invention (hereinafter also referred to as "the present driver circuit 35"), and a power converter (the present power converter 400) to which the same is applied. [Figure 9] 10 is a timing chart showing a turn-on operation in a parallel element of the power conversion device of the second embodiment. [Figure 10] 1 is a timing chart showing the on command delay time Gc (hereinafter simply referred to as “Gc delay”) of the Gc gate 4 relative to the Gs gate 3, and a correlation graph showing the Gc delay on the vertical axis and the collector saturation current of the IGBT on the horizontal axis. [Figure 11] 1 shows a semiconductor device driver circuit (present driver circuit 35) according to a third embodiment of the present invention, a power converter (present power converter 500) to which the same is applied, and a look-up table used therein. [Figure 12] FIG. 13 is a diagram showing how the Gc delays of the multi-gate IGBTs connected in parallel are set according to the saturation current performance of the multi-gate IGBTs. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. An embodiment 1 is shown in Figs. 1 to 7 (modifications). An embodiment 2 is shown in Figs. 8 to 10. An embodiment 3 is shown in Figs. 11 to 12. As shown in these embodiments 1 to 3, multi-gate IGBTs 1 and 2 (hereinafter, simply referred to as "IGBTs 1 and 2") are used as switching elements 1 and 2 in all main circuits. In the following figures, the illustration of the reference conductive lines that are conductive with the emitters of the multi-gate IGBTs 1 and 2 may be omitted for simplicity. Note that in the figures, the conductive lines that transmit the gate signal may be simply shown as a single line to the gate terminal, but in reality, a reference conductive line is also present to use the emitter potential as a reference, and a voltage relative to the reference potential is input.

[0012] In addition, the power conversion devices 200, 300, 400, 500, typified by inverters, are generally configured as a three-phase circuit in which three circuits for one phase, each of which has a load 8 connected to the IGBTs 1 and 2 and a free wheel diode (hereinafter also simply referred to as a "diode") 7 of each of the upper and lower arms 71 and 72, are arranged in parallel. However, only one phase of the three-phase circuit is shown here, and the circuit can be applied to the other phases. Also, the load 8 is connected in parallel to the IGBT and diode 7 of the lower arm 72, and drive circuits (gate circuits) 10, 11, and 35 are shown only for the IGBT of the upper arm 71, but are omitted from the description of the IGBT of the lower term 72 because they are similar. In the following description, a configuration in which two elements are connected in parallel as a main circuit to increase the current capacity is shown as an example, but the present invention can be applied to three or more elements in the same manner. EXAMPLES

[0013] Example 1 is shown in Fig. 1 to Fig. 7 (modification). Fig. 1 is a circuit diagram showing semiconductor device driving circuits 10, 11 according to Example 1 of the present invention, and a power conversion device 200 to which the same is applied. The driving circuits 10, 11 of Example 1 shown in Fig. 1 are a driving method for multi-gate type IGBTs 1, 2 each having two gates. Moreover, the main circuit of the power conversion device 200 in Fig. 1 is configured by connecting the multi-gate type IGBTs 1, 2 in parallel.

[0014] Multi-gate IGBTs 1 and 2 are composed of two insulated gate terminals 3 and 4, one emitter terminal, and one collector terminal, and are turned on when a gate-emitter voltage (hereafter referred to as gate voltage) equal to or greater than the threshold voltage is applied to at least one gate terminal, and are turned off when a gate voltage less than the threshold voltage is applied to the two gate terminals 3 and 4. In this way, the IGBTs 1 and 2 can control whether the main circuit (between the collector and emitter) is turned on or off (ON⇔OFF) by the gate voltage applied to the two gate terminals 3 and 4.

[0015] Here, the gate terminal 3 capable of controlling the timing of conduction or non-conduction is defined as a switching gate (Gs gate) 3, and the other gate terminal 4 is defined as a carrier control gate (Gc gate) 4 as a terminal capable of controlling the internal carrier concentration of the multi-gate IGBTs 1 and 2. The power conversion device 200 is composed of two multi-gate IGBTs 1 and 2 connected in parallel and arranged on arms 71 and 72 facing an inductive load 8.

[0016] The multi-gate IGBTs 1 and 2 are simultaneously controlled to be switched on or off by signals from the gate bias drive generating circuit 9 from the respective drive circuits 10 and 11. In order to suppress noise caused by time variations in voltage and current during switching, a Gs gate resistor 5 and a Gc gate resistor 6 are set in the Gs gate 3 and the Gc gate 4, respectively, for the purpose of suppressing time variations. In the circuit of the first embodiment, the Gs gate resistor 5 is set equally between the parallel elements 1 and 2, and the Gc gate resistor 6 is variably adjusted according to the saturation current performance of the IGBT elements 1 and 2.

[0017] Fig. 2 is a diagram for explaining the saturation current performance of a multi-gate IGBT. As shown in Fig. 2, an IGBT is a semiconductor device, and structurally, variations in saturation current performance occur due to variations in gate oxide film thickness and impurity concentration. The example in Fig. 2 shows the variation in saturation performance between two parallel IGBTs 1 and 2 applied to a power conversion device, with IGBT 2 having a higher saturation performance than IGBT 1. Below, a case where these are applied to a power conversion device 200 is assumed.

[0018] In the multi-gate IGBTs 1 and 2, which can control the magnitude of carriers, the bias applied to the Gc gate of IGBT 2, which has a large saturation performance, is adjusted to be lower than that of IGBT 1. As a result, it is possible to adjust IGBT 2 to have the same saturation performance as IGBT 1.

[0019] By utilizing this characteristic, the turn-on surge currents between the parallel elements 1 and 2 in the power conversion device 200 can be made uniform. In the first embodiment shown in Fig. 1, only the Gc gate resistor 6 is adjusted according to the saturation current performance. On the other hand, the Gs gate resistor 5 is set to a time constant τ (not shown) for aligning the turn-on timing (t1 in Fig. 3) between the parallel elements 1 and 2.

[0020] FIG. 3 is a timing chart showing the turn-on operation of the parallel elements of the power conversion device 200. The Gs gate bias V GS , Gc gate bias V GC , collector current I C , collector-emitter voltage V CE The effects of the present invention will be described below with reference to FIG.

[0021] In FIG. 3 as well, it is assumed that the saturation performance of the two IGBTs connected in parallel is small for IGBT 1 and large for IGBT 2. For both IGBTs 1 and 2, the Gs gate bias V GS When the Gs gate reaches the threshold voltage Vth after the charging time, the collector current IC In other words, the collector current I C begins to flow and turn-on begins.

[0022] After this, Gs gate bias V GS and Gc gate bias V GC As the collector current I C This large transient current is called the turn-on surge current 15, 16.

[0023] When using an element whose saturation performance varies due to some factor in the IGBT manufacturing, if the Gc gate resistor 5 is set to be equal, the same Gc gate bias V GS As a result, the turn-on surge current 16 of IGBT 2 becomes larger than the solid line 15 of IGBT 1, and a current imbalance occurs between the parallel elements 1 and 2, as shown by the solid lines 15 and 16.

[0024] In this state, the collector-emitter voltage V CE The high voltage is maintained at V CE Therefore, when the turn-on surge current flows, a power loss occurs due to the product of voltage and current. As a result, the temperatures of IGBTs 1 and 2 rise due to the heat generated by the power loss.

[0025] If the turn-on surge current varies between the parallel elements 1 and 2, the temperature rise between them will be uneven, causing problems such as the maximum current value of the power conversion device that can be passed, which is specified by the maximum temperature, being specified low, or causing problems such as a shortened lifespan due to temperature. In the present drive circuits 10 and 11, the variable Gc gate resistor 6 is adjusted according to the saturation performance of the IGBT.

[0026] The GC gate bias V GCWhile IGBT 1 is shown by the solid line 18, IGBT 2 is shown by the dashed line 20, which shows a slow rise over time. As a result, the Gc gate bias V GC Due to this function, the drive circuits 10 and 11 can equalize the turn-on surge currents between the IGBTs 1 and 2.

[0027] On the other hand, the Gs gate resistor 5 turns on and the collector current I C This determines the timing at which the Gs gate resistor 5 rises, and because this is set equally between the parallel elements 1 and 2, the turn-on timing is not shifted and they are turned on simultaneously at t1. That is, in a power conversion device 200 in which multi-gate IGBTs 1 and 2 are connected in parallel, the Gs gate resistor 5 is set to the same value between the parallel elements 1 and 2, and the Gc gate resistor 6 is variably adjusted according to the saturation current of each of the parallel-connected IGBTs. This makes it possible to equalize the turn-on surge current between the parallel elements 1 and 2, and to provide a highly reliable power conversion device 200 with no uneven temperature rise.

[0028] The effects of the first embodiment will be described with reference to Figs. 4 to 6. Fig. 4 is a diagram for explaining the saturation current performance of the multi-gate IGBTs 1 and 2 when the Gc gate bias is set to a variable value. That is, Fig. 4 shows the saturation current performance of the multi-gate IGBTs 1 and 2 applied to the power conversion device 200 when the Gs gate bias V GS is fixed, and Gc gate bias V GC is set to variable, and the collector-emitter bias V CE By sweeping the collector current I C 4 is a waveform of the saturated performance obtained by monitoring the

[0029] Thus, Gc gate bias V GC By variably setting, it is possible to adjust the saturation performance in various ways. Here, a saturation performance 22 that can balance between the parallel elements 1 and 2 is specified. That is, Gc on-bias V GCGc gate bias V is set between the large (Strong Bias) and small (Weak Bias) settings to output a balanced saturation performance. GC is determined to be the optimal value.

[0030] In addition, by using FIG. 5, the optimum Gc gate bias V that can balance the turn-on surge current can be obtained by adjusting the GC gate resistor 23. GC 5 is a drive circuit diagram of multi-gate IGBTs 1 and 2 (only one is shown) and a timing chart showing the turn-on operation. The Gs gate and Gc gate of each of the multi-gate IGBTs 1 and 2 have gate capacitances 24 and 25 due to the gate oxide film, respectively.

[0031] Command signal C in Figure 5 GS As shown in FIG. 1, when an OFF to ON command 26 is applied to the Gs gate, the Gs gate capacitance is charged and the Gs gate bias V GS The same is true for the Gc gate, and the command signal C in Figure 5 GC As shown in FIG. 1, when an OFF to ON command 27 is applied to the Gc gate, the Gc gate capacitance is charged, and the Gc gate bias V GC When the threshold voltage is reached, a channel is generated in the IGBT and a current I flows from the collector to the emitter. C flows.

[0032] When the gate resistor Gc 23 is set small, the collector current I C When the collector current I C The transient Gc bias 29 when becomes maximum is not small, resulting in a small turn-on surge current 33. On the other hand, if the Gs gate resistance 31 is fixed, it is possible to fix the turn-on start time to t1 without changing the time from when the Gs gate ON command is applied until the turn-on current becomes maximum.

[0033] That is, the multi-gate IGBTs 1 and 2 can adjust the magnitude of the turn-on surge current flowing through the collector without delay by changing the magnitude of the Gc gate resistance 23. It is also possible to set an optimal Gc gate resistance 23 that matches the Gc gate bias 30 to be applied at that time, for the performance 34 that can balance the turn-on surge current between the parallel elements 1 and 2.

[0034] FIG. 6A shows the saturation current I of IGBT 1 and 2, with the gate resistance R to be set as the vertical axis. C The horizontal axis shows the correlation between the turn-on surge current and the on-bias of the Gs gate. By increasing the Gc gate resistance R, the Gc gate bias V GC Since it is possible to reduce the correlation, FIG. 6A shows a positive correlation toward the upper right.

[0035] As described above, in the power conversion device 200 in which the multi-gate type IGBTs 1 and 2 are connected in parallel, the turn-on surge current can be made to flow evenly between the parallel elements 1 and 2 by variably adjusting the Gc gate resistor R according to the saturation current of the IGBT. A similar correlation also exists for the threshold voltage Vth of the IGBT.

[0036] In Fig. 6B, the horizontal axis of Fig. 6A is the saturation current I C 6B is a correlation graph in which the Gc gate resistance R to be set is plotted on the vertical axis and the threshold voltage Vth of the IGBTs 1 and 2 is plotted on the horizontal axis. GS is fixed.

[0037] As shown in Figure 6B, by reducing the Gc gate resistance R, the Gc gate bias V GC Therefore, for an IGBT with a high threshold voltage Vth, setting the Gc gate resistance R small will tend to keep the turn-on surge current constant, and Figure 6B shows a negative correlation toward the lower right.

[0038] From the above, in the power conversion device 200 in which the multi-gate type IGBTs 1 and 2 are connected in parallel, the gate resistance R is set to the saturation current I C The effect of allowing the turn-on surge current to flow evenly between the parallel elements 1 and 2 by variably adjusting and setting an optimum value according to the switching frequency (FIG. 6A) or according to the threshold voltage Vth (FIG. 6B) has been described.

[0039] Fig. 7 is a circuit diagram of a drive circuit 35 and a power conversion device 300 showing a modification of the power conversion device 200 in Fig. 1. The drive circuit 35 is shared between the parallel IGBTs 1 and 2, and includes variable type Gc gate resistors 6 arranged symmetrically about the midpoint where the Gc gates 4 of the multi-gate IGBTs 1 and 2 are connected, Gs gate resistors 5 arranged symmetrically about the midpoint where the Gs gates 3 are connected, and gate bias drive generating circuits 9 connected to each of these midpoints.

[0040] 7, by adjusting the variable Gc gate resistor 6 between the parallel elements 1 and 2 without increasing the number of gate bias drive generating circuits 9, it is possible to obtain the effect of causing the turn-on surge current to flow evenly between the parallel elements 1 and 2. The power conversion device 300 in FIG. 7 can simply and easily derive the above-mentioned effect by simply changing only the Gc gate resistor 6 without increasing the number of power supplies for the drive circuit. EXAMPLES

[0041] A second embodiment of the present invention will be described with reference to Figs. 8 to 10. Fig. 8 is a diagram showing a semiconductor device driving circuit 35 according to the second embodiment, and a power conversion device 400 to which the same is applied. As shown in Fig. 8, the power conversion device 400 is composed of two multi-gate type IGBTs 1 and 2 connected in parallel and arranged on arms 71 and 72 facing an inductive load 8. The switching operation of each of the multi-gate type IGBTs 1 and 2, whether conductive or non-conductive, is controlled by four command signals output from a common driving circuit 35 and supplied by two Gs gate lines and two Gc gate lines.

[0042] Here, the command signal C GS ,C GC (FIGS. 3 and 9) are generated by a common gate bias drive generation circuit 9. In order to suppress noise caused by time changes in voltage and current during switching, fixed gate resistors 5 and 6 are inserted between the two Gs gate lines and the two Gc gate lines for the purpose of suppressing time changes. In the circuit of Example 2, the command timing for turning on the Gs gate and Gc gate is variably adjusted between the two multi-gate IGBT 1 and 2 elements connected in parallel.

[0043] FIG. 9 is a timing chart showing the turn-on operation of the parallel elements of the power conversion device 400 of the second embodiment, and shows the command timing C of the Gs gate and the Gc gate of each of the multi-gate type IGBTs 1 and 2. GS ,C GC and the resulting Gs gate bias V GS , and Gc gate bias V GC The time course of the collector current I C , collector-emitter voltage V CE The effects of the present invention will be described below with reference to FIG.

[0044] In FIG. 9, the saturation performance of the two parallel-connected IGBTs 1 and 2 is assumed to be small for IGBT 1 and large for IGBT 2. Both IGBTs 1 and 2 receive an ON command from the Gs gate and are turned on by the Gs gate bias V GS When the Gs gate reaches the threshold voltage Vth after the charging time, the collector current I C rises. In other words, IGBTs 1 and 2 start to turn on and current begins to flow.

[0045] After this, Gs gate bias V GS and Gc gate bias V GC As a result of the increase in the saturation performance of IGBTs 1 and 2, the collector current I Crises to a maximum value, generating a turn-on surge current 15. If IGBTs 1 and 2, whose saturation performance varies due to some manufacturing factor, are used as parallel elements, and the command timing of the Gc gate is set to the same timing 37 on the multi-gate IGBT 1 side and the multi-gate IGBT 2 side, a current imbalance will occur between the parallel elements.

[0046] In other words, in FIG. 9, if the command timing of the Gs gate of IGBT 2 is set to be equal, the same Gc bias 37 is applied when the turn-on surge current flows, so that the turn-on surge current of IGBT 2 becomes larger than that of IGBT 1 as shown by solid line 16, and when the maximum current is applied, a current imbalance occurs between the elements connected in parallel in the power conversion device 400.

[0047] In this state, as explained in the first embodiment, there is a bias in the temperature rise between IGBT 1 and IGBT 2. If two parallel-connected elements reach different temperatures at the same time, the current is limited with some margin left for the low-temperature side that has not yet reached the limit, in order to avoid the danger of the high-temperature side first. As a result, the maximum current value of the power conversion device, which is regulated by the maximum temperature, is regulated low. In this way, if the temperature is raised to the limit at a point that has not yet reached the low-temperature limit regulated low, a problem of shortened life due to temperature will occur.

[0048] In the second embodiment, the timing of issuing an ON command to the Gc gate is variably adjusted according to the saturation performance of the IGBT. In this case, in the multi-gate IGBT 2 with a large saturation current, the timing of issuing an ON command to the Gc gate is set to be delayed until the Gs gate is turned on, as shown by the dashed line 38. As a result, the Gc gate bias V applied to the multi-gate IGBT 2 GC As shown by the dashed line 40, the Gc gate bias V of IGBT 1 GC Compared to the gate bias V, the turn-on current increases slowly over time, so the gate bias V GC It is possible to reduce the

[0049] This makes it possible to equalize the turn-on surge current between IGBT 1 and IGBT 2. On the other hand, the Gs gate-on command C GS The timing of turning on and the collector current I C This timing t1 determines the timing t1 at which the Gs gate-on command C GS Since the timing is set equally, they start turning on at the same time without any lag.

[0050] That is, between parallel elements 1 and 2, the Gs gate-on command C GS The timing is set equal, and the gate bias V is set according to the saturation current of each IGBT. GC By variably adjusting the turn-on surge current, it is possible to provide a highly reliable power conversion device 400 without uneven temperature rise.

[0051] The effect of the second embodiment will be described with reference to Fig. 10. Fig. 10 is a timing chart showing the on-command delay time Gc delay 41 of the Gc gate 4 with respect to the Gs gate 3, and the collector saturation current I S In FIG. 10, the turn-on surge current I C is kept constant, and the on-bias of the Gs gate is fixed.

[0052] Increase one Gc delay 41 and the Gc on command C GS The timing of the other Gc ON command C GS By delaying the timing of the gate bias Vc, the transient rise in the gate bias Vc at turn-on is suppressed. GC Therefore, in FIG. 10, the correlation becomes positive toward the upper right. From the above, in the power conversion devices 200, 300, and 400 in which the multi-gate type IGBTs 1 and 2 are connected in parallel, the Gc gate-on command C GC The timing of the IGBT saturation current I CBy adjusting the value according to the C The reason why current can flow evenly between parallel elements 1 and 2 is explained. EXAMPLES

[0053] Third embodiment is shown in Fig. 11 and Fig. 12. A driving method for multi-gate type IGBTs 1 and 2 having two gates according to a third embodiment of the present invention, and a power conversion device 500 to which the same is connected in parallel will be described with reference to Fig. 11 and Fig. 12. Fig. 11 shows a circuit diagram of the present driving circuit 35 and the power conversion device 500 to which the same is applied, and a look-up table used therefor.

[0054] The power conversion device 500 is composed of two parallel-connected multi-gate IGBTs 1 and 2 arranged on arms 71 and 72 facing an inductive load 8. The switching operation of each of the multi-gate IGBTs 1 and 2, whether conductive or non-conductive, is controlled by four command signals output from a common drive circuit 35 and supplied by two Gs gate lines and two Gc gate lines.

[0055] 11, the drive circuit 35 is equipped with a programmable microcomputer or FPGA (Free Programmable Gate Array) 43, which outputs four command signals. The four command signals are power-amplified by an output buffer circuit 42 inside the drive circuit 35, and drive the Gs gate 3 and the Gc gate 4 of the multi-gate type IGBTs 1 and 2.

[0056] The microcomputer or FPGA 43 (FPGA, etc. 43) is equipped with a lookup table function that sets and outputs the Gc delay 41 for each element according to the input value. A lookup table is a data structure such as an array or associative array that is created to improve efficiency by replacing complex calculation processing with simple array reference processing. This FPGA, etc. 43 is configured so that the Gc delay 41 is determined by a pre-programmed lookup table according to the saturation current performance of the multi-gate IGBTs 1 and 2.

[0057] Fig. 12 is a diagram showing how the Gc delays 41 of the multi-gate IGBTs 1 and 2 connected in parallel are set according to the saturation current performance of the multi-gate IGBTs 1 and 2. As shown in Fig. 12, the saturation current performance obtained before incorporating the IGBTs 1 and 2 into the power conversion device 500 is read into the FPGA or the like 43, for example, as a value equal to or greater than A and less than B, and a value equal to or greater than C and less than D. With this input information, the delay times a and c of the on-command signal of the Gc gate for equalizing the turn-on surge current are automatically set inside the FPGA or the like 43 based on the set look-up table.

[0058] As a result, in order to equalize the turn-on surge currents of the multi-gate IGBTs 1 and 2 connected in parallel, an on command delay period 41 for the Gc gate 4 relative to the Gs gate 3 is set and output from the present drive circuit 35. According to the configuration of the third embodiment, the turn-on surge currents between the parallel elements 1 and 2 can be easily equalized without increasing the number of drive circuits for each of the IGBTs connected in parallel, and a power conversion device 500 with low loss, high efficiency, and high reliability can be provided.

[0059] The semiconductor device driver circuits according to the embodiments of the present invention (the driver circuits 10, 11, and 35) can be summarized as follows. [1] The driving circuits 10, 11, 35 are driving circuits for ON⇔OFF control of a main circuit in a semiconductor device such as an inverter. In order to increase the current capacity of the main circuit, multiple switching elements 1, 2 are connected in parallel. If the operating characteristics of the parallel-connected switching elements 1, 2 are not uniform, the simultaneity of ON⇔OFF control is not guaranteed, which causes a decrease in power conversion efficiency.

[0060] Therefore, by adopting multi-gate IGBTs 1 and 2 (same symbols) for the switching elements 1 and 2 that make up the main circuit and easily aligning the ON⇔OFF operation timing, it is possible to suppress the decrease in power conversion efficiency. Each of the multi-gate IGBTs 1 and 2 has a first gate terminal 3 and a second gate terminal 4, and has a control function that transitions from a non-conductive state to a conductive state (turns on) when a voltage equal to or higher than the threshold voltage is applied to at least one of the gate terminals.

[0061] The first gate terminal 3 is a switching gate (Gs gate) terminal 3 that can control the timing of conduction or non-conduction in the multi-gate IGBTs 1 and 2. The second gate terminal 4 is a carrier control gate (Gc gate) terminal 4 that can control the internal carrier concentration, i.e., the current, of the multi-gate IGBTs 1 and 2.

[0062] The driving circuits 10, 11, and 35 each include an output section that applies a control signal to the first gate terminal 3 and the second gate terminal 4 of each of the multi-gate IGBTs 1 and 2. The output section has a first output section that controls the time required to charge the first gate terminal 3, and a second output section that controls the time required to charge the second gate terminal 4.

[0063] The first output section has a function of applying a control signal with an equal time constant τ (see FIG. 3 and FIG. 9) set to equalize the time required to charge the first gate terminal 3 of each of the parallel-connected multi-gate type IGBTs 1 and 2. This provides the effect of aligning the time required to turn on the parallel-connected multi-gate type IGBTs 1 and 2. The time constant τ is a value calculated by substituting the resistance value R and capacitance value C into a specified formula, and represents the rate of change of the transient phenomenon (time required to charge).

[0064] The capacitance value C here is the capacitance component C (gate capacitance 24, 25 in FIG. 5) present at the boundary surface between the emitter and gate of the switching elements 1, 2, which causes delays in switching operations, so the smaller the better, but eliminating it is structurally unavoidable, and it is not something that can be changed after the manufacturing of the switching elements 1, 2. The resistance value R is the electrical resistance R present in the path that applies a control signal from the output part of the present drive circuit 10, 11, 35 to the gate electrode. When the present drive circuit 10, 11, 35 applies a control signal from its output part to the gate, a predetermined voltage is charged in the RC charging circuit by a transient phenomenon determined by a time constant τ based on the RC value.

[0065] Even if the capacitance value C at the interface between the emitter and the gate cannot be changed after the manufacturing of the switching elements 1 and 2, it is not impossible to adjust the resistance value R of the path that charges the gate with a control signal at the output section of the present drive circuits 10, 11, and 35 before or after assembly or even during operation.

[0066] On the other hand, the second output section has a function of individually controlling the time required to charge each of the second gate terminals 4 so that the maximum values ​​of the turn-on surge currents in the multi-gate IGBTs 1 and 2 connected in parallel are equal to each other.

[0067] The driving circuits 10, 11, and 35 apply control signals to the first gate terminal 3 and the second gate terminal 4 of the parallel-connected multi-gate IGBTs 1 and 2 that are the objects of control, so as to equalize the charging times. As a result, the timing t1 in Fig. 3 is fixed and aligned in the two IGBTs 1 and 2. In other words, the timing t1 at which the collector current actually starts to rise after a certain time delay occurs after receiving a gate ON command is aligned to be the same in the parallel-connected multi-gate IGBTs 1 and 2.

[0068] In addition, the peak current values ​​arriving at timing t2 after timing t1 in the two IGBTs 1 and 2 are also fixed and aligned. For example, in the present driving circuits 10, 11, and 35, the Gc gate resistance is variably adjusted according to the saturation performance of the IGBTs. As a result, the Gc gate bias rises slowly over time compared to the Gc gate bias 18 of IGBT 1, as shown by the dashed line 20 in FIG. 3, so that the Gc gate bias V GC can be reduced.

[0069] This makes it possible to equalize the turn-on surge current between IGBT 1 and IGBT 2. In this way, the present drive circuits 10, 11, and 35 can equalize the turn-on surge current between the parallel-connected switching elements 1 and 2, reducing loss and reducing uneven temperature rise. As a result, the disadvantage of a low maximum current value that can flow through the power conversion devices 200, 300, 400, and 500, which is regulated by the maximum temperature, is eliminated, and the problem of reduced life span due to temperature is also resolved.

[0070] [2] In the driving circuits 10, 11, and 35 described in [1] above, the charging time required for the second gate terminals 4 of the parallel-connected multi-gate IGBTs 1 and 2 is controlled by the value of the gate resistors connected to the second gate terminals 4, respectively.

[0071] [3] In the drive circuits 10, 11, 35 described in [1] above, the charging time required for the second gate terminal 4 of each of the parallel-connected multi-gate IGBTs 1, 2 is controlled by the time difference between applying a voltage equal to or greater than the threshold voltage to each of the first gate terminals 3 prior to the second gate terminal 4. This control equalizes the turn-on surge currents between the parallel-connected switching elements 1, 2, reducing losses and reducing uneven temperature rises.

[0072] [4] In the present driving circuits 10, 11, 35 of the above [2] or [3], the values ​​of the gate resistances connected to the second gate terminals 4, or the respective time differences, are individually set based on the saturation current performance or threshold voltage of the respective multi-gate IGBTs 1, 2. This allows the present driving circuits 10, 11, 35 (driver circuits) and the present power conversion devices 200, 300, 400, 500 (inverters, etc.) to be adjusted to optimal values ​​during assembly, after assembly is completed, or even during actual operation.

[0073] [5] In the present driving circuits 10, 11, and 35 described in [4] above, the correlation between the saturation current performance and the gate resistance value or the time difference is positive, and the correlation between the threshold voltage and the gate resistance value or the time difference is negative. Optimal control based on such correlation is also possible.

[0074] [6] In any of the drive circuits 10, 11, and 35 described above in [2] to [5], the parallel-connected multi-gate IGBTs 1 and 2 are generated by the same voltage source. This can simplify the circuit.

[0075] [7] In the present driving circuit 35 described in [6] above, the gate resistances or time differences connected to the second gate terminals 4 are written into a programmable integrated circuit, and a correspondence table of gate resistances or time differences corresponding to the saturation current performance or threshold voltage of the multi-gate IGBTs 1 and 2 is programmed in the programmable integrated circuit, so that the gate resistances or time differences are determined according to the saturation current performance or threshold voltage. This allows computerization.

[0076] [8] The following power converter (inverter, etc.) 200, 300, 400, 500 may be configured by including the driving circuit 10, 11, 35 (driver circuit) described above in [7]. That is, it is preferable to include a DC / AC conversion (inverter) circuit configured by connecting a pair of DC terminals (collector and emitter) and at least two semiconductor devices (upper and lower arms 71, 72) that open and close (ON⇔OFF) the current in series, an AC terminal connected to a location in the DC / AC conversion circuit where at least two semiconductor devices 71, 72 are connected, and a free wheel diode 7 connected in anti-parallel to at least two semiconductor devices 71, 72. Such a power converter 200, 300, 400, 500 can configure a single-phase or three-phase inverter, etc.

[0077] The semiconductor device driving method according to the embodiment of the present invention (the present method) can be summarized as follows. [9] This method is a method for driving a semiconductor device having a main circuit in which multiple switching elements 1, 2 are connected in parallel. Multiple multi-gate IGBTs 1, 2 constituting the main circuit have a first gate terminal 3 and a second gate terminal 4. A control signal is applied to these first gate terminal 3 and second gate terminal 4 to control whether they are conductive or non-conductive. The main circuit can be turned on by applying a voltage equal to or higher than a threshold voltage to at least one of the first gate terminal 3 and the second gate terminal 4.

[0078] A first output section having the same time constant τ charges each of the first gate terminals 3 of the parallel-connected multi-gate IGBTs 1 and 2 for an equal required time. A second output section charges each of the parallel-connected second gate terminals 4 so as to equalize the transient maximum values ​​of the turn-on currents flowing through them. In this way, this method turns on the parallel-connected multi-gate IGBTs 1 and 2. This method makes it possible to simply and easily equalize the turn-on surge currents between the parallel-connected switching elements 1 and 2, thereby reducing power loss.

[0079]

[10] The manufacturing method (present manufacturing method) of the power conversion devices 200, 300, 400, 500 described above in [8] may include the following steps. First, the saturation current performance and threshold voltage are measured in advance as various measurement items for the operating characteristics of the multi-gate IGBTs 1 and 2 connected in parallel. After measuring each of these measurement items, wiring for connecting the multi-gate IGBTs 1 and 2 in parallel is assembled. Based on the measurement results, optimal values ​​for the gate resistance and time difference are obtained and then set for each of the multi-gate IGBTs 1 and 2 connected in parallel.

[0080] The multi-gate IGBTs 1 and 2 connected in parallel do not necessarily have to be measured for their operating characteristics at the assembly factory of the power conversion devices 200, 300, 400, and 500. The operating characteristics may be measured before or during assembly, and if the measurement results are extremely inappropriate, they may be replaced with a selected good pair. Ideally, it is sufficient to procure high-quality items with uniform operating characteristics in pairs. Such pair procurement items are manufactured by a semiconductor manufacturer with care so that the saturation current performance and threshold voltage are completely uniform, or they are assembled using high-quality multi-gate IGBTs 1 and 2 with the desired uniform operating characteristics, selected by a semiconductor tester or the like from a large number of manufactured items.

[0081] However, even with the constraint that pair procurement is impossible, it is possible to realize the power conversion device 200, 300, 400, 500 that is close to the ideal, while making some compromises. That is, for the multi-gate IGBT 1, 2 procured as a medium standard quality, the optimal values ​​for the gate resistance and time difference are obtained by a predetermined method based on the measurement results obtained before assembly, and then the devices are assembled and completed in a procedure such that the optimal settings are made after parallel connection. The power conversion device 200, 300, 400, 500 manufactured by this manufacturing method having such a procedure can simply and easily equalize the turn-on surge current between the switching elements 1, 2 connected in parallel to reduce power loss.

[0082] [supplement] In conventional power converters in which the main circuit is composed of IGBT elements connected in parallel, it is difficult to achieve both high efficiency and high reliability, and in addition to the current balance between the parallel elements, reducing the power loss that occurs is an important issue, but the present invention has made it possible to achieve both. That is, the present invention can provide semiconductor device driver circuits 10, 11, 35 that can achieve both high efficiency and high reliability, a driving method thereof, power converters 200, 300, 400, 500 to which they are applied, and a manufacturing method thereof.

[0083] According to the present driving circuits 10, 11, 35, the present method, the present power conversion devices 200, 300, 400, 500, and the manufacturing method thereof, in the parallel-connected IGBTs 1, 2 of a large-capacity power conversion device, the turn-on surge current that flows transiently at turn-on can be equalized between the parallel-connected switching elements 1, 2 (between parallel elements). As a result, the effect of suppressing the current bias between the parallel elements and the resulting bias in heat generation between the elements can be obtained.

[0084] In the present invention, the multi-gate IGBTs 1 and 2, which are capable of deriving characteristics with less power loss among IGBTs, are applied to a main circuit composed of parallel elements, which makes it easier and simple to balance the turn-on surge currents between the parallel elements, thereby deriving the above-mentioned advantageous effects. [Industrial Applicability]

[0085] The semiconductor device driving circuit, its driving method, power conversion device using them, and its manufacturing method according to the embodiments of the present invention have the potential to be widely adopted in a wide range of devices, from low-power devices such as air conditioners and microwave ovens to high-power devices such as inverters for railways and steelworks. [Explanation of symbols]

[0086] 1,2,21...Multi-gate IGBT, 3...Switching gate (Gs gate), 4...Carrier control gate (Gc gate), 5...Gs gate resistor, 6...Gc gate resistor, 7...Reflux diode, 8...Inductive load, 9...Gate bias drive generation circuit, 10 / 11,35 (IGBT 1 / 2, dual) drive circuit, 13 / 14...(IGBT 1 / 2)Saturation current performance, 15 / 16...(IGBT 1 / 2)Turn-on surge current, 17...Turn-on surge current balanced with IGBT 1, 18…Change in Gc gate bias with time when IGBT 1 is turned on. 19…Changes in Gc gate bias with time when IGBT 2 is turned on (Gc gate resistance value is the same), 20…Change in Gc gate bias time when IGBT 2 is turned on (Gc gate resistance value is IGBT 1) <IGBT 2)、 22...Balanced saturation current performance between parallel elements 1 and 2, 23,36...Gc gate resistance R, 24 / 25...(Gc / Gs) gate capacitance C, 26 / 27...(Gc / Gs) gate command signal, 28 / 29…(Gc gate resistance small / large) Gc gate bias time change, 30…Gc gate bias V required to balance turn-on surge current GC , 31...Gs gate resistor R, 32 / 33…Turn-on surge current (with Gc gate resistor set to small / large) 34…Balanced turn-on surge current I C , 37…IGBT 2 Gc command timing (same command timing as IGBT 1), 38…IGBT 2 Gc command timing (when delayed from IGBT 1) 39…IGBT 2 Gc gate bias V GC (same command timing as IGBT 1), 40…IGBT 2 Gc gate bias V GC Time change of (when delayed from IGBT 1), 41...Gc delay, 42...output buffer circuit, 43...FPGA, 200, 300, 400, 500...Power conversion device

Claims

1. A semiconductor device driver circuit for controlling a semiconductor device having a main circuit formed by connecting switching elements in parallel, The main circuit includes a plurality of multi-gate IGBTs as the switching elements, Each of the plurality of multi-gate IGBTs comprises: a first gate terminal capable of controlling timing of conduction or non-conduction; a second gate terminal capable of controlling an internal carrier concentration; Equipped with The transistor is configured to be turned on by applying a voltage equal to or greater than a threshold voltage to at least one of the first gate terminal and the second gate terminal; The semiconductor device driver circuit includes: a first output section that outputs a gate voltage so that the charging times of the first gate terminals of the plurality of multi-gate IGBTs are equal; a second output unit that outputs a gate voltage so that a charging time required for each of the second gate terminals of the plurality of multi-gate IGBTs can be individually controlled; Equipped with A driver circuit for a semiconductor device.

2. The charging time required for the second gate terminal of each of the multi-gate IGBTs connected in parallel is controlled by the value of a gate resistor connected to the second gate terminal.

2. The semiconductor device driver circuit according to claim 1.

3. The charging time of the second gate terminal of each of the multi-gate IGBTs connected in parallel is controlled by a time difference between applying a voltage equal to or higher than a threshold voltage to each of the first gate terminals prior to applying a voltage to the second gate terminal.

2. The semiconductor device driver circuit according to claim 1.

4. The values ​​of the gate resistors connected to the second gate terminals and the time differences are set individually based on the saturation current performance and the threshold voltage of the multi-gate IGBTs.

4. The semiconductor device driver circuit according to claim 3.

5. a correlation between the saturation current performance, the gate resistance value, and the time difference is positive; A correlation between the threshold voltage, the gate resistance value, and the time difference is negative.

5. The semiconductor device driver circuit according to claim 4.

6. The parallel-connected multi-gate IGBTs are generated by the same voltage source.

6. The semiconductor device driver circuit according to claim 2,

7. the gate resistors respectively connected to the second gate terminals and the time difference are written into a programmable integrated circuit; In addition, in the programmable integrated circuit, a correspondence table between the saturation current performance of the multi-gate IGBT, the gate resistance according to a threshold voltage, and the time difference is programmed; determining the gate resistance and the time difference according to the saturation current performance and the threshold voltage; 7. The semiconductor device driver circuit according to claim 6.

8. A pair of DC terminals; a DC / AC conversion circuit configured by connecting the pair of DC terminals in series in at least two semiconductor devices that switch current; an AC terminal connected to a portion of the DC / AC conversion circuit where the at least two semiconductor devices are connected; a diode that is a rectifying element connected in anti-parallel to the at least two semiconductor devices; comprising: A power conversion device comprising the semiconductor device drive circuit according to claim 7.

9. A semiconductor device driving method for controlling a semiconductor device having a main circuit formed by connecting switching elements in parallel, comprising: A plurality of multi-gate IGBTs are used as the switching elements, The multi-gate IGBT has a first gate terminal capable of controlling the timing of conduction or non-conduction and a second gate terminal capable of controlling the internal carrier concentration, and at least one of the first gate terminal and the second gate terminal is provided with a first gate terminal capable of controlling the timing of conduction or non-conduction. The main circuit is turned on by applying a voltage equal to or higher than a threshold voltage to the first gate terminal and the second gate terminal. a first output unit controls the first gate terminals of the parallel-connected multi-gate IGBTs by using a common time constant that equalizes the charging time required for each of the first gate terminals of the parallel-connected multi-gate IGBTs; The second output unit individually controls a charging time required for each of the second gate terminals to equalize a maximum value of each turn-on surge current among the multi-gate IGBTs connected in parallel. A method for driving a semiconductor device.

10. The charging time required for the second gate terminal of each of the parallel-connected multi-gate IGBTs is controlled by a value of a gate resistor connected to the second gate terminal.

10. The method for driving a semiconductor device according to claim 9.

11. The charging time required for the second gate terminal of each of the parallel-connected multi-gate IGBTs is controlled by a time difference between applying a voltage equal to or higher than a threshold voltage to each of the first gate terminals prior to applying a voltage to the second gate terminal.

10. The method for driving a semiconductor device according to claim 9.

12. The values ​​of the gate resistors connected to the second gate terminals and the time differences are individually set based on the saturation current performance and the threshold voltage of the multi-gate IGBTs. The method for driving a semiconductor device according to claim 11.

13. a correlation between the saturation current performance, the gate resistance value, and the time difference is positive; A correlation between the threshold voltage, the gate resistance value, and the time difference is negative.

13. The method for driving a semiconductor device according to claim 12.

14. The parallel-connected multi-gate IGBTs are generated by the same voltage source.

14. The method for driving a semiconductor device according to claim 10.

15. The gate resistors respectively connected to the second gate terminals and the time difference are written into a programmable integrated circuit; In addition, in the programmable integrated circuit, a correspondence table of the saturation current performance of the multi-gate IGBT, the gate resistance according to a threshold voltage, and the time difference is programmed; determining the gate resistance and the time difference according to the saturation current performance and the threshold voltage; 15. The method for driving a semiconductor device according to claim 14.

16. Measure the operating characteristics of the multi-gate IGBTs connected in parallel for various measurement items; After measuring the saturation current performance and the threshold voltage as the measurement items, wiring for parallel connection is assembled, The gate resistance and the time difference are set for each of the multi-gate IGBTs connected in parallel. A method for manufacturing a power converter according to claim 8.

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