Circuit for calibrating mismatch of chopping switches in time-interleaved analog-to-digital converters

Abstract

An analog-to-digital converter (ADC) circuit (400) and method of operation are disclosed. In some embodiments, the ADC circuit (400) can include a plurality of channels (500), a gain calibration circuit (420), and a time skew calibration circuit (430). Each of the plurality of channels (500) can include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration unit (530), a multiplier (540), and a pseudorandom bit sequence (PRBS) circuit (550) for providing a pseudorandom number (PN) to the switch (510), the calibration unit (530), and the multiplier (540). In some embodiments, the calibration device (530) includes a first offset calibration circuit (531) and a second offset calibration circuit (532) coupled in parallel between a demultiplexer (D1) and a multiplexer (M1), and the demultiplexer (D1) and the multiplexer (M1) can alternately route signals to the first offset calibration circuit (531) and the second offset calibration circuit (532) based on a pseudorandom number (PN).

Description

[Technical field]

[0001] Technical Field Aspects of the present disclosure relate generally to integrated circuits and, more particularly, to calibrating differential offsets of chopping switches in a time-interleaved analog-to-digital converter (ADC). [Background technology]

[0002] background Circuits and systems including analog-to-digital converters (ADCs) can use time-interleaved ADCs to increase bandwidth without significantly increasing power consumption. A typical time-interleaved ADC circuit includes multiple ADC channels, each configured to generate a corresponding digital output signal by sampling an analog input signal. The digital output signals generated by the ADC channels can be combined to generate a combined output signal having a sampling bandwidth equal to an integer multiple of the sampling bandwidth of each ADC channel. For example, a time-interleaved ADC circuit including N ADC channels can have a sampling bandwidth (f s ) is equal to N times the sampling bandwidth (f Bw ) (i.e., f Bw = N × f s ).

[0003] Time skew mismatch, gain mismatch, frequency offset, and phase offset between each channel of a time-interleaved ADC circuit can adversely affect the performance of the time-interleaved ADC circuit. A calibration circuit can be used to compensate for the mismatch and offset between each ADC channel. Summary of the Invention [Means for solving the problem]

[0004] overview This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0005] Aspects of the present disclosure relate to a time-interleaved analog-to-digital converter (ADC) circuit and method of operation. The time-interleaved ADC circuit disclosed herein can remove offsets associated with chopping circuits and ADCs provided in one or more channels of the ADC circuit by performing a background calibration operation. An exemplary time-interleaved ADC circuit can include at least a plurality of channels, a gain calibration circuit, and a time skew calibration circuit. Each of the plurality of channels can include an ADC, a switch configured to provide a differential input signal to the ADC, a calibration device coupled to an output of the ADC, a multiplier coupled to an output of the calibration device, and a pseudorandom bit sequence (PRBS) circuit for providing a pseudorandom number to the switch, the calibration device, and the multiplier. In some embodiments, the pseudorandom number generated by the PRBS circuit can be provided to the time skew calibration circuit. The calibration device provided in each channel can include selection logic configured to route a digital signal output from the ADC to a first offset calibration circuit or a second offset calibration circuit based on the pseudorandom number. The ADC circuit may also include a control circuit configured to adjust the clock signals provided to the multiple channels based at least in part on the control signals generated by the time skew calibration circuit.

[0006] In some embodiments, the selection logic may include a demultiplexer and a multiplexer. The demultiplexer may include an input coupled to an output of the ADC, a control terminal for receiving the pseudorandom number, and a first output and a second output. The multiplexer may include a first input and a second input, a control terminal for receiving the pseudorandom number, and an output coupled to the multiplier. The first offset calibration circuit may be coupled between the first output of the demultiplexer and the first input of the multiplexer, and the second offset calibration circuit may be coupled between the second output of the demultiplexer and the second input of the multiplexer. In some aspects, the selection logic may be configured to route the digital signal output from the ADC through the first offset calibration circuit based on a first value of the pseudorandom number and to route the digital signal output from the ADC through the second offset calibration circuit based on a second value of the pseudorandom number. This allows the selection logic to alternate between removing offset from the digital signal using a first offset calibration circuit (e.g., during a first time period) and removing offset from the digital signal using a second offset calibration circuit (e.g., during a second time period).

[0007] The switches in each channel may be any suitable circuit or logic capable of scrambling the differential input signal based on a pseudorandom number. The switches may be chopping circuits configured to alternately couple the positive and negative components of the differential input signal to the inverting and non-inverting input terminals of the ADC based on a pseudorandom number. In some embodiments, the chopping circuit may include a number of “straight” switches for transmitting the differential input signal to the ADC without polarity inversion and a number of “chopping” switches for transmitting the differential input signal with polarity inversion to the ADC. In some aspects, the straight switches and the chopping switches may be controlled by the pseudorandom number. In some embodiments, the first offset calibration circuit may be configured to remove offsets associated with the straight switches and remove offsets of the ADC, and the second offset calibration circuit may be configured to remove offsets associated with the chopping switches and remove offsets of the ADC.

[0008] An exemplary method disclosed herein can be used to calibrate a time-interleaved ADC circuit. The method includes scrambling a differential input signal based on a pseudorandom number, converting the scrambled differential input signal to a digital signal, calibrating an offset of the digital signal based on the pseudorandom number using a first offset calibration circuit or a second offset calibration circuit, descrambling the calibrated digital signal based on the pseudorandom number using a multiplier, and removing a time skew offset from the descrambled calibrated digital signal. In some embodiments, the removal of the time skew offset may be performed at least in part based on the pseudorandom number. The method may also include alternately coupling positive and negative components of the scrambled differential input signal to an inverting input terminal and a non-inverting input terminal of the ADC based on the pseudorandom number.

[0009] Exemplary embodiments are presented by way of example and not by way of limitation in the accompanying drawings, in which like numbers refer to like elements in the drawings and description, and in which: [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating an example system in which aspects of the present disclosure can be implemented. [Diagram 2] FIG. 1 is a block diagram illustrating an example time-interleaved analog-to-digital converter (ADC) circuit. [Diagram 3] FIG. 2 is a block diagram illustrating an example ADC channel. [Figure 4] 1 is a block diagram illustrating an example time-interleaved ADC circuit in accordance with some embodiments. [Diagram 5] 2 is a block diagram illustrating an example ADC channel in accordance with some embodiments. [Figure 6] 5 is an example flowchart illustrating example operations for operating a time-interleaved ADC circuit in accordance with some embodiments. [Figure 7] FIG. 1 illustrates an example field programmable gate array (FPGA) architecture in which aspects of the present disclosure can be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Detailed Description Aspects of the present disclosure can improve the performance of a time-interleaved ADC circuit by compensating for gain differences, switching offsets and time skews between each ADC channel across the frequency spectrum of the time-interleaved ADC circuit. In some implementations, the time-interleaved ADC circuit disclosed herein can remove flicker noise, offset spurs and other interferences of input signal components having frequencies equal to multiples of the sampling frequency of each ADC channel when converting an analog signal to a digital signal without sacrificing signal degradation or performance. In some aspects, the time-interleaved ADC circuit disclosed herein can take advantage of a full-rate Nyquist spectrum by removing harmonic noise and offsets associated with chopping circuits and ADCs.

[0012] In the following description, numerous specific details are provided, such as examples of specific components, circuits, and processes, to provide a thorough understanding of the present disclosure. The term "coupled" as used herein means a direct coupling or a coupling via one or more intervening elements or circuits. In addition, in the following description, specific names and / or details are set forth for purposes of explanation and to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to one skilled in the art that these specific details are not necessary to practice the exemplary embodiments. Also, well-known circuits and devices are shown in block diagrams to avoid obscuring the present disclosure. Any signals provided via the various buses described herein may be time multiplexed with other signals and provided via one or more common buses. Furthermore, the interconnections between circuit elements or software blocks may be shown as buses or single signal lines. Alternatively, each bus may be a single signal line, and each single signal line may be a bus. A single signal line or bus may represent one or more of a myriad of physical or logical mechanisms for communicating between elements. The exemplary embodiments should not be construed as limited to the specific examples set forth herein, but rather should be construed to include all embodiments defined by the appended claims.

[0013] FIG. 1 is a block diagram illustrating an exemplary system 100 in which aspects of the disclosure can be implemented. The system 100 includes an analog circuit 102, an analog-to-digital converter (ADC) circuit 104, and a digital circuit 106. In other embodiments, the system 100 can include any suitable number of analog circuits 102 and digital circuits 106. The analog circuit 102 can be any suitable circuit or element capable of processing an analog signal (e.g., a temperature sensor, a voltage sensor, a current sensor, or a radio frequency (RF) circuit) and can generate one or more analog signals by processing a signal, data, or other information. The ADC circuit 104 includes an input coupled to the analog circuit 104 and an output coupled to the digital circuit 106 and can convert an analog signal provided by the analog circuit 102 to one or more digital output signals, for example, by sampling the analog signal with one or more ADCs. The digital circuit 106 can be any suitable circuit or element capable of processing a digital signal (e.g., a digital signal processor (DSP) or a microprocessor) and can process one or more digital signals provided by the ADC circuit 104. In some embodiments, the ADC circuitry 104 and the digital circuitry 106 may be configured to monitor, analyze, interpret, or perform some other action or operation on the analog signal output by the analog circuitry 102.

[0014] 1, ADC circuit 104 may be a time-interleaved ADC circuit that includes multiple ADC channels (not shown for simplicity) and offset calibration circuit 108. As described with reference to Figures 2 and 3, offset calibration circuit 108 may be configured to compensate for multiple offsets between the ADC channels, for example, by calibrating one or more ADC channels.

[0015] FIG. 2 is a block diagram illustrating an exemplary time-interleaved analog-to-digital converter (ADC) circuit 200. The ADC circuit 200 can receive a differential analog input signal (IN) having a positive component (INp) and a negative component (INn), and includes a plurality of ADC channels 202(1)-202(N), a gain calibration circuit 204, a time skew calibration (TSC) circuit 206, and a control circuit 208. Each of the ADC channels 202(1)-202(N) includes a first input for receiving the positive component INp of the input signal, a second input for receiving the negative component INn of the input signal, an output coupled to the gain calibration circuit 204, and a control terminal coupled to a corresponding output of the control circuit 208. Each of the ADC channels 202(1)-202(N) can also include a corresponding one of the offset calibration circuits 108(1)-108(N). The gain calibration circuit 204 may include an output coupled to an input of the TSC circuit 206 and may be configured to adjust the output signals output by the ADC channels 202(1)-202(N) based on a reference value.

[0016] The TSC circuit 206 includes a first output providing a digital output signal (Dout) and a second output providing a clock calibration (CAL_clk) signal to the control circuit 208. In some embodiments, the TSC circuit 206 can compensate for the time skew between the ADC channels 202(1)-202(N) by adjusting the gain calibration signal provided by the gain calibration circuit 204. Additionally or alternatively, the TSC circuit 206 can embed information indicative of the time skew between the ADC channels 202(1)-202(N) into the clock calibration signal (CAL_clk).

[0017] In operation, each of the ADC channels 202(1)-202(N) samples the differential analog input signal IN in a time-interleaved manner using one or more clock signals (CLK) provided by the control circuit 208. In some embodiments, each of the ADC channels 202(1)-202(N) can sample the differential analog input signal IN at a different phase of a particular clock signal. Each of the offset calibration circuits 108(1)-108(N) can measure or determine an average value of an output signal generated by a corresponding one of the ADC channels 202(1)-202(N) and can remove the determined average value from the corresponding output signal. The gain calibration circuit 204 can compensate for gain offsets between the ADC channels 202(1)-202(N), for example, by comparing a root-mean-square (RMS) index of each of the ADC channel output signals to a reference value and adjusting the ADC channel output signal based on the result of the comparison.

[0018] The TSC circuit 206 can compensate for time skew offsets between the ADC channels 202(1)-202(N). In some embodiments, the TSC circuit 206 can be configured to measure a difference (or increment) between successive samples of the signal provided by the gain calibration circuit 204 and generate a clock calibration signal (CAL_clk) indicative of the measured difference. The control circuit 208 can selectively adjust or delay the clock signals provided to the ADC channels 202(1)-202(N) based on the clock calibration signal (CAL_clk) provided by the TSC circuit 206.

[0019] 3 is a block diagram illustrating an example ADC channel 300. The ADC channel 300, which may be an embodiment of one or more of the ADC channels 202(1)-202(N) of FIG. 2, includes a chopping circuit 302, an ADC 304, a first offset calibration circuit 306, a multiplier 308, a second offset calibration circuit 310, and a pseudorandom binary sequence (PRBS) circuit 312. The chopping circuit 302 includes an input for receiving a differential analog input signal IN and an output coupled to the differential input of the ADC 304. The chopping circuit 302 may be any suitable switch, coupling circuit, logic, or signal routing circuit capable of selectively providing a negative component (INn) of the input signal IN to a non-inverting terminal (+) of the ADC 304 and a positive component (INp) of the input signal IN to an inverting terminal (-) of the ADC 304. In some embodiments, the chopping circuit 302 may include multiple straight switches and multiple chopping switches (for simplicity, the straight switches and chopping switches are not shown). Thus, the chopping circuit 302 may dynamically, periodically, or programmably reverse the polarity of the analog input signal provided to the ADC 304.

[0020] The ADC 304 may be any suitable circuit or element capable of converting an analog signal to a digital signal. In some embodiments, the ADC 304 may be configured to convert a differential analog signal to a single-ended digital signal, for example as shown in FIG. 3. In other embodiments, the ADC 304 may be configured to convert a single-ended analog signal to a single-ended digital signal. Although not shown for simplicity, the ADC 304 may receive one or more clock signals (e.g., a sampling clock for sampling the differential analog input signal).

[0021] The first offset calibration circuit 306 includes an input coupled to the output of the ADC 304 and an output coupled to an input of the multiplier 308. The second offset calibration circuit 310 includes an input coupled to the output of the multiplier 308 and an output for providing an output signal (OUT) to the ADC channel 300. The PRBS circuit 312 may be any suitable circuit for generating a pseudorandom number or binary sequence and includes an output coupled to a control terminal of the chopping circuit 302 and a control terminal of the multiplier 308. In some embodiments, the chopping circuit 302 can provide a pseudorandom number (PN) to the chopping circuit 302 and the multiplier 308.

[0022] The chopping circuit 302 can sample the differential analog input signal IN and dynamically switch the input signal components INp and INn between the inverting (-) and non-inverting (+) terminals of the ADC 304 based on a pseudorandom number (PN) provided by the PRBS circuit 312. In some implementations, the chopping circuit 302 can randomize or scramble the input signal using the pseudorandom number (PN) such that flicker noise is spread throughout the frequency spectrum of the ADC channel 300 rather than appearing primarily at harmonics of the sampling frequency of the ADC channel 300. Additionally or alternatively, the chopping circuit 302 can prevent components of the analog input signal IN from appearing to the ADC 304 as noise (e.g., as a DC signal) at the sampling frequency of the ADC channel 300.

[0023] The first offset calibration circuit 306 can remove the offset associated with the ADC 304 by adjusting the digital signal generated by the ADC 304. The multiplier 308 can descramble the input signal components output from the first offset calibration circuit 306, for example, to preserve the components of the input signal at the sampling frequency and / or reduce the flicker noise caused by the chopping circuit 302. The first offset calibration circuit 306 may not be able to remove the offset of the ADC 304 during the sampling interval of the chopping circuit 302. As a result, the differential offset between the sampling intervals of the multiple ADC channels 300 may pass through the first offset calibration circuit 306 and the multiplier 308 and appear in the frequency spectrum associated with the time-interleaved ADC circuit 200 as time-interleaved residual spurs.

[0024] The second offset calibration circuit 310 can remove the residual differential offset introduced by the chopping circuit 302 by processing the descrambled (or unchopped) input signal. As mentioned above, for example, the first offset calibration circuit 306 may not be able to detect the offsets and mismatches associated with the chopping circuit 302 because these offsets and mismatches are scrambled across the frequency spectrum. Because the second offset calibration circuit 310 is downstream of the multiplier 308 (and thus receives a descrambled input signal rather than a scrambled input signal), the second offset calibration circuit 310 can detect and compensate for the offsets and mismatches associated with the chopping circuit 302.

[0025] The second offset calibration circuit 310 is connected to the ADC channel 300 at a sampling frequency f sTo support operation under such harsh conditions, an accumulator (not shown for simplicity) in the second offset calibration circuit 310 is provided to adjust the input signal frequency IN to a frequency equal to an integer multiple of the sampling frequency f of the ADC channel 300. s In some embodiments, the freeze signal (FRZ) can be used to selectively freeze or stop the operation of an accumulator in the second offset calibration circuit 310. In some aspects, the differential input signal IN can be frozen when the differential input signal IN includes a signal component equal to an integer multiple of the sampling frequency f s When the differential input signal IN contains signal components equal to an integer multiple of the sampling frequency f, the operation of the accumulator can be frozen or stopped by asserting the freeze signal FRZ (e.g., to a logic high). s When the input signal frequency does not include signal components equal to integer multiples of the sampling frequency / s, the accumulator can be operated normally by deasserting the freeze signal FRZ (e.g., to a logic low). Thus, the second offset calibration circuit 310 can continue to remove the residual differential offset introduced by the chopping circuit 302, even for input signal frequencies equal to integer multiples of the sampling frequency / s.

[0026] In some embodiments, a foreground calibration operation may be performed to remove residual differential offsets of input signal components at any frequency related to the bandwidth of ADC circuit 200. In some aspects, the foreground calibration operation may include the following steps or actions. Disable the input signal and continuously operate both the first offset calibration circuit 306 and the second offset calibration circuit 310. In some embodiments, the input signal can be disabled by setting the value of the input signal to zero. After a period of time, the first offset calibration circuit 306 may operate to remove the total common mode offset from the chopping circuit 302 and the ADC 304, and the second offset calibration circuit 310 may operate to remove the differential offset of the chopping circuit 302. Freezing an accumulator (not shown for simplicity) provided in the second offset calibration circuit 310. · Activate the input signal.

[0027] According to some aspects of the present disclosure, a time-interleaved ADC circuit is disclosed that can remove time-interleaved offset spurs (including flicker noise and offsets associated with chopping circuits). In some embodiments, the time-interleaved ADC circuit disclosed herein can acquire and sample input signal components having frequencies equal to integer multiples of the sampling frequency of each channel without adversely affecting the performance of the offset calibration circuit and without corrupting the signal. In some embodiments, the time-interleaved ADC circuit disclosed herein can provide complete controllability regardless of the input signal by performing a foreground calibration operation.

[0028] FIG. 4 is a block diagram illustrating an exemplary time-interleaved ADC circuit 400 in accordance with some embodiments. The ADC circuit 400 can receive a differential analog input signal (IN) having a positive component (INp) and a negative component (INn) and generate a digital output signal (Dout) based on the differential analog input signal IN. In some embodiments, the ADC circuit 400 can include a plurality of ADC channels 410(1)-410(N), a gain calibration circuit 420, a time skew calibration (TSC) circuit 430, and a control circuit 440. Each of the ADC channels 410(1)-410(N) includes a first input for receiving a positive component INp of the input signal IN, a second input for receiving a negative component INn of the input signal IN, an output coupled to an input of the gain calibration circuit 420, and a clock terminal coupled to a corresponding output of the control circuit 440. Also, each of the ADC channels 410(1)-410(N) may include a corresponding one of the multiple PRBS circuits 412(1)-412(N). The PRBS circuits 412(1)-412(N) may be any suitable circuit or element capable of generating pseudo-random numbers or binary sequences. In the exemplary embodiment of FIG. 4, the PRBS circuit 412(1) provided in the first ADC channel 410(1) may generate a first binary number (PN_1), the PRBS circuit 412(2) provided in the second ADC channel 410(2) may generate a second binary number (PN_2), and the PRBS circuit 412(N) provided in the Nth ADC channel 410(N) may generate an Nth binary number (PN_N). In other embodiments, each of the ADC channels 410(1)-410(N) may share a common PRBS circuit 412.

[0029] The gain calibration circuit 420 includes an output coupled to an input of the TSC circuit 430 and may be configured to compensate for gain offsets between the ADC channels 410(1)-410(N) by adjusting the gain of the output signals output by the ADC channels 410(1)-410(N), for example, based on a reference value. The TSC circuit 430 includes an input coupled to an output of the gain calibration circuit 420, a first output for outputting a digital output signal (Dout), and a second output for outputting a control signal (CTRL). The control signal (CTRL) generated by the TSC circuit 430 may include information that may be used to compensate for time skew between the ADC channels 410(1)-410(N). In some implementations, the control signal (CTRL) may be used to adjust or delay one or more clock signals (e.g., clock signals CLK_1-CLK_N) provided to or associated with the ADC channels 410(1)-410(N). In some embodiments, the control circuit 440 can calibrate the sampling period and / or sampling interval of one or more of the ADC channels 410(1)-410(N) to reduce or eliminate time skew, frequency offset, and / or phase offset between the ADC channels 410(1)-410(N) by adjusting the clock signal.

[0030] The pseudo-random numbers PN_1 to PN_N generated by the PRBS circuits 412(1) to 412(N), respectively, can be used to scramble the differential input signal before converting the differential input signal to a digital signal, thereby distributing the flicker noise across the frequency spectrum of the ADC circuit 400, and descrambling the calibrated digital signal. In some embodiments, one or more of the pseudo-random numbers PN_1 to PN_N can be used to remove one or more offsets from the analog input signal IN by selecting a corresponding one of a group of offset calibration circuits provided in each of the ADC channels 410(1) to 410(N). In some aspects, the pseudo-random numbers PN_1 to PN_N can remove one or more offsets from the differential input signal by alternately selecting different offset calibration circuits, as described with reference to FIG. 5.

[0031] The gain calibration circuit 420 can compensate for gain mismatches between the ADC channels 410(1)-410(N). In some embodiments, the gain calibration circuit 420 can compensate for gain mismatches between the ADC channels 410(1)-410(N) by comparing a root-mean-square (RMS) index of each of the ADC channel output signals to a reference value and adjusting the ADC channel output signals based on the results of the comparison. In other embodiments, the gain calibration circuit 420 can compensate for gain mismatches between the ADC channels 410(1)-410(N) using other suitable techniques.

[0032] The TSC circuit 430 can compensate for time skew between the ADC channels 410(1)-410(N). In some embodiments, the TSC circuit 430 can be configured to measure the difference (or increment) between successive samples output by the gain calibration circuit 420 and generate a control signal (CTRL) indicative of the measured difference. In other embodiments, the TSC circuit 430 can generate the control signal (CTRL) using other suitable techniques. For the exemplary embodiment of FIG. 4, the illustrated TSC circuit 430 includes an input coupled to receive the pseudorandom numbers PN_1-PN_N generated by each of the PRBS circuits 412(1)-412(N). In some embodiments, the TSC circuit 430 can use the pseudorandom numbers PN_1-PN_N to ensure accurate compensation of time skew in the digital signals output from the ADC channels 410(1)-410(N). In other embodiments, the TSC circuit 430 can use any other suitable pseudorandom numbers or signals to ensure accurate compensation of time skew.

[0033] The control circuit 440 may include an input for receiving the control signal (CTRL) generated by the TSC circuit 430 and a number of outputs coupled to the ADC channels 410(1)-410(N). In some embodiments, the control circuit 440 may compensate for time skew, frequency offset, and / or phase offset between the ADC channels 410(1)-410(N), for example, by selectively adjusting or delaying the clock signals CLK_1-CLK_N provided to each ADC channel 410(1)-410(N) based on the control signal (CTRL) provided by the TSC circuit 430.

[0034] FIG. 5 is a block diagram illustrating an exemplary ADC channel 500 according to some embodiments. The ADC channel 500 may be an embodiment of one or more of the ADC channels 410(1)-410(N) of FIG. 4 and includes a chopping circuit 510, an ADC 520, a calibration device 530, a multiplier 540, and a PRBS circuit 550. The chopping circuit 510 may be an implementation of the chopping circuit 302 of FIG. 3 and includes an input for receiving a differential input signal IN and an output coupled to a differential input of the ADC 520. The chopping circuit 510 may be any suitable switch, coupling circuit, logic, or crossover matrix capable of alternately coupling the positive component (INp) and the negative component (INn) of the differential input signal IN to the non-inverting terminal (+) and the inverting terminal (−) of the ADC 520, for example, based on a pseudorandom number PN. Thus, the ADC 520 can alternately sample the positive component (INp) and the negative component (INn) of the differential input signal IN. This allows the chopping circuit 510 to ensure randomization of the digital signal generated by the ADC 520 .

[0035] In some embodiments, the chopping circuit 510 may include a number of switches for alternately coupling positive and negative signal components of the differential input signal to the non-inverting and inverting terminals of the ADC 520 so as to scramble or randomize the differential input signal. For example, in the embodiment shown in Figure 5, the chopping circuit 510 includes four switches SW1-SW4 coupled between a pair of positive input terminals (in+) and negative input terminals (in-) and a pair of positive output terminals (out+) and negative output terminals (out-). The switch SW1 is connected between the positive input terminal (in+) and the positive output terminal (out+) of the chopping circuit 510, the switch SW2 is connected between the negative input terminal (in-) and the negative output terminal (out-) of the chopping circuit 510, the switch SW3 is connected between the positive input terminal (in+) and the negative output terminal (out-) of the chopping circuit 510, and the switch SW4 is connected between the negative input terminal (in-) and the positive output terminal (out+) of the chopping circuit 510.

[0036] When the pseudorandom number PN is one of a plurality of first values, the chopping circuit 510 is in a first state in which the switches SW1 and SW2 are closed (i.e., conductive) and the switches SW3 and SW4 are open (i.e., non-conductive). In this first state, the chopping circuit 510 transmits the positive component of the differential input signal IN to the non-inverting terminal (+) of the ADC 520 via the switch SW1 and transmits the negative component of the differential input signal IN to the inverting terminal (-) of the ADC 520 via the switch SW2. This allows the chopping circuit 510 to transmit the differential input signal "straight" to the ADC 520 (e.g., without polarity inversion). Thus, in this specification, the switches SW1 and SW2 may be referred to as "straight" switches of the chopping circuit 510.

[0037] When the pseudorandom number PN is one of a plurality of second values, the chopping circuit 510 is in a second state in which the switches SW1 and SW2 are open (i.e., in a non-conducting state) and the switches SW3 and SW4 are closed (i.e., in a conducting state). In this second state, the chopping circuit 510 transmits the positive component of the differential input signal IN to the inverting terminal (-) of the ADC 520 via the switch SW3 and transmits the negative component of the differential input signal IN to the non-inverting terminal (+) of the ADC 520 via the switch SW4. This allows the chopping circuit 510 to chop (invert the polarity) the differential input signal provided to the ADC 520. Thus, in this specification, the switches SW3-SW4 may be referred to as "chopping" switches of the chopping circuit 510.

[0038] The ADC 520 may be any suitable circuit or element capable of converting an analog signal to a digital signal. In some embodiments, the ADC 520 may be configured to convert a differential analog signal to a single-ended digital signal, for example, as shown in the example of Figure 5. In other embodiments, the ADC 520 may be configured to convert a single-ended analog signal to a single-ended digital signal.

[0039] The calibration device 530 is coupled between the ADC 520 and the multiplier 540 and includes a demultiplexer (DEMUX) D1, a first offset calibration circuit 531, a second offset calibration circuit 532, and a multiplexer (MUX) M1. The demultiplexer D1 includes an input coupled to an output of the ADC 520, a first output coupled to an input of the first OC circuit 531, a second output coupled to an input of the second OC circuit 532, and a control terminal coupled to an output of the PRBS circuit 550. The multiplexer M1 includes a first input coupled to an output of the first OC circuit 531, a second input coupled to an output of the second OC circuit 532, an output coupled to an input of the multiplier 540, and a control terminal coupled to an output of the PRBS circuit 550.

[0040] The first offset calibration circuit 531 and the second offset calibration circuit 532 are coupled in parallel between the demultiplexer D1 and the multiplexer M1. The first offset calibration circuit 531 may be configured to remove an offset caused by or associated with one or more straight switches provided in the chopping circuit 510 (and / or an offset caused by or associated with other circuit elements provided in the chopping circuit 510 for maintaining the polarity of the differential input signal IN when routing the differential input signal IN to the ADC 520) from the digital signal output by the ADC 520. The first offset calibration circuit 531 may also be configured to remove an offset caused by or associated with the ADC 520. The second offset calibration circuit 532 may be configured to remove an offset caused by or associated with one or more chopping switches provided in the chopping circuit 510 (and / or an offset caused by or associated with other circuit elements provided in the chopping circuit 510 for inverting the polarity of the differential input signal IN when routing the differential input signal IN to the ADC 520) from the digital signal output by the ADC 520. The second offset calibration circuit 532 may also be configured to remove an offset caused by or associated with the ADC 520. Note that the ADC channel 300 described with reference to FIG. 3 includes two offset calibration circuits 306 and 310 coupled in series, while the ADC channel 500 described with reference to FIG. 5 includes a first offset calibration circuit 531 and a second offset calibration circuit 531 coupled in parallel.

[0041] In some embodiments, one or more freeze signals may be used to selectively freeze or stop operation of an accumulator provided in the first offset calibration circuit 531 and an accumulator provided in the second offset calibration circuit 532 (not shown for simplicity). In the exemplary embodiment shown in FIG. 5, the first offset calibration circuit 531 may include an input for receiving a first freeze signal (FRZ_1), and the second offset calibration circuit 532 may include an input for receiving a second freeze signal (FRZ_2). In some aspects, the differential input signal IN may be coupled to a sampling frequency f of the ADC channel 500. s When the differential input signal IN includes a signal component equal to an integer multiple of the sampling frequency f of the ADC channel 500, the operation of an accumulator in the first offset calibration circuit 531 can be frozen or stopped by asserting the first freeze signal FRZ_1 (e.g., logic high). s When the differential input signal IN includes a signal component equal to an integer multiple of the sampling frequency f, the accumulator in the second offset calibration circuit 532 can be operated normally by deasserting the second freeze signal FRZ_2 (e.g., to logic low). s When the differential input signal IN does not include a signal component equal to an integer multiple of the sampling frequency f of the ADC channel 500, the accumulators provided in the first offset calibration circuit 531 and the second offset calibration circuit 532 can be operated normally by deasserting the first freeze signal FRZ_1 and the second freeze signal FRZ_2 (e.g., to logic low). s In another embodiment, the first offset calibration circuit 531 and the second offset calibration circuit 532 can receive the same freeze signal.

[0042] The multiplier 540 includes an output for providing a digital output signal Dout and a control terminal coupled to the output of the PRBS circuit 550. In some embodiments, the multiplier 540 can descramble the calibrated digital signal output from the calibration device 530, for example, to reduce flicker noise caused by the chopping circuit 510.

[0043] 4 and may be an embodiment of one or more of the PRBS circuits 412(1)-412(N) of FIG. 4 and may provide a chopping circuit 510, a pseudorandom number (PN) to a demultiplexer D1, a multiplexer M1, and a multiplier 540. In some embodiments, the PRBS circuit 550 may also provide a pseudorandom number (PN) to the TSC circuit 430 of FIG.

[0044] The chopping circuit 510 can sample the differential input signal and alternately switch the positive signal component INp and the negative signal component INn of the differential input signal IN between the non-inverting terminal (+) and the inverting terminal (-) of the ADC 520 based on a pseudorandom number (PN). In some embodiments, the chopping circuit 510 can sample the differential input signal and alternately switch the positive signal component INp and the negative signal component INn of the differential input signal IN between the non-inverting terminal (+) and the inverting terminal (-) of the ADC 520 based on a pseudorandom number (PN). This allows the chopping circuit 510 to ensure randomization of the digital signal generated by the ADC 520.

[0045] When the selection logic formed by the demultiplexer D1 and the multiplexer M1 selects the first offset calibration circuit 531 in response to the pseudorandom number (PN), the first offset calibration circuit 531 can remove the offset associated with the ADC 520 and the offset associated with the straight switch provided in the chopping circuit 510 by adjusting the digital signal generated by the ADC 520. When the selection logic formed by the demultiplexer D1 and the multiplexer M1 selects the second offset calibration circuit 531 in response to the pseudorandom number (PN), the second offset calibration circuit 532 can remove the offset associated with the ADC 520 and the offset associated with the straight switch provided in the chopping circuit 510 by adjusting the digital signal generated by the ADC 520. The multiplier 540 may "unchop" the adjusted digital signal provided by the first offset calibration circuit 531 or the second offset calibration circuit 532 based on the pseudorandom number (PN), for example, to reduce flicker noise caused by the ADC 520. Note that if the frequency response of the first offset calibration circuit 531 is smaller than a certain value, the first offset calibration circuit 531 cannot keep up with the flicker noise caused by the ADC 520, so the flicker noise is scrambled across the frequency bandwidth of the ADC channel 500 (rather than appearing at multiples of the sampling frequency of the ADC channel 500).

[0046] 6 is an example flow chart illustrating example operations 600 for operating a time-interleaved ADC circuit according to some embodiments. In this embodiment, the example operations 600 are described with reference to the ADC circuit 400 of FIGS. 4 and 5, but the example operations 600 may be performed by any other suitable ADC circuit. In some embodiments, the operations 600 may be performed as a foreground calibration operation.

[0047] The ADC circuit 400 may scramble the differential input signal based on a pseudorandom number (601). In some embodiments, the chopping circuit 510 may scramble the differential input signal using the pseudorandom number provided by the PRBS circuit 550. This causes the flicker noise to be spread across the entire frequency spectrum of the ADC circuit 400, rather than appearing primarily at harmonics of the sampling frequency of the ADC channels 410(1)-410(N).

[0048] The ADC circuit 400 can alternately couple the positive and negative components of the scrambled differential input signal to the inverting and non-inverting input terminals of the ADC based on a pseudorandom number (602). In some embodiments, the chopping circuit 510 can prevent components of the differential input signal from appearing to the ADC as noise (e.g., as a DC signal) at the sampling frequency of the ADC channels 410(1)-410(N).

[0049] The ADC circuit 400 may convert the scrambled differential input signal to a digital signal (603). In some embodiments, the ADC 520 may be configured to convert the differential analog signal to a single-ended digital signal, such as shown in the example of Figure 5. In other embodiments, the ADC 520 may be configured to convert the single-ended analog signal to a single-ended digital signal.

[0050] The ADC circuit 400 may calibrate the offset of the digital signal based on the pseudorandom number using the first offset calibration circuit or the second offset calibration circuit (604). Referring also to FIG. 5, the first offset calibration circuit 531 and the second offset calibration circuit 532 may be coupled in parallel between the demultiplexer D1 and the multiplexer M1. The first offset calibration circuit 531 may remove the offset of the ADC from the digital signal output by the ADC 520 and may remove the offset of the straight switch from the differential input signal. The second offset calibration circuit 532 may remove the offset of the ADC 520 from the digital signal output by the ADC 520 and may remove the offset from the chopping circuit 510. In some embodiments, the selection circuit formed by the demultiplexer D1 and the multiplexer M1 can route the digital signal output from the ADC 520 through a first offset calibration circuit 531A based on a first value of the pseudorandom number, and can route the digital signal output from the ADC 520 through a second offset calibration circuit 531B based on a second value of the pseudorandom number.

[0051] The ADC circuit 400 can use the multiplier to descramble the calibrated digital signal based on the pseudorandom number (605). In some embodiments, the multiplier 540 can reduce flicker noise caused by the chopping circuit 510, for example, by descrambling the calibrated digital signal output from the calibration device 530.

[0052] The ADC circuit 400 may remove the time skew offset from the descrambled calibrated digital signal (606). In some embodiments, the TSC circuit 430 may generate a control signal that may be used to compensate for the time skew between the ADC channels 410(1)-410(N). In some aspects, the control signal (CTRL) may be used to calibrate the sampling period and / or sampling interval of one or more of the ADC channels 410(1)-410(N) by adjusting or delaying one or more clock signals (e.g., clock signals CLK_1-CLK_N) provided to or associated with the ADC channels 410(1)-410(N) to reduce or remove the time skew, frequency offset and / or phase offset between the ADC channels 410(1)-410(N).

[0053] 7 illustrates an architecture 700 of a field programmable gate array (FPGA) implementation of a programmable IC 1. The FPGA includes a number of different programmable tiles, including transceivers 37, configurable logic blocks (CLBs) 33, random access memory blocks (BRAMs) 34, input / output blocks (IOBs) 36, configuration and clock logic (CONFIG / CLOCKS) 42, digital signal processing blocks (DSPs) 35, dedicated input / output blocks (I / Os) 41 (e.g., configuration and clock ports), and other programmable logic 39 (e.g., digital clock managers, analog-to-digital converters, and system monitoring logic, etc.). The FPGA may also include a PCIe interface 40, an analog-to-digital converter (ADC) 38, etc.

[0054] In some FPGAs, as shown by the illustration at the top of FIG. 7, each programmable tile may include at least one programmable interconnect element (INT) 43 having connections with input and output terminals 48 of programmable logic elements in the same tile. Each programmable interconnect element 43 may also include connections with interconnect segments 49 of adjacent programmable interconnect elements in the same tile or other tiles. Each programmable interconnect element 43 may also include connections with interconnect segments 50 of general routing resources between logic blocks (not shown). The general routing resources may include routing channels between logic blocks (not shown) that include tracks of interconnect segments (e.g., interconnect segments 50) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments 50) may extend across one or more logic blocks. The programmable interconnect elements 43 together with the general routing resources implement a programmable interconnect structure (programmable interconnect) for the illustrated FPGA.

[0055] In an exemplary implementation, the CLB 33 may include configurable logic elements (CLEs) 44 that can be programmed to implement user logic, and a single programmable interconnect element (INT) 43. The BRAM 34 may include a BRAM logic element (BRL) 45 in addition to one or more programmable interconnect elements. In general, the number of interconnect elements included in a tile depends on the height of the tile. In the illustrated example, the BRAM tile has a height similar to five CLBs, but may have a height similar to other numbers of CLBs (e.g., four). The DSP tile 35 may include a DSP logic element (DSPL) 46 in addition to any suitable number of programmable interconnect elements. The IOB 36 may include, for example, two instances of input / output logic elements (IOLs) 47 in addition to one instance of the programmable interconnect element 43. As will be apparent to one skilled in the art, for example, the actual I / O pads connected to the I / O logic element 47 are generally not limited to the area of ​​the input / output logic element 47.

[0056] In the illustrated example, a horizontal region near the center of the die (shown in FIG. 7) is used for configuration, clocks, and other control logic. Vertical columns 51 extending from this horizontal region or column are used to distribute clock and configuration signals across the entire width of the FPGA.

[0057] Some FPGAs utilizing the architecture shown in Figure 7 include additional logic blocks to disrupt the regular column structure that makes up most of the FPGA. The additional logic blocks may be programmable blocks and / or dedicated logic.

[0058] It should be noted that Figure 7 is intended to illustrate only an example SOC architecture. For example, the number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect / logic implementations shown at the top of Figure 7 are merely exemplary. For example, in an actual FPGA, to facilitate efficient implementation of user logic, typically two or more adjacent columns of CLBs will be included in any occurrence of a CLB, and the number of adjacent CLB rows will vary depending on the overall size of the FPGA.

[0059] Those skilled in the art will appreciate that information and signals can be represented using a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols and chips referred to in the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0060] Moreover, those skilled in the art will appreciate that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the above has outlined the functions of the various exemplary components, blocks, modules, circuits, and steps. Whether these functions are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functions in various ways depending on the particular application, but such implementations should not be interpreted as departing from the scope of the present disclosure.

[0061] The methods, sequences, or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in software modules executed by a processor, or in a combination of both. The software modules may reside in RAM latches, flash latches, ROM latches, EPROM latches, EEPROM latches, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor.

[0062] In the foregoing specification, illustrative embodiments have been described with reference to specific examples. It will be apparent, however, that various modifications and changes can be made without departing from the broader scope of the present disclosure as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. An apparatus for performing analog-to-digital conversion, comprising: With multiple channels, Each channel is an analog-to-digital converter (ADC); a switch configured to provide a differential input signal to the ADC; a calibration device coupled to an output of the ADC; a multiplier coupled to an output of the calibration device; a pseudorandom bit sequence (PRBS) circuit configured to provide pseudorandom numbers to the switch, the calibration device, and the multiplier; a gain calibration circuit including an input coupled to the calibration device for each of the plurality of channels; a time skew calibration circuit coupled to the gain calibration circuit and configured to output an output signal based at least in part on the differential input signal and the pseudorandom number; The calibration apparatus comprises a first offset calibration circuit and a second offset calibration circuit and selection logic, the selection logic being configured to select one of the first offset calibration circuit and the second offset calibration circuit based on the pseudo-random number.

2. the switch includes a chopping circuit configured to scramble the differential input signal based on the pseudorandom number; the switch is configured to alternately couple positive and negative components of the differential input signal to inverting and non-inverting inputs of the ADC based on the pseudorandom number; or 2. The apparatus of claim 1, wherein the time skew calibration circuit is coupled to at least one of the gain calibration circuit and the PRBS circuit provided in each channel of a plurality of channels.

3. The selection logic includes: a demultiplexer including an input coupled to the output of the ADC, a control terminal for receiving the pseudorandom number, and a plurality of outputs; a multiplexer including a plurality of inputs, a control terminal for receiving said pseudorandom numbers, and an output coupled to said multiplier; 2. The apparatus of claim 1, wherein the calibration device comprises the first offset calibration circuit and the second offset calibration circuit coupled in parallel between the multiple outputs of the demultiplexer and the multiple inputs of the multiplexer.

4. The demultiplexer and the multiplexer include Routing a digital signal output from the ADC through the first offset calibration circuit based on a first value of the pseudorandom number; and 4. The apparatus of claim 3, configured to route the digital signal output from the ADC through the second offset calibration circuit based on a second value of the pseudorandom number.

5. The switch includes a chopping circuit including a plurality of straight switches and a plurality of chopping switches; the first offset calibration circuit is configured to remove an offset associated with the straight switch and to remove an offset of the ADC; The apparatus of claim 3 , wherein the second offset calibration circuit is configured to remove an offset associated with the chopping switch and to remove an offset of the ADC.

6. A control circuit is further provided.

2. The apparatus of claim 1, wherein the control circuitry is configured to adjust clock signals provided to the multiple channels based on control signals generated by the time skew calibration circuitry.

7. 1. An integrated circuit comprising: an analog circuit configured to generate a differential input signal; an analog-to-digital converter (ADC) circuit including a plurality of channels; Each channel is an ADC including an inverting input terminal, a non-inverting input terminal, and one or more outputs; a pseudorandom bit sequence (PRBS) circuit configured to generate pseudorandom numbers; a chopping circuit configured to alternately couple positive and negative components of the differential input signal to the inverting and non-inverting input terminals of the ADC based on the pseudorandom number; a calibration device coupled to the one or more outputs of the ADC and configured to respond to the pseudorandom number; a multiplier coupled to the calibration device and configured to be responsive to the pseudorandom number; The calibration apparatus includes an integrated circuit comprising a first offset calibration circuit and a second offset calibration circuit and selection logic, the selection logic being configured to select one of the first offset calibration circuit and the second offset calibration circuit based on the pseudorandom number.

8. a gain calibration circuit coupled to an output of the calibration device for each of the plurality of channels; 8. The integrated circuit of claim 7, further comprising: a time skew calibration circuit coupled to the gain calibration circuit and including an output for outputting a digital output signal indicative of the differential input signal.

9. the time skew calibration circuit further includes an input coupled to the PRBS circuit for each channel of the plurality of channels; the integrated circuit further comprising a control circuit configured to adjust clock signals provided to the plurality of channels based on a control signal generated by the time skew calibration circuit; or The integrated circuit of claim 8 , wherein the chopping circuit is configured to scramble the differential input signal based on the pseudorandom number.

10. The selection logic: a demultiplexer including an input coupled to the one or more outputs of the ADC, a control terminal for receiving the pseudorandom number, a first output and a second output; a multiplexer including a first input and a second input, a control terminal for receiving the pseudorandom number, and an output coupled to the multiplier; the calibration device includes a first offset calibration circuit coupled between the first output of the demultiplexer and the first input of the multiplexer; the second offset calibration circuit coupled between the second output of the demultiplexer and the second input of the multiplexer; The integrated circuit of claim 8 , wherein the first offset calibration circuit and the second offset calibration circuit are coupled in parallel.

11. The demultiplexer and the multiplexer include Routing a digital signal output from the ADC through the first offset calibration circuit based on a first value of the pseudorandom number; and configured to route the digital signal output from the ADC through the second offset calibration circuit based on a second value of the pseudorandom number; or the chopping circuit includes a plurality of straight switches and a plurality of chopping switches; the first offset calibration circuit is configured to remove an offset associated with the straight switch from the differential input signal and to remove an offset of the ADC from a digital signal provided to the calibration device; and 11. The integrated circuit of claim 10, wherein the second offset calibration circuit is configured to remove an offset associated with the chopping switch from the differential input signal and to remove an offset of the ADC from a digital signal provided to the calibration device.

12. 1. A method for calibrating an analog-to-digital converter (ADC) circuit, comprising: scrambling the differential input signal based on a pseudorandom number using a chopping circuit; converting the scrambled differential input signal to a digital signal using an ADC; calibrating an offset of the digital signal using a first offset calibration circuit or a second offset calibration circuit based on the pseudorandom number; descrambling the calibrated digital signal based on the pseudorandom number using a multiplier; removing a time skew offset from the descrambled calibrated digital signal; The method, wherein the calibrating includes selection logic selecting one of the first and second offset calibration circuits based on the pseudorandom number.

13. The method of claim 12 , wherein removing the time skew offset is based on the pseudorandom number.

14. 13. The method of claim 12, further comprising alternately coupling positive and negative components of the scrambled differential input signal to inverting and non-inverting input terminals of the ADC based on the pseudorandom number.

15. the chopping circuit includes a plurality of straight switches and a plurality of chopping switches; the first offset calibration circuit is configured to remove an offset associated with the straight switch from the differential input signal and to remove an offset of the ADC; 13. The method of claim 12, wherein the second offset calibration circuit is configured to remove an offset associated with the chopping switch from the differential input signal and to remove an offset of the ADC.

16. 2. The apparatus of claim 1, wherein the selection logic is configured to select one of the first offset calibration circuit and the second offset calibration circuit based on the pseudorandom number to remove offsets associated with the ADC and the switch.

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