Semiconductor module and method for manufacturing the same

Abstract

To provide a semiconductor module capable of preventing the peeling of a sealing resin on the side where a connection section used for the connection to a semiconductor element is arranged.SOLUTION: A semiconductor module 1 includes: an outer frame 103; sealing resins 61u, 61v, 61w; gate signal output terminals 31ua-31vb; and partition sections 101, 102 laid across the outer flame 103 to partition a space 11 into a plurality of housing sections 111u, 111v, 111w, the gate signal output terminals 31ua-31vb with connection sections 311 exposed being arranged in the partition sections. The partition sections 101, 102 have through holes 101c, 102c where sealing resins 62, 62 are formed, the sealing resins connecting adjacent housing sections and the sealing resin formed in the through hole being continuous with the sealing resins formed in the housing sections.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor module that is applied to a power conversion device or the like, and a method for manufacturing the semiconductor module. [Background technology]

[0002] In recent years, power semiconductor modules, mainly using insulated gate bipolar transistors (IGBTs), have come to be widely used in power conversion devices. A power semiconductor module is a power semiconductor device that incorporates one or more power semiconductor chips to form a part or the whole of a conversion connection, and has a structure in which the power semiconductor chips are electrically insulated from a base plate or a cooling surface.

[0003] Patent Document 1 discloses a semiconductor device that can reduce the occurrence of peeling of bonding wires. Patent Document 2 discloses a semiconductor device that can suppress peeling of sealing resin even when operated at high temperatures. Patent Document 3 discloses a metal press processing method that enables partial roughening treatment in a short time, and a resin-sealed metal part obtained by the metal press processing method that ensures adhesion and cohesion to resin of a metal part for resin sealing and has excellent sealing properties and peel strength. Patent Document 4 discloses a semiconductor device that prevents peeling of resin when thermal stress is applied, improving reliability. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-229848 A [Patent Document 2] JP 2012-204366 A [Patent Document 3] JP 2012-64880 A [Patent Document 4] JP 2003-124406 A Summary of the Invention [Problem to be solved by the invention]

[0005] Power semiconductor modules are required to be available in various sizes, from small to large, in response to the need for higher current and higher voltage resistance. Under such circumstances, stress increases on the surface of a structure that is in close contact with the sealing resin provided in the power semiconductor module, and there is a risk that the sealing resin will peel off from the structure. If the sealing resin peels off from the structure, there is a problem that a wire provided in the sealing resin and used for wire bonding will break.

[0006] An object of the present invention is to provide a semiconductor module and a method for manufacturing the semiconductor module that can prevent peeling of the sealing resin on the side where a connection portion used for connection to a semiconductor element is disposed. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, a semiconductor module according to one embodiment of the present invention comprises an outer frame defining a space in which a plurality of semiconductor elements are arranged, a sealing resin formed in the space covering the plurality of semiconductor elements, a control terminal connected to the semiconductor element and outputting a control signal for controlling the semiconductor element, and a partition portion in which the control terminal is arranged with its connection portion with the semiconductor element exposed, the partition portion being stretched across the outer frame and dividing the space into a plurality of regions, the partition portion having a through hole through which sealing resin is formed that connects adjacent regions and is continuous with the sealing resin formed in the region.

[0008] In addition, in order to achieve the above-mentioned object, a manufacturing method for a semiconductor module according to one aspect of the present invention includes forming a first member having a control terminal connected to a semiconductor element and outputting a control signal to control the semiconductor element, forming a through hole that penetrates the first member, placing the first member in a specified mold, and pouring resin into the mold to form an outer frame that defines a space in which the semiconductor element is to be placed, and a partition portion that is formed integrally with the outer frame and that, together with the first member, divides the space into a plurality of regions. Effect of the Invention

[0009] According to one aspect of the present invention, peeling of the sealing resin on the side where the connection portion used for connection to the semiconductor element is disposed can be prevented. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing an example of a schematic configuration of a semiconductor module according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view taken along line XX in FIG. 1, showing an example of a schematic configuration of a semiconductor module according to an embodiment of the present invention. [Diagram 3] 2 is a circuit diagram showing an example of an inverter circuit provided in a semiconductor module according to an embodiment of the present invention; FIG. [Figure 4] 3 is a diagram for explaining a partition provided in the semiconductor module according to the embodiment of the present invention, and is a cross-sectional view showing an enlarged view of the vicinity of the partition shown in FIG. 2. FIG. [Diagram 5] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor module according to an embodiment of the present invention; [Figure 6] 5A to 5C are diagrams (part 2) for explaining the method for manufacturing a semiconductor module according to an embodiment of the present invention. [Figure 7] 11A to 11C are views (part 3) for explaining a method for manufacturing a semiconductor module according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Each embodiment of the present invention is an example of an apparatus or method for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the material, shape, structure, arrangement, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0012] A semiconductor module according to an embodiment of the present invention will be described with reference to Figs. 1 to 7. First, a schematic configuration of the semiconductor module according to this embodiment will be described with reference to Figs. 1 to 4. In this embodiment, a power conversion module capable of DC / AC conversion will be described as an example of the semiconductor module. Note that Fig. 1 does not show the sealing resin provided in the semiconductor module. Also, in Fig. 1, hidden lines such as through holes are shown with dashed lines. Furthermore, in Fig. 2, hidden lines such as gate signal output terminals are shown with dashed lines.

[0013] 1, the semiconductor module 1 according to this embodiment includes an outer frame 103 that defines a space 11 in which a plurality of (six in this embodiment) semiconductor elements Sua, Sub, Sva, Svb, Swa, and Swb are arranged. The outer frame 103 defines the space 11 in a rectangular shape in a plan view. The outer frame 103 is formed of, for example, an insulating thermoplastic resin. Examples of the thermoplastic resin include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, and acrylonitrile butadiene styrene (ABS) resin.

[0014] As shown in FIG. 2, the semiconductor module 1 includes sealing resins 61u, 61v, and 61w formed in the space 11 to cover the semiconductor elements Sua to Swb. The sealing resins 61u, 61v, and 61w are formed of, for example, a material different from that of the outer frame 103. The sealing resins 61u, 61v, and 61w are formed of, for example, an epoxy resin. The sealing resins 61u, 61v, and 61w are sealing members that seal components such as the semiconductor elements Sua to Swb provided in the space 11 and the laminated substrates 14u, 14v, and 14w on which the semiconductor elements Sua to Swb are mounted. The sealing resins 61u, 61v, and 61w seal the laminated substrates 14u, 14v, and 14w, thereby improving the insulation between predetermined conductive patterns (described in detail later) formed on the laminated substrates 14u, 14v, and 14w. Furthermore, the sealing resins 61u, 61v, and 61w seal various control terminals (described in detail below) connected to the laminated substrates 14u, 14v, and 14w by wire bonding and wires used in the wire bonding, thereby suppressing stress and distortion generated at the joints of the various control terminals and the wires. As a result, the sealing resins 61u, 61v, and 61w can improve the reliability of the semiconductor module 1.

[0015] 1, the semiconductor module 1 includes gate signal output terminals 31ua, 31ub, 31va, 31vb, 31wa, and 31wb (examples of control terminals) that are connected to the semiconductor elements Sua to Swb and output gate pulse signals (examples of control signals) that control the semiconductor elements Sua to Swb, and reference signal output terminals 32ua, 32ub, 32va, 32vb, 32wa, and 32wb (examples of control terminals) that output reference signals. Details of the gate signal output terminal 31ua and other terminals will be described later.

[0016] The semiconductor module 1 has gate signal output terminals 31ua-31wb with exposed connection portions 31 with the semiconductor elements Sua-Swb and reference signal output terminals 32ua-32wb with exposed connection portions 31 with the semiconductor elements Sua-Swb arranged therein, and includes partition portions 101, 102 that are stretched across an outer frame 103 and divide a space 11 into a plurality of storage portions 111u, 111v, 111w (an example of a plurality of regions). The partition portions 101, 102 are integrally formed of the same material as the outer frame 103. The partition portions 101, 102 and the outer frame 103 form a case 10. The partition portions 101, 102 will be described in detail later.

[0017] 1, the case 10 divides the space 11 into three regions, a storage section 111u for storing an inverter section for a U phase, a storage section 111v for storing an inverter section for a V phase, and a storage section 111w for storing an inverter section for a W phase, by partitions 101 and 102. The partitions 101 divide a part of the space 11 into the storage section 111u and the storage section 111v, and the partitions 102 divide another part of the space 11 into the storage section 111v and the storage section 111w.

[0018] The storage section 111u has a rectangular shape in a plan view. The storage section 111u is defined by a part of the outer frame 103 arranged on three consecutive sides (two short sides and one long side) of the four outer periphery sides, and the partition section 101 arranged on the remaining side (the remaining long side). The storage section 111v has a rectangular shape in a plan view. The storage section 111v is defined by another part of the outer frame 103 arranged on the opposing short sides of the four outer periphery sides, and the partition sections 101 and 102 arranged on the opposing long sides. The storage section 111w has a rectangular shape in a plan view. The storage section 111w is defined by the remaining part of the outer frame 103 arranged on three consecutive sides (two short sides and one long side) of the four outer periphery sides, and the partition section 102 arranged on the remaining side (the remaining long side).

[0019] 1, the semiconductor module 1 has a U-phase laminated substrate 14u stored in the storage section 111u and a U-phase inverter circuit 15u mounted on the laminated substrate 14u. The semiconductor module 1 has a V-phase laminated substrate 14v stored in the storage section 111v and a V-phase inverter circuit 15v mounted on the laminated substrate 14v. The semiconductor module 1 has a W-phase laminated substrate 14w stored in the storage section 111w and a W-phase inverter circuit 15w mounted on the laminated substrate 14w.

[0020] 1, the semiconductor module 1 has a U-phase power input terminal 21u to which DC power is input from the outside, a V-phase power input terminal 21v to which the DC power is input, and a W-phase power input terminal 21w to which the DC power is input. Each of the power input terminals 21u, 21v, and 21w has a positive terminal 211 connected to the positive side of the DC power and a negative terminal 212 connected to the negative side of the DC power.

[0021] The semiconductor module 1 has a power output terminal 81u arranged in a part of the outer frame 103 and facing the power input terminal 21u across the storage section 111u. The semiconductor module 1 has a power output terminal 81v arranged in a part of the outer frame 103 and facing the power input terminal 21v across the storage section 111v. The semiconductor module 1 has a power output terminal 81w arranged in a part of the outer frame 103 and facing the power input terminal 21w across the storage section 111w.

[0022] A positive terminal 211 of the power input terminal 21u is connected to a positive electrode pattern 41 formed on the laminated substrate 14u and connected to a semiconductor element Sua. A negative terminal 212 of the power input terminal 21u is connected to a negative electrode pattern 42 formed on the laminated substrate 14u and connected to a semiconductor element Sub. The power output terminal 81u is connected to an output portion pattern 43 formed on the laminated substrate 14u. This allows the semiconductor module 1 to generate U-phase AC power by the inverter circuit 15u using DC power supplied from the outside via the power input terminal 21u, and to supply the generated U-phase AC power from the power output terminal 81u to a drive target, for example, a motor M (not shown in FIG. 1, see FIG. 3).

[0023] A positive terminal 211 of the power input terminal 21v is connected to a positive electrode pattern 41 formed on the laminated substrate 14v and connected to a semiconductor element Sva. A negative terminal 212 of the power input terminal 21v is connected to a negative electrode pattern 42 formed on the laminated substrate 14v and connected to a semiconductor element Svb. The power output terminal 81v is connected to an output portion pattern 43 formed on the laminated substrate 14v. This allows the semiconductor module 1 to generate V-phase AC power by the inverter circuit 15v using DC power supplied from the outside via the power input terminal 21v, and to supply the generated V-phase AC power from the power output terminal 81v to a drive target, for example, the motor M.

[0024] A positive terminal 211 of the power input terminal 21w is connected to a positive electrode portion pattern 41 formed on the laminated substrate 14w and connected to a semiconductor element Swa. A negative terminal 212 of the power input terminal 21w is connected to a negative electrode portion pattern 42 formed on the laminated substrate 14w and connected to a semiconductor element Swb. The power output terminal 81w is connected to an output portion pattern 43 formed on the laminated substrate 14w. This allows the semiconductor module 1 to generate W-phase AC power by the inverter circuit 15w using DC power supplied from the outside via the power input terminal 21w, and to supply the generated W-phase AC power from the power output terminal 81w to a drive target, for example, a motor M.

[0025] 1, the reference signal output terminal 32ua, the gate signal output terminal 31ua, the gate signal output terminal 31ub, and the reference signal output terminal 32ub connected to the inverter circuit 15u are arranged in this order from the power input terminal 21u side toward the power output terminal 81u side in the partition portion 101. The order and number of the gate signal output terminals 31ua, 31ub and the reference signal output terminals 32ua, 32ub arranged in the extending direction of the partition portion 101 are not limited to the order and number shown in FIG. 1, and may be different depending on the configuration and arrangement pattern of the inverter circuit 15u provided on the laminated substrate 14u.

[0026] In the partition portion 102, the reference signal output terminal 32va, the gate signal output terminal 31va, the gate signal output terminal 31vb, and the reference signal output terminal 32vb connected to the inverter circuit 15v are arranged in this order from the power input terminal 21v side toward the power output terminal 81v side. The order and number of the gate signal output terminals 31va, 31vb and the reference signal output terminals 32va, 32vb arranged in the extending direction of the partition portion 102 are not limited to the order and number shown in Fig. 1, and may be different depending on the configuration and arrangement pattern of the inverter circuit 15v provided on the laminated substrate 14v.

[0027] In the terminal arrangement region 103a, which is parallel to the partitions 101, 102 and is a part of the outer frame 103 that defines the storage section 111w, the reference signal output terminal 32wa, the gate signal output terminal 31wa, the gate signal output terminal 31wb, and the reference signal output terminal 32wb connected to the inverter circuit 15w are arranged in this order from the power input terminal 21w side toward the power output terminal 81w side. The order and number of the gate signal output terminals 31wa, 31wb and the reference signal output terminals 32wa, 32wb arranged in the extension direction of the terminal arrangement region 103a are not limited to the order and number shown in FIG. 1 and may be different depending on the configuration and arrangement pattern of the inverter circuit 15w provided on the laminated substrate 14w.

[0028] The gate signal output terminal 31ua and the reference signal output terminal 32ua arranged in the partition portion 101 are electrically connected to the semiconductor element Sua constituting the inverter circuit 15u by wire bonding. Specifically, the connection portion 311 of the gate signal output terminal 31ua and the connection portion 321 of the reference signal output terminal 32ua are connected to the semiconductor element Sua by individual wires 150. In addition, the input portion 312 of the gate signal output terminal 31ua and the input portion 322 of the reference signal output terminal 32ua are each connected to a control circuit (not shown) that controls the inverter circuits 15u, 15v, 15w.

[0029] The gate signal output terminal 31ub and the reference signal output terminal 32ub arranged in the partition portion 101 are electrically connected to the semiconductor element Sub constituting the inverter circuit 15u by wire bonding. Specifically, the connection portion 311 of the gate signal output terminal 31ub and the connection portion 321 of the reference signal output terminal 32ub are connected to the semiconductor element Sub by different wires 150. In addition, the input portion 312 of the gate signal output terminal 31ua and the input portion 322 of the reference signal output terminal 32ua are each connected to a control circuit (not shown) that controls the inverter circuits 15u, 15v, 15w.

[0030] The gate signal output terminal 31va and the reference signal output terminal 32va arranged in the partition portion 102 are electrically connected to the semiconductor element Sva constituting the inverter circuit 15v by wire bonding. Specifically, the connection portion 311 of the gate signal output terminal 31va and the connection portion 321 of the reference signal output terminal 32va are connected to the semiconductor element Sva by individual wires 150. In addition, the input portion 312 of the gate signal output terminal 31va and the input portion 322 of the reference signal output terminal 32va are each connected to a control circuit (not shown) that controls the inverter circuits 15u, 15v, and 15w.

[0031] The gate signal output terminal 31vb and the reference signal output terminal 32vb arranged in the partition portion 102 are electrically connected to the semiconductor element Svb constituting the inverter circuit 15v by wire bonding. Specifically, the connection portion 311 of the gate signal output terminal 31vb and the connection portion 321 of the reference signal output terminal 32vb are connected to the semiconductor element Svb by different wires 150. In addition, the input portion 312 of the gate signal output terminal 31va and the input portion 322 of the reference signal output terminal 32va are each connected to a control circuit (not shown) that controls the inverter circuits 15u, 15v, and 15w.

[0032] The gate signal output terminal 31wa and the reference signal output terminal 32wa arranged in the terminal arrangement region 103a of the outer frame 103 are electrically connected to the semiconductor element Swa constituting the inverter circuit 15w by wire bonding. Specifically, the connection portion 311 of the gate signal output terminal 31wa and the connection portion 321 of the reference signal output terminal 32wa are connected to the semiconductor element Swa by individual wires 150. In addition, the input portion 312 of the gate signal output terminal 31wa and the input portion 322 of the reference signal output terminal 32wa are each connected to a control circuit (not shown) that controls the inverter circuits 15u, 15v, and 15w.

[0033] The gate signal output terminal 31wb and the reference signal output terminal 32wb arranged in the terminal arrangement region 103a of the outer frame 103 are electrically connected to the semiconductor element Swb constituting the inverter circuit 15w by wire bonding. Specifically, the connection portion 311 of the gate signal output terminal 31wb and the connection portion 321 of the reference signal output terminal 32wb are connected to the semiconductor element Swb by different wires 150. In addition, the input portion 312 of the gate signal output terminal 31wa and the input portion 322 of the reference signal output terminal 32wa are each connected to a control circuit (not shown) that controls the inverter circuits 15u, 15v, and 15w.

[0034] Although the details will be described later, the partitioning portion 101 has a through hole 101c (see FIGS. 1 and 2) in which a sealing resin 62 (see FIG. 2) is formed that connects the adjacent storage portions 111u and 111v and is continuous with the sealing resin 61u (see FIG. 2) formed in the storage portion 111u and the sealing resin 61v (see FIG. 2) formed in the storage portion 111v. The partitioning portion 101 has a plurality of through holes 101c (six in this embodiment). Similarly, the partitioning portion 102 has a through hole 102c (see FIGS. 1 and 2) in which a sealing resin 63 (see FIG. 2) is formed that connects the adjacent storage portions 111v and 111w and is continuous with the sealing resin 61v formed in the storage portion 111v and the sealing resin 61w (see FIG. 2) formed in the storage portion 111w. The partitioning portion 102 has a plurality of through holes 102c (six in this embodiment).

[0035] 2, the semiconductor module 1 has a cooler 16 attached to the case 10. The cooler 16 is mechanically fixed to the case 10 by, for example, an adhesive 161. The laminated substrates 14u, 14v, and 14w are, for example, soldered to the cooler 16. This allows the semiconductor module 1 to release heat generated from the semiconductor elements Sua to Swb provided on each of the laminated substrates 14u, 14v, and 14w to the outside via the cooler 16.

[0036] The laminated substrate 14u arranged in the storage section 111u has a rectangular flat insulating substrate 141 and a rectangular flat heat transfer member 142 formed on the lower surface (cooler 16 side) of the insulating substrate 141. The insulating substrate 141 is made of, for example, ceramic. The heat transfer member 142 is made of, for example, copper. The heat transfer member 142 is connected to the cooler 16 by, for example, soldering. An inverter circuit 15u is provided on the upper surface of the insulating substrate 141 (the surface opposite to the surface on which the heat transfer member 142 is provided).

[0037] The laminated substrate 14u arranged in the storage section 111u and the inverter circuit 15u provided on the upper surface of the insulating substrate 141 of the laminated substrate 14u are covered with the sealing resin 61u formed in the storage section 111u. In addition, the wire 150 connecting the gate signal output terminal 31ub and the semiconductor element Sub, the wire 150 connecting the semiconductor element Sub and the output part pattern 43, and other wires 150 (not shown in FIG. 2) used for wire bonding in the inverter circuit 15u are also covered with the sealing resin 61u. The sealing resin 61u seals the inverter circuit 15u and the like in a state where it fills the space constituting the storage section 111u. As a result, the sealing resin 61u is also formed in the gaps between the positive electrode part pattern 41, the negative electrode part pattern 42, and the output part pattern 43 formed on the insulating substrate 141. As a result, the sealing resin 61u can improve the insulation of the laminated substrate 14u. The sealing resin 61u is formed in the storage section 111u while covering metal parts such as the connection parts 311 of the gate signal output terminals 31ua and 31ub, the connection parts 321 of the reference signal output terminals 32ub and 32ub, and the connection parts and wires 150 used for electrical connection in the inverter circuit 15u. As a result, the sealing resin 61u seals the connection parts and wires 150, and thus it is possible to suppress stress and distortion occurring at the joints of the connection parts and wires 150, thereby improving the reliability of the semiconductor module 1.

[0038] As shown in FIG. 2, the laminated substrate 14v arranged in the storage section 111v and the sealing resin 61v formed in the storage section 111v have the same state as the laminated substrate 14u and the sealing resin 61u in the storage section 111u. Therefore, the sealing resin 61v is also formed in the gaps between the positive electrode part pattern 41, the negative electrode part pattern 42, and the output part pattern 43 formed on the insulating substrate 141 of the laminated substrate 14v. As a result, the sealing resin 61v can improve the insulation of the laminated substrate 14v. In addition, the sealing resin 61v is formed in the storage section 111u in a state where it covers metal parts such as the connection parts 311 of the gate signal output terminals 31va and 31vb, the connection parts 321 of the reference signal output terminals 32vb and 32vb, the connection parts used for electrical connection in the inverter circuit 15v, and the wires 150. As a result, by sealing the connection parts and the wires 150, the sealing resin 61v can suppress stress and distortion occurring at the joints of each connection part and the wires 150, thereby improving the reliability of the semiconductor module 1.

[0039] As shown in FIG. 2, the laminated substrate 14w arranged in the storage section 111w and the sealing resin 61w formed in the storage section 111w have the same state as the laminated substrate 14u and the sealing resin 61u in the storage section 111u. Therefore, the sealing resin 61w is also formed in the gaps between the positive electrode part pattern 41, the negative electrode part pattern 42, and the output part pattern 43 formed on the insulating substrate 141 of the laminated substrate 14w. As a result, the sealing resin 61w can improve the insulation of the laminated substrate 14w. In addition, the sealing resin 61w is formed in the storage section 111w in a state where it covers metal parts such as the connection parts 311 of the gate signal output terminals 31wa and 31wb, the connection parts 321 of the reference signal output terminals 32wb and 32wb, the connection parts used for electrical connection in the inverter circuit 15w, and the wires 150. As a result, by sealing the connection parts and the wires 150, the sealing resin 61w can suppress stress and distortion occurring at the joints of the connection parts and the wires 150, thereby improving the reliability of the semiconductor module 1.

[0040] Next, the circuit configuration of the inverter circuits 15u, 15v, and 15w provided in the semiconductor module 1 will be described with reference to FIG.

[0041] 3, the inverter circuit 15u provided in the semiconductor module 1 includes a semiconductor element Sua and a semiconductor element Sub connected in series between a positive terminal 211 and a negative terminal 212 of a power input terminal 21u. A connection between the semiconductor element Sua and the semiconductor element Sub is connected to a power output terminal 81u from which U-phase AC power is output. In the inverter circuit 15u, the semiconductor element Sua forms an upper arm of the U-phase AC power, and the semiconductor element Sub forms a lower arm of the U-phase AC power.

[0042] The inverter circuit 15v provided in the semiconductor module 1 includes semiconductor elements Sva and Svb connected in series between the positive terminal 211 and the negative terminal 212 of the power input terminal 21v. The connection between the semiconductor elements Sva and Svb is connected to a power output terminal 81v from which V-phase AC power is output. The semiconductor element Sva constitutes the upper arm of the V-phase AC power, and the semiconductor element Svb constitutes the lower arm of the V-phase AC power.

[0043] The inverter circuit 15w provided in the semiconductor module 1 includes semiconductor elements Swa and Swb connected in series between the positive terminal 211 and the negative terminal 212 of the power input terminal 21w. The connection between the semiconductor elements Swa and Swb is connected to a power output terminal 81w from which W-phase AC power is output. The semiconductor element Swa constitutes the upper arm of the W-phase AC power, and the semiconductor element Swb constitutes the lower arm of the W-phase AC power.

[0044] As shown in Fig. 3, the semiconductor element Sua has a transistor Qua, which is, for example, an insulated gate bipolar transistor (IGBT), and a free wheel diode Dua connected in anti-parallel to the transistor Qua. The transistor Qua and the free wheel diode Dua are, for example, formed on a single semiconductor substrate and integrated into a single chip. The semiconductor element Sub has a transistor Qub, which is, for example, an IGBT, and a free wheel diode Dub connected in anti-parallel to the transistor Qub. The transistor Qub and the free wheel diode Dub are, for example, formed on a single semiconductor substrate and integrated into a single chip.

[0045] The collector C of the transistor Qua and the cathode K of the freewheeling diode Dua are connected to each other and connected to the positive terminal 211 of the power input terminal 21u. The emitter E of the transistor Qua and the anode A of the freewheeling diode Dua are connected to each other. The collector C of the transistor Qub and the cathode K of the freewheeling diode Dub are connected to each other. The emitter E of the transistor Qua and the anode A of the freewheeling diode Dub are connected to each other and connected to the power output terminal 81u. The emitter E of the transistor Qub and the anode A of the freewheeling diode Dub are connected to each other and connected to the negative terminal 212 of the power input terminal 21u.

[0046] A gate G of the transistor Qua is connected to a connection part 311 (see FIG. 1) of the gate signal output terminal 31ua by a wire 150. An emitter E of the transistor Qua is connected to a connection part 321 (see FIG. 1) of the reference signal output terminal 32ua by a wire 150.

[0047] As shown in Fig. 3, the semiconductor element Sva has a transistor Qva, for example an IGBT, and a free wheel diode Dva connected in anti-parallel to the transistor Qva. The transistor Qva and the free wheel diode Dva are formed, for example, on a single semiconductor substrate and integrated into a single chip. The semiconductor element Svb has a transistor Qvb, for example an IGBT, and a free wheel diode Dvb connected in anti-parallel to the transistor Qvb. The transistor Qvb and the free wheel diode Dvb are formed, for example, on a single semiconductor substrate and integrated into a single chip.

[0048] The collector C of the transistor Qva and the cathode K of the freewheeling diode Dva are connected to each other and connected to the positive terminal 211 of the power input terminal 21v. The emitter E of the transistor Qva and the anode A of the freewheeling diode Dva are connected to each other. The collector C of the transistor Qvb and the cathode K of the freewheeling diode Dvb are connected to each other. The emitter E of the transistor Qva and the anode A of the freewheeling diode Dva, and the collector C of the transistor Qvb and the cathode K of the freewheeling diode Dvb are connected to each other and connected to the power output terminal 81v. The emitter E of the transistor Qvb and the anode A of the freewheeling diode Dvb are connected to each other and connected to the negative terminal 212 of the power input terminal 21v.

[0049] The gate G of the transistor Qva is connected to the connection part 311 (see FIG. 1) of the gate signal output terminal 31va by a wire 150. The emitter E of the transistor Qva is connected to the connection part 321 (see FIG. 1) of the reference signal output terminal 32va by a wire 150.

[0050] As shown in Fig. 3, the semiconductor element Swa has a transistor Qwa, for example an IGBT, and a free wheel diode Dwa connected in anti-parallel to the transistor Qwa. The transistor Qwa and the free wheel diode Dwa are formed, for example, on a single semiconductor substrate and integrated into a single chip. The semiconductor element Swb has a transistor Qwb, for example an IGBT, and a free wheel diode Dwb connected in anti-parallel to the transistor Qwb. The transistor Qwb and the free wheel diode Dwb are formed, for example, on a single semiconductor substrate and integrated into a single chip.

[0051] The collector C of the transistor Qwa and the cathode K of the freewheeling diode Dwa are connected to each other and connected to the positive terminal 211 of the power input terminal 21w. The emitter E of the transistor Qwa and the anode A of the freewheeling diode Dwa are connected to each other. The collector C of the transistor Qwb and the cathode K of the freewheeling diode Dwb are connected to each other. The emitter E of the transistor Qwa and the anode A of the freewheeling diode Dwa, and the collector C of the transistor Qwb and the cathode K of the freewheeling diode Dwb are connected to each other and connected to the power output terminal 81w. The emitter E of the transistor Qwb and the anode A of the freewheeling diode Dwb are connected to each other and connected to the negative terminal 212 of the power input terminal 21w.

[0052] The gate G of the transistor Qwa is connected to the connection part 311 (see FIG. 1) of the gate signal output terminal 31wa by a wire 150. The emitter E of the transistor Qwa is connected to the connection part 321 (see FIG. 1) of the reference signal output terminal 32wa by a wire 150.

[0053] A gate pulse signal output from a control circuit (not shown) is input to the gate G of a transistor Qua provided in the semiconductor element Sua, and a DC reference signal output from the control circuit is input to the emitter E of the transistor Qua provided in the semiconductor element Sua. Therefore, the potential difference between the potential of the gate pulse signal and the potential of the reference signal is applied to the transistor Qua as a gate-emitter voltage.

[0054] A potential difference between the potential of the gate pulse signal output from the control circuit and the potential of the reference signal is applied as a gate-emitter voltage to the transistor Qub provided in the semiconductor element Sub. A potential difference between the potential of the gate pulse signal output from the control circuit and the potential of the reference signal is applied as a gate-emitter voltage to the transistor Qva provided in the semiconductor element Sva. A potential difference between the potential of the gate pulse signal output from the control circuit and the potential of the reference signal is applied as a gate-emitter voltage to the transistor Qvb provided in the semiconductor element Svb. A potential difference between the potential of the gate pulse signal output from the control circuit and the potential of the reference signal is applied as a gate-emitter voltage to the transistor Qwa provided in the semiconductor element Swa. A potential difference between the potential of the gate pulse signal output from the control circuit and the potential of the reference signal is applied as a gate-emitter voltage to the transistor Qwb provided in the semiconductor element Swb.

[0055] For example, the transistors Qua, Qub, Qva, Qvb, Qwa, and Qwb are turned on when the voltage level of the gate pulse signal is high, and turned off when the voltage level of the gate pulse signal is low. Although detailed description is omitted, the transistors Qua and Qub provided in the inverter circuit 15u, the transistors Qva and Qvb provided in the inverter circuit 15v, and the transistors Qwa and Qwb provided in the inverter circuit 15w are repeatedly turned on and off at a predetermined timing and combination. This allows the semiconductor module 1 to supply U-phase AC power, V-phase AC power, and W-phase AC power, the phases of which are shifted from each other by a predetermined amount, to the motor M from the power output terminals 81u, 81v, and 81w of the inverter circuits 15u, 15v, and 15w.

[0056] (Partition configuration) Next, the configuration of the partitioning parts 101, 102 provided in the semiconductor module 1 according to this embodiment will be described using Fig. 4 while referring to Figs. 1 to 3. Note that in Fig. 4, the hidden lines of the gate signal output terminals 31ub are shown by dashed lines. The partitioning parts 101 and 102 have the same configuration. Therefore, the configuration of the partitioning parts 101, 102 will be described by taking the partitioning part 101 as an example.

[0057] As shown in Fig. 4, the partition section 101 has a through hole 101c in which a sealing resin 62 is formed that connects the adjacent storage sections 111u and 111v and is continuous with the sealing resin 61u (see Fig. 2) formed in the storage section 111u and the sealing resin 61v (see Fig. 2) formed in the storage section 111v. The partition section 101 has a first member 101a in which the through hole 101c is formed and which is separate from the outer frame 103, and a second member 101b in which the through hole 101c is not formed and which is integrated with the outer frame 103. The second member 101b is fixed to the first member 101a.

[0058] The first member 101a has a base 101a1 fixed to the cooler 16 and a wall 101a2 protruding from the base 101a1. The base 101a1 and the wall 101a2 are integrally formed. The wall 101a2 is disposed on the base 101a1, biased toward the storage section 111v side of the base 101a1. The through hole 101c is formed in the first member 101a, more specifically, in the wall 101a2.

[0059] The second member 101b is disposed on the first member 101a in contact with the wall portion 101a2. The second member 101b is formed in a wall shape with approximately the same thickness as the wall portion 101a2. The second member 101b is disposed covering the upper surface of the first member 101a from which the input portion 312 of the gate signal output terminal 31ub protrudes, and the side surface of the first member 101a facing each of the outer frames 103 on which the power input terminal 21u and the power output terminal 81u are disposed. That is, the second member 101b is disposed covering three consecutive side surfaces of the wall portion 101a2. As a result, the partition portion 101 has a curved shape. The partition portion 101 has an L-shaped cross section perpendicular to the extension direction.

[0060] As shown in FIG. 4, the through hole 101c is inclined so that the opening on the side where the connection part 311 is arranged is higher than the opening on the side where the connection part 311 is not arranged. In other words, the through hole 101c formed in the partition part 101 is inclined so that the opening on the side of the storage part 111u is higher than the opening on the side of the storage part 111v. Here, the reference for the height of the opening of the through hole 101c is the position where the partition part 101 contacts the cooler 16. All the through holes 101c formed in the partition part 101 are inclined at approximately the same angle. In this way, by inclining the through hole 101c, bubbles can be removed when the sealing resins 61u and 61v formed in the storage parts 111u and 111v enter the through hole 101c to form the sealing resin 62. This prevents the formation of cavities in the sealing resin 62 due to bubbles.

[0061] The through hole 101c is formed, for example, in a cylindrical shape. The through hole 101c has a diameter of, for example, 1 mm or more and 3 mm or less. However, the multiple through holes 101c are not limited to a cylindrical shape, and may be formed in other shapes, such as a rectangular column shape. In addition, in this embodiment, the through hole 101c has a substantially constant diameter, but may have, for example, a truncated cone shape whose diameter becomes longer from the side where the connection part 311 is arranged (the storage part 111u side) toward the side where the connection part 311 is not arranged (the storage part 111v side). In addition, the through hole 101c may have, for example, a truncated pyramid shape whose diameter becomes wider from the side where the connection part 311 is arranged (the storage part 111u side) toward the side where the connection part 311 is not arranged (the storage part 111v side).

[0062] Each of the openings of the through holes 101c is disposed in a direction perpendicular to the surface on which the connecting portions 311 and 321 are disposed. Each of the openings of the through holes 101c is provided in a wall portion 101a2 formed in a wall shape of the first member 101a of the partition portion 101. Therefore, one opening of the through holes 101c becomes an opening that opens a part of the side wall of the storage portion 111u, and the other opening of the through holes 101c becomes an opening that opens a part of the side wall of the storage portion 111v. As a result, the through holes 101c form a cavity that connects the adjacent storage portions 111u and 111v. As a result, when the sealing resins 61u, 61v are formed in the storage portions 111u, 111v, the sealing resin 61u entering from one opening of the plurality of through holes 101c and the sealing resin 61v entering from the other opening of the plurality of through holes 101c come into contact with each other inside the plurality of through holes 101c and are solidified to form the sealing resin 62. In this manner, the sealing resin 62 is formed by a part of the sealing resin 61u and a part of the sealing resin 61v.

[0063] By forming the sealing resin 62 while filling the multiple through holes 101c, the sealing resin 62 formed in the multiple through holes 101c provided in the partition portion 101, the sealing resin 61u formed in the storage portion 111u, and the sealing resin 61v formed in the storage portion 111v are integrated to become a single continuous resin.

[0064] As described above, the semiconductor element Sua is connected to the gate signal output terminal 31ua and the reference signal output terminal 32ua by wire bonding. The semiconductor element Sub is connected to the gate signal output terminal 31ub and the reference signal output terminal 32ub by wire bonding. Therefore, the connection portion 311 of the gate signal output terminal 31ua and the connection portion 321 of the reference signal output terminal 32ua are joints between the semiconductor element Sua and the wire 150. Similarly, the connection portion 311 of the gate signal output terminal 31ub and the connection portion 321 of the reference signal output terminal 32ub are joints between the semiconductor element Sub and the wire 150.

[0065] Although the details will be described later, when a temperature load is applied to the semiconductor module 1 and deformation occurs in the sealing resin of the semiconductor module 1, tensile stresses with opposite directions are generated on the side of the partition 101 where the connection portion 311 is arranged (hereinafter, may be referred to as the "connection portion side") and the side where the connection portion 311 is not arranged (hereinafter, may be referred to as the "rear side") as shown by the thick arrow in FIG. 4. In other words, tensile stresses with opposite directions are applied to both sides of the partition 101. As a result, a force is applied to the sealing resins 61u and 61v to peel them off from the partition 101. The sealing resin 62 is formed in the through hole 101c of the partition 101 and is integrated with the sealing resins 61u and 61v. The strength with which the sealing resins 61u and 61v and the sealing resin 62 maintain their integrated state is greater than the force with which the sealing resins 61u and 61v are peeled off from the partition 101 due to the tensile stress generated in the partition 101. This prevents the sealing resins 61u and 61v from peeling off from the partition portion 101, and therefore prevents the wires 150 from being broken at the connection portions 311 of the gate signal output terminals 31ub disposed in the partition portion 101.

[0066] The partition section 102 has the same structure as the partition section 101. As shown in Fig. 2, the partition section 102 has a through hole 102c in which the sealing resin 63 is formed, which connects the adjacent storage section 111v and storage section 111w and is continuous with the sealing resin 61v formed in the storage section 111v and the sealing resin 61w formed in the storage section 111w. The partition section 102 has a first member 102a in which the through hole 102c is formed and which is separate from the outer frame 103, and a second member 102b in which the through hole 102c is not formed and which is integrated with the outer frame 103. The second member 102b is fixed to the first member 102a.

[0067] The first member 102a has a base 102a1 fixed to the cooler 16 and a wall 102a2 protruding from the base 102a1. The base 102a1 and the wall 102a2 are integrally formed. The wall 102a2 is disposed on the base 102a1, biased toward the storage section 111w side of the base 102a1. The through hole 102c is formed in the first member 102a, more specifically, in the wall 102a2.

[0068] 1 and 2, the first member 102a has the same shape as the first member 101a of the partition portion 101, and the second member 102b has the same shape as the second member 101b of the partition portion 101. For this reason, in the partition portion 102, similar to the gate signal output terminal 31ua and the like arranged in the partition portion 101, the gate signal output terminals 31va, 31vb and the reference signal output terminals 32va, 32vb are arranged in a bent state so as to follow the bent shape of the partition portion 102.

[0069] The through-hole 102c is formed in the partition portion 102 so as to avoid the gate signal output terminals 31va, 31vb and the reference signal output terminals 32va, 32vb. The partition portion 102 has a plurality of through-holes 102c. All of the plurality of through-holes 102c are formed in the wall portion 102a2 of the first member 102a.

[0070] The through hole 102c is inclined so that the opening on the side where the connection part 311 is arranged is higher than the opening on the side where the connection part 311 is not arranged. In other words, the through hole 102c formed in the partition part 102 is inclined so that the opening on the side of the storage part 111v is higher than the opening on the side of the storage part 111w. Here, the reference height of the opening of the through hole 102c is the position where the partition part 102 contacts the cooler 16. All the through holes 102c formed in the partition part 102 are inclined at approximately the same angle. In this way, by inclining the through hole 102c, bubbles can be removed when the sealing resins 61v and 61w formed in the storage parts 111v and 111w enter the through hole 102c to form the sealing resin 63. This prevents the formation of cavities in the sealing resin 63 due to bubbles.

[0071] In this embodiment, the through hole 102c has the same shape as the through hole 101c, but may have a different shape. Each of the openings of the multiple through holes 102c is arranged in a direction perpendicular to the surface on which the connecting parts 311 and 321 are arranged. Each of the openings of the multiple through holes 102c is provided in the wall part 102a2 formed in a wall shape of the first member 102a of the partition part 102. Therefore, one opening of the multiple through holes 102c becomes an opening that opens a part of the side wall of the storage part 111v, and the other opening of the multiple through holes 102c becomes an opening that opens a part of the side wall of the storage part 111w. As a result, the multiple through holes 102c form a cavity that connects the adjacent storage parts 111v and 111w. As a result, when the sealing resins 61v, 61w are formed in the storage portions 111v, 111w, the sealing resin 61v entering from one opening of the plurality of through holes 102c and the sealing resin 61w entering from the other opening of the plurality of through holes 102c come into contact with each other inside the plurality of through holes 102c and are solidified to form the sealing resin 63. In this manner, the sealing resin 63 is formed by a part of the sealing resin 61v and a part of the sealing resin 61w.

[0072] By forming the sealing resin 63 while filling the through holes 102c, the sealing resin 63 formed in the through holes 102c provided in the partition 102, the sealing resin 61v formed in the storage section 111v, and the sealing resin 61w formed in the storage section 111w are integrated into one continuous resin. The strength with which the sealing resins 61v, 61w and the sealing resin 63 maintain their integrated state is greater than the force with which the sealing resins 61v, 61w are peeled off from the partition 102. Therefore, even if a temperature load is applied to the semiconductor module 1 and the semiconductor module 1 is deformed, the sealing resins 61v, 61w are prevented from being peeled off from the partition 102. As a result, it is possible to prevent breakage of the wires 150 at the connection parts 311 of the gate signal output terminals 31va, 31vb and the connection parts 321 of the reference signal output terminals 32va, 32vb arranged in the partition 102.

[0073] 2, the shape of the terminal arrangement region 103a of the outer frame 103, in which the gate signal output terminals 31wa, 31wb and the reference signal output terminals 32wa, 32wb connected to the laminated substrate 14w are arranged, has a curved shape similar to the partitions 101, 102. Therefore, the gate signal output terminals 31wa, 31wb and the reference signal output terminals 32wa, 32wb are arranged in the outer frame 103 in a curved state so as to follow the curved shape of the terminal arrangement region 103a of the outer frame 103.

[0074] In the terminal arrangement region 103a of the outer frame 103, the side where the connecting parts 311, 321 are not arranged is the outside, and no sealing resin is formed thereon. Therefore, even if the semiconductor module 1 is deformed due to a temperature load, the terminal arrangement region 103a is not subjected to tensile stress from both sides, unlike the partition parts 101, 102. As a result, when the semiconductor module 1 is deformed, the wires 150 (not shown) joined to the connecting parts 311, 321 arranged in the terminal arrangement region 103a are not likely to be subjected to tensile stress from the sealing resin 61w formed in the storage part 111w. For this reason, in this embodiment, no through holes are formed in the terminal arrangement region 103a of the outer frame 103.

[0075] (Function and effect of the partition) Next, the function and effect of the partitions 101, 102 provided in the semiconductor module 1 will be described with reference to FIGS.

[0076] In the semiconductor module 1 according to the present embodiment, as described above, the case 10 and the cooler 16 are fixed in a state in which the laminated substrates 14u, 14v, and 14w soldered to the cooler 16 are housed in the housings 111u, 111v, and 111w. Furthermore, the housings 111u, 111v, and 111w are provided with sealing resins 61u, 61v, and 61w that cover the laminated substrates 14u, 14v, and 14w (see FIG. 2). The cooler 16 is made of, for example, aluminum, and the insulating substrates 141 provided on each of the laminated substrates 14u, 14v, and 14w are made of, for example, ceramic. For this reason, the linear expansion coefficient of the cooler 16 is about 7 to 8 times larger than the linear expansion coefficient of the insulating substrate 141.

[0077] A thermal shock test is performed on the semiconductor module 1 as part of the reliability test. In the thermal shock test, a temperature load is applied to the semiconductor module 1, and due to the difference in the linear expansion coefficient between the cooler 16 and the sealing resins 61u, 61v, and 61w, the sealing resins 61u, 61v, and 61w expand when heated in the longitudinal direction of the case 10, and the sealing resins 61u, 61v, and 61w contract when cooled. As a result, stress is applied between the partition 101 and the sealing resins 61u and 61v, and stress is applied between the partition 102 and the sealing resins 61v and 61w. In particular, when cooling, tensile stress is applied to both sides of the partition 101 and to both sides of the partition 102, as shown by the thick straight arrows in FIG. 2. As a result, a force is applied to the sealing resin 61u in a direction in which it is peeled off from the partition portion 101, a force is applied to the sealing resin 61v in a direction in which it is peeled off from the partition portions 101 and 102, and a force is applied to the sealing resin 61w in a direction in which it is peeled off from the partition portion 102. In addition to the thermal shock test, deformation of the semiconductor module 1 may also occur due to contraction of the sealing resins 61u, 61v, and 61w caused by cooling during the formation of the sealing resins 61u, 61v, and 61w, and tensile stress may be applied from the sealing resins 61u, 61v, and 61w to the partition portions 101 and 102.

[0078] A cross-sectional disassembly investigation of the partition of a conventional semiconductor module and a simulation analysis of the tensile stress applied to the partition were performed. The conventional semiconductor module investigated has a similar structure to the semiconductor module 1 according to the present embodiment, except that the partition does not have a through hole.

[0079] Simulation analysis of tensile stress confirmed that tensile stress is applied in opposite directions to the connection side and back side of the partition. In addition, in a cross-sectional disassembly investigation, peeling between the partition and the sealing resin was confirmed on either the connection side or the back side of the partition. However, peeling of the sealing resin from the connection side and peeling of the sealing resin from the back side did not occur simultaneously.

[0080] The connection parts of the control terminals (i.e., the gate signal output terminals and the reference signal output terminals) exposed on the connection part side and the wires joined to the connection parts are covered with the sealing resin. In other words, the connection parts and the wires joined to the connection parts are embedded in the sealing resin and fixed to the sealing resin. For this reason, when a semiconductor module provided with a partition part is deformed in the forward warping direction and the sealing resin peels off from the connection part side of the partition part, a force is applied to the wires embedded in the sealing resin in a direction away from the partition part. As a result, a force is applied to the wires in a direction away from the connection part of the control terminals arranged on the partition part, and the wires are broken at the connection part, which may cause an open defect in the semiconductor module. When the wires are broken, the gate pulse signal and the reference signal are no longer input from the control circuit to the inverter circuit, so that the semiconductor module does not perform the specified operation and is no longer able to supply power to the driven object, for example, a motor.

[0081] In contrast, in the semiconductor module 1 according to the present embodiment, the sealing resin 61u and the sealing resin 61v are connected by the sealing resin 62 formed in each of the multiple through holes 101c formed in the partition portion 101. Furthermore, the sealing resin 61u, the sealing resin 62, and the sealing resin 61v are integrally formed. Therefore, the adhesion between the partition portion 101 and the sealing resin 61u and the adhesion between the partition portion 101 and the sealing resin 61v are improved compared to the case where the through holes 101c are not formed. Furthermore, the adhesion between the partition portion 101 and each of the sealing resin 61u and the sealing resin 61v is determined by the base material which is the material of the sealing resin 62 formed in the through holes 101c. With respect to the tensile stress applied to the partition portion 101 due to the deformation of the semiconductor module 1, the base material of the sealing resin 62 has a strength greater than the adhesion between the partition portion 101 and each of the sealing resin 61u and the sealing resin 61v when the through holes 101c are not formed. As a result, even if the sealing resins 61u, 61v, 61w of the semiconductor module 1 shrink, the sealing resins 61u, 61v are prevented from peeling off from the partition portion 101, so that the semiconductor module 1 can prevent breakage of the wires 150 at the connection portions 311, 321 exposed to the partition portion 101.

[0082] Similarly, the sealing resin 61v and the sealing resin 61w are connected by the sealing resin 63 formed in each of the through holes 102c formed in the partition portion 102. Furthermore, the sealing resin 61v, the sealing resin 63, and the sealing resin 61w are integrally formed. The adhesion between the partition portion 102 and the sealing resin 61v and the adhesion between the partition portion 102 and the sealing resin 61w are improved compared to the case where the through holes 102c are not formed. Furthermore, the adhesion between the partition portion 102 and each of the sealing resin 61v and the sealing resin 61w is determined by the base material which is the material for forming the sealing resin 63 formed in the through holes 102c. The base material of the sealing resin 63 has a strength greater than the adhesion between the partition portion 102 and each of the sealing resin 61v and the sealing resin 61w when the through holes 102c are not formed, against the tensile stress applied to the partition portion 102 due to the deformation of the semiconductor module 1. As a result, even if the sealing resins 61u, 61v, and 61w of the semiconductor module 1 shrink, the sealing resins 61v, 61w are prevented from peeling off from the partition portion 102, so that the semiconductor module 1 can prevent breakage of the wires 150 at the connection portions 311, 321 exposed to the partition portion 102.

[0083] The tensile stress applied to the partitions 101, 102 of the semiconductor module 1 varies depending on the size of the case 10. For example, the tensile stress becomes stronger as the case 10 becomes larger. For this reason, by forming the sealing resins 61u, 61v, 61w and the sealing resins 62, 63 by selecting a material having a strength capable of withstanding the tensile stress according to the size of the case 10, the semiconductor module 1 can prevent breakage of the wires 150 at the connection portions 311, 321 exposed at the partitions 101, 102, respectively.

[0084] (Manufacturing method of semiconductor module) A method for manufacturing a semiconductor module according to this embodiment will be described with reference to FIG. 4 and with reference to FIG. 5 to FIG. 7. The methods for manufacturing the partitions 101 and 102 are the same. Therefore, the method for manufacturing the partitions 101 and 102 will be described with reference to the partition 101. FIG. 5 and FIG. 6 are diagrams for explaining a method for forming the first member 101a provided in the partition 101. FIG. 5(a) is a view of the first member 101a before the through-holes 101c are formed, seen from the connection side in a direction perpendicular to the wall 101a2, and FIG. 5(b) is a cross-sectional view of the first member 101a cut along the line YY shown in FIG. 5(a). FIG. 6(a) is a view of the first member 101a after the through-holes 101c are formed, seen from the connection side in a direction perpendicular to the wall 101a2, and FIG. 6(b) is a cross-sectional view of the first member 101a cut along the line YY shown in FIG. 6(a). In Fig. 5(b) and Fig. 6(b), the hidden lines of the gate signal output terminal 31ub are shown by dashed lines. Fig. 7 is a diagram for explaining a method of forming the case 10, and is a cross-sectional view of the case 10 cut at a position corresponding to the line XX shown in Fig. 1. In Fig. 7, the hidden lines of the gate signal output terminals 31ub, 31vb, and 31wb are shown by dashed lines.

[0085] As shown in Figure 5, in the manufacturing method of the semiconductor module 1 according to this embodiment, first, a first member 101a is formed in which gate signal output terminals 31ua, 31ub (an example of a control terminal) that are connected to semiconductor elements Sua, Sub (not shown in Figure 5, see Figure 1) and output gate pulse signals (an example of a control signal) that control the semiconductor elements Sua, Sub, and reference signal output terminals 32ua, 32ub (an example of a control terminal) that output reference signals are arranged.

[0086] The first member 101a is molded by insert molding in which heated and melted thermoplastic resin is injected into an injection molding die in which the gate signal output terminals 31ua, 31ub and the reference signal output terminals 32ua, 32ub are arranged, and the resin is integrated with the arranged gate signal output terminals 31ua, etc.

[0087] Next, as shown in Fig. 6, through holes 101c are formed through the first member 101a. The through holes 101c are formed by machining, for example, with a drill, after the first member 101a is molded. As shown in Fig. 6(a), the through holes 101c are formed at multiple locations (six locations in this embodiment) avoiding the gate signal output terminals 31ua, 31ub and the reference signal output terminals 32ua, 32ub. Also, as shown in Fig. 6(b), the through holes 101c are formed at an angle so that the opening on the connection side is higher than the opening on the back side.

[0088] A first member 102a constituting the partition portion 102 is formed by a method similar to that for the first member 101a. Furthermore, a predetermined member constituting the terminal arrangement region 103a is formed in the same shape as the first member 101a except for the through hole 101c.

[0089] Next, the first member 101a in which the through hole 101c is formed and the first member 102a in which the through hole 102c is formed are placed in an injection molding die (an example of a predetermined die). At that time, a predetermined member constituting the terminal arrangement region 103a is also placed in the injection molding die.

[0090] Next, as shown in Fig. 7, resin is poured into the injection mold to form an outer frame 103 that defines a space 11 in which semiconductor elements Sua, Sub, Sva, Svb, Swa, and Swb (not shown in Fig. 7, see Fig. 1) are arranged, and partition parts 101 and 102 that are formed integrally with the outer frame 103 and divide the space 11 into a plurality of storage parts 111u, 111v, and 111w (one example of a plurality of regions) together with first members 101a and 102a. At the same time as the formation of the partition parts 101 and 102, a terminal arrangement region 103a in which gate signal output terminals 31wa and 31wb and reference signal output terminals 32wa and 32wb are arranged is also formed. In this way, the case 10 is formed.

[0091] Although not shown, after the laminated substrates 14u, 14v, and 14w and the cooler 16 are attached to the case 10, resin for forming the sealing resins 61u, 61v, and 61w is injected into the storage sections 111u, 111v, and 111w at the same time. As a result, in the process of filling the storage sections 111u, 111v, and 111w with the sealing resins 61u, 61v, and 61w, the sealing resins 61u and 61v enter the through holes 101c, and the sealing resins 61v and 61w enter the through holes 102c. As a result, the formation of the sealing resins 61u, 61v, and 61w in the storage sections 111u, 111v, and 111w is completed, and the formation of the sealing resins 62 in the multiple through holes 101c and the sealing resin 63 in the multiple through holes 102c is also completed. In this way, the semiconductor module 1 is completed.

[0092] However, conventional injection molds are separated into two types, an upper mold and a lower mold. Therefore, conventional injection molds can only provide shapes in the direction in which the upper mold and the lower mold are removed. Therefore, conventional injection molds have a problem in that it is difficult to form lateral through holes such as through holes 101c and 102c.

[0093] In contrast, in this embodiment, the first members 101a, 102a in which the through holes 101c, 102c are formed are placed in an injection mold for forming the case 10. Therefore, in this embodiment, the case 10 can be molded using an injection mold having a structure that is separated into two types of molds, an upper mold and a lower mold. As a result, although the number of steps for forming the case 10 is increased compared to the steps for forming the case of a conventional semiconductor module, the case 10 can be molded without using a special method.

[0094] As described above, the semiconductor module 1 according to the present embodiment includes an outer frame 103 that defines a space 11 in which a plurality of semiconductor elements Sua, Sub, Sva, Svb, Swa, and Swb are arranged, sealing resins 61u, 61v, and 61w that are formed in the space 11 to cover the plurality of semiconductor elements Sua to Swb, and gate signal output terminals 31ua, 31ub, 31va, and 31x that are connected to the semiconductor elements Sua to Swb and output gate pulse signals that control the semiconductor elements Sua to Swb. The semiconductor device includes partitioning sections 101 and 102 in which the gate signal output terminals 31ua to 31wb and the reference signal output terminals 32ua to 32wb, which output reference signals, and the gate signal output terminals 31ua to 31wb and the reference signal output terminals 32ua to 32wb, which have exposed connection sections 311 and 321 with the semiconductor elements Sua to Swb, are arranged and which are stretched across an outer frame 103 and divide the space 11 into a plurality of storage sections 111u, 111v, and 111w. The partitioning section 101 has a through hole 101c in which a sealing resin 62 is formed, which connects the adjacent storage sections 111u and 111v and is continuous with the sealing resin 61u (see FIG. 2) formed in the storage section 111u and the sealing resin 61v (see FIG. 2) formed in the storage section 111v. In addition, the partition portion 102 has a through hole 102c in which a sealing resin 63 is formed, which connects adjacent storage portions 111v and 111w and is continuous with the sealing resin 61v formed in the storage portion 111v and the sealing resin 61w formed in the storage portion 111w (see Figure 2).

[0095] In the semiconductor module 1 according to the present embodiment, by forming the sealing resin 62 integral with the sealing resins 61u, 61v in the multiple through holes 101c formed in the partition portion 101, the partition portion 101 can maintain a close contact state with the sealing resins 61u, 61v due to the strength of the base material of the sealing resin 62 in addition to the adhesion between the partition portion 101 and the sealing resins 61u, 61v. Similarly, by forming the sealing resin 63 integral with the sealing resins 61v, 61w in the multiple through holes 102c in the partition portion 102, the semiconductor module 1 can maintain a close contact state between the partition portion 102 and the sealing resins 61v, 61w due to the strength of the base material of the sealing resin 63 in addition to the adhesion between the partition portion 101 and the sealing resins 61v, 61w. Therefore, the semiconductor module 1 can maintain the sealing resins 61u, 61v in close contact with the partition 101 and the sealing resins 61v, 61w in close contact with the partition 102 by a stronger adhesion force than when the semiconductor module 1 does not have the through holes 101c, 102c. This can prevent the sealing resins 61u, 61v from peeling off on the side where the connection parts 311 of the gate signal output terminals 31ua, 31ub, 31va, 31vb used for connection with the semiconductor elements Sua, Sub, Sva, Svb and the connection parts 321 of the reference signal output terminals 32ua, 32ub, 32va, 32vb are arranged. As a result, the semiconductor module 1 can prevent the occurrence of open defects caused by disconnection of the wires 150 at the connection parts 311, 321.

[0096] As described above, the method for manufacturing the semiconductor module 1 according to the present embodiment forms the first members 101a and 102a in which the gate signal output terminals 31ua, 31ub, 31va, and 31vb that are connected to the semiconductor elements Sua, Sub, Sva, and Svb and output gate pulse signals that control the semiconductor elements Sua, Sub, Sva, and Svb and the reference signal output terminals 32ua, 32ub, 32va, and 32vb that output reference signals are arranged, and a wiring conductor 102b is formed through the first member 101a. A through hole 101c that passes through the first member 102a and a through hole 102c that passes through the first member 102a are formed, the first members 101a, 102a are placed in an injection molding die, and resin is poured into the injection molding die to form an outer frame 103 that defines a space 11 in which the semiconductor elements Sua, Sub, Sva, and Svb are arranged, and partition sections 101, 102 that are formed integrally with the outer frame 103 and that, together with the first members 101a, 102a, divide the space 11 into a plurality of storage sections 111u, 111v, and 111w.

[0097] According to the manufacturing method of the semiconductor module 1 of the present embodiment, the case 10 including the partitions 101, 102 having the through holes 101c, 102c can be formed by insert molding using an injection molding die. This makes it possible to prevent the manufactured semiconductor module 1 from having an open defect caused by disconnection of the wire 150 at the connection parts 311, 321.

[0098] The present invention is not limited to the above-described embodiment, and various modifications are possible. In the above embodiment, six through holes 101c are provided in the partition portion 101, and six through holes 102c are provided in the partition portion 102, but the present invention is not limited to this. One through hole 101c, a plurality of through holes 102c other than six may be formed in the partition portions 101, 102, respectively. Furthermore, the respective numbers of through holes 101c and through holes 102c may be the same number or different numbers.

[0099] In the above embodiment, the multiple through holes 101c are formed at approximately the same height (i.e., approximately in a straight line), and the multiple through holes 102c are formed at approximately the same height (i.e., approximately in a straight line), but the present invention is not limited to this. The multiple through holes 101c may be formed at different heights in the partition portion 101. Similarly, the multiple through holes 102c may be formed at different heights in the partition portion 102.

[0100] In the above embodiment, through hole 101c is formed in partition portion 101 with an incline, but the openings opening to the connection portion side and the back surface side of partition portion 101 may have the same height and the through hole 101c may be formed in partition portion 101 without an incline. Similarly, through hole 102c may be formed in partition portion 102 with the openings opening to the connection portion side and the back surface side of partition portion 102 having the same height and the through hole 102c may be formed in partition portion 102 without an incline.

[0101] In the method for manufacturing a semiconductor module according to the above embodiment, the first members 101a, 102a having the through holes 101c, 102c formed therein are placed in an injection molding die to form the case 10, but the present invention is not limited to this. After the case 10 is formed, the through holes 101c, 102c may be formed in predetermined positions of the partitions 101, 102 by machining using a drill or the like, thereby manufacturing the semiconductor module 1.

[0102] In the above embodiment, the transistors provided in the semiconductor element are IGBTs, but they may be MOSs. The material of the semiconductor element may be silicon or a wide band gap semiconductor.

[0103] The scope of the present invention is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve the same effect as the object of the present invention. Furthermore, the scope of the present invention is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective features disclosed. [Explanation of symbols]

[0104] 1 Semiconductor module 10 Cases 11 Space 14u, 14v, 14w laminate board 15u, 15v, 15w inverter circuit 16 Cooler 21u, 21v, 21w power input terminal 31ua, 31ub, 31va, 31vb, 31wa, 31wb Gate signal output terminal 32ua,32ub,32va,32vb,32wa,32wb Reference signal output terminal 41 Positive electrode pattern 42 Negative electrode pattern 43 Output section pattern 61u,61v,61w Sealing resin 81u, 81v, 81w power output terminal 101,102 Partition 101a, 102a First member 101a1,102a1 base 101a2,102a2 wall 101b, 102b Second member 101c,102c through hole 103 Outer Frame 103a Terminal placement area 111u, 111v, 111w storage section 141 Insulating Substrate 142 Heat transfer materials 150 Wire 161 Adhesive 211 Positive terminal 212 Negative terminal 311,321 Connection 312,322 Input section Sua, Sub, Sva, Svb, Swa, Swb Semiconductor elements

Claims

1. an outer frame defining a space in which a plurality of semiconductor elements are arranged; a sealing resin formed in the space to cover the semiconductor elements; a control terminal connected to the semiconductor element and outputting a control signal for controlling the semiconductor element; a partition section in which the control terminal is arranged with the connection section with the semiconductor element exposed and which is stretched across the outer frame to partition the space into a plurality of regions; Equipped with The partition portion has a through hole in which a sealing resin is formed that connects the adjacent regions and is continuous with the sealing resin formed in the adjacent regions. Semiconductor module.

2. The through hole is inclined so that the opening on the side where the connection portion is disposed is higher than the opening on the side where the connection portion is not disposed. The semiconductor module according to claim 1 .

3. The through hole is formed in the partition portion so as to avoid the control terminal. The semiconductor module according to claim 1 .

4. The partition portion has a plurality of the through holes. The semiconductor module according to claim 1 .

5. The partition portion has a first member in which the through hole is formed and which is separate from the outer frame, and a second member in which the through hole is not formed and which is integrated with the outer frame. The semiconductor module according to claim 1 .

6. The through hole has a diameter of 1 mm or more and 3 mm or less. The semiconductor module according to claim 1 .

7. the semiconductor element and the control terminal are connected by wire bonding; The connection portion is a joint between the semiconductor element and a wire. The semiconductor module according to claim 1 .

8. forming a first member in which a control terminal is disposed, the control terminal being connected to a semiconductor element and outputting a control signal for controlling the semiconductor element; forming a through hole penetrating the first member; The first member is placed in a predetermined mold; A resin is poured into the mold to form an outer frame that defines a space in which the semiconductor element is disposed, and a partition portion that is formed integrally with the outer frame and that, together with the first member, divides the space into a plurality of regions. A method for manufacturing a semiconductor module.

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