Semiconductor Device

Abstract

The semiconductor device (1) comprises a rectangular semiconductor chip (2) whose long sides extend in a first direction and whose short sides extend in a second direction. The semiconductor chip (2) comprises a first vertical MOS transistor (10) having a first gate pad (119) and a plurality of first source pads (111), and a second vertical MOS transistor (20) having a second gate pad (129) and a plurality of second source pads (121). On an upper surface of the semiconductor chip (2), a plurality of first row-shaped arrangement regions (71) in which the source pads are arranged linearly in the first direction, and a plurality of second row-shaped arrangement regions (72) in which the source pads are arranged linearly in the second direction are formed. The semiconductor device (1) further comprises a plurality of ball-shaped bump electrodes (3) connected to the first gate pad (119), the plurality of first source pads (111), the second gate pad (129), and the plurality of second source pads (121), respectively.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices have been known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-005732 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increase in cases where a semiconductor chip is mounted on a mounting substrate and an underfill material is filled between the semiconductor chip and the mounting substrate.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor device including a semiconductor chip, which is suitable for filling an underfill material between the semiconductor chip and the mounting substrate after the semiconductor device is mounted on the mounting substrate. [Means for solving the problem]

[0006] A semiconductor device according to an aspect of the present disclosure is a chip-size package type semiconductor device capable of face-down mounting, the semiconductor device comprising a rectangular semiconductor chip having a long side extending in a first direction and a short side extending in a second direction in a plan view of the semiconductor device, the semiconductor chip comprising a semiconductor layer having a semiconductor substrate, a first vertical MOS transistor formed in the semiconductor layer in a first region that is one of two regions that divide the semiconductor chip in area in half in the plan view, and a second vertical MOS transistor formed in the semiconductor layer in a second region that is the other of the two regions. the semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, a boundary between the first region and the second region is a line segment extending in the second direction, the first vertical MOS transistor comprises a first gate pad and a plurality of first source pads on an upper surface of the semiconductor chip in the first region, the second vertical MOS transistor comprises a second gate pad and a plurality of second source pads on an upper surface of the semiconductor chip in the second region, and the plane In the plan view, the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads are circular with a diameter of less than 378 [μm], and the upper surface of the semiconductor chip is provided with a plurality of first linear arrangement regions in which, in the plan view, 4 to 2nx source pads of the plurality of first source pads and the plurality of second source pads are linearly arranged with their centers aligned in the first direction, and a plurality of second row-arrangement regions are arranged in which an upper ny number or less of source pads are arranged with their centers aligned linearly in the second direction, and in the plan view, a width of each of the plurality of first row-arrangement regions is equal to a maximum diameter among diameters of the 4 to 2nx number of source pads arranged in the first row-arrangement region, a width of each of the plurality of second row-arrangement regions is equal to a maximum diameter among diameters of the 2 to ny number of source pads arranged in the second row-arrangement region, and in the plan view, a length of the long side is Lx [μm],When the length of the short side is Ly [μm] and the maximum diameter of the diameters of the plurality of first source pads and the plurality of second source pads is rs [μm], nx is a maximum integer of 2 or more that satisfies the relationship of nx<1 / 3×(Lx / rs-3), ny is a maximum integer of 2 or more that satisfies the relationship of ny<2 / 3×(Ly / rs-1), in the plan view, the closest distance between the plurality of first source pads and the plurality of second source pads and the closest distance between the plurality of second line-arrangement regions is rs / 2 [μm] or more, the diameter of the first gate pad and the diameter of the second gate pad are rs [μm], the first gate pad is disposed, in the plan view, farther from the boundary line than a second line-arrangement region among the plurality of second line-arrangement regions that is closest to the boundary line in the first region, the second gate pad is disposed, in the plan view, farther from the boundary line than a second line-arrangement region among the plurality of second line-arrangement regions that is closest to the boundary line in the second region, and the semiconductor device further includes a plurality of ball-shaped bump electrodes that are connected in one-to-one contact with the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads at positions directly above each of them. Effect of the Invention

[0007] According to one aspect of the present disclosure, a semiconductor device is provided that is suitable for filling an underfill material between a semiconductor chip and a mounting substrate after the semiconductor device is mounted on the mounting substrate. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view showing an example of a structure of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of a state in which the semiconductor device according to the embodiment is mounted on the mounting board according to the embodiment. [Diagram 3]FIG. 3 is a plan view illustrating an example of a structure of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment. [Diagram 5] FIG. 5 is a plan view of a typical example of a semiconductor chip according to an embodiment. [Figure 6] FIG. 6 is a schematic diagram showing the relationship between the diameter of the pad according to the embodiment and the height of the ball-shaped bump electrode after the heat treatment according to the embodiment. [Figure 7A] FIG. 7A is a plan view showing an example of a positional relationship between a first gate pad and a plurality of first source pads, and an example of a positional relationship between a second gate pad and a plurality of second source pads according to an embodiment. [Figure 7B] FIG. 7B is a plan view showing an example of a positional relationship between a first gate pad and a plurality of first source pads and an example of a positional relationship between a second gate pad and a plurality of second source pads in the embodiment. [Figure 8] FIG. 8 is a plan view showing the maximum adjacent distance between source pads in the second columnar arrangement region according to the embodiment. [Figure 9A] FIG. 9A is a cross-sectional view showing an example of a cross section of a ball-shaped bump electrode after heat treatment according to an embodiment. [Figure 9B] FIG. 9B is a cross-sectional view showing an example of a cross section of a ball-shaped bump electrode after heat treatment according to an embodiment. [Figure 10] FIG. 10 is a table showing the relationship between the diameter of the pad, the height of the ball-shaped bump electrode after heat treatment, and the diameter of the ball-shaped bump electrode before heat treatment according to the embodiment. [Figure 11A] FIG. 11A is a line graph illustrating the relationship between the diameter of the source pad and the number of source pads that can be arranged in the second row arrangement region according to an embodiment. [Figure 11B] FIG. 11B is a line graph showing the relationship between the diameter of the source pad and the occupancy rate of the total area of ​​the source pad with respect to the area of ​​the top surface of the semiconductor chip according to the embodiment. [Figure 12]FIG. 12 is a plan view showing another example of the structure of the semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a plan view showing another example of the structure of the semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a plan view showing another example of the structure of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] (How one aspect of the present disclosure was achieved) 2. Description of the Related Art Conventionally, a semiconductor chip made of vertical MOS transistors in a dual configuration sharing a drain is known, which is used for the purpose of overcharge protection and / or overdischarge protection of a lithium-ion battery.

[0010] A relatively large current flows through such a semiconductor chip, and therefore it is desirable to reduce the resistance of the current path of the current flowing through the semiconductor chip and to improve the heat dissipation of the semiconductor chip.

[0011] On the other hand, as described above, in recent years, there has been an increasing number of cases in which an underfill material is filled between a semiconductor chip and a mounting substrate after the semiconductor chip is mounted on the mounting substrate.

[0012] In order to properly fill the gap between the semiconductor chip and the mounting substrate with underfill material, it is effective to provide ball-shaped bump electrodes on the mounting surface of the semiconductor chip.

[0013] However, if the interval between the ball-shaped bump electrodes is widened in order to increase the permeability of the underfill material, the resistance of the current path of the current flowing through the semiconductor chip increases and the heat dissipation of the semiconductor chip decreases. Conversely, if the interval between the ball-shaped bump electrodes is narrowed in order to reduce the resistance of the current path of the current flowing through the semiconductor chip and / or to improve the heat dissipation of the semiconductor chip, the permeability of the underfill material decreases.

[0014] Therefore, the inventors conducted intensive experiments and research to develop a semiconductor device that can increase the penetration of an underfill material after a semiconductor chip consisting of a dual-configuration vertical MOS transistor sharing a drain is mounted on a mounting substrate, while suppressing an increase in resistance of the current path of the current flowing through the semiconductor chip, and suppressing a decrease in the heat dissipation properties of the semiconductor chip.

[0015] As a result, the inventors have come up with the semiconductor device according to the present disclosure described below.

[0016] A semiconductor device according to an aspect of the present disclosure is a chip-size package type semiconductor device capable of face-down mounting, the semiconductor device comprising a rectangular semiconductor chip having a long side extending in a first direction and a short side extending in a second direction in a plan view of the semiconductor device, the semiconductor chip comprising a semiconductor layer having a semiconductor substrate, a first vertical MOS transistor formed in the semiconductor layer in a first region that is one of two regions that divide the semiconductor chip in area in half in the plan view, and a second vertical MOS transistor formed in the semiconductor layer in a second region that is the other of the two regions. the semiconductor substrate functions as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, a boundary between the first region and the second region is a line segment extending in the second direction, the first vertical MOS transistor comprises a first gate pad and a plurality of first source pads on an upper surface of the semiconductor chip in the first region, the second vertical MOS transistor comprises a second gate pad and a plurality of second source pads on an upper surface of the semiconductor chip in the second region, and the plane In the plan view, the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads are circular with a diameter of less than 378 [μm], and the upper surface of the semiconductor chip is provided with a plurality of first linear arrangement regions in which, in the plan view, 4 to 2nx source pads of the plurality of first source pads and the plurality of second source pads are linearly arranged with their centers aligned in the first direction, and a plurality of second row-arrangement regions are arranged in which an upper ny number or less of source pads are arranged with their centers aligned linearly in the second direction, and in the plan view, a width of each of the plurality of first row-arrangement regions is equal to a maximum diameter among diameters of the 4 to 2nx number of source pads arranged in the first row-arrangement region, a width of each of the plurality of second row-arrangement regions is equal to a maximum diameter among diameters of the 2 to ny number of source pads arranged in the second row-arrangement region, and in the plan view, a length of the long side is Lx [μm],When the length of the short side is Ly [μm] and the maximum diameter of the diameters of the plurality of first source pads and the plurality of second source pads is rs [μm], nx is a maximum integer of 2 or more that satisfies the relationship of nx<1 / 3×(Lx / rs-3), ny is a maximum integer of 2 or more that satisfies the relationship of ny<2 / 3×(Ly / rs-1), in the plan view, the closest distance between the plurality of first source pads and the plurality of second source pads and the closest distance between the plurality of second line-arrangement regions is rs / 2 [μm] or more, the diameter of the first gate pad and the diameter of the second gate pad are rs [μm], the first gate pad is disposed, in the plan view, farther from the boundary line than a second line-arrangement region among the plurality of second line-arrangement regions that is closest to the boundary line in the first region, the second gate pad is disposed, in the plan view, farther from the boundary line than a second line-arrangement region among the plurality of second line-arrangement regions that is closest to the boundary line in the second region, and the semiconductor device further includes a plurality of ball-shaped bump electrodes that are connected in one-to-one contact with the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads at positions directly above each of them.

[0017] According to the semiconductor device having the above configuration, when the semiconductor device is mounted face-down on the mounting substrate, straight gaps extending in the second direction are secured between the semiconductor chip and the mounting substrate, which allows an underfill material to be poured between the semiconductor chip and the mounting substrate through the straight gaps.

[0018] In addition, it is generally known that when a semiconductor device having a rectangular semiconductor chip is mounted face-down on a mounting substrate by reflow, the heat generated during reflow can cause the semiconductor chip to bend in a direction away from the mounting substrate at its center along a first direction, which is the direction of the long side of the semiconductor chip.

[0019] In contrast, in the semiconductor device having the above configuration, the straight gap that is ensured extends in a second direction perpendicular to the first direction. Ba When mounting the semiconductor device on a mounting substrate, even if the semiconductor chip is curved in a direction such that the central portion thereof is away from the mounting substrate along a first direction, underfill material can be poured between the semiconductor chip and the mounting substrate through a straight gap extending in a second direction perpendicular to the first direction.

[0020] Therefore, according to the semiconductor device having the above configuration, when the semiconductor device is mounted on a mounting substrate, it is possible to enhance the penetration of the underfill material regardless of whether the semiconductor chip is curved or not.

[0021] Furthermore, according to the semiconductor device having the above configuration, a relatively large number of ball-shaped bump electrodes can be provided directly above the first source pads and the second source pads.

[0022] Therefore, with the semiconductor device having the above configuration, after the semiconductor device is mounted on a mounting board, it is possible to suppress an increase in resistance of the current path of the current flowing through the semiconductor chip, and to suppress a decrease in the heat dissipation properties of the semiconductor chip.

[0023] Thus, with the semiconductor device having the above configuration, it is possible to enhance the penetration of the underfill material after mounting the semiconductor device on a mounting substrate, while suppressing an increase in resistance of the current path of the current flowing through the semiconductor chip, and suppress a decrease in the heat dissipation properties of the semiconductor chip.

[0024] Therefore, the semiconductor device having the above configuration is suitable for filling the gap between the semiconductor chip and the mounting substrate with an underfill material after the semiconductor device is mounted on the mounting substrate.

[0025] In addition, in the plan view, a closest distance between the plurality of first line-arrangement regions may be rs / 2 [μm] or more.

[0026] With this, in a state in which the semiconductor device is mounted face-down on the mounting board, a straight gap extending in the first direction is further ensured between the semiconductor chip and the mounting board.

[0027] Therefore, after the semiconductor device is mounted on the mounting board, the penetration of the underfill material can be further improved.

[0028] Moreover, in the plan view, the plurality of first source pads and the plurality of second source pads may have a diameter of rs [μm].

[0029] This makes it possible, in a state in which the semiconductor device is mounted face-down on a mounting board, to further prevent the current path of the current flowing through the semiconductor chip from becoming high in resistance, and to prevent a decrease in the heat dissipation properties of the semiconductor chip.

[0030] Furthermore, in the planar view, in each of the plurality of first row-arrangement regions, the diameters of the 4 to 2nx source pads arranged in the first row-arrangement region may monotonically decrease in a direction from the source pad farthest from the boundary line to the nearest source pad in the first region, and may monotonically decrease in a direction from the source pad farthest from the boundary line to the nearest source pad in the second region.

[0031] Generally, when a ball-shaped bump electrode is placed on a circular pad and a heat treatment is performed to bond the ball-shaped bump electrode and the circular pad, the height of the ball-shaped bump electrode from the surface of the semiconductor chip after the heat treatment increases as the diameter of the circular pad decreases.

[0032] Therefore, in a semiconductor device having the above configuration, when the semiconductor chip is curved in a direction such that its central portion moves away from the mounting substrate along a first direction when the semiconductor chip is mounted on a mounting substrate, if a direction perpendicular to the first direction and the second direction is defined as a third direction, the positions of the highest points in the third direction of the ball-shaped bump electrodes located directly above each of the source pads in each of the first row-shaped arrangement regions can be relatively aligned.

[0033] Furthermore, in the planar view, in each of the plurality of first row-arrangement regions, the nearest distance of the 4 to 2nx source pads arranged in the first row-arrangement region may monotonically increase in the first region in a direction from the source pad farthest from the boundary line to the nearest source pad, and may monotonically increase in the second region in a direction from the source pad farthest from the boundary line to the nearest source pad.

[0034] As described above, in general, when a ball-shaped bump electrode is placed on a circular pad and a heat treatment is performed to bond the ball-shaped bump electrode and the circular pad, the height of the ball-shaped bump electrode from the semiconductor chip surface after the heat treatment increases as the diameter of the circular pad decreases. Also, when the distance between the centers of the circular pads is the same, the closest distance of the circular pads increases as the diameter of the circular pads decreases. In other words, in this case, it can be said that the height of the ball-shaped bump electrode from the semiconductor chip surface increases as the closest distance of the pads increases.

[0035] Therefore, in a semiconductor device having the above configuration, when the semiconductor chip is curved in a direction such that its central portion moves away from the mounting substrate along a first direction when the semiconductor chip is mounted on a mounting substrate, if a direction perpendicular to the first direction and the second direction is defined as a third direction, the positions of the highest points in the third direction of the ball-shaped bump electrodes located directly above each of the source pads in each of the first row-shaped arrangement regions can be relatively aligned.

[0036] In addition, in the planar view, in each of the second row-arrangement regions that are closest to each other across the boundary line among the multiple second row-arrangement regions, the diameter of the 2 to ny source pads may be equal to the smallest diameter among the diameters of the multiple first source pads and the multiple second source pads.

[0037] As described above, generally, when a ball-shaped bump electrode is placed on a circular pad and a heat treatment is performed to bond the ball-shaped bump electrode and the circular pad, the height of the ball-shaped bump electrode from the surface of the semiconductor chip after the heat treatment increases as the diameter of the circular pad decreases.

[0038] Therefore, in a semiconductor device having the above configuration, when the semiconductor chip is curved in a direction such that its central portion moves away from the mounting substrate along a first direction when the semiconductor chip is mounted on a mounting substrate, if a direction perpendicular to the first direction and the second direction is defined as a third direction, the positions of the highest points in the third direction of the ball-shaped bump electrodes located directly above each of the source pads in each of the first row-shaped arrangement regions can be relatively aligned.

[0039] Furthermore, in the planar view, in each of the multiple first row-arrangement regions, the height from the top surface of the semiconductor chip of a ball-type bump electrode among the multiple ball-type bump electrodes located directly above each of the 4 to 2nx source pads arranged in the first row-arrangement region may monotonically increase in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the first region, and may monotonically increase in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the second region.

[0040] As a result, when mounting the semiconductor device on a mounting substrate, if the semiconductor chip bends in a direction such that its central portion moves away from the mounting substrate along a first direction, and a direction perpendicular to the first and second directions is defined as a third direction, the positions of the highest points in the third direction of the ball-shaped bump electrodes located directly above each of the source pads in each of the first row-shaped arrangement regions can be relatively aligned.

[0041] Furthermore, in the planar view, in each of the multiple first row-arrangement regions, the surface area of ​​a ball-type bump electrode among the multiple ball-type bump electrodes located directly above each of the 4 to 2nx source pads arranged in the first row-arrangement region may monotonically increase in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the first region, and may monotonically increase in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the second region.

[0042] As described above, generally, when a ball-shaped bump electrode is placed on a circular pad and a heat treatment is performed to bond the ball-shaped bump electrode and the circular pad, the height of the ball-shaped bump electrode from the semiconductor chip surface after the heat treatment increases as the diameter of the circular pad decreases. Also, generally, the higher the height of the ball-shaped bump electrode from the semiconductor chip surface, the larger its surface area becomes. In other words, it can be said that the larger the surface area of ​​the ball-shaped bump electrode, the higher the height from the semiconductor chip surface.

[0043] Therefore, in a semiconductor device having the above configuration, when the semiconductor chip is curved in a direction such that its central portion moves away from the mounting substrate along a first direction when the semiconductor chip is mounted on a mounting substrate, if a direction perpendicular to the first direction and the second direction is defined as a third direction, the positions of the highest points in the third direction of the ball-shaped bump electrodes located directly above each of the source pads in each of the first row-shaped arrangement regions can be relatively aligned.

[0044] In addition, in the planar view, the number of source pads may be ny in each of the second row-arrangement regions that are closest to each other across the boundary line among the plurality of second row-arrangement regions.

[0045] In a semiconductor device having the above-mentioned configuration, among the current paths of the current flowing in the semiconductor chip, the current path of the current flowing in the semiconductor chip via the source pad arranged in the second row-like arrangement region that is closest to and opposed to the second row-like arrangement region across the boundary line among the multiple second row-like arrangement regions is the shortest within the semiconductor chip.

[0046] Therefore, as in the above configuration, by setting the number of source pads arranged in the second row-arrangement region that is closest to and faces the boundary line among the multiple second row-arrangement regions to ny, which is the maximum number among 2 to ny, it is possible to suppress the increase in resistance of the current path of the current flowing through the semiconductor chip after the semiconductor device is mounted on a mounting substrate.

[0047] In addition, in the plan view, the distance between the first gate pad and a first source pad among the plurality of first source pads that is closest to the first gate pad is rs [μm] or more, and is greater than the closest distance of the plurality of first source pads, and the distance between the second gate pad and the second source pad closest to the second gate pad among the plurality of second source pads is rs [μm] The distance may be equal to or greater than the closest distance between the plurality of second source pads.

[0048] This makes it possible to suppress a short circuit between the first gate pad and any of the plurality of first source pads, and a short circuit between the second gate pad and any of the plurality of second source pads.

[0049] In addition, in the plan view, an adjacent longest distance, which is a longest distance among distances between adjacent source pads among the 2 to ny source pads in each of the plurality of second row-arrangement regions, monotonically decreases in the first region in a direction from a second row-arrangement region farthest from the boundary line among the plurality of second row-arrangement regions toward a nearest second row-arrangement region, and monotonically decreases in the second region in a direction from a second row-arrangement region farthest from the boundary line among the plurality of second row-arrangement regions toward a nearest second row-arrangement region, and The number of the four or more and 2nx or less source pads in each of the plurality of first row-arrangement regions may be configured to monotonically decrease in a direction from the first row-arrangement region closest to the one long side to the farthest first row-arrangement region for two or more first row-arrangement regions in which the distance to one of the long sides is shorter than the distance to the other long side, and (2) to monotonically decrease in a direction from the first row-arrangement region closest to the other long side to the farthest first row-arrangement region for two or more first row-arrangement regions in which the distance to the other long side is shorter than the distance to the one long side.

[0050] Furthermore, in the planar view, the positions in the second direction of each of the 4 to 2nx source pads in one first row arrangement region of adjacent first row arrangement regions among the multiple first row arrangement regions may not coincide with the positions in the second direction of any of the 4 to 2nx source pads in the other first row arrangement region of the adjacent first row arrangement regions.

[0051] Alternatively, rs may be set to be 196 or more and 226 or less, or 250 or more and 280 or less.

[0052] Furthermore, in the planar view, in each of the multiple first row-arrangement regions, of the 4 to 2nx source pads arranged in the first row-arrangement region, the diameter of the source pad farthest from the boundary line in the first region and the diameter of the source pad farthest from the boundary line in the second region may be 250 μm or more and 280 μm or less, and the diameter of the source pad closest to the boundary line in the first region and the diameter of the source pad closest to the boundary line in the second region may be 196 μm or more and 226 μm or less.

[0053] In addition, rs may be greater than 150, the height of the multiple ball-shaped bump electrodes from the top surface of the semiconductor chip may be greater than or equal to 70 μm and less than or equal to 130 μm, and the cross-sectional area of ​​the multiple ball-shaped bump electrodes in a plane parallel to the top surface of the semiconductor chip may monotonically decrease from the side closer to the top surface of the semiconductor chip to the side farther away from the top surface of the semiconductor chip.

[0054] Hereinafter, a specific example of a semiconductor device according to one aspect of the present disclosure will be described with reference to the drawings. Each embodiment shown here shows one specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangement and connection of the components, steps (processes) and the order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and is not necessarily a precise illustration. In each figure, the same reference numerals are given to substantially the same configurations, and duplicated explanations are omitted or simplified.

[0055] In this disclosure, the distance between a first element and a second element refers to the shortest distance between any point on the circumference of the first element and any point on the circumference of the second element.

[0056] In addition, in the present disclosure, the closest distance between multiple elements refers to the shortest distance between the two elements in each combination of all two elements among the multiple elements.

[0057] In addition, in the present disclosure, monotonically changing means being a monotonically increasing function in a broad sense or a monotonically decreasing function in a broad sense. That is, a monotonically increasing function in a broad sense refers to a function f(x) such that f(x1) ≤ f(x2) when x1 < x2, and a monotonically decreasing function in a broad sense refers to a function f(x) such that f(x1) ≥ f(x2) when x1 < x2.

[0058] (Embodiment) <Structure of Semiconductor Device> Hereinafter, the structure of the semiconductor device according to the embodiment will be described. The semiconductor device according to the embodiment is a semiconductor device including a semiconductor chip of a dual configuration in which two vertical MOS (Metal Oxide Semiconductor) transistors sharing a drain are formed, and a plurality of ball-shaped bump electrodes. The two vertical MOS transistors are, for example, so-called trench MOS transistors. Here, the two vertical MOS transistors will be described assuming that they are so-called trench MOS transistors.

[0059] FIG. 1 is a perspective view showing an example of the structure of a semiconductor device 1 according to the embodiment. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor chip 2 and a plurality of ball-shaped bump electrodes 3 disposed on the upper surface of the semiconductor chip 2.

[0060] More specifically, the semiconductor device 1 includes a plurality of ball-shaped bump electrodes 3 that are in one-to-one contact and connected, that is, joined, at positions directly above the first gate pad 119 to be described later, the plurality of first source pads 111 to be described later, the second gate pad 129 to be described later, and the plurality of second source pads 121 to be described later, respectively, on the upper surface of the semiconductor chip 2.

[0061] The plurality of ball-shaped bump electrodes 3 are formed, for example, by heat-treating a solder ball material.

[0062] 2 is a cross-sectional view showing a schematic example of a state in which the semiconductor device 1 is mounted on a mounting substrate 500. As shown in FIG.

[0063] 2, the semiconductor device 1 is provided with a plurality of ball-shaped bump electrodes 3 on the upper surface of the semiconductor chip 2, so that a gap is secured between the semiconductor chip 2 and the mounting substrate 500 when the semiconductor device 1 is mounted on the mounting substrate 500. Therefore, when the semiconductor device 1 is mounted on the mounting substrate 500, an underfill material can be allowed to permeate between the semiconductor chip 2 and the mounting substrate 500.

[0064] Fig. 3 is a plan view showing an example of the structure of the semiconductor device 1. However, Fig. 3 omits illustration of a plurality of ball-shaped bump electrodes 3. Therefore, Fig. 3 is also a plan view of the semiconductor chip 2.

[0065] As shown in Figure 3, when viewed in a plan view of the semiconductor device 1, i.e., when viewed in a plan view of the semiconductor chip 2, the semiconductor chip 2 is a rectangle whose long side extends in a first direction (the X-axis direction in Figure 3) and whose short side extends in a second direction (the Y-axis direction in Figure 3).

[0066] 4 is a cross-sectional view showing an example of the structure of the semiconductor device 1. FIG 4 shows a cross section taken along line II in FIG 3.

[0067] As shown in Figures 3 and 4, the semiconductor chip 2 includes a metal layer 30, a semiconductor layer 40, an oxide film 34, a protective film 35, a first vertical MOS transistor 10 formed in the semiconductor layer 40 in a first region A1 which is one half of the area of ​​the semiconductor chip 2 when viewed in a plane, and a second vertical MOS transistor 20 formed in the semiconductor layer 40 in a second region A2 which is the other half.

[0068] Here, in a plan view of the semiconductor device 1, a boundary line 90 between the first region A1 and the second region A2 is a line segment extending in the second direction (the Y-axis direction in FIG. 3).

[0069] The boundary line 90 may be regarded as an imaginary line that traces the center position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Although the width of the boundary line 90 is finite, the boundary line 90 may be regarded as the interval itself. Even in the case of the interval, the boundary line 90 can be recognized as a line by the naked eye or when viewed at low magnification.

[0070] Also, here, the first vertical MOS transistor 10 has, in the first region A1, a first source electrode 11 and a first gate electrode 19 (not shown in FIGS. 3 and 4 but shown in FIG. 5 to be described later), and the second vertical MOS transistor 20 has, in the second region A2, a second source electrode 21 and a second gate electrode 29 (not shown in FIGS. 3 and 4 but shown in FIG. 5 to be described later).

[0071] Also, here, the first vertical MOS transistor 10 has a first gate pad 119 and a plurality of first source pads 111 on the upper surface of the semiconductor chip 2 in the first region A1, and the second vertical MOS transistor 20 has a second gate pad 129 and a plurality of second source pads 121 on the upper surface of the semiconductor chip 2 in the second region A2.

[0072] In addition, here, in a plan view of the semiconductor device 1, the first gate pad 119, the multiple first source pads 111, the second gate pad 129, and the multiple second source pads 121 are circular with a diameter of less than 378 μm.

[0073] In this disclosure, the semiconductor chip 2 is described as including the metal layer 30 , but the semiconductor chip 2 is not necessarily limited to a configuration including the metal layer 30 .

[0074] The semiconductor layer 40 is configured by laminating a semiconductor substrate 32 and a low concentration impurity layer 33 .

[0075] The semiconductor substrate 32 is disposed on the lower surface side of the semiconductor layer 40, and is made of silicon containing impurities of the first conductivity type.

[0076] The low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and contains a first-conductivity-type impurity at a concentration lower than the concentration of the first-conductivity-type impurity in the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0077] The oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low concentration impurity layer 33 .

[0078] The protective film 35 is a protective film that covers the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20, and has a plurality of openings.

[0079] Here, the protective film 35 covering the top surface of the first vertical MOS transistor 10 and the top surface of the second vertical MOS transistor 20 means that the protective film 35 is formed on almost the entire surface of the semiconductor chip 2 except for the openings when viewed from above in the semiconductor layer 40. Here, almost the entire surface of the semiconductor chip 2 means the entire surface of the semiconductor chip 2 except for the small peripheral regions remaining on the four sides of the semiconductor chip 2 after dicing, among the regions of the wafer reserved as dicing margins when dicing the semiconductor chip 2 from the wafer. For this reason, in this peripheral region, the oxide film 34 is exceptionally exposed on the top surface of the semiconductor chip 2.

[0080] Moreover, the opening in protective film 35 in the present disclosure refers to a shape in which the entire circumference of the opening is closed by protective film 35 in a plan view of semiconductor device 1. For this reason, a shape in which a part of the circumference of the opening overlaps with the exceptional outer periphery region where oxide film 34 is exposed on the upper surface of semiconductor chip 2 in a plan view of semiconductor device 1 does not correspond to the opening in protective film 35 in the present disclosure.

[0081] The metal layer 30 is formed in contact with the lower surface of the semiconductor substrate 32, and may be made of silver, copper, nickel, or an alloy thereof, or may be made of a metal material with good conductivity that can function as an electrode. Note that the metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material.

[0082] A first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the low concentration impurity layer 33 of the first region A1. A first gate conductor 15, a first gate insulating film 16, and a first source region 14 containing impurities of the first conductivity type are formed in the first body region 18.

[0083] The first source electrode 11 is composed of a portion 12 and a portion 13 , and the portion 12 is connected via the portion 13 to a first source region 14 and a first body region 18 .

[0084] The first gate conductor 15 is electrically connected to a first gate electrode 19 (not shown in Figures 3 and 4, but shown in Figure 5, which will be described later) via a first gate wiring 61 (not shown in Figures 3 and 4, but shown in Figure 5, which will be described later).

[0085] Portion 12 is a layer that is in contact with and connected to ball-shaped bump electrode 3, i.e., bonded to ball-shaped bump electrode 3, and may be made of a metal material including, by way of non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The upper surface of portion 12 may be plated with gold or the like.

[0086] The upper surface of portion 12 has a plurality of exposed portions that are exposed to the upper surface of semiconductor chip 2 through each of the plurality of openings in protective film 35. Each of these exposed portions corresponds to a plurality of first source pads 111. That is, each of the plurality of first source pads 111 is a corresponding one of the plurality of exposed portions of portion 12.

[0087] Portion 13 is a layer that connects portion 12 with first source region 14 and first body region 18, and may be composed of a metallic material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0088] 3 and 4, the upper surface of the first gate electrode 19 (to be shown in FIG. 5 to be described later) has an exposed portion that is exposed to the upper surface of the semiconductor chip 2 through an opening in the protective film 35. This exposed portion corresponds to the first gate pad 119. In other words, the first gate pad 119 is the exposed portion of the first gate electrode 19 (to be shown in FIG. 5 to be described later) that is not shown in FIGS.

[0089] A second body region 28 containing impurities of a second conductivity type different from the first conductivity type is formed in the low concentration impurity layer 33 of the second region A2. A second source region 24 containing impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28.

[0090] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23.

[0091] The second gate conductor 25 is electrically connected to a second gate electrode 29 (not shown in Figures 3 and 4, but shown in Figure 5, which will be described later) via a second gate wiring 62 (not shown in Figures 3 and 4, but shown in Figure 5, which will be described later).

[0092] Portion 22 is a layer that is in contact with and connected to ball-shaped bump electrode 3, i.e., that is bonded to ball-shaped bump electrode 3, and may be made of a metal material including, by way of non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The upper surface of portion 22 may be plated with gold or the like.

[0093] The upper surface of portion 22 has a plurality of exposed portions that are exposed to the upper surface of semiconductor chip 2 through each of the plurality of openings in protective film 35. Each of these exposed portions corresponds to a second source pad 121. That is, each of the second source pads 121 is a corresponding one of the exposed portions of portion 22.

[0094] Portion 23 is a layer that connects portion 22 with second source region 24 and second body region 28, and may be made of a metallic material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0095] 3 and 4, the upper surface of the second gate electrode 29 (to be shown in FIG. 5, which will be described later) has an exposed portion that is exposed to the upper surface of the semiconductor chip 2 through an opening in the protective film 35. This exposed portion corresponds to the second gate pad 129. In other words, the second gate pad 129 is the exposed portion of the second gate electrode 29 (to be shown in FIG. 5, which will be described later) that is not shown in FIGS.

[0096] With the above-described configuration of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, a part of the low-concentration impurity layer 33 and the semiconductor substrate 32 function as a common drain region that is a common region of the first drain region of the first vertical MOS transistor 10 and the second drain region of the second vertical MOS transistor 20. In other words, the semiconductor substrate 32 functions as a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0097] In the semiconductor chip 2, for example, the first conductivity type may be N type and the second conductivity type may be P type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being N-type semiconductors, and the first body region 18 and the second body region 28 being P-type semiconductors.

[0098] In addition, in the semiconductor chip 2, for example, the first conductivity type may be P type and the second conductivity type may be N type, with the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 being P-type semiconductors, and the first body region 18 and the second body region 28 being N-type semiconductors.

[0099] In this disclosure, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 will be described as so-called N-channel transistors, in which the first conductivity type is N-type and the second conductivity type is P-type.

[0100] In addition, in the present disclosure, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are described as being similar to each other. Furthermore, in the present disclosure, the structure of the first vertical MOS transistor 10 and the structure of the second vertical MOS transistor 20 are described as being in a line-symmetric relationship with respect to the boundary line 90 as the axis of symmetry in a plan view of the semiconductor device 1.

[0101] As shown in FIG. 3, on the upper surface of the semiconductor chip 2, in a plan view of the semiconductor device 1, there are arranged a plurality of first row-shaped arrangement regions 71 (corresponding to the first row-shaped arrangement region 71A to the first row-shaped arrangement region 71E in FIG. 3) in which four or more and 2nx (the definition of nx will be described later; in the example shown in FIG. 3, nx is 4) source pads out of the plurality of first source pads 111 and the plurality of second source pads 121 are arranged with their centers aligned linearly in a first direction, and a plurality of second row-shaped arrangement regions 72 (corresponding to the second row-shaped arrangement region 72A to the second row-shaped arrangement region 72H in FIG. 3) in which two or more and ny (the definition of ny will be described later; in the example shown in FIG. 3, ny is 4) source pads out of the plurality of first source pads 111 or the plurality of second source pads 121 are arranged with their centers aligned linearly in a second direction.

[0102] Here, in a planar view of the semiconductor device 1, the width of each of the multiple first row-shaped arrangement regions 71 is equal to the maximum diameter among the diameters of the source pads arranged in the first row-shaped arrangement region 71, and the width of each of the multiple second row-shaped arrangement regions 72 is equal to the maximum diameter among the diameters of the source pads arranged in the second row-shaped arrangement region 72.

[0103] In addition, here, in a planar view of the semiconductor device 1, the length of the long side of the semiconductor chip 2 is Lx [μm], the length of the short side is Ly [μm], and the maximum diameter among the diameters of the multiple first source pads 111 and the multiple second source pads 121 is rs [μm], then nx is the largest integer of 2 or more for which the relationship nx<1 / 3×(Lx / rs-3) holds, and ny is the largest integer of 2 or more for which the relationship ny<2 / 3×(Ly / rs-1) holds.

[0104] In addition, here, in a planar view of the semiconductor device 1, the closest distance between the multiple first source pads 111 and the multiple second source pads 121, and the closest distance between the multiple second row-shaped arrangement regions 72 are rs / 2 [μm] or more, and the diameter of the first gate pad 119 and the diameter of the second gate pad 129 are rs [μm].

[0105] Also, in a planar view of the semiconductor device 1, the first gate pad 119 is positioned farther from the boundary line 90 than the second row-shaped arrangement region 72 that is closest to the boundary line 90 in the first region A1, and the second gate pad 129 is positioned farther from the boundary line 90 than the second row-shaped arrangement region 72 that is closest to the boundary line 90 in the second region A2.

[0106] <Typical example of a semiconductor chip> A typical example of the semiconductor chip 2 will now be described.

[0107] Fig. 5 is a plan view of a typical example of the semiconductor chip 2. In Fig. 5, the first source electrode 11, the first gate electrode 19, the first gate wiring 61, the second source electrode 21, the second gate electrode 29, and the second gate wiring 62 are illustrated as if they could be seen from outside the semiconductor chip 2, but in reality, these components cannot be seen directly from outside the semiconductor chip 2.

[0108] 5, the semiconductor chip 2 may typically have all pads with the same diameter of 200 μm in a plan view of the semiconductor device 1. Here, the pads refer to the first gate pad 119, the multiple first source pads 111, the second gate pad 129, and the multiple second source pads 121.

[0109] Furthermore, the semiconductor chip 2 may typically have a long side of 3400 [μm] and a short side of 1960 [μm] in a plan view of the semiconductor device 1.

[0110] Furthermore, the semiconductor chip 2 may typically have five first linear arrangement regions 71 and eight second linear arrangement regions 72.

[0111] Furthermore, in a typical example, the semiconductor chip 2 may have all of the source pads arranged in any one of the multiple first row-like arrangement regions 71 and arranged in any one of the multiple second row-like arrangement regions 72. Here, the source pads refer to the multiple first source pads 111 and the multiple second source pads 121.

[0112] In addition, in a typical example, the semiconductor chip 2 may have the number of source pads arranged in each first row arrangement region 71 be greater than or equal to 4 and less than or equal to 8, and the number of source pads arranged in each second row arrangement region 72 be greater than or equal to 2 and less than or equal to 5.

[0113] In addition, the semiconductor chip 2 may typically have, in a planar view of the semiconductor device 1, a closest distance between the multiple first row-like arrangement regions 71 of 150 μm, and a closest distance between the multiple second row-like arrangement regions 72 of 150 μm.

[0114] <Consideration> The structure of the semiconductor chip 2 configured as above will be considered below with reference to FIGS.

[0115] The ball-shaped bump electrodes 3 may protrude from the outer periphery of the pad by a maximum of 1 / 4 of the pad diameter in a plan view of the semiconductor device 1 during a heat treatment process for bonding the ball-shaped bump electrodes 3 to the pads and / or during mounting on a mounting substrate. For this reason, the positioning of the pads must be determined taking into consideration this protrusion amount so that ball-shaped bump electrodes 3 located directly above adjacent pads do not come into contact with each other even when the ball-shaped bump electrodes 3 are subjected to heat treatment.

[0116] In the following, in order to avoid making the explanation more complicated than necessary, it is assumed that the diameters of all the source pads are equal, that is, the maximum diameter is rs [μm].

[0117] Even if adjacent source pads each protrude by an amount rs / 4 [μm] from the ball-shaped bump electrode 3 located directly above them, the distance between the adjacent source pads only needs to be (rs / 4)×2=rs / 2 [μm] or more to prevent the ball-shaped bump electrodes 3 from coming into contact.

[0118] If the ball-shaped bump electrodes 3 located directly above adjacent pads do not come into contact with each other, the penetration of the underfill material is not hindered.

[0119] In particular, by setting the distance between adjacent second linear arrangement regions 72 to rs / 2 [μm], straight gaps extending in the second direction are secured between the semiconductor chip 2 and the mounting substrate 500. This allows the underfill material to be poured between the semiconductor chip 2 and the mounting substrate 500 through these straight gaps.

[0120] The distance between the long side of the semiconductor chip 2 and the ball-shaped bump electrode 3 is preferably rs / 2 [μm] or more to prevent the ball-shaped bump electrode 3 from flowing out of the semiconductor chip 2 along the second direction. Furthermore, as described above, the ball-shaped bump electrode 3 may protrude from the outer periphery of the pad by up to 1 / 4 of the pad diameter in a plan view of the semiconductor device 1 during the heat treatment process for bonding the ball-shaped bump electrode 3 to the pad and / or during mounting on the mounting board, so the distance between the long side of the semiconductor chip 2 and the source pad located nearby is preferably rs / 2+rs / 4=rs×3 / 4 [μm] or more.

[0121] From these facts, it can be seen that the maximum number ny of source pads that can be arranged in the second row-shaped arrangement region 72 should be the largest integer for which the formula Ly-ny×rs≧(rs / 2)×(ny-1)+rs×(3 / 4)×2 holds.

[0122] In other words, ny may be the maximum integer for which the relationship ny<2 / 3×(Ly / rs−1) holds.

[0123] It is known that when a semiconductor device 1 having a rectangular semiconductor chip 2 is mounted face-down on a mounting substrate 500 by reflow, the heat generated during reflow can cause the semiconductor chip 2 to bend in a direction away from the mounting substrate 500 at its center along a first direction, which is the direction of the long side of the semiconductor chip 2.

[0124] For this reason, it is desirable that the distance between the short side of the semiconductor chip 2 and the ball-shaped bump electrode 3 be rs×3 / 4 [μm] or more to prevent the ball-shaped bump electrode 3 from flowing out of the semiconductor chip 2 along the first direction.

[0125] In addition, in the central part of the semiconductor chip 2, in order to prevent a short circuit between the first vertical MOS transistor 10 and the second vertical MOS transistor 20, it is desirable that the distance between the boundary line 90 and the ball-shaped bump electrode 3 be rs×3 / 4 [μm] or more.

[0126] Furthermore, as mentioned above, the ball-shaped bump electrode 3 may protrude from the outer periphery of the pad by up to 1 / 4 of the pad diameter in a planar view of the semiconductor device 1 during the heat treatment process for joining the ball-shaped bump electrode 3 to the pad and / or when mounted on a mounting substrate, so it is desirable for the distance between the short side of the semiconductor chip 2 and the source pad located in the vicinity thereof to be greater than or equal to rs × 3 / 4 + rs / 4 = rs [μm].

[0127] Similarly, the distance between the boundary line 90 and the source pad located nearby is preferably rs×3 / 4+rs / 4=rs [μm] or more.

[0128] From these facts, when considering only the range of the first vertical MOS transistor 10 in the first column-arrangement region 71, if the maximum number of source pads that can be arranged is nx, it can be seen that nx should be the maximum integer for which the equation Lx / 2-nx×rs≧(rs / 2)×(nx-1)+rs×2 holds.

[0129] The maximum number of source pads that can be arranged in the first row arrangement region 71 is twice nx, so it is apparent that the number should be twice the maximum integer nx for which the relationship nx<1 / 3×(Lx / rs−3) holds.

[0130] In a planar view of the semiconductor device 1, the region sandwiched between the two second columnar arrangement regions 72 closest to each other across the boundary line 90 is an opposing region where the first vertical MOS transistor 10 and the second vertical MOS transistor 20 face each other, and is the region where the current density is highest in the current path of the current flowing through the semiconductor chip 2.

[0131] For this reason, it is desirable to avoid placing anything that may hinder the flow of current in this facing region.

[0132] Therefore, in a planar view of the semiconductor device 1, it is desirable for the first gate pad 119 to be positioned farther from the boundary line 90 than the second row-shaped arrangement region 72 that is closest to the boundary line 90 in the first region A1, and it is desirable for the second gate pad 129 to be positioned farther from the boundary line 90 than the second row-shaped arrangement region 72 that is closest to the boundary line 90 in the second region A2.

[0133] With the semiconductor device 1 having the above configuration, when the semiconductor device 1 is mounted face-down on the mounting substrate 500, straight gaps extending in the second direction are secured between the semiconductor chip 2 and the mounting substrate 500. This allows an underfill material to be poured between the semiconductor chip 2 and the mounting substrate 500 through these straight gaps.

[0134] In addition, it is generally known that when a semiconductor device 1 having a semiconductor chip 2 that is rectangular in a planar view of the semiconductor device 1 is mounted face-down on a mounting substrate 500 by reflow, the heat generated during reflow can cause the semiconductor chip 2 to bend in a direction away from the mounting substrate 500 at its center along a first direction (the X-axis direction in FIG. 3), which is the long side direction of the semiconductor chip 2.

[0135] In contrast, in the semiconductor device 1 having the above-described configuration, the straight gap that is ensured extends in a second direction (the Y-axis direction in FIG. 3) perpendicular to the first direction. BaWhen mounting the semiconductor device 1 on the mounting substrate 500, even if the central portion of the semiconductor chip 2 is curved in a direction away from the mounting substrate 500 along the first direction, the underfill material can be poured between the semiconductor chip 2 and the mounting substrate 500 through a straight gap extending in a second direction perpendicular to the first direction.

[0136] Therefore, according to the semiconductor device 1 having the above configuration, when the semiconductor device 1 is mounted on the mounting substrate 500, it is possible to increase the penetration of the underfill material regardless of whether the semiconductor chip 2 is curved or not.

[0137] Furthermore, according to the semiconductor device 1 having the above-described configuration, a relatively large number, or as many as possible, of ball-shaped bump electrodes 3 can be provided directly above the multiple first source pads 111 and the multiple second source pads 121.

[0138] Therefore, according to the semiconductor device 1 having the above configuration, after the semiconductor device 1 is mounted on the mounting substrate 500, it is possible to suppress an increase in resistance of the current path of the current flowing through the semiconductor chip 2, and to suppress a decrease in the heat dissipation properties of the semiconductor chip 2.

[0139] Thus, with the semiconductor device 1 having the above configuration, after the semiconductor device 1 is mounted on the mounting substrate 500, the penetration of the underfill material can be increased, and the current path of the current flowing through the semiconductor chip 2 can be prevented from becoming high-resistance, thereby preventing a decrease in the heat dissipation properties of the semiconductor chip 2.

[0140] Therefore, according to the semiconductor device 1 having the above configuration, a semiconductor device is provided that is suitable for filling an underfill material between the semiconductor chip 2 and the mounting substrate 500 after the semiconductor device 1 is mounted on the mounting substrate 500.

[0141] In addition, in a plan view of the semiconductor device 1, the closest distance between the first row-like arrangement regions 71 is rs / 2 [μm]. That's all. It is also possible to use the following.

[0142] As a result, in a state in which the semiconductor device 1 is mounted face-down on the mounting substrate 500, a straight gap extending in the first direction is further ensured between the semiconductor chip 2 and the mounting substrate 500.

[0143] In addition, in a plan view of the semiconductor device 1, the diameter of the plurality of first source pads 111 and the plurality of second source pads 121 may be rs [μm].

[0144] This further prevents the current path of the current flowing through the semiconductor chip 2 from becoming high-resistance when the semiconductor device 1 is mounted face-down on the mounting substrate 500, and prevents a decrease in the heat dissipation properties of the semiconductor chip 2.

[0145] FIG. 6 is a schematic diagram showing the relationship between the diameter of the pads (first gate pad 119, multiple first source pads 111, second gate pad 129, and multiple second source pads 121 in FIG. 6) and the height of ball-shaped bump electrode 3 from the surface of semiconductor chip 2 after heat treatment in the third direction (Z-axis direction in FIG. 6), when a direction perpendicular to the first direction (X-axis direction in FIG. 6) and the second direction (Y-axis direction in FIG. 6) is defined as a third direction (Z-axis direction in FIG. 6).

[0146] Generally, the same size solder ball material is used to form the ball-shaped bump electrode 3. For this reason, when the ball-shaped bump electrode 3 is brought into contact with and connected to the top surface of the pad by heat treatment, the height of the ball-shaped bump electrode 3 from the surface of the semiconductor chip 2 increases as the diameter of the pad decreases.

[0147] Therefore, as shown in Figure 6, when the semiconductor chip 2 curves in the first direction with its central portion curved away from the mounting substrate 500, by making the pad diameter smaller the closer it is to the boundary line 90, the higher the position of the highest point in the third direction of the ball-shaped bump electrode 3 after heat treatment can be made relatively aligned.

[0148] That is, in each of the multiple first row-shaped arrangement regions 71, the diameter of the source pads arranged in the first row-shaped arrangement region 71 may monotonically decrease in the direction from the source pad farthest from the boundary line 90 to the nearest source pad in the first region A1, and may monotonically decrease in the direction from the source pad farthest from the boundary line 90 to the nearest source pad in the second region A2.

[0149] This allows the positions of the highest points in the third direction of the ball-shaped bump electrodes 3 located directly above the respective source pads in each of the first row arrangement regions 71 to be relatively uniform.

[0150] For equal distances between the centers of the source pads, the closest distance of the source pads increases as the diameter of the source pads decreases, i.e., in this case, the diameter of the source pads decreases as the closest distance of the source pads increases.

[0151] Therefore, in each of the multiple first row-shaped arrangement regions 71, the nearest distance of the source pads arranged in that first row-shaped arrangement region 71 may, in the first region A1, increase monotonically in the direction from the source pad farthest from the boundary line 90 to the nearest source pad, and in the second region A2, increase monotonically in the direction from the source pad farthest from the boundary line 90 to the nearest source pad.

[0152] This allows the positions of the highest points in the third direction of the ball-shaped bump electrodes 3 located directly above the respective source pads in each of the first row arrangement regions 71 to be relatively uniform.

[0153] In addition, in each of the second row-shaped arrangement regions 72 closest to each other across the boundary line 90, the diameter of the source pad may be equal to the smallest diameter among the diameters of the multiple first source pads 111 and the multiple second source pads 121.

[0154] This allows the positions of the highest points in the third direction of the ball-shaped bump electrodes 3 located directly above the respective source pads in each of the first row arrangement regions 71 to be relatively uniform.

[0155] Furthermore, in each of the multiple first row arrangement regions 71, the height from the top surface of the semiconductor chip 2 of the ball-shaped bump electrode 3 located directly above each of the source pads arranged in the first row arrangement region 71 may monotonically increase in the direction from the ball-shaped bump electrode 3 farthest from the boundary line 90 to the nearest ball-shaped bump electrode 3 in the first region A1, and may monotonically increase in the direction from the ball-shaped bump electrode 3 farthest from the boundary line 90 to the nearest ball-shaped bump electrode 3 in the second region A2.

[0156] This allows the positions of the highest points in the third direction of the ball-shaped bump electrodes 3 located directly above the respective source pads in each of the first row arrangement regions 71 to be relatively uniform.

[0157] In general, the surface area of ​​the ball-shaped bump electrode 3 increases as the height from the surface of the semiconductor chip 2 increases. In other words, the larger the surface area of ​​the ball-shaped bump electrode 3, the higher the height from the surface of the semiconductor chip 2.

[0158] Therefore, in each of the multiple first row arrangement regions 71, the surface area of ​​the ball-shaped bump electrode 3 located directly above each source pad arranged in the first row arrangement region 71 may monotonically increase in the direction from the ball-shaped bump electrode 3 farthest from the boundary line 90 to the nearest ball-shaped bump electrode 3 in the first region A1, and may monotonically increase in the direction from the ball-shaped bump electrode 3 farthest from the boundary line 90 to the nearest ball-shaped bump electrode 3 in the second region A2.

[0159] This allows the positions of the highest points in the third direction of the ball-shaped bump electrodes 3 located directly above the respective source pads in each of the first row arrangement regions 71 to be relatively uniform.

[0160] Furthermore, in the semiconductor device 1, the current flowing to the semiconductor chip 2 via the source pad arranged in the second row-shaped arrangement region 72 that is closest to and faces the boundary line 90 has the shortest distance within the semiconductor chip 2 that the current flows among all the currents flowing in the semiconductor chip 2.

[0161] Therefore, the number of source pads may be ny in each of the second row-arrangement regions 72 that are closest to each other across the boundary line 90. That is, the number of source pads in each of the second row-arrangement regions 72 that are closest to each other across the boundary line 90 may be ny, which is the maximum number between 2 and ny.

[0162] As a result, after the semiconductor device 1 is mounted on the mounting substrate 500, the current path of the current flowing through the semiconductor chip 2 can be prevented from becoming high in resistance.

[0163] 7A and 7B are plan views showing an example of the positional relationship between a first gate pad 119 and a plurality of first source pads 111, and an example of the positional relationship between a second gate pad 129 and a plurality of second source pads 121.

[0164] As shown in FIGS. 7A and 7B, the distance between the first gate pad 119 and the first source pad 111 closest to the first gate pad 119 is rs [μm] The distance between the second gate pad 129 and the second source pad 121 closest to the second gate pad 129 is equal to or greater than the closest distance between the first source pads 111, and is rs [μm] This may be equal to or greater than the closest distance between the multiple second source pads 121.

[0165] This makes it possible to suppress a short circuit between the first gate pad and any of the plurality of first source pads, and a short circuit between the second gate pad and any of the plurality of second source pads.

[0166] FIG. 8 is a plan view showing the maximum adjacent distance, which is the longest distance between adjacent source pads in the second row arrangement region 72. As shown in FIG.

[0167] As shown in FIG. 8, in the first area A1, the longest adjacent distance in the multiple second row arrangement areas 72 monotonically decreases in a direction from the second row arrangement area 72 farthest from the boundary line 90 toward the nearest second row arrangement area 72, and in the second area A2, the longest adjacent distance in the multiple second row arrangement areas 72 monotonically decreases in a direction from the second row arrangement area 72 farthest from the boundary line 90 toward the nearest second row arrangement area 72. The number of source pads in each of the multiple first row arrangement areas 71 is as follows: (1) one side of the semiconductor chip 2 It is also acceptable that (1) for two or more first row arrangement regions 71 in which the distance to one long side is shorter than the distance to the other long side, the distance monotonically decreases in the direction from the first row arrangement region 71 closest to one long side to the first row arrangement region 71 that is the furthest, and (2) for two or more first row arrangement regions 71 in which the distance to the other long side is shorter than the distance to the one long side, the distance monotonically decreases in the direction from the first row arrangement region 71 closest to the other long side to the first row arrangement region 71 that is the furthest.

[0168] Furthermore, as shown in FIG. 8, in each of the multiple first row-like arrangement regions 71, the number of source pads arranged in that first row-like arrangement region 71 may decrease by two as the distance from the long side of the nearest semiconductor chip 2 increases by one row.

[0169] As a result, by arranging the first gate pad 119 and the second gate pad 129 at the positions shown in FIG. 8, it is possible to prevent a short circuit between the first gate pad 119 and any of the multiple first source pads 111, and a short circuit between the second gate pad 129 and any of the multiple second source pads 121.

[0170] 9A and 9B are cross-sectional views showing an example of a cross section of ball-shaped bump electrode 3 after heat treatment in the case where ball-shaped bump electrode 3 is brought into contact with and connected to the upper surface of a pad by heat treatment.

[0171] FIG. 9A is a cross-sectional view of ball-shaped bump electrode 3 in which the cross-sectional area in a plane parallel to the top surface of semiconductor chip 2 monotonically decreases from the side closer to the top surface of semiconductor chip 2 to the side farther away.

[0172] Here, the ball-shaped bump electrode 3 shown in FIG. 9A is also referred to as a dome-shaped bump electrode.

[0173] Figure 9B is a cross-sectional view of a ball-shaped bump electrode 3 in which the cross-sectional area in a plane parallel to the top surface of the semiconductor chip 2 first increases monotonically and then decreases monotonically from closer to the top surface of the semiconductor chip 2 to farther away from it.

[0174] Here, the ball-shaped bump electrode 3 shown in FIG. 9B is also referred to as a non-dome-shaped bump electrode. Condition The bump electrodes are also non-dome Condition Both bump electrodes are ball-shaped bump electrodes 3 .

[0175] In order to avoid difficulties in manufacturing the semiconductor device 1, it may be preferable that the ball-shaped bump electrode 3 is a dome-shaped bump electrode.

[0176] In particular, when a water-soluble film is formed on the upper surface of the semiconductor chip 2 in a process after a ball-shaped bump electrode 3 is brought into contact with and connected to the upper surface of the pad by heat treatment, it is known that it becomes difficult to form the water-soluble film when the ball-shaped bump electrode 3 is a non-dome-shaped bump electrode.

[0177] Furthermore, from the viewpoint of ensuring the permeability of the underfill material between the semiconductor chip 2 and the mounting substrate 500 when the semiconductor device 1 is mounted on the mounting substrate 500, it is desirable that the height of the ball-shaped bump electrode 3 from the top surface of the semiconductor chip 2 after heat treatment be 70 μm or more and 130 μm or less.

[0178] When a ball-shaped bump electrode 3 is brought into contact with and connected to the top surface of a pad by heat treatment, the radius of the pad is r [μm], and the radius of the solder ball material before heat treatment is R [μm]. It is known that the height H [μm] of the ball-shaped bump electrode 3 from the top surface of the semiconductor chip 2 after heat treatment can be expressed by the following (Equation 1).

[0179]

number

[0180] FIG. 10 is a table showing the values ​​[μm] of the diameter (=2R) of the solder ball material before heat treatment required to set the height (=H) of the ball-shaped bump electrode 3 after heat treatment to 70 [μm], 100 [μm], and 130 [μm] when the pad diameter (=2r) calculated by (Equation 1) is 150 [μm], 200 [μm], 250 [μm], and 300 [μm], respectively.

[0181] 10, when the diameter of the pad is 150 [μm], the diameter of the solder ball material before the heat treatment required to make the height of the ball-shaped bump electrode 3 after the heat treatment 130 [μm] is 164 [μm]. That is, in this case, the ball-shaped bump electrode 3 after the heat treatment becomes a non-dome-shaped bump electrode.

[0182] Therefore, in order for the ball-shaped bump electrode 3 after heat treatment to be a dome-shaped bump electrode, in order to achieve the desired height of the ball-shaped bump electrode 3 from the top surface of the semiconductor chip 2 after heat treatment of 70 μm or more and 130 μm or less, the diameter of the pad needs to be greater than 150 μm.

[0183] Therefore, rs is greater than 150, the height of the multiple ball-shaped bump electrodes 3 from the top surface of the semiconductor chip 2 is greater than or equal to 70 μm and less than or equal to 130 μm, and the cross-sectional area of ​​the multiple ball-shaped bump electrodes 3 in a plane parallel to the top surface of the semiconductor chip 2 may monotonically decrease from closer to the top surface of the semiconductor chip 2 to farther away from it.

[0184] It is also known that when the semiconductor chip 2 is curved in such a way that the central portion thereof is curved away from the mounting substrate 500 along the first direction, which is the long side direction of the semiconductor chip 2, the amount of warping can reach 30 μm.

[0185] Therefore, in such a case, when the height of the ball-shaped bump electrode 3 placed directly above the pad located near the short side of the semiconductor chip 2 is set to 100 [μm], it is desirable to adjust the diameter of the pad in advance so that the height of the ball placed directly above the pad located near the boundary line 90 is 130 [μm].

[0186] Therefore, in such cases, it is desirable to adjust the diameter of the pads located near the short sides of the semiconductor chip 2 to approximately 250 μm, and the diameter of the pads located near the boundary line 90 to approximately 200 μm, as shown by the arrows in Figure 10.

[0187] Furthermore, it is desirable to adjust the diameter of the pad so that it gradually changes to an appropriate value in the first direction according to the amount of warping of the semiconductor chip 2.

[0188] Figure 11A is a line graph showing the relationship between the source pad diameter rs1 [μm] and the number ny1 [units] of source pads that can be arranged in the second row-shaped arrangement region 72 when the semiconductor chip 2 has a long side length Lx of 3400 [μm], a short side length Ly of 1960 [μm], and all source pads have the same diameter rs1 [μm].

[0189] As shown in FIG. 11A, the number of source pads that can be arranged in one second row arrangement region 72 varies stepwise depending on the diameter of the source pad.

[0190] 11A, if the diameter of the source pad is 378 μm or more, only one source pad can be arranged in one second row arrangement region 72. That is, it becomes impossible to arrange source pads in a row in the second direction. For this reason, it is desirable that the diameter of the source pad is less than 378 μm.

[0191] As mentioned above, the diameter of the source pad must be greater than 150 μm.

[0192] Figure 11B is a line graph showing the relationship between the source pad diameter rs1 [μm] and the occupancy rate [%] of the total area of ​​the source pads of the semiconductor chip 2 relative to the area of ​​the top surface of the semiconductor chip 2, when the long side length Lx of the semiconductor chip 2 is 3400 [μm], the short side length Ly is 1960 [μm], and the diameter of all source pads is the same at rs1 [μm].

[0193] In order to prevent the current path of the current flowing through the semiconductor chip 2 from becoming high in resistance and to prevent a decrease in the heat dissipation properties of the semiconductor chip 2, it is desirable for the ratio of the total area of ​​the source pads of the semiconductor chip 2 to the surface area of ​​the top surface of the semiconductor chip 2 to be as large as possible.

[0194] Therefore, the diameter of the source pad is desirably 226 μm or 280 μm, at which the occupancy rate of the total area of ​​the source pads of the semiconductor chip 2 relative to the surface area of ​​the top surface of the semiconductor chip 2 is maximized, as shown in FIG. 11B.

[0195] On the other hand, when the semiconductor chip 2 is actually manufactured, the diameter of the source pad varies by about ±15 μm due to manufacturing variations. Therefore, taking this manufacturing variation into consideration, it is desirable that the diameter of the source pad is 196 μm to 226 μm, or 250 μm to 280 μm, so that it does not exceed 226 μm or 280 μm even if manufacturing variations occur.

[0196] Furthermore, taking into consideration the possibility that the semiconductor chip 2 may bend in the first direction with its central portion away from the mounting substrate 500, in each of the multiple first row arrangement regions 71, among the source pads arranged in the first row arrangement region 71, the diameter of the source pad farthest from the boundary line 90 in the first region A1 and the diameter of the source pad farthest from the boundary line 90 in the second region A2 may be 250 μm or more and 280 μm or less, and the diameter of the source pad closest to the boundary line 90 in the first region A1 and the diameter of the source pad closest to the boundary line 90 in the second region A2 may be 196 μm or more and 226 μm or less.

[0197] Fig. 12 is a plan view showing another example of the structure of the semiconductor device 1. However, Fig. 12 is a drawing in which the illustration of the multiple ball-shaped bump electrodes 3 is omitted. Therefore, Fig. 12 is also a plan view of the semiconductor chip 2.

[0198] As shown in FIG. 12, in a plan view of the semiconductor device 1, the first gate pad 119 and the second gate pad 129 do not necessarily have to be arranged in the second row arrangement region 72.

[0199] In addition, in a plan view of the semiconductor device 1, the closest distance between the individual source pads is rs / 2 [μm] If this is the case, the closest distance of the first row arrangement region 71 is rs / 2 [μm] It may be less than.

[0200] Furthermore, in a planar view of the semiconductor device 1, the positions in the second direction (Y-axis direction in FIG. 12) of each of the source pads in one of the multiple first row arrangement regions 71 that are adjacent to each other may not coincide with the positions in the second direction of any of the source pads in the other first row arrangement region 71 that are adjacent to each other.

[0201] Furthermore, in a plan view of the semiconductor device 1, there may be source pads that are not arranged in the first row-arrangement region 71. That is, as shown in Fig. 12, in a plan view of the semiconductor device 1, there may be source pads that are less than four, that is, two source pads, such as the source pads shaded in black, arranged with their centers aligned linearly in the first direction (the X-axis direction in Fig. 12).

[0202] Fig. 13 is a plan view showing another example of the structure of the semiconductor device 1. However, Fig. 13 is a drawing in which the illustration of a plurality of ball-shaped bump electrodes 3 is omitted. Therefore, Fig. 13 is also a plan view of the semiconductor chip 2.

[0203] As shown in FIG. 13, in a plan view of the semiconductor device 1, the closest distance between the individual source pads is rs / 2 [μm] As long as this is the case, among the multiple first row arrangement regions 71, one first row arrangement region 71 and the other first row arrangement region 71 among adjacent first row arrangement regions 71 may overlap.

[0204] In addition, in a plan view of the semiconductor device 1, the nearest distances between adjacent source pads may not be the same in the same second row-arrangement region 72. That is, as shown in Fig. 13, in a plan view of the semiconductor device 1, for example, the nearest distances between source pads shaded in black may be longer than the nearest distances between other adjacent source pads in the second row-arrangement region 72 including those source pads shaded in black.

[0205] Fig. 14 is a plan view showing another example of the structure of the semiconductor device 1. However, Fig. 14 omits illustration of a plurality of ball-shaped bump electrodes 3. Therefore, Fig. 14 is also a plan view of the semiconductor chip 2.

[0206] As shown in FIG. 14, in a plan view of the semiconductor device 1, the closest distance of the second row-like arrangement region 72 is rs / 2 [μm] may be equal to

[0207] (supplement) Although the semiconductor device according to one aspect of the present disclosure has been described based on the embodiment, the present disclosure is not limited to the embodiment. As long as it does not deviate from the gist of the present disclosure, various modifications conceived by a person skilled in the art to the embodiment and forms constructed by combining components in different modifications may also be included within the scope of one or more aspects of the present disclosure. [Industrial Applicability]

[0208] The present disclosure is widely applicable to semiconductor devices and the like. [Explanation of symbols]

[0209] 1 Semiconductor device 2. Semiconductor chips 3. Ball-shaped bump electrode 10 First vertical MOS transistor 11 First source electrode 12, 13, 22, 23 parts 14 First Source Region 15 First gate conductor 16 First gate insulating film 18 First Body Region 19 First gate electrode 20 Second vertical MOS transistor 21 Second source electrode 24 Second Source Region 25 Second gate conductor 26 Second gate insulating film 28 Second Body Region 29 Second gate electrode 30 metal layer 32 Semiconductor Substrate 33 Low concentration impurity layer 34 Oxide Film 35 Protective film 40 Semiconductor layer 61 First gate wiring 62 Second gate wiring 71, 71A, 71B, 71C, 71D, 71E First columnar arrangement area 72, 72A, 72B, 72C, 72D, 72E, 72F, 72G, 72H Second columnar arrangement area 90 Border 111 First Source Pad 119 First Gate Pad 121 Second Source Pad 129 Second Gate Pad 500 Mounting Board A1 First Area A2 Second Area

Claims

1. A chip size package type semiconductor device capable of face-down mounting, the semiconductor device includes a rectangular semiconductor chip having long sides extending in a first direction and short sides extending in a second direction in a plan view of the semiconductor device; The semiconductor chip comprises: a semiconductor layer having a semiconductor substrate; a first vertical MOS transistor formed in the semiconductor layer in a first region, which is one of two regions dividing the semiconductor chip in terms of area in the plan view, and a second vertical MOS transistor formed in the semiconductor layer in a second region, which is the other of the two regions; the semiconductor substrate serves as a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; a boundary line between the first region and the second region is a line segment extending in the second direction, the first vertical MOS transistor includes a first gate pad and a plurality of first source pads on an upper surface of the semiconductor chip in the first region; the second vertical MOS transistor includes a second gate pad and a plurality of second source pads on an upper surface of the semiconductor chip in the second region; In the plan view, the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads are circular with a diameter of less than 378 μm, On an upper surface of the semiconductor chip, in the plan view, a plurality of first row arrangement regions are arranged in which 4 to 2nx source pads of the plurality of first source pads and the plurality of second source pads are arranged linearly in the first direction, and a plurality of second row arrangement regions are arranged in which 2 to ny source pads of the plurality of first source pads or the plurality of second source pads are arranged linearly in the second direction, In the plan view, a width of each of the plurality of first row-arrangement regions is equal to a maximum diameter among diameters of the 4 to 2nx source pads arranged in the first row-arrangement region, and a width of each of the plurality of second row-arrangement regions is equal to a maximum diameter among diameters of the 2 to ny source pads arranged in the second row-arrangement region, In the plan view, the length of the long side is Lx [μm], the length of the short side is Ly [μm], and the maximum diameter among the diameters of the plurality of first source pads and the plurality of second source pads is rs [μm]. nx is an integer equal to or greater than 2 that satisfies the relationship nx<1 / 3×(Lx / rs−3), ny is an integer equal to or greater than 2 that satisfies the relationship ny<2 / 3×(Ly / rs−1), in the plan view, a closest distance between the plurality of first source pads and the plurality of second source pads and a closest distance between the plurality of second row-shaped arrangement regions is rs / 2 [μm] or more, a diameter of the first gate pad and a diameter of the second gate pad are rs [μm], the first gate pad is disposed, in the plan view, farther from the boundary line than a second row-arrangement region that is closest to the boundary line in the first region among the plurality of second row-arrangement regions; the second gate pad is disposed, in the plan view, farther from the boundary line than a second row-arrangement region that is closest to the boundary line in the second region among the plurality of second row-arrangement regions; The semiconductor device further includes a plurality of ball-shaped bump electrodes that are connected in one-to-one contact with the first gate pad, the plurality of first source pads, the second gate pad, and the plurality of second source pads at positions directly above each of the first gate pad, the plurality of first source pads, and the second gate pad. Semiconductor device.

2. In the plan view, the nearest distance between the first line-arrangement regions is rs / 2 [μm] or more. The semiconductor device according to claim 1 .

3. In the plan view, the diameter of each of the first source pads and the second source pads is rs [μm].

3. The semiconductor device according to claim 1 or 2.

4. In the plan view, in each of the plurality of first row-arrangement regions, diameters of the 4 to 2nx source pads arranged in the first row-arrangement region monotonically decrease in a direction from the source pad farthest from the boundary line to the nearest source pad in the first region, and monotonically decrease in a direction from the source pad farthest from the boundary line to the nearest source pad in the second region. The semiconductor device according to claim 1 .

5. In the plan view, in each of the plurality of first row-arrangement regions, a nearest distance of the 4 to 2nx source pads arranged in the first row-arrangement region monotonically increases in a direction from the source pad farthest from the boundary line to the nearest source pad in the first region, and monotonically increases in a direction from the source pad farthest from the boundary line to the nearest source pad in the second region. The semiconductor device according to claim 4.

6. In the plan view, among the plurality of second row-arrangement regions, in each of the second row-arrangement regions that are closest to each other across the boundary line, a diameter of the 2 to ny source pads is equal to a minimum diameter of diameters of the plurality of first source pads and the plurality of second source pads. The semiconductor device according to claim 1 .

7. In the plan view, in each of the plurality of first row-arrangement regions, a height from a top surface of the semiconductor chip of a ball-type bump electrode located directly above each of the 4 to 2nx source pads arranged in the first row-arrangement region among the plurality of ball-type bump electrodes monotonically increases in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the first region, and monotonically increases in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the second region. The semiconductor device according to claim 1 .

8. In the plan view, in each of the plurality of first row-arrangement regions, a surface area of ​​a ball-type bump electrode located directly above each of the 4 to 2nx source pads arranged in the first row-arrangement region among the plurality of ball-type bump electrodes monotonically increases in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the first region, and monotonically increases in a direction from the ball-type bump electrode farthest from the boundary line to the nearest ball-type bump electrode in the second region. The semiconductor device according to claim 1 .

9. In the plan view, among the plurality of second row-arrangement regions, in each of the second row-arrangement regions that are closest to each other across the boundary line, the number of source pads that is between 2 and ny is ny. The semiconductor device according to claim 3 .

10. In the plan view, a distance between the first gate pad and a first source pad among the plurality of first source pads that is closest to the first gate pad is equal to or greater than rs [μm] and is greater than a closest distance between the plurality of first source pads; A distance between the second gate pad and a second source pad among the plurality of second source pads that is closest to the second gate pad is equal to or greater than rs [μm] and is greater than a closest distance between the plurality of second source pads. The semiconductor device according to claim 9.

11. In the plan view, an adjacent longest distance, which is a longest distance among distances between adjacent source pads among the 2 to ny source pads in each of the plurality of second row-arrangement regions, monotonically decreases in the first region in a direction from a second row-arrangement region farthest from the boundary line among the plurality of second row-arrangement regions toward a nearest second row-arrangement region, and monotonically decreases in the second region in a direction from a second row-arrangement region farthest from the boundary line among the plurality of second row-arrangement regions toward a nearest second row-arrangement region, The number of the source pads, which is 4 to 2nx in each of the plurality of first row-arrangement regions, monotonically decreases in a direction from the first row-arrangement region closest to one long side to the farthest first row-arrangement region for two or more first row-arrangement regions in which the distance to one of the long sides is shorter than the distance to the other long side, and (2) monotonically decreases in a direction from the first row-arrangement region closest to the other long side to the farthest first row-arrangement region for two or more first row-arrangement regions in which the distance to the other long side is shorter than the distance to the one long side. The semiconductor device according to claim 10.

12. In the plan view, The positions of the four to 2nx source pads in the second direction in one first row arrangement region of the plurality of first row arrangement regions adjacent to each other do not match the positions of any of the four to 2nx source pads in the second direction in the other first row arrangement region of the adjacent first row arrangement regions. The semiconductor device according to claim 1 .

13. rs is 196 to 226, or 250 to 280 The semiconductor device according to claim 3 .

14. In the plan view, in each of the plurality of first row-arrangement regions, of the 4 to 2nx source pads arranged in the first row-arrangement region, a diameter of the source pad farthest from the boundary line in the first region and a diameter of the source pad farthest from the boundary line in the second region are 250 μm to 280 μm, and a diameter of the source pad closest to the boundary line in the first region and a diameter of the source pad closest to the boundary line in the second region are 196 μm to 226 μm. The semiconductor device according to claim 4.

15. rs is greater than 150, a height of the plurality of ball-shaped bump electrodes from a top surface of the semiconductor chip is 70 μm or more and 130 μm or less; The cross-sectional areas of the plurality of ball-shaped bump electrodes in a plane parallel to the top surface of the semiconductor chip decrease monotonically from the side closer to the top surface of the semiconductor chip to the side farther from the top surface of the semiconductor chip. The semiconductor device according to claim 1 .

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