Semiconductor Device

Abstract

To improve performance of a semiconductor device.SOLUTION: A semiconductor device comprises a semiconductor chip CPL and a clip CLL mounted on the semiconductor chip CPL via a silver paste 60B. The semiconductor chip CPL comprises a passivation film including an opening, a source pad SPL for a main transistor including a portion exposed from the opening, and a wall part 100 provided on the passivation film provides so as to surround the source pad SPL for a main transistor in a plan view. At this time, all the exposed surfaces LES of the source pad SPL for a main transistor exposed from the passivation film are covered with the silver paste 60B. In a plan view, the silver paste 60B connecting the source pad SPL for a main transistor and the clip CLL is confined in a region surrounded with the wall part 100 without overflowing from the region.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device that is a component of an inverter, for example. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2018-121035 (Patent Document 1) describes a technology related to a packaging structure of a semiconductor device that is a component of an inverter.

[0003] Japanese Patent Laid-Open Publication No. 2003-92374 (Patent Document 2) describes a technique for preventing the outflow of adhesive that bonds a wiring board and a semiconductor chip by providing grooves in a solder resist formed on the surface of the wiring board. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-121035 A [Patent Document 2] JP 2003-92374 A Summary of the Invention [Problem to be solved by the invention]

[0005] For example, there is a semiconductor device that encapsulates a semiconductor chip on which a power transistor is formed, in which the leads and pads formed on the surface of the semiconductor chip are connected with a plate-like member called a clip. In this semiconductor device, the pads and the clip are connected with an adhesive, and solder is generally used as the adhesive.

[0006] However, in order to improve the connection reliability between the pad and the clip and reduce the on-resistance, an adhesive called "silver paste," which is made by mixing silver particles with epoxy resin, is sometimes used instead of solder.

[0007] In this regard, the inventors have found that "silver paste" has a property of having a lower viscosity than solder, and that this property means that there is room for improvement that is not apparent with solder. Therefore, in semiconductor devices that use "silver paste," there is a need for a method for overcoming this newly found room for improvement. [Means for solving the problem]

[0008] A semiconductor device according to an embodiment includes a semiconductor chip and a clip mounted on the semiconductor chip via silver paste. Here, the semiconductor chip includes a passivation film having an opening, a pad having a portion exposed from the opening, and a wall portion provided on the passivation film and surrounding the pad in a plan view. At this time, the entire exposed surface of the pad exposed from the passivation film is covered with silver paste. Also, the silver paste connecting the pad and the clip is confined within the area surrounded by the wall portion in a plan view without overflowing. Effect of the Invention

[0009] According to one embodiment, the performance of a semiconductor device can be improved. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a 12-phase brushless DC motor control system. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of an inverter circuit. [Diagram 3] FIG. 1 is a diagram showing a mounting configuration of a semiconductor device that realizes an inverter circuit. [Figure 4] FIG. 1 is a schematic diagram illustrating a “sense ratio.” [Diagram 5] FIG. 13 is a diagram for explaining how the "sense ratio" changes significantly when a crack occurs in an adhesive material. [Figure 6]FIG. 1 is a diagram for explaining room for improvement in “silver paste.” [Figure 7] FIG. 1 is a diagram illustrating a related art. [Figure 8] FIG. 8 is a cross-sectional view taken along line AA in FIG. [Figure 9] FIG. 13 is a diagram showing a configuration in which the clip is shifted to the left side of the page. [Figure 10] FIG. 13 is a diagram showing a configuration in which the clip is shifted to the right side of the page. [Figure 11] FIG. 1 is a diagram for explaining a technical idea in an embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line AA in FIG. [Figure 13] FIG. 12 is a cross-sectional view taken along line BB in FIG. [Figure 14] FIG. 14 is an enlarged view showing a partial area of ​​FIG. [Figure 15] FIG. 12 is a cross-sectional view taken along line CC in FIG. 11, showing a configuration in which the clip is shifted to the left side of the page. [Figure 16] FIG. 12 is a cross-sectional view taken along line CC in FIG. 11, showing a configuration in which the clip is shifted to the right side of the page. [Figure 17] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor chip. [Figure 18] 18 is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 17. [Figure 19] 19 is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 18. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process of the semiconductor chip following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 20. [Figure 22] 1A to 1C are plan views showing a manufacturing process of a semiconductor device. [Figure 23] 23 is a plan view showing a manufacturing process of the semiconductor device subsequent to FIG. 22. [Figure 24] 24 is a plan view showing a manufacturing process of the semiconductor device subsequent to FIG. 23. [Diagram 25]25 is a plan view showing a manufacturing process of the semiconductor device subsequent to FIG. 24. [Figure 26] 26 is a plan view showing a manufacturing process of the semiconductor device subsequent to FIG. 25. FIG. [Figure 27] FIG. 13 is a schematic diagram showing a configuration of Modification 1. [Figure 28] FIG. 11 is a schematic diagram showing a configuration of Modification 2. [Figure 29] FIG. 13 is a schematic diagram showing a configuration of Modification 3. [Diagram 30] FIG. 13 is a schematic diagram showing a configuration of Modification 4. [Diagram 31] 31 is a cross-sectional view taken along line AA in FIG. 30. [Diagram 32] FIG. 13 is a schematic diagram showing a configuration of Modification 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0012] <12-phase brushless DC motor control system> In recent years, in anticipation of functional safety for the practical application of autonomous driving in automobiles, the conventional three-phase brushless DC motors have been designed and developed to be six-phase or twelve-phase brushless DC motors. Brushless DC motors are not self-commuting, and are generally recognized to be complex to control. Therefore, a six-phase brushless DC motor control system that controls a six-phase brushless DC motor uses two sets of the conventional three phases (U phase, V phase, W phase), while a 12-phase brushless DC motor control system that controls a 12-phase brushless DC motor uses four sets of the conventional three phases (U phase, V phase, W phase), so that even if a malfunction occurs in one set, the malfunction does not immediately become apparent.

[0013] An inverter circuit is used as a circuit to control each phase, and the AC power supplied from this inverter circuit is supplied to the coils of each phase of the brushless DC motor. For this reason, a brushless DC motor control system that controls a 6-phase brushless DC motor or a 12-phase brushless DC motor uses 6 or 12 inverter circuits.

[0014] FIG. 1 is a diagram illustrating a schematic configuration of a 12-phase brushless DC motor control system.

[0015] The motor MOT shown in FIG. 1 is a 12-phase brushless DC motor and has 12 coils CL. Each coil CL is connected to an inverter circuit INV. That is, an inverter circuit INV is provided for each of the 12 coils of the motor MOT. Therefore, the 12-phase brushless DC motor control system shown in FIG. 1 has a total of 12 inverter circuits INV. Each inverter circuit INV is connected to a control circuit CT provided in an MCU (Micro Controller Unit), and each inverter circuit is controlled by this control circuit CT. Then, each inverter circuit INV controlled by the control circuit CT supplies AC power to the coils CL connected to the respective inverter circuits INV, thereby driving the motor MOT.

[0016] <Inverter circuit configuration> Next, a circuit configuration of the inverter circuit INV, which is a component of the above-mentioned 12-phase brushless DC motor control system, will be described.

[0017] FIG. 2 is a diagram showing a circuit configuration of the inverter circuit INV.

[0018] 2, the inverter circuit INV has a high-side switching circuit 10, a low-side switching circuit 20, and a control circuit 30.

[0019] The high-side switching circuit 10 includes a main transistor 11 which is a power transistor, and a sense transistor 12 .

[0020] On the other hand, the low-side switching circuit 20 includes a main transistor 21 made of a power transistor, and a sense transistor 22 .

[0021] In the high-side switching circuit 10 and the low-side switching circuit 20 configured in this manner, the main transistor 11 included in the high-side switching circuit 10 and the main transistor 21 included in the low-side switching circuit 20 are connected in series between a power supply potential VIN and a ground potential GND.

[0022] 2, the connection node between the main transistor 11 and the main transistor 21 is "OUT", and this connection node is connected to the coil CL shown in FIG.

[0023] Next, the control circuit 30 includes, for example, a pre-driver that applies a gate voltage to the gate electrode of the main transistor 11 and the gate electrode of the sense transistor 12, and a pre-driver that applies a gate voltage to the gate electrode of the main transistor 21 and the gate electrode of the sense transistor 22. Furthermore, the control circuit 30 has a sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20.

[0024] 2, an input node that inputs a control signal from the control circuit CT shown in FIG. 1 to the control circuit 30 is "IN", and an output node that outputs an output signal from the sense circuit 31 of the control circuit 30 is "OUT2". This output node is electrically connected to the control circuit CT shown in FIG. 1. In this manner, the inverter circuit INV is configured.

[0025] The control circuit 30 is configured to control the on / off of the main transistor 11 included in the high-side switching circuit 10 and to control the on / off of the main transistor 21 included in the low-side switching circuit 20, based on a control signal from the control circuit CT shown in Fig. 1. That is, the control circuit 30 controls the on / off of the main transistor 11 by switching the gate voltage applied to the gate electrode of the main transistor 11, and controls the on / off of the main transistor 21 by switching the gate voltage applied to the gate electrode of the main transistor 21.

[0026] In this manner, by controlling the main transistor 11 on / off and the main transistor 21 on / off, AC power is supplied from the connection node ("OUT") between the main transistor 11 and the main transistor 21 to the coil CL shown in FIG.

[0027] Here, the sense transistor 22 included in the low-side switching circuit 20 is provided to detect the current value of the current flowing through the main transistor 21 .

[0028] For example, the main transistor 21 and the sense transistor 22 form a current mirror circuit such that the current value of the current flowing through the main transistor 21:the current value of the current flowing through the sense transistor 22=12500:1 (sense ratio).

[0029] The sense transistor 22 is electrically connected to a sense circuit 31, and the current flowing through the sense transistor 22 is converted into a voltage by the sense circuit 31, and then output from the output node "OUT2" to the control circuit CT shown in Fig. 1. At this time, the control circuit CT shown in Fig. 1 calculates the current value of the current flowing through the main transistor 21 based on the voltage signal input from "OUT2" and the "sense ratio".

[0030] The inverter circuit INV is configured as described above.

[0031] <Package structure> Next, the mounting configuration of the inverter circuit INV will be described.

[0032] FIG. 3 is a diagram showing a mounting configuration of a semiconductor device PKG that realizes an inverter circuit.

[0033] 3, the semiconductor device PKG has a sealing body MR having a rectangular planar shape. The sealing body MR has a side S1 which is a long side, a side S2 which faces the side S1, a side S3 which is a short side intersecting the sides S1 and S2, and a side S4 which faces the side S3. The leads LD protrude from the long sides S1 and S2.

[0034] 3, the outline of the sealing body MR is indicated by a dashed line, and components sealed inside the sealing body MR are illustrated. The internal configuration of the sealing body MR will be described below.

[0035] The semiconductor device PKG has a die pad DPC which is a chip mounting portion, a die pad DPL which is a chip mounting portion, and a die pad DPH which is a chip mounting portion. Specifically, the die pad DPL, the die pad DPC, and the die pad DPH are arranged in this order in the x direction. In other words, the die pad DPL is arranged on the left side, the die pad DPC is arranged in the center, and the die pad DPH is arranged on the right side.

[0036] A semiconductor chip CPC is mounted on the die pad DPC. A control circuit 30 shown in FIG. 2 is formed on this semiconductor chip CPC. A plurality of pads including, for example, a plurality of pads PDC1 and a plurality of pads PDC2 are formed on the surface of the semiconductor chip CPC. In this manner, the semiconductor chip CPC mounted on the die pad DPC is disposed in the center of the semiconductor device PKG.

[0037] Next, the semiconductor chip CPL is mounted on the die pad DPL. The low-side switching circuit 20 shown in FIG. 2 is formed on this semiconductor chip CPL. That is, the main transistor 21 and the sense transistor 22 constituting the low-side switching circuit 20 are formed on the semiconductor chip CPL. The main transistor 21 and the sense transistor 22 are composed of vertical trench power transistors that pass a current in the thickness direction of the semiconductor chip CPL. Then, a plurality of pads PDL are formed on the surface of the semiconductor chip CPL together with a source pad SPL for the main transistor. The plurality of pads PDL include a source pad for the sense transistor and a gate pad common to the main transistor 21 and the sense transistor 22.

[0038] As shown in Fig. 3, a clip CLL, which is a plate-like member made of copper, is disposed on the main transistor source pad SPL. As shown in Fig. 3, the clip CLL is electrically connected to the leads LDL. Meanwhile, each of the pads PDL is electrically connected to each of the pads PDC2 formed on the surface of the semiconductor chip CPC by a bonding wire W.

[0039] Next, the semiconductor chip CPH is mounted on the die pad DPH. The high-side switching circuit 10 shown in FIG. 2 is formed on this semiconductor chip CPH. That is, the main transistor 11 and the sense transistor 12 constituting the high-side switching circuit 10 are formed on the semiconductor chip CPH. The main transistor 11 and the sense transistor 12 are composed of vertical trench power transistors that pass a current in the thickness direction of the semiconductor chip CPH. On the surface of the semiconductor chip CPH, a plurality of pads PDH are formed together with a source pad SPH for the main transistor. The plurality of pads PDH include a source pad for the sense transistor and a gate pad common to the main transistor 11 and the sense transistor 12.

[0040] As shown in Fig. 3, a clip CLH, which is a plate-shaped member made of copper, is disposed on the main transistor source pad SPH. As shown in Fig. 3, the clip CLH is electrically connected to the leads LDH. Meanwhile, each of the pads PDH is electrically connected to each of the pads PDC1 formed on the surface of the semiconductor chip CPC by a bonding wire W.

[0041] In this embodiment, the planar shape of the semiconductor device PKG is substantially rectangular (specifically, a rectangle with each corner chamfered) as shown in Fig. 3. In this embodiment, the planar shape of each semiconductor chip is also rectangular as shown in Fig. 3. In this embodiment, the semiconductor chip CPC, the semiconductor chip CPL, and the semiconductor chip CPH are arranged so that the short side of each semiconductor chip is aligned with the long side of the semiconductor device PKG as shown in Fig. 3. This reduces the size of each semiconductor chip and the size of the semiconductor device PKG.

[0042] In this embodiment, the semiconductor chip CPL in which the low-side switching circuit 20 is formed and the semiconductor chip CPH in which the high-side switching circuit 10 is formed are the same type of semiconductor chip.

[0043] In this manner, a semiconductor device PKG is implemented and configured, which is composed of a SiP (System in Package) in which the semiconductor chip CPC, on which the circuit that constitutes the inverter circuit INV is formed, the semiconductor chip CPL, and the semiconductor chip CPH are implemented in a single package structure.

[0044] <The usefulness of "silver paste"> For example, the die pad and the semiconductor chip are bonded with an adhesive, and the main transistor source pad and the clip formed on the surface of the semiconductor chip are also bonded with an adhesive, with solder generally being used as the adhesive for each.

[0045] However, in this embodiment, from the viewpoint of alleviating stress in the adhesive, improving the reliability of connectivity, and reducing on-resistance, a "silver paste" made by mixing silver particles with epoxy resin is used as the adhesive. This "silver paste" has a lower viscosity than solder, and therefore has the advantage of being able to suppress the occurrence of peeling and voids. Furthermore, since "silver paste" is useful in that it can suppress the occurrence of voids more than solder, in this embodiment, "silver paste" is used instead of solder as the adhesive that connects the die pad and the semiconductor chip and the adhesive that connects the main transistor source pad and the clip. In this embodiment, the above-mentioned "voids" are, for example, cracks (hereinafter referred to as "cracks").

[0046] In particular, the inventors have newly discovered that when a crack occurs in the adhesive, the "sense ratio," which indicates the ratio of the current value of the main transistor to the current value of the sense transistor, changes significantly. When the "sense ratio" changes significantly, the current value of the main transistor cannot be accurately estimated from the current value of the sense transistor.

[0047] This point will be explained below.

[0048] FIG. 4 is a schematic diagram illustrating the "sense ratio."

[0049] 4, a semiconductor chip CPL is mounted on a die pad DPL, and the die pad DPL and the semiconductor chip CPL are bonded together with an adhesive material 50A. A clip CLL is disposed on the semiconductor chip CPL, and the semiconductor chip CPL and the clip CLL are bonded together with an adhesive material 50B.

[0050] 4 indicates a current path of the die pad DPL → adhesive 50A → main transistor formed on the semiconductor chip CPL → adhesive 50B → clip CLL, while the "sense side" in Fig. 4 indicates a current path of the die pad DPL → adhesive 50A → sense transistor formed on the semiconductor chip CPL → adhesive 50B → bonding wire.

[0051] In FIG. 4, a large current flows through the main transistor, but does not flow through the sense transistor. Therefore, for example, the resistance value due to the main transistor is set to "1 mΩ" while the resistance value due to the sense transistor is set to "5000 mΩ." In this case, the "sense ratio" is "5000." That is, in a 12-phase brushless DC motor control system, the current value of the current flowing through the main transistor can be estimated based on the current value (or the converted voltage value) of the current flowing through the sense transistor and the "sense ratio" (= "5000"). Therefore, from the viewpoint of accurately estimating the current value of the current flowing through the main transistor, it is important that the "sense ratio" is constant.

[0052] In this regard, for example, when a crack occurs in the adhesive 50A, the "sense ratio" changes significantly. This will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining that when a crack occurs in the adhesive 50A, the "sense ratio" changes significantly.

[0053] 5, when a crack occurs in the adhesive 50A, resistance due to the crack is added. Specifically, a resistance value ("2 mΩ") due to the crack is added in series in a current path ("main side") of the die pad DPL → adhesive 50A → main transistor formed on the semiconductor chip CPL → adhesive 50B → clip CLL. Meanwhile, a resistance value ("2 mΩ") due to the crack is also added in series in a current path ("sense side") of the die pad DPL → adhesive 50A → sense transistor formed on the semiconductor chip CPL → adhesive 50B → bonding wire.

[0054] As a result, the "sense ratio" is greatly reduced from "5000" to "1667." In other words, when a crack occurs in adhesive 50A, the "sense ratio" is greatly changed. This means that it becomes difficult to accurately estimate the current value of the current flowing through the main transistor in the 12-phase brushless DC motor control system.

[0055] In particular, when the adhesive 50A and the adhesive 50B are made of solder, the solder is prone to cracking, and the cracks will cause a large change in the "sense ratio." In other words, when the adhesive 50A and the adhesive 50B are made of solder, there is a high possibility that the current value of the current flowing through the main transistor cannot be accurately estimated due to the occurrence of cracks. In this regard, when the adhesive 50A and the adhesive 50B are made of "silver paste" instead of solder, it is considered that the "silver paste" can suppress a large change in the "sense ratio" caused by cracks, considering that the "silver paste" is less likely to cause cracks than solder. In other words, it can be said that the "silver paste" is useful in that it can reduce the potential that the current value of the current flowing through the main transistor cannot be accurately estimated due to the occurrence of cracks.

[0056] <Room for improvement in "silver paste"> As described above, the "silver paste" is useful in that it is less susceptible to cracking than solder and can suppress changes in the "sense ratio" caused by cracking. However, according to the inventor's research, there is room for improvement in the "silver paste" as follows.

[0057] FIG. 6 is a diagram for explaining the room for improvement that exists in the "silver paste."

[0058] In Fig. 6, a semiconductor chip CPL is mounted on a die pad DPL, and a main transistor source pad SPL and a plurality of pads PDL are formed on the surface of the semiconductor chip CPL. Then, after "silver paste" is applied to the main transistor source pad SPL shown in Fig. 6, a clip is placed on the main transistor source pad SPL via the "silver paste". In other words, the main transistor source pad SPL and the clip are connected by the "silver paste".

[0059] Here, as shown in FIG. 6, when the "silver paste" is applied onto the main transistor source pad SPL, the "silver paste" overflows and spreads out from the main transistor source pad SPL due to the fact that the viscosity of the "silver paste" is lower than that of solder. For this reason, for example, when the "silver paste" overflowing from the main transistor source pad SPL reaches a plurality of pads PDL, the "silver paste" shorts out the main transistor source pad SPL and the pads PDL. Furthermore, when the "silver paste" spills from the surface of the semiconductor chip CPL and falls onto the die pad DPL, the "silver paste" shorts out the die pad DPL and the main transistor source pad SPL. In other words, the source and drain of the main transistor formed on the semiconductor chip CPL are shorted. For this reason, the following related technology is available to suppress the overflow of the "silver paste" from the main transistor source pad SPL.

[0060] <Description of Related Art> The term "related art" as used herein refers to art that is not publicly known, but has problems that the inventors have found, and is a technology that serves as a premise for the present invention.

[0061] FIG. 7 is a diagram illustrating a related technique.

[0062] 7, a semiconductor chip CPL is mounted on a die pad DPL, and a main transistor source pad SPL and a plurality of pads PDL are formed on the surface of the semiconductor chip CPL. A clip CLL is disposed on the main transistor source pad SPL via a silver paste 60B. Meanwhile, each of the plurality of pads PDL is electrically connected to a wire W.

[0063] FIG. 8 is a cross-sectional view taken along line AA in FIG.

[0064] 8, the die pad DPL and the semiconductor chip CPL are connected by a silver paste 60 A. A passivation film (surface protection film) PAS made of, for example, 1) a silicon oxide film, 2) a silicon nitride film, or 3) a laminated film of a silicon oxide film and a silicon nitride film is formed on the surface of the semiconductor chip CPL, and an opening is formed in this passivation film PAS.

[0065] At this time, a portion of the main transistor source pad SPL, i.e., a portion of the exposed surface LES of the main transistor source pad SPL exposed from the passivation film PAS, is exposed from the opening, and a clip CLL is mounted on the exposed main transistor source pad SPL via silver paste 60B.

[0066] Here, in the related art, as shown in Fig. 7, in order to prevent the silver paste 60B from spilling out and spreading out of the main transistor source pad SPL, the silver paste 60B is applied only to the minimum area required for connection with the clip CLL. As a result, as shown in Figs. 7 and 8, a part of the exposed surface LES of the main transistor source pad SPL exposed from the passivation film PAS is not covered with the silver paste 60B and is exposed from the silver paste 60B. As a result, according to the related art, since the silver paste 60B is applied only to the minimum area required, it is possible to prevent the silver paste 60B from spilling out and spreading out of the main transistor source pad SPL.

[0067] In this regard, the present inventors have newly discovered that there is room for improvement in the related art from the viewpoint of suppressing changes in the "sense ratio," and this discovery will be described below.

[0068] <Room for improvement in related technologies> The novel finding made by the present inventors is that the "sense ratio" changes depending on the position of the clip. This finding will be explained with reference to the drawings.

[0069] FIG. 9 is a diagram showing a configuration in which the clip CLL is shifted to the left side of the paper surface.

[0070] In FIG. 9, a vertical trench power transistor that passes a current in the thickness direction of the semiconductor chip CPL is formed in the semiconductor chip CPL, but not only in FIG. 9 but also in the drawings of the present application, the trench gate structure of the vertical trench power transistor is omitted from illustration.

[0071] Here, in the assembly process of the semiconductor device, the clip CLL is mounted on the main transistor source pad SPL of the semiconductor chip CPL via the silver paste 60B, but the mounting position of the clip CLL may vary depending on the semiconductor device. As a result, the "sense ratio" changes depending on the position of the clip.

[0072] For example, as shown in Figure 9, when the clip CLL is shifted to the left of the page, the current flowing through the main transistor increases while the current flowing through the sense transistor decreases. As a result, the "sense ratio" increases. In other words, when the clip CLL is shifted to the left of the page, the resistance value of the main transistor decreases while the resistance value of the sense transistor increases, resulting in an increase in the "sense ratio."

[0073] In contrast, as shown in Figure 10, when the clip CLL is shifted to the right side of the page, the current flowing through the main transistor decreases while the current flowing through the sense transistor increases. As a result, the "sense ratio" decreases. In other words, when the clip CLL is shifted to the right side of the page, the resistance value of the main transistor increases while the resistance value of the sense transistor decreases, resulting in a decrease in the "sense ratio."

[0074] It can be seen that the "sense ratio" changes depending on the position of the clip. In this regard, from the viewpoint of accurately estimating the current value of the current flowing through the main transistor, it is undesirable for the "sense ratio" to change depending on the position of the clip, and it is desirable for the "sense ratio" to be approximately constant even if the clip is misaligned. In other words, there is room for improvement in the related art from the viewpoint of suppressing the change in the "sense ratio" caused by the clip being misaligned. Therefore, in this embodiment, a device is implemented to overcome the room for improvement that exists in the related art. The technical idea of ​​this embodiment that implements this device will be described below.

[0075] <Technical Concept of the Embodiment> FIG. 11 is a diagram for explaining the technical idea of ​​this embodiment.

[0076] In Fig. 11, a semiconductor chip CPL is mounted on a die pad DPL. A main transistor source pad SPL and a plurality of pads PDL are formed on the surface of the semiconductor chip CPL. The main transistor source pad SPL is electrically connected to a clip CLL. Meanwhile, each of the plurality of pads PDL is electrically connected to a bonding wire W.

[0077] Here, the semiconductor chip CPL is formed with a main transistor for passing a current and a sense transistor for detecting the current value of the current passing through the main transistor. The main transistor and the sense transistor are composed of vertical trench power transistors for passing a current in the thickness direction of the semiconductor chip CPL.

[0078] This vertical trench power transistor is, for example, composed of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto and may be composed of an IGBT (Insulated Gate Bipolar Transistor). That is, the main transistor and the sense transistor are composed of power transistors such as power MOSFETs and IGBTs.

[0079] In the following description, however, it is assumed that the main transistor and the sense transistor are configured as power MOSFETs, each of which has a source, a drain, and a gate electrode.

[0080] Particularly, focusing on the main transistor, the source of the main transistor is electrically connected to the main transistor source pad SPL formed on the front surface of the semiconductor chip CPL, while the drain of the main transistor is electrically connected to a drain electrode formed on the back surface of the semiconductor chip CPL, and this drain electrode is electrically connected to the die pad DPL.

[0081] Focusing on the sense transistor, the source of the sense transistor is electrically connected to a sense transistor source pad, which is one of a plurality of pads PDL formed on the surface of the semiconductor chip CPL, while the drain of the sense transistor is shared with the drain of the main transistor.

[0082] Furthermore, the gate electrode of the main transistor and the gate electrode of the sense transistor are electrically connected to each other, and are also electrically connected to a gate pad, which is another one of the multiple pads PDL formed on the surface of the semiconductor chip CPL.

[0083] 11, the semiconductor chip CPL in this embodiment has a wall portion 100 formed to surround the main transistor source pad SPL in a plan view. The area surrounded by the wall portion 100 is filled with silver paste 60B, and the filled silver paste 60B electrically connects the main transistor source pad SPL and the clip CLL. In other words, the entire exposed surface LES of the main transistor source pad SPL exposed from the passivation film PAS is covered with the silver paste 60B. Moreover, the silver paste 60B connecting the main transistor source pad SPL and the clip CLL is confined within the area surrounded by the wall portion 100 in a plan view and is in contact with the wall portion 100.

[0084] 11, in a plan view, the main transistor source pad SPL and the multiple pads PDL are separated by a wall portion 100. The wall portion 100 has portions that overlap with each of the multiple pads PDL in a plan view.

[0085] 11, the semiconductor chip CPL has a rectangular planar shape, with a side SD1 being a short side, a side SD2 opposite to the side SD1, a side SD3 being a long side intersecting with the sides SD1 and SD2, and a side SD4 opposite to the side SD3. The pull-out portion of the clip CLL intersects with the side SD1. That is, the clip CLL is pulled out so as to intersect with the side SD1 of the semiconductor chip CPL.

[0086] FIG. 12 is a cross-sectional view taken along line AA in FIG.

[0087] In Fig. 12, a semiconductor chip CPL is mounted on a die pad DPL via a silver paste 60A. A main transistor source pad SPL is formed on the surface of the semiconductor chip CPL, and a passivation film PAS made of, for example, a silicon oxide film or a silicon nitride film is also formed. An opening is provided in this passivation film PAS, and the main transistor source pad SPL has a portion exposed from the opening (exposed surface LES). As shown in Fig. 12, a wall portion 100 is provided on the passivation film PAS. This wall portion 100 is arranged so as to surround the main transistor source pad SPL in a plan view (see Fig. 11).

[0088] Here, a silver paste 60B is formed on the surface of the main transistor source pad SPL surrounded by the wall portion 100, and the main transistor source pad SPL and the clip CLL are electrically connected by this silver paste 60B.

[0089] For example, the wall 100 is made of an organic insulating film such as a polyimide resin film, and the clip CLL is made of copper.

[0090] FIG. 13 is a cross-sectional view taken along line BB in FIG.

[0091] In FIG. 13, it can be seen that the wall 100 is formed on the passivation film PAS, and the clip CLL is mounted on the main transistor source pad SPL via the silver paste 60B. Here, if the thickness of the wall 100 is too thick, there is a risk of interference if the clip CLL is misaligned. For example, the thicker the wall 100, the more reliably the silver paste 60B can be suppressed from protruding. Therefore, from the viewpoint of suppressing the protrusion of the silver paste 60B, it is desirable to make the wall 100 thick. In this embodiment, as shown in FIG. 12, the thickness of the wall 100 is greater than the thickness of the passivation film PAS. On the other hand, if the thickness of the wall 100 is too thick, it becomes difficult to ensure a clearance against the misalignment of the clip CLL. For this reason, an example of the clearance between the clip CLL and the wall 100 will be described below.

[0092] FIG. 14 is an enlarged view of the region RA in FIG. 13. As shown in FIG. 14, even if the positional deviation of the clip CLL is set to "50 μm", when a clearance of "10 μm" is ensured between the wall portion 100 and the clip CLL, it can be seen that the thickness of the wall portion 100 can be increased to about "90 μm". In this way, when considering the clearance between the wall portion 100 and the clip CLL, it can be seen that there is an allowable range for the thickness of the wall portion 100. Therefore, when determining the thickness of the wall portion 100, it can be seen that it is necessary to consider not only the viewpoint of suppressing the overflow of the silver paste 60B, but also the viewpoint of ensuring the clearance between the wall portion 100 and the clip CLL.

[0093] <<Features of the embodiment>> Next, features of this embodiment will be described.

[0094] The feature of this embodiment is that, for example, as shown in FIG. 11, a wall portion 100 is provided so as to surround the main transistor source pad SPL. As a result, the silver paste 60B supplied onto the main transistor source pad SPL is confined in the area surrounded by the wall portion 100 and cannot spread outside the main transistor source pad SPL. As a result, it is possible to prevent the low-viscosity silver paste 60 from reaching the multiple pads PDL formed on the surface of the semiconductor chip CPL, or from spilling out from the semiconductor chip CPL and reaching the die pad DPL. Therefore, according to this embodiment, it is possible to prevent the main transistor source pad SPL and the pad PDL from being short-circuited via the silver paste 60B. Furthermore, it is possible to prevent a short circuit between the die pad DPL and the main transistor source pad SPL caused by the silver paste 60B spilling from the surface of the semiconductor chip CPL and falling onto the die pad DPL.

[0095] Thus, the first technical significance of the characteristic feature of this embodiment, that is, providing the wall portion 100 to surround the main transistor source pad SPL, is that it is possible to prevent the silver paste 60B from spilling out to the outside of the main transistor source pad SPL.

[0096] Furthermore, the feature of this embodiment has not only the first technical significance described above, but also the second technical significance described below, which will be explained below. Specifically, the feature of this embodiment has the second technical significance of being able to overcome the room for improvement in the related art, that is, the "sense ratio" changes depending on the position of the clip.

[0097] Fig. 15 is a cross-sectional view taken along line CC in Fig. 11, showing a configuration in which the clip CLL is shifted to the left side of the paper, while Fig. 16 is a cross-sectional view taken along line CC in Fig. 11, showing a configuration in which the clip CLL is shifted to the right side of the paper.

[0098] As shown in Figures 15 and 16, in this embodiment, even if the position of the clip CLL itself is shifted, the entire exposed surface LES of the main transistor source pad SPL is covered with the silver paste 60B, unlike the related art (see Figures 9 and 10). Therefore, since the silver paste 60B is present on the entire exposed surface of the main transistor source pad SPL, even if the clip CLL itself is shifted in position, the "sense ratio" between the current value of the current flowing through the main transistor and the current value of the current flowing through the sense transistor does not change much. This is because, in both the configurations of Figures 15 and 16, the silver paste 60B itself is present on the entire exposed surface of the main transistor source pad SPL, and therefore, even if the arrangement position of the clip CLL is shifted, the fluctuation of the current path indicated by the arrow direction in Figures 15 and 16 is suppressed.

[0099] That is, according to the feature of the present embodiment, since the wall portion 100 is provided, unlike the related art, the silver paste 60B can be filled on the entire exposed surface of the main transistor source pad SPL surrounded by the wall portion 100. As a result, the silver paste 60B has a function of mitigating the change in the "sense ratio" caused by the positional deviation of the clip CLL itself. In other words, since the silver paste 60B is formed on the entire exposed surface of the main transistor source pad SPL, even if the position of the clip CLL is shifted, the fluctuation of the current path indicated by the arrow direction in FIG. 15 and FIG. 16 is suppressed, so that the change in the "sense ratio" can be suppressed.

[0100] Thus, the feature of this embodiment has not only the first technical significance of being able to suppress the silver paste 60B from protruding out of the main transistor source pad SPL, but also the second technical significance of being able to suppress changes in the "sense ratio" due to misalignment of the clip. From this, it can be said that the technical idea of ​​this embodiment is an extremely excellent technical idea in that it uses silver paste, which is superior to solder in terms of improving connection reliability and reducing on-resistance, while also overcoming room for improvement due to the properties of the silver paste itself.

[0101] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0102] First, a manufacturing process of a semiconductor chip will be described, and then an assembly process of assembling the manufactured semiconductor chip into a semiconductor device, which is a package structure, will be described.

[0103] <<Semiconductor chip manufacturing process>> First, a semiconductor element including a main transistor and a sense transistor is formed on the semiconductor substrate SUB by using normal semiconductor manufacturing techniques (patterning technique, ion implantation technique, etching technique, film formation technique, etc.). In this embodiment, it is assumed that the semiconductor element has already been formed on the semiconductor substrate SUB.

[0104] Next, the main transistor source pad SPL is formed on the surface of the semiconductor substrate SUB as shown in Fig. 17. The main transistor source pad SPL can be formed, for example, by forming an aluminum film on the surface of the semiconductor substrate SUB by using a sputtering method, and then patterning the aluminum film by using photolithography and etching techniques.

[0105] 18, a passivation film PAS is formed to cover the main transistor source pad SPL by using a CVD (Chemical Vapor Deposition) method. The passivation film PAS can be formed of, for example, a single layer film or a multilayer film of a silicon oxide film or a silicon nitride film.

[0106] 19, an opening OP1 is formed in the passivation film PAS by using photolithography and etching techniques. At this time, a part of the surface of the main transistor source pad SPL is exposed from the opening OP1.

[0107] Then, as shown in Fig. 20, a polyimide resin film PIF is applied onto the passivation film PAS including the inside of the opening OP1. Next, as shown in Fig. 21, the polyimide resin film PIF is processed by using photolithography and etching techniques. As a result, an opening OP2 that exposes most of the main transistor source pad SPL can be formed in the polyimide film PIF, and a wall portion 100 is formed.

[0108] Thereafter, the chip regions of the semiconductor substrate SUB (semiconductor wafer) are diced to separate them into individual pieces. This makes it possible to obtain a plurality of semiconductor chips. In this manner, the semiconductor chip of this embodiment can be manufactured.

[0109] <<Semiconductor device assembly process>> Next, the assembly process of the semiconductor device will be described.

[0110] First, as shown in FIG. 22, a lead frame LF is prepared.

[0111] The lead frame LF is provided with a plurality of leads LD, a die pad DPL, a die pad DPC, and a die pad DPH.

[0112] Next, as shown in Fig. 23, after applying silver paste onto the die pad DPL, the die pad DPC, and the die pad DPH, the semiconductor chip CPL is mounted on the die pad DPL, the semiconductor chip CPC is mounted on the die pad DPC, and the semiconductor chip CPH is mounted on the die pad DPH. At this time, the low-side switching circuit 20 shown in Fig. 2 is formed on the semiconductor chip CPL, the control circuit 30 shown in Fig. 2 is formed on the semiconductor chip CPC, and the high-side switching circuit 10 shown in Fig. 2 is formed on the semiconductor chip CPH.

[0113] The semiconductor chip CPL has a surface formed with a main transistor source pad SPL, a plurality of pads PDL, and a wall portion 100L surrounding the main transistor source pad SPL. Similarly, the semiconductor chip CPH has a surface formed with a main transistor source pad SPH, a plurality of pads PDH, and a wall portion 100H surrounding the main transistor source pad SPH. Meanwhile, the semiconductor chip CPC has a surface formed with a plurality of pads including a plurality of pads PDC1 and a plurality of pads PDC2.

[0114] Next, as shown in FIG. 24, a silver paste 60B is applied onto the main transistor source pad SPL of the semiconductor chip CPL, and a silver paste 60B is applied onto the main transistor source pad SPH of the semiconductor chip CPH.

[0115] At this time, since the wall portion 100L is formed so as to surround the main transistor source pad SPL, it is possible to suppress the silver paste 60B from spilling out from the main transistor source pad SPL to the outside, thereby preventing a short circuit between the main transistor source pad SPL and the pad PDL via the silver paste 60B in the semiconductor chip CPL.

[0116] Similarly, since the wall portion 100H is formed so as to surround the main transistor source pad SPH, the silver paste 60B can be prevented from spilling out from the main transistor source pad SPH to the outside. This makes it possible to prevent a short circuit between the main transistor source pad SPH and the pad PDH via the silver paste 60B in the semiconductor chip CPH as well.

[0117] 25, a clip CLL is mounted on the main transistor source pad SPL and the clip CLL and the lead LD are connected via a silver paste 60B. Similarly, a clip CLH is mounted on the main transistor source pad SPH and the clip CLH and the lead LD are connected.

[0118] Moreover, the pads PDL and PDC2 are connected by a bonding wire W, and the pads PDH and PDC1 are connected by a bonding wire W.

[0119] Thereafter, as shown in Fig. 26, a resin sealing is performed to form the sealing body MR. Then, a plating layer (not shown) is formed as necessary on the outer lead portion of the lead LD exposed from the sealing body MR. Next, outside the sealing body MR, the lead LD is cut at a predetermined position to separate the sealing body MR from the frame of the lead frame LF. Next, the outer lead portion of the lead LD protruding from the sealing body MR is bent.

[0120] In this manner, the semiconductor device PKG can be manufactured.

[0121] <Variation 1> Next, a first modification of the above embodiment will be described.

[0122] FIG. 27 is a schematic diagram showing the configuration of the present modified example 1. As shown in FIG.

[0123] In FIG. 27, the semiconductor chip CPL has a side SD1, a side SD2 opposite to the side SD1, It has a side SD3 intersecting with the sides SD1 and SD2, and a side SD4 opposite to the side SD3. At this time, the clip CLL has an extraction portion intersecting with the side SD1, while a plurality of pads PDL formed on the surface of the semiconductor chip CPL are concentrated and arranged at the intersection (corner) of the sides SD2 and SD3.

[0124] As a result, according to this modification 1, it is possible to increase the y-direction width of the main transistor source pad SPL and the y-direction width of the clip CLL indicated by "L" in Fig. 27 without being obstructed by multiple pads PDL. This means that the y-direction width of the pull-out portion of the clip CLL close to the lead can be increased, so according to this modification 1, it is possible to obtain the effect of reducing the on-resistance caused by the clip CLL.

[0125] <Variation 2> Next, a second modification of the above embodiment will be described.

[0126] FIG. 28 is a schematic diagram showing the configuration of the second modified example.

[0127] In FIG. 28, the semiconductor chip CPL has a side SD1, a side SD2 opposite to the side SD1, The semiconductor chip CPL has a side SD3 intersecting with the sides SD1 and SD2, and a side SD4 opposite to the side SD3. The clip CLL has an extraction portion intersecting with the side SD1. Meanwhile, the multiple pads PDL formed on the surface of the semiconductor chip CPL are composed of a first pad group (three pads PDL on the left side of the paper) and a second pad group (four pads PDL on the right side of the paper). The first pad group is arranged at the intersection of the sides SD1 and SD3, while the second pad group is arranged at the intersection of the sides SD2 and SD3.

[0128] As a result, in this modification 2 as well, it is possible to increase the y-direction width of the main transistor source pad SPL and the y-direction width of the clip CLL indicated by "L" in Fig. 28 without being hindered by multiple pads PDL, although not as much as in modification 1. This means that the y-direction width of the clip CLL can be increased, and therefore, modification 2 also has the effect of reducing the on-resistance caused by the clip CLL.

[0129] <Variation 3> Next, a third modification of the above embodiment will be described.

[0130] FIG. 29 is a schematic diagram showing the configuration of the third modified example.

[0131] In FIG. 29, the semiconductor chip CPL is configured in a rectangular shape in a plan view. The semiconductor chip CPL has a side SD1 which is a short side, a side SD2 which faces the side SD1, a side SD3 which is a long side intersecting the sides SD1 and SD2, and a side SD4 which faces the side SD3. At this time, the clip CLL has an extended portion which intersects with the long side SD4. As a result, in this modification 3, the x-direction width (width of the extended portion) of the clip CLL indicated by "L" in FIG. 29 can be made larger than those of the modification 1 and the modification 2. As a result, according to this modification 3, it is possible to increase the potential for reducing the on-resistance caused by the clip CLL.

[0132] <Variation 4> Next, a fourth modified example of the embodiment will be described.

[0133] FIG. 30 is a schematic diagram showing the configuration of the fourth modified example.

[0134] In FIG. 30, a main transistor source pad SPL is formed on the surface of a semiconductor chip CPL, and a trench DIT is provided so as to surround this main transistor source pad SPL in plan view.

[0135] FIG. 31 is a cross-sectional view taken along line AA in FIG.

[0136] In Fig. 31, a passivation film PAS having an opening is formed on the surface of the semiconductor chip CPL, and a part of the main transistor source pad SPL is exposed from this opening. A silver paste 60B is formed on the exposed main transistor source pad SPL, and a clip CLL is mounted on the silver paste 60B. Meanwhile, a polyimide resin film PIF is formed on the passivation film PAS, and a groove DIT is formed in this polyimide resin film PIF. This groove DIT is configured to be able to suppress the outflow of the silver paste 60B to the outside of the groove DIT.

[0137] According to the present modified example 4 configured in this manner, it is possible to obtain the same effect as the above-described embodiment in which the wall portion 100 is provided. That is, the groove DIT in the present modified example 4 is a component corresponding to the wall portion 100 in the above-described embodiment, and this groove DIT can suppress the silver paste 60B from spilling out of the groove DIT, and can also suppress a change in the "sense ratio" due to a positional deviation of the clip.

[0138] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0139] For example, in the above embodiment, it has been described that the planar shape of the semiconductor device PKG and each semiconductor chip is rectangular, but depending on the planar shape and size of each semiconductor chip, the planar shape of the semiconductor device PKG may be square.

[0140] In addition, in the semiconductor device PKG of the above embodiment, the wall portion 100 is formed on the passivation film (i.e., inorganic insulating film) PAS consisting of 1) a silicon oxide film, 2) a silicon nitride film, or 3) a laminated film of a silicon oxide film and a silicon nitride film. However, as shown in FIG. 32 (Modification 5), an organic insulating film 200 such as a polyimide resin film may be interposed between the wall portion 100 and the passivation film PAS. The organic insulating film 200 interposed between the wall portion 100 and the passivation film PAS is formed in a process different from the process of forming the wall portion 100. The thickness of the organic insulating film 200 interposed between the wall portion 100 and the passivation film PAS is, for example, about 10 μm. Therefore, in the case of a polyimide resin film having such a thickness, there is a risk that the silver paste applied on the source pad will overflow from the source pad. This is because a sufficient amount of silver paste must be used to reliably cover the entire exposed surface of the source pad with silver paste, and in this case, the thickness of the applied (supplied) silver paste is thicker than the thickness of the organic insulating film 200, which is 10 μm. As a result, if the organic insulating film 200 is simply formed on the passivation film PAS, the highly fluid silver paste may overflow from the source pad. On the other hand, the thickness of the wall portion 100 in this embodiment is sufficiently thicker than the thickness of the organic insulating film 200 and the thickness of the supplied silver paste, so that overflow of the silver paste supplied onto the source pad can be suppressed. [Explanation of symbols]

[0141] 10 High-side switching circuit 11 Main transistor 12 Sense transistor 20 Low-side switching circuit 21 Main transistor 22 Sense transistor 30 Control circuit 31 Sense circuit 50A adhesive 50B Adhesive 60A Silver Paste 60B Silver Paste 100 wall 200 Organic insulating film CL coil CLH Clip CLL Clip CPC Semiconductor Chip CPH Semiconductor Chip CPL Semiconductor Chip CT control circuit DIT groove DPC Die Pad DPH Die Pad DPL Die Pad INV Inverter circuit LD Lead LDH Lead LDL Lead LES Exposed surface LF Lead Frame MOT motor MR sealed body OP1 opening OP2 opening PAS passivation film PDC1 Pad PDC2 Pad PDH Pad PDL Pad PIF Polyimide resin film RA area PKG Semiconductor device S1 side S2 side S3 side S4 side SD1 side SD2 side SD3 side SD4 side SPH Main transistor source pad SPL Source pad for main transistor SUB Semiconductor Substrate

Claims

1. A chip mounting portion; a semiconductor chip mounted on the chip mounting portion; a clip mounted on the semiconductor chip via a first silver paste; Equipped with The semiconductor chip comprises: a passivation film having an opening; a first pad having a portion exposed from the opening; a second pad different from the first pad; a third pad different from each of the first pad and the second pad; a wall portion provided on the passivation film and surrounding the first pad in a plan view; having In a plan view, the first pad and the second pad are separated by the wall portion, The semiconductor chip comprises: A first side intersecting with a pull-out portion of the clip; a second side opposite to the first side; a third side intersecting the first side and the second side; and a fourth side opposite to the third side; having a first pad group including the second pads is disposed at an intersection of the first side and the third side, a second pad group including the third pad is disposed at an intersection of the second side and the third side, In a cross-sectional view, a thickness of the wall portion is greater than a thickness of the passivation film, an entire exposed surface of the first pad exposed from the passivation film is covered with the first silver paste; The first silver paste connecting the first pad and the clip is confined within an area surrounded by the wall portion in a plan view.

2. 2. The semiconductor device according to claim 1, The first silver paste is in contact with the wall portion.

3. 2. The semiconductor device according to claim 1, The wall portion has a portion that overlaps with each of the second pads in a plan view.

4. 2. The semiconductor device according to claim 1, A bonding wire is connected to the second pad.

5. 2. The semiconductor device according to claim 1, The semiconductor chip includes: A main transistor that conducts current; a sense transistor for detecting a current value of the current; is formed, the first pad is a source pad for a main transistor; The second pad is a source pad for a sense transistor.

6. 2. The semiconductor device according to claim 1, The second pad is disposed at an intersection of the second side and the third side.

7. 2. The semiconductor device according to claim 1, The semiconductor chip has a rectangular planar shape, The semiconductor chip comprises: A first side which is a short side; a second side opposite to the first side; a third side which is a long side intersecting the first side and the second side; a fourth side opposite to the third side; having The fourth side intersects with a pull-out portion of the clip.

8. 6. The semiconductor device according to claim 5, the main transistor and the sense transistor are vertical trench power transistors that pass the current in a thickness direction of the semiconductor chip.

9. 2. The semiconductor device according to claim 1, The wall portion is made of an organic insulating film.

10. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the clip is made of copper.

11. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the thickness of the wall portion is greater than 10 μm and less than or equal to 90 μm.

12. 2. The semiconductor device according to claim 1, the semiconductor chip further includes an organic insulating film provided on the passivation film, the wall portion is provided on the organic insulating film, In a cross-sectional view, the thickness of the wall portion is greater than the thickness of each of the passivation film and the organic insulating film.

13. 13. The semiconductor device according to claim 12, The semiconductor device, wherein the thickness of the wall portion is greater than 10 μm and less than or equal to 90 μm.

14. 14. The semiconductor device according to claim 13, The wall portion is made of an organic insulating film.

Images