Semiconductor Device

Abstract

A semiconductor device is provided with: a substrate having a circuit pattern and including a first circuit board and a second circuit board positioned at a distance from the first circuit board; a semiconductor chip that is positioned on the first circuit board and in which a current flows in the thickness direction; a capacitor connecting the first circuit board and the second circuit board. The semiconductor chip includes: a semiconductor layer; a first electrode pad positioned on one side, with respect to the thickness direction, of the semiconductor layer so as to face the first circuit board; and a second electrode pad positioned on the other side, with respect to the thickness direction, of the semiconductor layer. The semiconductor device further includes a first wire connecting the second electrode pad and the second circuit board.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device.

[0002] This application claims priority to Japanese Application No. 2020-83681, filed on May 12, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] In a semiconductor device including a capacitor for absorbing surge voltage, a fuse may be disposed to protect an external device connected to the semiconductor device. According to Patent Document 1, a fuse is disposed on a P-side connection terminal. According to Patent Document 2, a fuse is formed in a part of a substrate pattern located outside a semiconductor module. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-225612 A [Patent Document 2] International Publication No. 2015 / 049736 Summary of the Invention

[0005] A semiconductor device according to the present disclosure includes a substrate having a circuit pattern including a first circuit plate and a second circuit plate spaced apart from the first circuit plate, a semiconductor chip arranged on the first circuit plate and through which a current flows in the thickness direction, and a capacitor connecting the first circuit plate and the second circuit plate. The semiconductor chip includes a semiconductor layer, a first electrode pad arranged on one side in the thickness direction of the semiconductor layer so as to face the first circuit plate, and a second electrode pad arranged on the other side in the thickness direction of the semiconductor layer. The semiconductor device further includes a first wire connecting the second electrode pad and the second circuit plate. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a part of a semiconductor device in a first embodiment as viewed in a thickness direction of a substrate. [Diagram 2] FIG. 2 is an enlarged cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 3 is an enlarged cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of a part of the semiconductor device in the second embodiment as viewed in the thickness direction of the substrate. [Diagram 5] FIG. 5 is an equivalent circuit diagram of a part of the semiconductor device according to the third embodiment. [Figure 6] FIG. 6 is a schematic plan view of a part of a semiconductor device in accordance with the fourth embodiment as viewed in the thickness direction of a substrate. [Figure 7] FIG. 7 is a schematic plan view of a part of a semiconductor device in accordance with the fifth embodiment as viewed in the thickness direction of a substrate. [Figure 8] FIG. 8 is a schematic perspective view showing the appearance of a semiconductor device according to the fifth embodiment. [Figure 9] FIG. 9 is an enlarged view of a part of the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a schematic plan view of a part of a semiconductor device in accordance with the sixth embodiment as viewed in the thickness direction of a substrate. [Figure 11] FIG. 11 is a schematic plan view of a part of a semiconductor device in the seventh embodiment as viewed in the thickness direction of a substrate. [Figure 12] FIG. 12 is a schematic plan view of a part of the semiconductor device in the eighth embodiment as viewed in the thickness direction of the substrate. [Figure 13] FIG. 13 is an equivalent circuit diagram of a part of the semiconductor device according to the ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] [Problem that this disclosure aims to solve] In the techniques disclosed in Patent Documents 1 and 2, the distance between the semiconductor chip and the capacitor included in the semiconductor device becomes long, making it difficult to reduce the inductance. In semiconductor devices, reduction in inductance is required. In addition, if an excessive current flows in the circuit of the semiconductor device and the capacitor shorts out, an excessive current may flow in a device connected to the semiconductor device, damaging the device. It is necessary to suppress damage to the device connected to the semiconductor device.

[0008] Therefore, an object of the present invention is to provide a semiconductor device that can reduce inductance while suppressing damage to devices connected to the semiconductor device.

[0009] [Effects of this disclosure] According to the semiconductor device, it is possible to reduce the inductance while suppressing damage to devices connected to the semiconductor device.

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes a substrate having a circuit pattern including a first circuit plate and a second circuit plate spaced apart from the first circuit plate, a semiconductor chip arranged on the first circuit plate and through which a current flows in the thickness direction, and a capacitor connecting the first circuit plate and the second circuit plate. The semiconductor chip includes a semiconductor layer, a first electrode pad arranged on one side in the thickness direction of the semiconductor layer so as to face the first circuit plate, and a second electrode pad arranged on the other side in the thickness direction of the semiconductor layer. The semiconductor device further includes a first wire connecting the second electrode pad and the second circuit plate.

[0011] According to the semiconductor device of the present disclosure, the capacitor is connected to the first circuit plate and the second circuit plate. Thus, the capacitor is electrically connected in parallel to the semiconductor chip to form a snubber circuit, which can absorb surge voltage. In the semiconductor device, the capacitor can be disposed near the semiconductor chip, and inductance can be reduced. The semiconductor device includes a first wire connecting the second electrode pad and the second circuit plate. Thus, the first wire can be electrically connected in series to the capacitor, and the first wire can function as a fuse. Then, when an excessive current flows in the circuit of the semiconductor device and the capacitor is shorted, the first wire connected in series to the capacitor melts. Therefore, the circuit including the capacitor can be opened, and excessive current can be prevented from flowing to the device connected to the semiconductor device. As a result, damage to the device connected to the semiconductor device can be suppressed. As described above, according to the semiconductor device, inductance can be reduced while preventing damage to the device connected to the semiconductor device.

[0012] The semiconductor device may include a plurality of capacitors, which increases the total capacitance of the capacitors and further enhances the effect of absorbing surge voltages.

[0013] In the semiconductor device, the capacitor may be a multilayer ceramic capacitor, which has excellent heat resistance and is therefore particularly effective when a large amount of heat is generated from the semiconductor chip.

[0014] In the semiconductor device, the semiconductor chip may include a semiconductor layer made of SiC or GaN. Such a semiconductor chip is capable of high-speed switching, but generates a large surge voltage. Since the semiconductor device can absorb the surge voltage while reducing inductance, the semiconductor chip is preferably used in the semiconductor device.

[0015] The semiconductor device may include a plurality of semiconductor chips. The plurality of semiconductor chips may be electrically arranged in series. In this manner, a surge voltage can be efficiently absorbed in a circuit including the plurality of semiconductor chips.

[0016] The semiconductor device may further include a first resistor electrically connected in series with the capacitor. Such a semiconductor device includes an RC snubber circuit formed by the capacitor and the first resistor in its circuit, and can absorb surge voltages.

[0017] In the above semiconductor device, the semiconductor chip may be a transistor chip. The second electrode pad may be a source electrode pad. The circuit pattern may further include a third circuit plate arranged at a distance from each of the first circuit plate and the second circuit plate. The semiconductor device may further include a second wire connecting the source electrode pad and the third circuit plate, and a third wire connected to the gate electrode pad of the semiconductor chip. The diameter of the first wire may be the same as the diameter of at least one of the second wire and the third wire. In this way, when connecting each part using the second wire or the third wire, the connection using the first wire can also be performed. Therefore, the number of types of wires can be reduced, and efficient manufacturing can be achieved.

[0018] The semiconductor device may further include a housing including a frame surrounding the substrate, a first terminal electrically connected to either the first circuit board or the third circuit board and disposed outside the housing, and a second terminal electrically connected to the second circuit board and disposed outside the housing. When an excessive current flows in the circuit of the semiconductor device and the capacitor is shorted, the first wire connected in series with the capacitor melts. When the first wire melts, the circuit including the capacitor can be opened, and excessive current can be prevented from flowing to the device connected to the semiconductor device. Here, although excessive current can be prevented from flowing to the device connected to the semiconductor device due to melting of the first wire, it is difficult to detect whether the first wire has melted from the outside of the semiconductor device. Therefore, a user who uses the semiconductor device may continue to use the semiconductor device without knowing that the first wire is melted. In this case, the semiconductor device continues to operate in a state in which the circuit including the capacitor cannot absorb the surge voltage because the circuit including the capacitor is open. As a result, when a surge voltage occurs, the capacitor cannot absorb the surge voltage, and the reliability of the semiconductor device decreases.

[0019] The semiconductor device of the above configuration includes a first terminal electrically connected to either the first circuit plate or the third circuit plate, and a second terminal electrically connected to the second circuit plate. The first terminal is electrically connected to the source electrode side or the drain electrode side. On the other hand, the second terminal is electrically connected to the source electrode side before the first wire is fused, and is electrically connected to the drain electrode side after the first wire is fused. Therefore, the potential difference between the first terminal and the second terminal changes before and after the first wire is fused. Therefore, by monitoring the potential difference between the first terminal and the second terminal and detecting a change in the potential difference between the first terminal and the second terminal, it is possible to know that the first wire has been fused. Since the first terminal and the second terminal are each disposed outside the housing, it is easy to electrically connect each of the first terminal and the second terminal to a device that measures the potential difference and monitor the potential difference. Therefore, according to such a semiconductor device, it is easy to know whether the first wire has been fused or not, and it is possible to determine whether the operation of the semiconductor device should be continued. As a result, it is possible to improve reliability.

[0020] In the semiconductor device, the first terminal may be either an independent terminal or a source terminal. In this way, either terminal can be used as the first terminal, resulting in a simpler configuration.

[0021] The semiconductor device may further include a second resistor electrically connected to the second terminal, whereby the resistance value of the second resistor can be adjusted to detect a more appropriate potential difference between the first terminal and the second terminal.

[0022] In the semiconductor device, the second resistor may be formed within a circuit constituting the second circuit board, which makes it easier to manufacture the semiconductor device including the second resistor.

[0023] The semiconductor device may further include a detection unit that detects a potential difference between the first terminal and the second terminal. In this way, it is possible to know whether the first wire has been blown or not according to a detection result by the detection unit. Therefore, it is possible to more reliably determine whether the first wire has been blown or not.

[0024] The semiconductor device of the present disclosure includes a substrate having a circuit pattern including a first circuit plate, a second circuit plate spaced apart from the first circuit plate, and a third circuit plate spaced apart from each of the first and second circuit plates, a semiconductor chip arranged on the first circuit plate and through which a current flows in the thickness direction, and a capacitor connecting the first and second circuit plates. The semiconductor chip is a transistor chip including a semiconductor layer, a drain electrode pad arranged on one side in the thickness direction of the semiconductor layer so as to face the first circuit plate, and a source electrode pad arranged on the other side in the thickness direction of the semiconductor layer. The semiconductor device further includes a first wire connecting the source electrode pad and the second circuit plate, a second wire connecting the source electrode pad and the third circuit plate, a housing including a frame surrounding the substrate, a first terminal electrically connected to either the first circuit plate or the third circuit plate and arranged outside the housing, and a second terminal electrically connected to the second circuit plate and arranged outside the housing.

[0025] Such a semiconductor device includes a first terminal electrically connected to either the first circuit plate or the third circuit plate, and a second terminal electrically connected to the second circuit plate. The first terminal is electrically connected to the source electrode side or the drain electrode side. On the other hand, the second terminal is electrically connected to the source electrode side before the first wire is fused, and is electrically connected to the drain electrode side after the first wire is fused. Then, the potential difference between the first terminal and the second terminal changes before and after the first wire is fused. Therefore, by monitoring the potential difference between the first terminal and the second terminal and detecting the change in the potential difference between the first terminal and the second terminal, it is possible to know that the first wire has been fused. Since the first terminal and the second terminal are each disposed outside the housing, it is easy to electrically connect each of the first terminal and the second terminal to a device that measures the potential difference and monitor the potential difference. Therefore, according to such a semiconductor device, it is easy to know whether the first wire has been fused or not, and it is possible to determine whether the operation of the semiconductor device should be continued. As a result, it is possible to improve reliability.

[0026] [Details of the embodiment of the present disclosure] Next, an embodiment of a semiconductor device according to the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0027] (Embodiment 1) The configuration of a semiconductor device according to a first embodiment of the present disclosure will be described. Fig. 1 is a schematic plan view of a part of the semiconductor device according to the first embodiment as viewed in the thickness direction of a substrate. Fig. 2 is an enlarged cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is an enlarged cross-sectional view taken along line III-III in Fig. 1. For ease of understanding, a capacitor and a first wire are illustrated in Fig. 2.

[0028] With reference to Figures 1, 2 and 3, a semiconductor device 11a in embodiment 1 includes a heat sink 12, a first bonding material 13a, a substrate 14a, a second bonding material 13b, a transistor chip 23a, a capacitor 31a, a first wire 29a, a second wire 29b, and a third wire 29c.

[0029] The heat sink 12 is made of metal. The heat sink 12 is made of, for example, copper. The surface of the heat sink 12 may be nickel-plated. A first bonding material 13a is disposed on one surface 12a in the thickness direction of the heat sink 12. The material of the first bonding material 13a may be, for example, solder, specifically, Sn-Ag-Cu solder or Sn-Sb solder.

[0030] The substrate 14a is bonded to the heat sink 12 by a first bonding material 13a. The substrate 14a includes a conductive circuit pattern 15a, an insulating plate 21 having insulating properties, and a metal plate 22. The circuit pattern 15a is disposed on one surface of the insulating plate 21 in the thickness direction, and the metal plate 22 is disposed on the other surface of the insulating plate 21 in the thickness direction. That is, the substrate 14a is configured by laminating the metal plate 22, the insulating plate 21, and the circuit pattern 15a.

[0031] The metal plate 22 is made of, for example, copper. The insulating plate 21 is made of, for example, ceramic. Examples of the material of the insulating plate 21 include Al2O3, AlN, and Si3N4. In this embodiment, the circuit pattern 15a is copper wiring. The thickness direction of the heat sink 12 and the thickness direction of the substrate 14a are both Z directions. The circuit pattern 15a includes a first circuit plate 16a, a second circuit plate 16b, and a third circuit plate 16c that are spaced apart from each other. The first circuit plate 16a and the third circuit plate 16c, and the second circuit plate 16b and the third circuit plate 16c are spaced apart from each other in the Y direction. The first circuit plate 16a is electrically connected to, for example, a P terminal (not shown) included in the semiconductor device 11a, and the third circuit plate 16c is electrically connected to an O terminal (not shown) included in the semiconductor device 11a.

[0032] The transistor chip 23a is a wide band gap semiconductor chip. Specifically, the transistor chip 23a includes a semiconductor layer made of SiC. The transistor chip 23a is, for example, a metal-oxide-semiconductor field effect transistor (MOSFET). The transistor chip 23a is a vertical transistor chip. That is, the transistor chip 23a is a transistor chip in which a current flows in the thickness direction (Z direction).

[0033] The transistor chip 23a includes a semiconductor layer 24a, a drain electrode pad 25a (see FIG. 2 in particular) as a first electrode pad arranged on one side of the semiconductor layer 24a in the thickness direction, a source electrode pad 26a as a second electrode pad arranged on the other side of the semiconductor layer 24a in the thickness direction, and a gate electrode pad 27a as a third electrode pad arranged on the other side of the semiconductor layer 24a in the thickness direction. The source electrode pad 26a and the gate electrode pad 27a are arranged at different positions when viewed in the thickness direction of the substrate 14a. The drain electrode pad 25a of the transistor chip 23a and the first circuit board 16a are joined by a second bonding material 13b. The source electrode pad 26a of the transistor chip 23a is electrically connected to the third circuit board 16c by a second wire 29b also called a source wire. A plurality of second wires 29b are provided. The gate electrode pad 27a of the transistor chip 23a is electrically connected to a gate terminal (not shown) included in the semiconductor device 11a by a third wire 29c also called a gate wire.

[0034] The semiconductor device 11a includes a resin portion 19 that fills a space surrounded by a frame body (not shown). The resin portion 19 is made of, for example, epoxy resin. In FIG. 1, the resin portion 19 is not shown. The frame body is attached to the heat sink 12 and is disposed so as to surround the substrate 14a. The frame body and the heat sink 12 form a housing (not shown) of the semiconductor device 11a. That is, the housing includes the frame body and the heat sink 12.

[0035] The capacitor 31a is disposed in a space surrounded by the frame. For example, a multilayer ceramic capacitor is used as the capacitor 31a. The heat-resistant temperature of the multilayer ceramic capacitor is 150° C. or less. The multilayer ceramic capacitor has good heat resistance. The capacitor 31a includes a plurality of layered ceramic internal layers 32a, a plurality of internal electrodes 33a, and a pair of external electrodes 34a, 35a. In this embodiment, the multiple internal layers 32a are stacked in the Z direction. A plurality of internal electrodes 33a connected to one of the external electrodes 34a, 35a are alternately disposed in the Z direction between the layered internal layers 32a.

[0036] The external electrode 34a and the first circuit plate 16a of the circuit pattern 15a are electrically connected. Specifically, the external electrode 34a and the first circuit plate 16a are joined by a third bonding material 13c made of, for example, solder. The external electrode 35a and the second circuit plate 16b of the circuit pattern 15a are electrically connected. Specifically, the external electrode 35a and the second circuit plate 16b are joined by a third bonding material 13c. The capacitor 31a is electrically connected in parallel with the transistor chip 23a. Specifically, the capacitor 31a is connected to the circuit pattern 15a such that the external electrode 34a is the drain side of the transistor chip 23a and the external electrode 35a is the source side of the transistor chip 23a.

[0037] Here, the semiconductor device 11a includes a first wire 29a that connects the source electrode pad 26a, which is the second electrode pad, to the second circuit plate 16b of the circuit pattern 15a. The first wire 29a electrically connects the source electrode pad 26a, which is the second electrode pad, to the second circuit plate 16b of the circuit pattern 15a. That is, the second circuit plate 16b to which the external electrode 35a is connected has the same potential as the source electrode pad 26a. The capacitor 31a is electrically connected in parallel to the transistor chip 23a, with the external electrode 34a serving as the drain side and the external electrode 35a serving as the source side. The capacitor 31a and the first wire 29a are electrically connected in series.

[0038] The diameter of the first wire 29a is the same as the diameter of at least one of the second wire 29b and the third wire 29c. In this embodiment, the first wire 29a, the second wire 29b, and the third wire 29c all have the same diameter. The first wire 29a, the second wire 29b, and the third wire 29c are also made of the same material. That is, the same wire is used for the first wire 29a, the second wire 29b, and the third wire 29c. The diameter of the first wire 29a is selected according to requirements because the melting current differs depending on the rated current of the transistor chip 23a, the material of the resin part 19, and the like.

[0039] Next, the manufacturing process of the semiconductor device 11a will be briefly described. After bonding the substrate 14a, the transistor chip 23a, and the capacitor 31a on the heat sink 12 with the first bonding material 13a, wire bonding is performed. Specifically, the source electrode pad 26a is bonded to the second circuit board 16b with the first wire 29a. The source electrode pad 26a is bonded to the third circuit board 16c with the second wire 29b. The gate electrode pad 27a is bonded to the gate terminal with the third wire 29c. Thereafter, the space in which the transistor chip 23a and the capacitor 31a are arranged is sealed with the resin part 19 to manufacture the semiconductor device 11a.

[0040] Next, an example of the current flow during operation of the semiconductor device 11a will be briefly described. When the transistor chip 23a is turned on, a current flows from the P terminal through the first circuit plate 16a of the circuit pattern 15a, the on-state transistor chip 23a, the second wire 29b, and the third circuit plate 16c of the circuit pattern 15a to the O terminal.

[0041] In the semiconductor device 11a, the capacitor 31a is connected to the first circuit board 16a and the second circuit board 16b. Thus, the capacitor 31a is electrically connected in parallel to the transistor chip 23a to form a snubber circuit, which can absorb surge voltage. In the semiconductor device 11a, the capacitor 31a can be disposed near the transistor chip 23a, and inductance can be reduced. The semiconductor device 11a includes a first wire 29a that connects the source electrode pad 26a, which is the second electrode pad, to the second circuit board 16b. Thus, the first wire 29a can be electrically connected in series to the capacitor 31a, and the first wire 29a can function as a fuse. Then, when an excessive current flows in the circuit of the semiconductor device 11a and the capacitor 31a is shorted, the first wire 29a connected in series to the capacitor 31a melts. Thus, the circuit including the capacitor 31a can be opened, and excessive current can be prevented from flowing to the device connected to the semiconductor device 11a. As a result, damage to the device connected to the semiconductor device 11a can be prevented. As described above, according to the semiconductor device 11a, it is possible to reduce the inductance while suppressing damage to devices connected to the semiconductor device 11a.

[0042] In this embodiment, the capacitor 31a is a multilayer ceramic capacitor. A multilayer ceramic capacitor has excellent heat resistance. Therefore, it is particularly effective when the heat generated from the transistor chip 23a is large. In this embodiment, the transistor chip 23a includes a semiconductor layer made of SiC, and therefore generates a large amount of heat during operation. Therefore, a multilayer ceramic capacitor is preferably used in the semiconductor device 11a.

[0043] In this embodiment, the transistor chip 23a includes a semiconductor layer made of SiC. That is, the transistor chip 23a is a SiC transistor chip. Such a SiC transistor chip is capable of high-speed switching, but generates a large surge voltage. The semiconductor device 11a can absorb the surge voltage while reducing inductance, so the transistor chip 23a is suitably used for the semiconductor device 11a.

[0044] In this embodiment, the diameter of the first wire 29a is the same as the diameter of the second wire 29b and the diameter of the third wire 29c. Therefore, when connecting each part using the second wire 29b and the third wire 29c, the connection can also be made using the first wire 29a. Therefore, the semiconductor device 11a can reduce the number of types of wires and can be efficiently manufactured.

[0045] The double pulse switching effect was verified by simulation in two cases: when the first wire 29a functioning as a fuse was directly connected to the source electrode pad 26a, and when the first wire 29a was directly connected to the third circuit board 16c, i.e., when the source electrode pad 26a and the second circuit board 16b were not directly connected. For the simulation, LTspice was used as software. The simulation conditions were a voltage of 850V, a current of 150A, and a resistance of 3.3 ohms. In the configuration of the semiconductor device 11a, i.e., when the first wire 29a was directly connected to the source electrode pad 26a, ringing was less than when the first wire 29a was not directly connected to the source electrode pad 26a.

[0046] (Embodiment 2) Next, a second embodiment, which is another embodiment, will be described. Fig. 4 is a schematic plan view of a part of a semiconductor device in the second embodiment, as viewed in the thickness direction of a substrate. The semiconductor device in the second embodiment differs from the first embodiment in that it includes two capacitors.

[0047] 4, semiconductor device 11b in the second embodiment includes a plurality of capacitors, in the present embodiment, two capacitors 31a and 31b. Capacitor 31b has the same configuration as capacitor 31a. Capacitor 31b is electrically connected in parallel with both transistor chip 23a and capacitor 31a. That is, external electrode 34b is connected to first circuit board 16a, and external electrode 35b is connected to second circuit board 16b.

[0048] The semiconductor device 11b of this embodiment can increase the total capacitance of the capacitors 31a, 31b. Therefore, the semiconductor device 11b is a semiconductor device that can further enhance the effect of absorbing surge voltage. In particular, when a multilayer ceramic capacitor is used as the capacitors 31a, 31b, it is advantageous from the viewpoint of heat resistance, but is disadvantageous from the viewpoint of capacitance. Therefore, depending on the required characteristics of the semiconductor device 11b, particularly the capacitance, it is possible to increase the number of capacitors 31a, 31b electrically connected in parallel with the transistor chip 23a. The semiconductor device 11b may include three or more capacitors.

[0049] (Embodiment 3) Next, a third embodiment, which is yet another embodiment, will be described. Fig. 5 is an equivalent circuit diagram of a part of a semiconductor device in the third embodiment. The semiconductor device in the third embodiment differs from the first embodiment in that it includes two transistor chips and includes a resistor in the circuit.

[0050] 5, the semiconductor device 11c in the third embodiment includes a plurality of transistor chips 23a and 23b (two in the present embodiment), a capacitor 31a, and a first resistor 36a. The first resistor 36a is electrically connected in series with the capacitor 31a. The transistor chips 23a and 23b are electrically connected in series. In the semiconductor device 11c, the capacitor 31a and the first resistor 36a are electrically connected in series to form an RC snubber circuit.

[0051] Even with such a semiconductor device 11c, it is possible to reduce the inductance while suppressing damage to devices connected to the semiconductor device 11c. Such a semiconductor device 11c can efficiently absorb surge voltages by including an RC snubber circuit formed of a capacitor 31a and a first resistor 36a in a circuit including a plurality of transistor chips 23a and 23b. The semiconductor device 11b may include three or more transistor chips.

[0052] (Embodiment 4) Next, a fourth embodiment, which is yet another embodiment, will be described. Fig. 6 is a schematic plan view of a part of a semiconductor device in the fourth embodiment, as viewed in the thickness direction of a substrate. The semiconductor device in the fourth embodiment differs from the first embodiment in that it includes two transistor chips on one power supply line.

[0053] 6, the circuit pattern 15b included in the semiconductor device 11d includes a fourth circuit board 16d. The fourth circuit board 16d is disposed at intervals from each of the first circuit board 16a, the second circuit board 16b, and the third circuit board 16c. The semiconductor device 11d in the fourth embodiment includes two transistor chips 23a and 23c. The transistor chip 23c includes a semiconductor layer, a drain electrode disposed on one side in the thickness direction of the semiconductor layer so as to face the fourth circuit board 16d, a source electrode pad 26b disposed on the other side in the thickness direction of the semiconductor layer, and a gate electrode pad 27b disposed on the other side in the thickness direction of the semiconductor layer and to which a gate wire, which is a third wire 29e, is connected. The external electrode 34a of the capacitor 31a is connected to the fourth circuit board 16d. The source wire, which is a second wire 29d, connects the source electrode pad 26b of the transistor chip 23c to the first circuit board 16a.

[0054] Even with such a semiconductor device 11d, it is possible to reduce inductance while suppressing damage to devices connected to the semiconductor device 11d. In such a semiconductor device 11d, a snubber circuit can be configured that is collectively attached to the power supply line formed by the transistor chips 23a and 23c.

[0055] (Embodiment 5) Next, a fifth embodiment, which is yet another embodiment, will be described. FIG. 7 is a schematic plan view of a part of the semiconductor device in the fifth embodiment, seen in the thickness direction of the substrate. FIG. 8 is a schematic perspective view showing the appearance of the semiconductor device in the fifth embodiment. FIG. 9 is an enlarged view of a part of the semiconductor device shown in FIG. 8. In FIG. 7, the boundary between the inside and the outside of the housing, which will be described later, is shown by a dashed line. Also, the illustration of the first end and the second end in FIG. 7 is schematic, and the positions of the first end and the second end are shown in FIG. 8 and FIG. 9. Also, in order to facilitate understanding, the illustration of the resin part 19 is omitted in FIG. 9. The semiconductor device in the fifth embodiment is different from the first embodiment in that it includes a first terminal and a second terminal, which will be described later.

[0056] 7, 8 and 9, the semiconductor device 11e in the fifth embodiment includes a housing 39 including the heat sink 12 and a frame 38, a substrate 14a having a circuit pattern 15a including a first circuit board 16a, a second circuit board 16b and a third circuit board 16c, a transistor chip 23a, a capacitor 31a, a resin part 19, a first wire 29a, a second wire 29b and a third wire 29c. The frame 38 is attached to the heat sink 12 and is disposed so as to surround the substrate 14a. The frame 38 and the heat sink 12 constitute the housing 39 of the semiconductor device 11a. The resin part 19 fills the space surrounded by the frame 38. The first wire 29a connects the source electrode pad 26a, which is the second electrode pad of the transistor chip 23a, to the second circuit board 16b. The second wire 29b connects the source electrode pad 26a and the third circuit plate 16c. A plurality of second wires 29b are provided. The third wire 29c connects the gate electrode pad 27a, which is the third electrode pad of the transistor chip 23a, to the gate terminal.

[0057] The semiconductor device 11e includes a first terminal 41e and a second terminal 42e. The first terminal 41e and the second terminal 42e are disposed outside the housing 39. In this embodiment, the first terminal 41e and the second terminal 42e are disposed so as to protrude from the end surface 40 on the upper side of the frame body 38 with a gap in the X direction. The first terminal 41e is electrically connected to the third circuit board 16c. Specifically, a connection portion 43e electrically connected to the first terminal 41e and disposed in the housing 39 is electrically connected to the third circuit board 16c by a wire 44e. In this embodiment, the first terminal 41e is an independent terminal. Alternatively, the first terminal 41e may be a source terminal. The second terminal 42e is an independent terminal and is electrically connected to the second circuit board 16b. Specifically, a connection portion 45e, which is electrically connected to the second terminal 42e and disposed within the housing 39, is electrically connected to the second circuit board 16b by a wire 46e.

[0058] The first terminal 41e is electrically connected to the source electrode side. The second terminal 42e is electrically connected to the source electrode side before the first wire 29a is fused. The second terminal 42e is electrically connected to the drain electrode side after the first wire 29a is fused. Therefore, the potential difference between the first terminal 41e and the second terminal 42e changes before and after the first wire 29a is fused. The user of the semiconductor device 11e constantly or periodically measures the potential difference between the first terminal 41e and the second terminal 42e using a tester or the like that measures the potential difference to detect the potential difference between the first terminal 41e and the second terminal 42e.

[0059] According to the semiconductor device 11a having such a configuration, by monitoring the potential difference between the first terminal 41e and the second terminal 42e and detecting a change in the potential difference between the first terminal 41e and the second terminal 42e, it is possible to know that the first wire 29a has been blown. In this embodiment, the first terminal 41e is electrically connected to the third circuit board 16c which is the source electrode side, and the second terminal 42e is electrically connected to the second circuit board 16b which is the source electrode side before the first wire 29a is blown. Therefore, before the first wire 29a is blown, the potential difference between the first terminal 41e and the second terminal 42e is in a non-existent state (0V). Here, when the first wire 29a is blown, the second circuit board 16b is electrically connected to the drain electrode side, so that the potential difference between the first terminal 41e and the second terminal 42e becomes the potential difference applied between the source and drain. Therefore, if it is detected that the potential difference between the first terminal 41e and the second terminal 42e has changed from a non-existent state to a potential difference applied between the source and drain, it can be determined that the first wire 29a has melted. In addition, since the first terminal 41e and the second terminal 42e are each disposed outside the housing 39, it is easy to electrically connect each of the first terminal 41e and the second terminal 42e to a device for measuring the potential difference and monitor the potential difference. Therefore, it is easy to monitor the potential difference between the first terminal 41e and the second terminal 42e. Therefore, according to such a semiconductor device 11e, it is easy to know whether the first wire 29a has melted or not, and it is possible to determine whether the operation of the semiconductor device 11e should be continued or not. As a result, it is possible to improve reliability.

[0060] In this embodiment, the first terminal 41e may be a source terminal. In this way, the source terminal can be used as the first terminal 41e, which allows for a simpler configuration.

[0061] (Embodiment 6) Next, a sixth embodiment, which is yet another embodiment, will be described. Fig. 10 is a schematic plan view of a part of a semiconductor device in the sixth embodiment, viewed in the thickness direction of the substrate. The semiconductor device in the sixth embodiment differs from the fifth embodiment in that the first terminal 41e is electrically connected to the first circuit board 16a. That is, in the semiconductor device of the present disclosure, the first terminal 41e may be electrically connected to either the first circuit board 16a or the third circuit board 16c.

[0062] Referring to FIG. 10, the first terminal 41e arranged outside the housing 39 is electrically connected to the first circuit board 16a, not the third circuit board 16c. According to the semiconductor device 11f having such a configuration, by monitoring the potential difference between the first terminal 41e and the second terminal 42e and detecting a change in the potential difference between the first terminal 41e and the second terminal 42e, it is possible to grasp that the first wire 29a has been melted. In this embodiment, the first terminal 41e is electrically connected to the first circuit board 16a, which is the drain electrode side. The second terminal 42e is electrically connected to the second circuit board 16b, which is the source electrode side, before the first wire 29a is melted. Therefore, the potential difference between the first terminal 41e and the second terminal 42e is the potential difference applied between the source and drain. Here, when the first wire 29a is melted, the second circuit board 16b is electrically connected to the drain electrode side. Therefore, the potential difference between the first terminal 41e and the second terminal 42e becomes zero (0V). Therefore, if it is detected that the potential difference between the first terminal 41e and the second terminal 42e becomes zero based on the potential difference applied between the source and drain, it can be determined that the first wire 29a has melted. Therefore, with such a semiconductor device 11f, it can be easily determined whether the first wire 29a has melted, and it can be determined whether the operation of the semiconductor device 11f should be continued. As a result, reliability can be improved.

[0063] (Embodiment 7) Next, a seventh embodiment, which is yet another embodiment, will be described. Fig. 11 is a schematic plan view of a part of a semiconductor device in the seventh embodiment, viewed in the thickness direction of the substrate. The semiconductor device in the seventh embodiment differs from the fifth embodiment in that it includes a detection unit that detects the potential difference between the first terminal 41e and the second terminal 42e.

[0064] Referring to FIG. 11, the semiconductor device 11g of the seventh embodiment includes a first terminal 41e electrically connected to the third circuit board 16c, a second terminal 42e electrically connected to the second circuit board 16b, and a detection unit 49 that detects a potential difference between the first terminal 41e and the second terminal 42e. The detection unit 49 is connected to the first terminal 41e by a wiring 47e and to the second terminal 42e by a wiring 48e. The detection unit 49 is, for example, a tester capable of measuring a voltage. In this way, it is possible to grasp whether the first wire 29a has been melted or not according to the detection result by the detection unit 49. That is, in this embodiment, if it is detected that the potential difference detected by the detection unit 49 has changed from the potential difference applied between the source and drain to a state where there is no potential difference, it is possible to determine whether the first wire 29a has been melted or not. Therefore, it is possible to more reliably determine whether the first wire 29a has been melted or not.

[0065] (Embodiment 8) Next, an eighth embodiment, which is yet another embodiment, will be described. Fig. 12 is a schematic plan view of a part of a semiconductor device in the eighth embodiment, as viewed in the thickness direction of a substrate. The semiconductor device in the eighth embodiment differs from the fifth embodiment in that it includes a second resistor.

[0066] Referring to FIG. 12, the semiconductor device 11h of the eighth embodiment includes a second resistor 51 electrically connected to the second terminal 42e. The second resistor 51 is disposed between the second circuit board 16b and the fifth circuit board 16e included in the circuit pattern 15a of the semiconductor device 11h, and is electrically connected to the second circuit board 16b and the fifth circuit board 16e, respectively. The fifth circuit board 16e is electrically connected to the second terminal 42e by the fourth wire 29f. That is, the second circuit board 16b is electrically connected to the second terminal 42e through the second resistor 51. In this way, the resistance value of the second resistor 51 can be adjusted to detect the potential difference between the first terminal 41e and the second terminal 42e as a more appropriate potential difference. Specifically, for example, the potential difference between the first terminal 41e and the second terminal 42e can be made smaller than the potential difference applied between the source and the drain. Therefore, even when the potential difference applied between the source and drain is large, for example, from several hundred V to more than 1000 V, it can be detected as an appropriate potential difference, for example, several V. The value of the second resistor 51 is preferably set to a value 10 to 10,000 times the internal resistance of a tester that measures the potential difference between the first terminal 41e and the second terminal 42e, or more preferably set to a value 100 to 1000 times.

[0067] (Embodiment 9) Next, a ninth embodiment, which is yet another embodiment, will be described. Fig. 13 is an equivalent circuit diagram of a part of a semiconductor device in the ninth embodiment. In Fig. 13, first circuit board 16a, second circuit board 16b, and third circuit board 16c are shown roughly by dashed lines. The semiconductor device in the ninth embodiment differs from the eighth embodiment in that a second resistor is formed in a circuit constituting the second circuit board.

[0068] With reference to FIG. 13, the semiconductor device 11i of the ninth embodiment includes a power supply 53 that applies a potential difference between the source and the drain. The semiconductor device 11i also includes a second resistor 52 electrically connected to the second terminal 42e. The second resistor 52 is formed in a circuit that constitutes the second circuit board 16b. That is, the second circuit board 16b includes the second resistor 52. In this way, the second resistor 52 can be easily formed. That is, when forming the wiring in the second circuit board 16b, the wiring can be formed in a configuration that includes the second resistor 52. Then, when manufacturing the semiconductor device 11i, it is not necessary to provide a resistor between the second terminal 42e and the second circuit board 16b. Therefore, the semiconductor device 11i including the second resistor 52 can be easily manufactured.

[0069] (Other embodiments) In the above embodiment, the semiconductor device uses a multilayer ceramic capacitor as the capacitor, but the present invention is not limited to this and other capacitors, for example, a film capacitor, may be used.

[0070] In the above embodiment, the semiconductor chip included in the semiconductor device is a transistor chip, but the present invention is not limited to this. The semiconductor chip may be, for example, a diode chip, specifically, a Schottky barrier diode chip (SBD). In this case, for example, the first electrode pad is a cathode pad, and the second electrode pad is an anode pad. The semiconductor chip included in the semiconductor device may be an insulated gate bipolar transistor (IGBT).

[0071] In the above embodiment, the semiconductor chip includes a semiconductor layer made of SiC, but the present invention is not limited to this, and the semiconductor chip may include a semiconductor layer made of GaN. That is, the semiconductor chip may include a semiconductor layer made of SiC or GaN. The semiconductor device can absorb a surge voltage while reducing inductance, and therefore the semiconductor chip is preferably used for the semiconductor device.

[0072] In addition, in the above embodiment, the diameter of the first wire is the same as the diameter of the second wire and the diameter of the third wire, but this is not limited to this. When the diameter of the second wire and the diameter of the third wire are different, the diameter of the first wire may be the same as that of either one of them. That is, the diameter of the first wire may be the same as the diameter of at least one of the second wire and the third wire. In this way, when connecting each part using the second wire or the third wire, the connection by the first wire can also be performed. Therefore, the number of types of wires can be reduced, and efficient manufacturing can be achieved.

[0073] In the above embodiment, the first terminal 41e is an independent terminal, but the first terminal 41e may be either an independent terminal or a source terminal. By using the source terminal as the first terminal, a simpler configuration can be achieved. Furthermore, by providing the first terminal 41e and the second terminal 42e as independent terminals, the distance between the terminals can be easily shortened, and the detection circuit configuration for detecting the potential difference can be made small. Therefore, a simpler configuration can be achieved. Furthermore, the first terminal 41e may be the only terminal provided as an independent terminal, and the second terminal 42e may be shared with the drain terminal or source terminal of the main terminal. This can reduce the number of required terminals, resulting in a simpler configuration.

[0074] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0075] 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i Semiconductor device 12 Heat sink 12a side 13a 1st bonding material 13b Second bonding material 13c 3rd bonding material 14a Substrate 15a, 15b Circuit pattern 16a 1st circuit board 16b 2nd circuit board 16c 3rd circuit board 16d 4th circuit board 16e 5th circuit board 19 Resin part 21 Insulating plate 22 Metal plate 23a, 23b, 23c Transistor chips 24a Semiconductor layer 25a Drain electrode pad 26a, 26b Source electrode pad 27a, 27b Gate electrode pad 29a 1st Wire 29b, 29d Second Wire 29c, 29e 3rd wire 29f 4th wire 31a, 31b Capacitor 32a Ceramic 33a Internal electrode 34a,34b,35a,35b External electrode 36a The First Resistance 38 Frame 39 Case 40 End face 41e First terminal 42e 2nd terminal 43e,45e Connection 44e, 46e, 54e, 55e Wire 47e,48e Wiring 49 Detection section 51,52 The Second Resistance 53 Power supply

Claims

1. A semiconductor device comprising: a substrate having a circuit pattern including a first circuit board and a second circuit board spaced apart from the first circuit board; a semiconductor chip disposed on the first circuit board, through which a current flows in a thickness direction; a capacitor connecting the first circuit board and the second circuit board; The semiconductor chip comprises: A semiconductor layer; a first electrode pad disposed on one side of the semiconductor layer in a thickness direction so as to face the first circuit board; a second electrode pad disposed on the other side of the semiconductor layer in the thickness direction; The semiconductor device further includes a first wire connecting the second electrode pad and the second circuit plate.

2. A plurality of said capacitors are included, The semiconductor device according to claim 1 , wherein each of said plurality of capacitors connects said first circuit plate and said second circuit plate.

3. 3. The semiconductor device according to claim 1, wherein the capacitor is a multilayer ceramic capacitor.

4. The semiconductor device according to claim 1 , wherein the semiconductor layer is made of SiC or GaN.

5. A plurality of the semiconductor chips are included, The semiconductor device according to claim 1 , wherein the plurality of semiconductor chips are electrically connected in series.

6. The semiconductor device according to claim 1 , further comprising a first resistor electrically connected in series with the capacitor.

7. the semiconductor chip is a transistor chip, the second electrode pad is a source electrode pad, the circuit pattern further includes a third circuit board spaced apart from each of the first circuit board and the second circuit board; The semiconductor device includes: a second wire connecting the source electrode pad and the third circuit board; a third wire connected to a gate electrode pad of the semiconductor chip; The semiconductor device according to claim 1 , wherein a diameter of the first wire is the same as a diameter of at least one of the second wire and the third wire.

8. The semiconductor device includes: a housing including a frame surrounding the substrate; a first terminal electrically connected to either the first circuit board or the third circuit board and disposed outside the housing; The semiconductor device according to claim 7 , further comprising: a second terminal electrically connected to said second circuit board and disposed outside said housing.

9. The semiconductor device according to claim 8 , wherein the first terminal is either an independent terminal or a source terminal.

10. 10. The semiconductor device according to claim 8, further comprising a second resistor electrically connected to said second terminal.

11. The semiconductor device according to claim 10 , wherein the second resistor is formed in a circuit that constitutes the second circuit board.

12. The semiconductor device according to claim 8 , further comprising a detection unit that detects a potential difference between the first terminal and the second terminal.

13. A semiconductor device comprising: a substrate having a circuit pattern including a first circuit board, a second circuit board spaced apart from the first circuit board, and a third circuit board spaced apart from each of the first circuit board and the second circuit board; a semiconductor chip disposed on the first circuit board, through which a current flows in a thickness direction; a capacitor connecting the first circuit board and the second circuit board; The semiconductor chip is a transistor chip, A semiconductor layer; a drain electrode pad disposed on one side of the semiconductor layer in a thickness direction so as to face the first circuit plate; a source electrode pad disposed on the other side in the thickness direction of the semiconductor layer; The semiconductor device includes: a first wire connecting the source electrode pad and the second circuit board; a second wire connecting the source electrode pad and the third circuit board; a housing including a frame surrounding the substrate; a first terminal electrically connected to either the first circuit board or the third circuit board and disposed outside the housing; The semiconductor device further includes a second terminal electrically connected to the second circuit board and disposed outside the housing.

14. A semiconductor device comprising: a substrate having a circuit pattern including a first circuit board and a second circuit board spaced apart from the first circuit board; a semiconductor chip disposed on the first circuit board, through which a current flows in a thickness direction; a capacitor connecting the first circuit board and the second circuit board; The semiconductor chip comprises: A semiconductor layer; a first electrode pad disposed on one side of the semiconductor layer in a thickness direction so as to face the first circuit board; a second electrode pad disposed on the other side of the semiconductor layer in the thickness direction; The semiconductor device further includes a first wire connecting the second electrode pad and the second circuit board, and a plurality of the semiconductor chips. The semiconductor device, wherein the plurality of semiconductor chips are electrically connected in series.

15. A semiconductor device comprising: a substrate having a circuit pattern including a first circuit board and a second circuit board spaced apart from the first circuit board; a semiconductor chip disposed on the first circuit board, through which a current flows in a thickness direction; a capacitor connecting the first circuit board and the second circuit board; The semiconductor chip comprises: A semiconductor layer; a first electrode pad disposed on one side of the semiconductor layer in a thickness direction so as to face the first circuit board; a second electrode pad disposed on the other side of the semiconductor layer in the thickness direction; the semiconductor device further includes a first wire connecting the second electrode pad and the second circuit board; the semiconductor chip is a transistor chip, the second electrode pad is a source electrode pad, the circuit pattern further includes a third circuit board spaced apart from each of the first circuit board and the second circuit board; The semiconductor device includes: a second wire connecting the source electrode pad and the third circuit board; a third wire connected to a gate electrode pad of the semiconductor chip; A semiconductor device, wherein a diameter of the first wire is the same as a diameter of at least one of the second wire and the third wire.

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