Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device with high reliability that can be manufactured (produced) easily, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor substrate 10 is manufactured by stacking only first and second n-type epitaxial layers 72 and 73 on an n+ type start substrate 71. A front surface of the semiconductor substrate 10 is a flat surface continuing from an active region 1 to a chip end part. In an edge terminal region 2, an annular FLR 20 having a plurality of p-type FLR regions 24 disposed apart from each other concentrically surrounding the periphery of the active region 1 is provided as a breakdown voltage structure. Each of the plurality of p-type FLR regions 24 includes a laminate structure formed by a plurality of p-type regions (partial FLRs) adjacent in a depth direction Z and formed by ion injection of p-type impurities every time the first and second n-type epitaxial layers 72 and 73 composing the semiconductor substrate 10 are epitaxially grown. By adjusting the impurity concentration and the number of laminations of the partial FLR in the p-type FLR region 24, a predetermined withstanding voltage can be obtained.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, there are several types of power semiconductor devices that control high voltages and large currents, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors with an insulated gate (MOS gate) made of a three-layer structure of metal-oxide film-semiconductor), and these are used according to the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density and can handle larger currents than MOSFETs, but they cannot be switched at high speeds. Specifically, bipolar transistors are limited to use at switching frequencies of a few kHz, while IGBTs are limited to use at switching frequencies of a few tens of kHz. On the other hand, MOSFETs have a lower current density and are difficult to use at high currents than bipolar transistors and IGBTs, but they are capable of high-speed switching operations up to a few MHz.

[0004] In addition, unlike IGBTs, MOSFETs have a p-type base region and an n-type - A MOSFET has a built-in parasitic diode formed by a pn junction with the type drift region. Therefore, when the MOSFET is used as an inverter device, this parasitic diode can be used as a diode (FWD: Free Wheeling Diode) to divert the load current that flows through the MOSFET itself, and as a free wheeling diode to protect the MOSFET itself.

[0005] Silicon (Si) is used as a constituent material of power semiconductor devices, but the market demands power semiconductor devices that combine high current and high speed, and efforts have been focused on improving IGBTs and MOSFETs, with development currently approaching the material limit. For this reason, semiconductor materials to replace silicon are being considered from the perspective of power semiconductor devices, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with low on-voltage, high-speed characteristics, and excellent high-temperature characteristics.

[0006] Silicon carbide is a chemically very stable semiconductor material with a wide band gap of 3 eV, allowing it to be used extremely stably as a semiconductor even at high temperatures. In addition, silicon carbide has a maximum electric field strength that is at least one order of magnitude greater than that of silicon, making it a promising semiconductor material that can sufficiently reduce on-resistance. These characteristics of silicon carbide are shared not only by silicon carbide, but also by all semiconductors with a wider band gap than silicon (hereafter referred to as wide band gap semiconductors).

[0007] In addition, as the current of power semiconductor devices increases, it is more cost-effective to use a trench gate structure in which a channel is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor chip, compared to a planar gate structure in which a channel (inversion layer) is formed along the front surface of the semiconductor chip, for MOS semiconductor devices such as IGBTs and MOSFETs. This is because the trench gate structure can increase the density of unit cells (component units of an element) per unit area, thereby increasing the current density per unit area.

[0008] Since the rate of temperature rise corresponding to the volume occupied by a unit cell increases as the current density per unit area increases, a double-sided cooling structure is required to improve discharge efficiency and stabilize reliability. Furthermore, a power semiconductor device has been proposed that has improved reliability by adopting a highly functional structure in which highly functional parts such as a current sensor, a temperature sensor, and an overvoltage protection unit are arranged on the same semiconductor substrate as the MOSFET, which is the main semiconductor element that performs the main operation of the power semiconductor device, as a circuit unit for protecting and controlling the main semiconductor element.

[0009] In addition, in a high-voltage semiconductor device, a high voltage is applied not only to the active region in which the element structure is formed, but also to the edge termination region surrounding the active region, causing an electric field to concentrate in the edge termination region. The breakdown voltage of a semiconductor device is determined by the impurity concentration, thickness, and electric field strength of the semiconductor (drift region), and the breakdown resistance determined by these semiconductor-specific characteristics is equal from the active region to the edge termination region. For this reason, if an electric field concentrates in the edge termination region and an electrical load exceeding the breakdown resistance is applied to the edge termination region, there is a risk of breakdown in the edge termination region, and the breakdown voltage of the entire semiconductor device is determined by the breakdown voltage of the edge termination region.

[0010] Therefore, a structure is known in which a breakdown voltage structure such as a junction termination extension (JTE) structure or a field limiting ring (FLR) is arranged in the edge termination region to alleviate or disperse the electric field in the edge termination region, thereby improving the breakdown voltage of the edge termination region and improving the breakdown voltage of the entire semiconductor device. Also known is a structure in which a floating metal electrode in contact with the FLR is arranged in the edge termination region as a field plate (FP).

[0011] The structure of a conventional silicon carbide semiconductor device will be described. Fig. 20 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. A conventional semiconductor device 230 shown in Fig. 20 is a vertical MOSFET with a trench gate structure, which is provided with an active region 201 through which a main current (drift current) flows and an edge termination region 202 surrounding the periphery of the active region 201, on a semiconductor substrate (semiconductor chip) 210 made of silicon carbide. The semiconductor substrate 210 is a n-type semiconductor device made of silicon carbide. + On the starting substrate 271 - The n-type epitaxial layer 272 and the p-type epitaxial layer 273 are epitaxially grown in this order.

[0012] A portion of the p-type epitaxial layer 273 in the edge termination region 202 is removed by etching, and a step 291 is formed in the edge termination region 202 on the front surface of the semiconductor substrate 210. The front surface of the semiconductor substrate 210 is recessed toward the drain electrode 252 at the second surface 210b on the outer side (the chip end (the end of the semiconductor substrate 210) side) than at the first surface 210a on the inner side (the chip center (the center of the semiconductor substrate 210) side), with the step 291 as a boundary. Due to this step 291, the p-type epitaxial layer 273 remains in a mesa shape on the central side of the front surface (the main surface on the p-type epitaxial layer 273 side) of the semiconductor substrate 210.

[0013] The first and second surfaces 210a and 210b of the front surface of the semiconductor substrate 210 are respectively a p-type epitaxial layer 273 and an n-type epitaxial layer 274. - The active region 201 is formed of an n-type epitaxial layer 272. - The n-type epitaxial layer 272 has an n-type current diffusion region 233 and first and second p-type epitaxial layers 273 on its surface. + In the active region, the p-type epitaxial layer 273 is provided in the surface region of the first surface 210a of the front surface of the semiconductor substrate 210, and the n-type epitaxial layer 273 is provided in the p-type epitaxial layer 273. + type source region 235 and p ++ A respective mold contact region 236 is selectively provided.

[0014] 2nd p. +The p-type region 262 (262a), the p-type base region 234 (234a) and the p ++ The n-type contact region 236 (236a) extends from the active region 201 to an intermediate region 203 between the active region 201 and the edge termination region 202, and reaches a third surface (step mesa edge) 210c that connects the first surface 210a and the second surface 210b of the front surface of the semiconductor substrate 210. The edge termination region 202 includes a n-type contact region 236 (236a) that is formed in a surface region of the second surface 210b of the front surface of the semiconductor substrate 210. - A plurality of p-type epitaxial layers selectively provided in the epitaxial layer 272 - Type region 221 and multiple p -- A spatial modulation type FLR 220 is formed in the mold region 222 .

[0015] The spatially modulated type is a structure in which the p-type impurity concentration per unit volume is gradually decreased toward the outside. - The mold regions 221 are spaced apart from one another, with the innermost p - The mold region 221 is concentrically surrounded by the mold region 221. - The width of the mold region 221 is narrower, and the p - The distance between the mold region 221 is narrow. -- The type region 222 is all p - All p - The innermost p - Type region 221 and the innermost p -- The mold region 222 is a second p + The p-type base region 234a is electrically connected to the p-type base region 234a via the p-type region 262a.

[0016] Multiple p -- The mold regions 222 are spaced apart from one another, with the innermost p -- The mold region 222 is concentrically surrounded by the mold region 222. -- The mold region 222 is narrower in width and has adjacent p -- The distance between the mold region 222 is narrow. -- The innermost p region 222 --Except for the type region 222, p - It is located outside the mold region 221. - The drift region 232 is made of all p - All p - The mold region 221 is disposed between the mold regions 221. - Type region 221 and p -- By adjusting the width and arrangement of the mold region 222, a spatial modulation type FLR 220 is configured.

[0017] n + Type source region 235, p ++ type contact region 236, n-type current diffusion region 233, + type area 261,262, p - type region 221, p -- Type regions 222 and n + The n-type channel stop region 223 is a diffusion region formed by ion implantation. + type source region 235 and p ++ The portion excluding the p-type contact region 236 is the p-type base region 234. - The n-type epitaxial layer 272 includes an n-type current diffusion region 233, a first p + type area 261,262, p - type region 221, p -- Type regions 222 and n + The portion excluding the channel stop region 223 is - type drift region 232.

[0018] The code 231 is n + n-type starting substrate 271 +2 is a gate-type drain region. Reference numerals 238, 239, 240, 240a, 241, 281 to 283 respectively denote a gate insulating film, a gate electrode, an interlayer insulating film, a contact hole, a metal silicide film, a field oxide film, a gate polysilicon wiring layer, and a gate metal wiring layer. Reference numerals 242 to 245 denote metal films constituting a barrier metal 246. Reference numerals 248 and 249 denote plating films and terminal pins constituting a wiring structure on a source pad 247, respectively. Reference numerals 250 and 251 denote protective films (passivation films).

[0019] A conventional semiconductor device has been proposed in which a plurality of termination trenches and one outermost isolating trench are formed in an edge termination region, the trenches penetrating a p-type base region to reach an n-type drift region and filled with an insulating material, and a p-type diffusion region surrounds each bottom surface of these trenches (see, for example, Patent Document 1 below). In Patent Document 1 below, a high breakdown voltage is maintained by arranging the plurality of termination trenches at intervals that connect the depletion layers extending from the active region outward when the MOSFET is off, and the interval between the outermost termination trench and the isolating trench is set to a distance that does not connect the depletion layers, thereby preventing the occurrence of leakage current.

[0020] In addition, in a conventional silicon carbide semiconductor device, n - A device has been proposed in which the silicon carbide layers that form the n-type drift region and p-type base region are extended, and the edge termination region of the p-type base region is made relatively thin by a step formed on the front surface of the semiconductor substrate in the edge termination region (see, for example, Patent Document 2 below). In Patent Document 2 below, the portion that extends into the edge termination region of the p-type base region is made into the electric field relaxation layer, thereby making the electric field relaxation layer free of bends and - This structure has no material discontinuity between the type drift region and the semiconductor device, thereby improving the breakdown voltage of the semiconductor device.

[0021] Another conventional silicon carbide semiconductor device has been proposed in which a trench of the same depth as the gate trench is formed in the edge termination region, and the FLR is formed of a floating p-type region made of a p-type silicon carbide layer epitaxially grown in a U-shaped cross-sectional shape along the inner wall of the trench (see, for example, Patent Document 3 below). In Patent Document 3 below, when a surge voltage is applied to the drain electrode, the depletion layer is expanded from the FLR, and the electric field applied to the active region is extended evenly to the edge termination region, thereby alleviating the electric field at the edge of the active region, thereby improving the breakdown voltage of the active region.

[0022] Another conventional silicon carbide semiconductor device is a silicon carbide semiconductor device having an FLR formed of one or more p-type regions formed by ion implantation, and a n-type region forming the front surface of a semiconductor substrate. + A silicon carbide layer and the n-type silicon carbide layer in the depth direction + The n-type silicon carbide layer is adjacent to - A device has been proposed in which the boundary between the p-type silicon carbide layer and the p-type region constituting the FLR is located closer to the front surface side of the semiconductor substrate than the end of the back electrode side of the p-type region (see, for example, Patent Document 4 below). In Patent Document 4 below, a device has been proposed in which a n-type silicon carbide layer is formed in the surface region of the front surface of the semiconductor substrate. + By providing the silicon carbide layer, variations in breakdown voltage occurring according to the thickness of the silicon carbide layer disappearing from the front surface of the semiconductor substrate are suppressed.

[0023] Another conventional silicon carbide semiconductor device has been proposed in which each of the multiple p-type regions constituting the FLR is composed of a high-concentration region including its own peak concentration position near the front surface of the semiconductor substrate and a low-concentration region immediately below and surrounding the side surfaces of the high-concentration region, with the p-type impurity concentration distribution decreasing from the peak concentration position toward the n-type drift region (see, for example, Patent Document 5 below). In Patent Document 5 below, in the outermost p-type region constituting the FLR, the width of the low-concentration region surrounding the outer peripheral side surface of the high-concentration region is made relatively wide to prevent an electric field from being applied to the high-concentration region, thereby suppressing the generation of leakage current.

[0024] In another conventional silicon carbide semiconductor device, an n-type semiconductor device is provided on the drain electrode side from the bottom surface of the gate trench. - p-type drift region and a p-n junction are formed. + A device has been proposed in which the n-type region is disposed at a position facing the bottom surface of the gate trench in the depth direction and between adjacent gate trenches (see, for example, Patent Document 6 below). In Patent Document 6 below, a device is proposed in which the n-type region is disposed closer to the drain electrode side than the bottom surface of the gate trench. - p-type drift region and a p-n junction are formed. + The mold region reduces the electric field applied to the gate insulating film at the bottom of the gate trench, making it easy to achieve high breakdown voltage when silicon carbide is used as the semiconductor material. [Prior art documents] [Patent documents]

[0025] [Patent Document 1] Patent No. 5206248 [Patent Document 2] Patent No. 5691259 [Patent Document 3] JP 2005-340250 A [Patent Document 4] Patent No. 5628462 [Patent Document 5] JP 2018-067690 A [Patent Document 6] International Publication No. 2017 / 064949 Summary of the Invention [Problem to be solved by the invention]

[0026] However, when the FLR 220 is of the spatial modulation type as described above (see FIG. 20), the overlap of ion implantation becomes complicated, and p - Type region 221 and p -- It is difficult to align the ion implantation mask used to form the mold region 222. - Type region 221 and p --Type region 222 and n - Since the pn junction with the type drift region 232 bears the high voltage applied laterally (in a direction parallel to the front surface of the semiconductor substrate 210) to the edge termination region 202 when the semiconductor device 230 is off, if the alignment precision of the ion implantation mask is low, the degree of completion of the FLR 220 will be low, and the reliability of the semiconductor device 230 will decrease.

[0027] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a semiconductor device that is easy to fabricate (manufacture) and has high reliability, and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0028] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention is a semiconductor device having an active region through which a main current flows and a termination region surrounding the periphery of the active region, and has the following features: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of a semiconductor having a wider band gap than silicon. A second semiconductor region of a second conductivity type is provided in the active region between a first main surface of the semiconductor substrate and the first semiconductor region. A predetermined element structure is formed in the active region by a pn junction between the second semiconductor region and the first semiconductor region. A first electrode is electrically connected to the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate.

[0029] In the termination region, a plurality of second conductivity type withstand voltage regions are provided between the first main surface of the semiconductor substrate and the first semiconductor region, away from the element structure, and concentrically surrounding the active region. The first main surface of the semiconductor substrate is a flat surface extending from the active region to the termination region. A first conductivity type epitaxial layer is provided to form the first main surface of the semiconductor substrate. The second semiconductor region and the second conductivity type withstand voltage regions are each The first conductive type epitaxial layer is selectively provided inside The first semiconductor region is a first conductive type epitaxial layer. The second semiconductor region and the second conductive type voltage-resistant regionand reaches the first main surface of the semiconductor substrate between the adjacent second conductivity type withstanding voltage regions. The second conductivity type withstand voltage regions each have a plurality of second conductivity type regions adjacent in a depth direction. Three or more second conductivity type regions are provided in the termination region adjacent in a depth direction. Of the three or more second conductivity type regions adjacent in a depth direction, the second conductivity type region at the center in the depth direction of the second conductivity type withstand voltage region has a lower impurity concentration than the other second conductivity type regions.

[0030] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has an active region through which a main current flows and a termination region surrounding the periphery of the active region, and has the following features: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of a semiconductor having a band gap wider than that of silicon. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region in the active region. A predetermined element structure is formed in the active region by a pn junction between the second semiconductor region and the first semiconductor region. A first electrode is electrically connected to the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. A plurality of second conductivity type breakdown voltage regions are provided concentrically around the periphery of the active region and spaced apart from each other between the first main surface of the semiconductor substrate and the first semiconductor region in the termination region, away from the element structure. The first main surface of the semiconductor substrate is a flat surface from the active region to the termination region. A first conductivity type epitaxial layer forming the first main surface of the semiconductor substrate is provided. The second semiconductor region and the second conductive type breakdown voltage region are selectively provided inside the first conductive type epitaxial layer. The first semiconductor region is a portion of the first conductive type epitaxial layer excluding the second semiconductor region and the second conductive type breakdown voltage region, and reaches the first main surface of the semiconductor substrate between the adjacent second conductive type breakdown voltage regions. Each of the second conductive type breakdown voltage regions has a plurality of second conductive type regions adjacent in the depth direction. The element structure further includes a third semiconductor region of a first conductive type, a trench, a gate electrode, a fourth semiconductor region of a second conductive type having a higher impurity concentration than the second semiconductor region, and a second conductive type high concentration region having a higher impurity concentration than the second semiconductor region. The third semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region. The gate electrode is provided inside the trench via a gate insulating film.The fourth semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region at a position farther from the trench than the third semiconductor region. The second conductivity type high concentration region is selectively provided within the first semiconductor region and is located closer to the second main surface of the semiconductor substrate than a bottom surface of the trench. Any of the plurality of second conductivity type regions is. Located at the same depth as the second semiconductor region; The second semiconductor region has the same impurity concentration as the second semiconductor region. The remaining second conductivity type regions of the plurality of second conductivity type regions are located at a different depth from the second semiconductor region and have a different impurity concentration from the second semiconductor region.

[0031] In addition, the semiconductor device of the present invention, in the above-mentioned invention, further includes a first conductivity type region in the termination region, which is provided inside the first semiconductor region and contacts multiple second conductivity type breakdown voltage regions, and has an impurity concentration higher than that of the first semiconductor region.

[0032] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the positions in the normal direction of the multiple second conductivity type regions adjacent in the depth direction are shifted from each other by 0.05 μm or more and 0.3 μm or less.

[0033] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the normal width of at least one of the multiple second conductivity type regions adjacent in the depth direction is different from the normal widths of the other second conductivity type regions.

[0034] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the impurity concentration of at least one of the multiple second conductivity type regions adjacent in the depth direction is different from the impurity concentrations of the other second conductivity type regions.

[0035] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the termination region is provided with three or more second conductivity type regions adjacent in a depth direction, and among the three or more second conductivity type regions adjacent in a depth direction, the second conductivity type region near a center portion in the depth direction of the second conductivity type withstand voltage region has an impurity concentration lower than the impurity concentrations of the other second conductivity type regions.

[0036] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the element structure further includes a third semiconductor region of a first conductivity type, a trench, a gate electrode, a fourth semiconductor region of a second conductivity type, and a second conductivity type high concentration region. The third semiconductor region is selectively provided between a first main surface of the semiconductor substrate and the second semiconductor region. The trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region. The gate electrode is provided inside the trench via a gate insulating film. The fourth semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, at a position farther from the trench than the third semiconductor region.

[0037] The fourth semiconductor region has a higher impurity concentration than the second semiconductor region. The second conductive type high concentration region is selectively provided inside the first semiconductor region and is located closer to the second main surface of the semiconductor substrate than the bottom surface of the trench. The second conductive type high concentration region has a higher impurity concentration than the second semiconductor region. Three second conductive type regions are provided adjacent to each other in the depth direction in the termination region. Of the three second conductive type regions adjacent to each other in the depth direction, the second conductive type region closest to the first main surface of the semiconductor substrate has the same impurity concentration as the fourth semiconductor region. The second conductive type region farthest from the first main surface of the semiconductor substrate has the same impurity concentration as the second conductive type high concentration region. The remaining second conductive type regions have the same impurity concentration as the second semiconductor region.

[0039] In addition, in the semiconductor device according to the present invention, in the above-mentioned invention, the element structure further includes a third semiconductor region of a first conductivity type, a trench, a gate electrode, and a second conductivity type high concentration region. The third semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region. The gate electrode is provided inside the trench via a gate insulating film. The second conductivity type high concentration region is selectively provided inside the first semiconductor region and is located closer to the second main surface of the semiconductor substrate than the bottom surface of the trench. The second conductivity type high concentration region has a higher impurity concentration than the second semiconductor region. The second conductivity type withstand voltage region is characterized in that it terminates at a position shallower than the second conductivity type high concentration region from the first main surface of the semiconductor substrate.

[0040] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the second conductivity type high concentration region has a first high concentration region facing the bottom surface of the trench in the depth direction, and a second high concentration region separated from the first high concentration region and the trench and in contact with the second semiconductor region.

[0041] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including an active region in which a predetermined element structure formed by a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type is provided in a semiconductor substrate made of a semiconductor having a band gap wider than that of silicon, and a termination region surrounding the active region, and has the following features: A first step is performed in which a first conductivity type epitaxial layer forming a first main surface of the semiconductor substrate is epitaxially grown. A second step is performed in which a predetermined impurity is introduced into a surface region of the first conductivity type epitaxial layer in the active region to form at least a diffusion region that becomes the second semiconductor region, and the element structure including the pn junction between the second semiconductor region and the first semiconductor region that is a portion of the first conductivity type epitaxial layer in the active region excluding the diffusion region.

[0042] A third step is performed in the surface region of the first conductivity type epitaxial layer in the termination region, forming a plurality of second conductivity type withstand voltage regions concentrically separated from each other and surrounding the periphery of the active region, away from the element structure, and leaving the first conductivity type epitaxial layer to become the first semiconductor region between the adjacent second conductivity type withstand voltage regions. In the first step, a stacked structure is formed in which a plurality of the first conductivity type epitaxial layers are stacked in multiple stages, and the first main surface of the semiconductor substrate is formed flat from the active region to the termination region. In the second step, the device structure includes forming the second semiconductor region in any one of the first conductive type epitaxial layers, selectively forming a third semiconductor region of the first conductive type between a first main surface of the semiconductor substrate and the second semiconductor region, forming a trench penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region, forming a gate electrode within the trench via a gate insulating film, selectively forming a fourth semiconductor region of the second conductive type having a higher impurity concentration than the second semiconductor region between the first main surface of the semiconductor substrate and the second semiconductor region at a position farther from the trench than the third semiconductor region, and selectively forming a second conductive type high concentration region having a higher impurity concentration than the second semiconductor region at a position deeper than a bottom surface of the trench within the first semiconductor region. In the third step, a second conductive type region is formed in each of the multiple first conductive type epitaxial layers, the multiple second conductive type regions are adjacent to each other in a depth direction to form a second conductive type breakdown voltage region, and any one of the multiple second conductive type regions is At the same depth as the second semiconductor region, The same impurity concentration as the second semiconductor region and the remaining second conductive type regions of the plurality of second conductive type regions are formed at a depth position different from that of the second semiconductor region and with an impurity concentration different from that of the second semiconductor region.

[0043] In the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, the second step forms the second semiconductor region in one of the first conductive type epitaxial layers, and the third step forms the second conductive type region simultaneously with the second semiconductor region in the first conductive type epitaxial layer in which the second semiconductor region is to be formed, among the plurality of first conductive type epitaxial layers. Effect of the Invention

[0044] According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, the impurity concentration and depth of the second conductivity type voltage withstanding region can be easily adjusted, a highly complete voltage withstanding structure can be easily formed, and a highly reliable semiconductor device can be provided. [Brief description of the drawings]

[0045] [Figure 1] 1 is a plan view showing a layout of a semiconductor device according to a first embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view showing another example of the cross-sectional structure taken along line AA' in FIG. 1. [Figure 4] 2 is a cross-sectional view showing another example of the cross-sectional structure taken along line AA' in FIG. 1. [Diagram 5] 4 is a cross-sectional view showing another example of the semiconductor device according to the first embodiment. FIG. [Figure 6] 4 is a cross-sectional view showing another example of the semiconductor device according to the first embodiment. FIG. [Figure 7] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 8] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 9] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 10]1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 11] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 12] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 13] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 14] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 15] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 16] 1 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment. [Figure 17] FIG. 11 is a cross-sectional view showing an example of a voltage-resistant structure of a semiconductor device according to a second embodiment. [Figure 18] FIG. 11 is a cross-sectional view showing an example of a voltage-resistant structure of a semiconductor device according to a second embodiment. [Figure 19] FIG. 11 is a cross-sectional view showing an example of a voltage-resistant structure of a semiconductor device according to a second embodiment. [Figure 20] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations will be omitted.

[0047] (Embodiment 1) The structure of the semiconductor device according to the first embodiment will be described by taking a vertical MOSFET with a trench gate structure as an example. FIG. 1 is a plan view showing a layout of the semiconductor device according to the first embodiment as viewed from the front surface side of a semiconductor substrate. FIG. 2 is a cross-sectional view showing a cross-sectional structure taken along line A-A' in FIG. 1. FIGS. 3 and 4 are cross-sectional views showing another example of the cross-sectional structure taken along line A-A' in FIG. 1. FIGS. 5 and 6 are cross-sectional views showing another example of the semiconductor device according to the first embodiment. FIGS. 5 and 6 show another example of a unit cell of a MOSFET in active regions 1a and 1b.

[0048] 1 and 2, a semiconductor device 30 according to a first embodiment is a vertical MOSFET having a trench gate structure (element structure) in an active region 1 of a semiconductor substrate (semiconductor chip) 10 made of silicon carbide (SiC), and a field limiting ring (FLR) 20 as a breakdown voltage structure in an edge termination region 2 surrounding the active region 1. The active region 1 is a region through which a main current (drift current) flows when the MOSFET is on. In the active region 1, a plurality of unit cells (components of an element) of the MOSFET having the same structure are arranged adjacent to each other.

[0049] The active region 1 has a substantially rectangular planar shape and is disposed substantially in the center of the semiconductor substrate 10 (chip center). The active region 1 is a region inside (toward the chip center) of the sidewall (side surface of the interlayer insulating film 40) on the outer side (chip end side) of the outermost peripheral contact hole 40b. The intermediate region 3 between the active region 1 and the edge termination region 2 is adjacent to the active region 1 and surrounds the periphery of the active region 1. The boundary between the intermediate region 3 and the edge termination region 2 is defined by the peripheral p-type base region 34c and the peripheral p-type base region 34d described later. + The outer end of the mold region 62a and - This is the boundary between the first semiconductor region 32 and the second semiconductor region 33.

[0050] Edge termination region 2 is a region between active region 1 and the edge (chip edge) of semiconductor substrate 10, and surrounds active region 1 via intermediate region 3, and has the function of alleviating the electric field on the front surface side of semiconductor substrate 10 to maintain a breakdown voltage. In edge termination region 2, a field limiting ring (FLR) 20 is disposed on the front surface side of semiconductor substrate 10 as a breakdown voltage structure. The breakdown voltage is the limit voltage at which avalanche breakdown occurs at the pn junction and the voltage between the source and drain does not increase any further even if the current between the source and drain is increased.

[0051] The semiconductor substrate 10 is made of silicon carbide. + On the front surface of the starting mold substrate 71, the first, second, and third - The n-th epitaxial layer (first conductivity type epitaxial layer) 72, 73 of the semiconductor substrate 10 is epitaxially grown in this order. - The main surface on the side of the type epitaxial layer 73 (the 2n - The surface of the n-type epitaxial layer 73) is the front surface, + The main surface (n + The back side of the starting substrate 71 is referred to as the back side. + The starting substrate 71 is n + A type drain region 31. In the active region 1, on the front surface side of the semiconductor substrate 10, a MOS gate is provided.

[0052] The MOS gate is a p-type base region (second semiconductor region) 34, + type source region (third semiconductor region) 35, p ++ The gate trench 37 is made up of a p-type contact region (fourth semiconductor region) 36, a gate trench 37, a gate insulating film 38, and a gate electrode 39. The outside of the outermost gate trench 37 (the portion of the outer peripheral p-type base region 34c described later) is made up of n + The gate trench 37 is configured to have no n-type source region 35. The gate trench 37 is formed to extend from the front surface of the semiconductor substrate 10 to the 2n-th - The first n-type epitaxial layer 73 is then - 4. The epitaxial layer 72 is then formed.

[0053] The gate trench 37 extends in a stripe shape in the active region 1 in a first direction X parallel to the front surface of the semiconductor substrate 10, and reaches the intermediate region 3. A gate electrode 39 is provided inside the gate trench 37 via a gate insulating film 38. + type source region 35 and p ++ The outer p-type contact region 36 (the outer p-type base region 34c and the outer p ++ The 2nd n-type contact region 36a is - The diffusion region is selectively formed in the type epitaxial layer 73 by ion implantation.

[0054] The p-type base region 34 is a 2n-th - The first epitaxial layer 73 and the first n - The p-type base region 34 may terminate at a position shallower than the bottom surface of the gate trench 37 from the front surface of the semiconductor substrate 10. - The p-type base region 34 may extend into the p-type epitaxial layer 72. The p-type base region 34 is provided throughout the active region 1 and intermediate region 3. A peripheral portion 34c of the p-type base region 34 (hereinafter referred to as the peripheral p-type base region) surrounds the periphery of the central portion of the active region 1 in a substantially rectangular shape.

[0055] The peripheral p-type base region 34c is a region of the p-type base region 34 that is n-type + The n-type source region 35 is located outside the n-type source region 35, and is located outside the outermost gate trench 37 in a second direction Y (the lateral direction of the gate trench 37) that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X. + type source region 35 and p ++ The contact regions 36 are selectively provided between the front surface of the semiconductor substrate 10 and the p-type base region 34 and in contact with the p-type base region 34.

[0056] n + type source region 35 and p ++The n-type contact region 36 is exposed on the front surface of the semiconductor substrate 10. Here, the exposure on the front surface of the semiconductor substrate 10 means that + type source region 35 and p ++ The contact region 36 contacts a NiSi film 41 (described later) through a contact hole 40a in an interlayer insulating film 40 (described later). + Type source region 35 and p ++ The contact regions 36 are alternately and repeatedly arranged between adjacent gate trenches 37 in a first direction X, which is the same as the direction in which the gate electrode 39 extends (not shown).

[0057] p ++ The contact regions 36 are spaced apart from the gate trenches 37 and are interspersed in the first direction X. + The n-type source region 35 contacts the gate insulating film 38 on the side wall of the gate trench 37. + The source region 35 is, for example, p ++ The n-type contact region 36 has a ladder-like planar shape. + The p-type source region 35 includes a portion extending in the first direction X along the sidewall of the gate trench 37 and a p ++ and a portion sandwiched between the mold contact regions 36.

[0058] Also, p ++ The outer circumferential contact region 36 (hereinafter referred to as the outer circumferential contact region 36) ++ The p-type contact region 36a is provided in contact with the peripheral p-type base region 34c over the entire area between the front surface of the semiconductor substrate 10 and the peripheral p-type base region 34c, and is exposed on the front surface of the semiconductor substrate 10. ++ The contact region 36a contacts the NiSi film 41 at the outermost contact hole 40b. ++ The mold contact region 36 a contacts the gate insulating film 38 on the outer sidewall of the outermost gate trench 37 .

[0059] p ++ The contact region 36 and the outer periphery p++ The p-type contact region 36a may not be provided. ++ The contact region 36 and the outer periphery p ++ Instead of the n-type contact region 36a, the p-type base region 34 and the peripheral p-type base region 34c reach and are exposed on the front surface of the semiconductor substrate 10. + Type drain region 31(n + Between these regions, n - A mold drift region 32 is provided.

[0060] The p-type base region 34 and the peripheral p-type base region 34c and - An n-type current diffusion region 33 may be provided between the active region 1 and the edge termination region 2 so as to be in contact with these regions. The n-type current diffusion region 33 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 33 extends from the active region 1 to the edge termination region 2 with approximately the same thickness, and its peripheral portion (first conductivity type region: hereinafter referred to as peripheral n-type current diffusion region) 33a is in contact with the FLR 20 and the n-type current diffusion region 33 described later. + It terminates between the mold stopper area 25 .

[0061] In addition, inside the semiconductor substrate 10, there is a n + The first and second p-type insulating layers 31 are disposed near the drain region 31 to reduce the electric field applied to the bottom surface of the gate trench 37. + The first and second conductivity type regions (second conductivity type high concentration regions) 61 and 62 are provided. + The mold regions 61 and 62 extend linearly in a first direction X, which is the same as the direction in which the gate trench 37 extends, and have substantially the same length as the gate trench 37. + Both the mold regions 61 and 62 have a depth Z of n + It is sufficient that the distance to the type drain region 31 is approximately the same, and the depth position can be changed in various ways.

[0062] For example, 1st and 2nd pages +The n-type regions 61 and 62 may terminate inside the n-type current diffusion region 33 and be surrounded by the n-type current diffusion region 33 (not shown), or may be connected to the n-type current diffusion region 33 and the n-type current diffusion region 33. - terminating at the interface with the n-type drift region 32 - The first and second p + The n-type regions 61 and 62 are located closer to the n-type current diffusion region 33 in the depth direction Z. + Extending to a position close to the n-type drain region 31 - It may terminate within the mold drift region 32 (see FIG. 2).

[0063] 1st p. + The p-type region 61 (first high concentration region) is provided apart from the p-type base region 34 and faces the bottom surface of the gate trench 37 in the depth direction Z. + The mold region 61 may be wider than the gate trench 37 and may face the bottom corner of the gate trench 37. + The mold region 61 may reach the bottom surface of the gate trench 37 and be in contact with the gate insulating film 38 at the bottom surface (or from the bottom surface to the bottom corner portion) of the gate trench 37. The bottom corner portion of the gate trench 37 is a portion that connects the bottom surface and the sidewall of the gate trench 37.

[0064] 1st p. + The second p-type region 61 may be at a floating potential (FIG. 2). + The first p-type region 62 may be electrically connected to the source electrode (first electrode) at a predetermined location and fixed to the potential of the source electrode (first electrode). + When the type region 61 is fixed to the potential of the source electrode, the first and second p + Another p is placed at a predetermined position between the mold regions 61 and 62. + A mold region (not shown) is placed or other p + Instead of the mold area, the first p + A part of the mold region 61 is + The first p + The mold region 61 is + It is sufficient that the mold region (second high concentration region) 62 is partially connected.

[0065] 1st p. + By fixing the potential of the first p-type region 61 to the potential of the source electrode, + A n-type region 61 and an n-type current diffusion region 33 or - When avalanche breakdown occurs at the pn junction of the n-type drift region 32 (or both), - Holes (positive holes) generated in the type drift region 32 can be efficiently discharged to the source electrode. This reliably relaxes the electric field applied to the gate insulating film 38 at the bottom of the gate trench 37 when the MOSFET is off, thereby improving the reliability of the semiconductor device 30.

[0066] 2nd p. + The first p-type region 62 is disposed between the adjacent gate trenches 37. + The second p-type region 61 and the gate trench 37 are disposed apart from each other, and are adjacent to the p-type base region 34 in the depth direction Z. + Mold area 62 (hereinafter, outer circumference p + The first p-type region 62a is formed on the outside of the outermost gate trench 37. + The outer p-type base region 34c is provided apart from the outer p-type region 61 and the outermost gate trench 37 and is adjacent to the outer p-type base region 34c in the depth direction Z. + The mold region 62 a extends outward from the active region 1 and occupies the entire area of ​​the intermediate region 3 .

[0067] Perimeter p + The mold region 62a surrounds the central portion of the active region 1 in a substantially rectangular shape, and includes all the first and second p + In FIG. 2, the second p + Since the n-type region 62 penetrates the n-type current diffusion region 33 in the depth direction Z, the peripheral p + The outer p-type region 62a penetrates the outer periphery n-type current diffusion region 33a in the depth direction Z. + The type region 62a may terminate in the depth direction Z inside the peripheral n-type current diffusion region 33a.

[0068] n-type current diffusion region 33, peripheral n-type current diffusion region 33a, + Mold regions 61, 62 and the periphery p + The n-type region 62a is a first n-type region in the active region 1 and the intermediate region 3. - The n-type epitaxial layer 72 is a diffusion region formed by ion implantation in the active region 1 and the intermediate region 3. - The portion of the epitaxial layer 72 other than the diffusion regions formed by these ion implantations is n - The n-type drift region 32. - The drift region 32 extends from the active region 1 to the edge of the chip.

[0069] The interlayer insulating film 40 is provided over almost the entire front surface of the semiconductor substrate 10, and covers the gate electrodes 39 of all unit cells of the MOSFET. The active region 1 is provided with contact holes 40a, 40b penetrating the interlayer insulating film 40 in the depth direction Z. The contact hole 40a is provided linearly in the first direction X, which is the same direction as the extension direction of the gate trenches 37, between adjacent gate trenches 37, for example. The contact hole 40a has n + type source region 35 and p ++ The mold contact area 36 is exposed.

[0070] The contact hole 40b is provided, for example, in a substantially rectangular shape surrounding the periphery of the central portion of the active region 1. The contact hole 40b has an outer periphery p ++ The n-type contact region 36a is exposed. A nickel silicide (NixSiy, where x and y are integers: hereinafter, collectively referred to as NiSi) film 41 is in ohmic contact with the semiconductor substrate 10 inside the contact holes 40a and 40b. + Type source region 35, p ++ The contact region 36 and the outer periphery p ++ The contact region 36a is electrically connected to the contact area 36b.

[0071] p ++ The contact region 36 and the outer periphery p ++If the contact region 36a is not provided, ++ The contact region 36 and the outer periphery p ++ Instead of the contact region 36a, the p-type base region 34 and the peripheral p-type base region 34c are exposed through contact holes 40a, 40b, respectively, and are electrically connected to the NiSi film 41. A barrier metal 46 is provided along the entire surfaces of the interlayer insulating film 40 and the NiSi film 41 in the active region 1.

[0072] The barrier metal 46 has a function of preventing mutual reaction between the metal films of the barrier metal 46 or between regions facing each other across the barrier metal 46. The barrier metal 46 may have a layered structure in which, for example, a first titanium nitride (TiN) film 42, a first Ti film 43, a second TiN film 44, and a second Ti film 45 are layered in this order. The first TiN film 42 covers the entire surface of the interlayer insulating film 40 in the active region 1. The first Ti film 43 is provided on the entire surfaces of the first TiN film 42 and the NiSi film 41.

[0073] The second TiN film 44 is provided on the entire surface of the first Ti film 43. The second Ti film 45 is provided on the entire surface of the second TiN film 44. An Al electrode film 47 is provided on the entire surface of the second Ti film 45. The aluminum (Al) electrode film 47 is connected to an n-type electrode via a barrier metal 46 and a NiSi film 41. + Type source region 35, p ++ The contact region 36 and the outer periphery p ++ The Al electrode film 47 and the barrier metal 46 are electrically connected to the gate contact region 36a. The Al electrode film 47 and the barrier metal 46 are terminated on the inner side of the intermediate region 3 relative to a gate metal wiring layer 83, which will be described later.

[0074] The Al electrode film 47 may be, for example, an Al film, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film having a thickness of about 5 μm. The Al electrode film 47, the barrier metal 46, and the NiSi film 41 function as a source electrode. One end of a terminal pin 49 is bonded onto the Al electrode film 47 via a plating film 48 and a solder layer (not shown). The other end of the terminal pin 49 is bonded to a metal bar (not shown) disposed opposite the front surface of the semiconductor substrate 10.

[0075] The other end of terminal pin 49 is exposed to the outside of a case (not shown) in which semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown). Terminal pin 49 is soldered to plating film 48 in a state where it stands approximately perpendicular to the front surface of semiconductor substrate 10. Terminal pin 49 is a round bar-shaped (cylindrical) wiring member having a predetermined diameter according to the current capacity of the MOSFET, and is connected to an external ground potential (minimum potential). Terminal pin 49 is an external connection terminal that takes out the potential of Al electrode film 47 to the outside.

[0076] The first and second protective films 50, 51 are, for example, polyimide films. The first protective film 50 covers the surface of the Al electrode film 47 except for the plating film 48. The first protective film 50 extends to the chip edge so as to cover the Al electrode film 47, the interlayer insulating film 40, and the gate metal wiring layer 83, and functions as a passivation film. The portion of the Al electrode film 47 exposed in the opening of the first protective film 50 becomes a source pad. The second protective film 51 covers the boundary between the plating film 48 and the first protective film 50.

[0077] The front surface of the semiconductor substrate 10 is a flat surface that continues from the active region 1 to the chip edge, and a step 291 (see FIG. 20) as in the conventional structure is not formed in the edge termination region 2. That is, the entire front surface of the semiconductor substrate 10 is the 2nth - The intermediate region 3 is formed of a 2n-type epitaxial layer 73. -The peripheral p-type base region 34c and the peripheral p-type epitaxial layer 73 are formed by ion implantation. ++ Mold contact regions 36a are selectively provided.

[0078] The peripheral p-type base region 34c is fixed to the potential of the source electrode and has the function of making the electric field uniform within the surface of the front surface of the semiconductor substrate 10, thereby improving the breakdown voltage. ++ The n-type contact region 36a is connected to the n-type contact region 3 of the intermediate region 3 and the edge termination region 2 when the MOSFET is turned off. - The intermediate region 3 is an extraction region for extracting holes from the drift region 32 to the source electrode. - The peripheral n-type current diffusion region 33a and the peripheral p-type epitaxial layer 72 are formed by ion implantation. + A mold area 62a is provided.

[0079] An insulating layer is provided on the front surface of semiconductor substrate 10 in intermediate region 3 and edge termination region 2, in which field oxide film 81 and interlayer insulating film 40 are laminated in that order. This insulating layer extends outward from intermediate region 3 to the chip edge, covering the entire front surface of semiconductor substrate 10 in intermediate region 3 and edge termination region 2. In intermediate region 3, an insulating layer is provided between field oxide film 81 and interlayer insulating film 40 in depth direction Z, extending from the outer periphery p ++ A gate polysilicon wiring layer 82 is provided facing the mold contact region 36a.

[0080] The gate metal wiring layer 83 contacts the gate polysilicon wiring layer 82 via a contact hole 40c opened in the interlayer insulating film 40. The gate polysilicon wiring layer 82 and the gate metal wiring layer 83 form a gate runner that surrounds the periphery of the central portion of the active region 1 in a substantially rectangular shape. The gate metal wiring layer 83 faces the end of the gate trench 37 in the depth direction Z. The gate metal wiring layer 83 contacts the gate electrode 39 at the end of the gate trench 37, and electrically connects all the gate electrodes 39 in the active region 1 to a gate pad (not shown).

[0081] In the intermediate region 3, the front surface of the semiconductor substrate 10 is provided with an outer periphery p ++ In the edge termination region 2, the front surface of the semiconductor substrate 10 is provided with a partial FLR (third region 23) of the top layer constituting the FLR 20, which will be described later, and a n-type contact region 36a. - The type drift region 32 is exposed on the front surface of the semiconductor substrate 10 in the intermediate region 3 and the edge termination region 2, which means that the type drift region 32 is provided in the surface region of the front surface of the semiconductor substrate 10 in the intermediate region 3 and the edge termination region 2 and is in contact with the field oxide film 81.

[0082] In the edge termination region 2, an FLR 20 is provided as a breakdown voltage structure. The FLR 20 is an annular (ring-shaped) junction structure in which a plurality of floating p-type regions (hereinafter referred to as p-type FLR regions (second conductivity type breakdown voltage regions)) 24 of the same configuration are arranged apart from each other and concentrically surround the periphery of the active region 1 via the intermediate region 3. - When the MOSFET (semiconductor device 30) is turned off, the high voltage applied to the edge termination region 2 in the lateral direction (the direction parallel to the front surface of the semiconductor substrate 10) is borne by the pn junction with the type drift region 32, thereby ensuring a predetermined breakdown voltage of the edge termination region 2.

[0083] The p-type FLR region 24 is a first, second, - Each time p-type epitaxial layer 72 (72a), 73 (73a, 73b) is epitaxially grown to a predetermined thickness, p-type regions (hereinafter referred to as partial FLRs (second conductivity type regions)) of approximately the same width (width in the normal direction) adjacent in depth direction Z are formed by ion implantation of p-type impurities, and have an impurity concentration distribution that changes stepwise in depth direction Z. The normal direction is the direction perpendicular to the direction in which p-type FLR region 24 extends annularly (direction from the chip center toward the chip end). A predetermined breakdown voltage of edge termination region 2 is ensured by adjusting the impurity concentration and depth position of each of the partial FLRs that constitute p-type FLR region 24.

[0084] The total impurity concentration of a set of a plurality of partial FLRs (for example, a three-layer structure of first to third regions 21 to 23 in FIG. 2) adjacent to each other in the depth direction Z may satisfy a predetermined impurity concentration of one p-type FLR region 24 composed of the plurality of partial FLRs. The plurality of partial FLRs constituting one p-type FLR region 24 are formed by first, second, and third regions 21 to 23 which are sequentially deposited to a predetermined thickness as described later. - The p-type epitaxial layers 72 (72a) and 73 (73a, 73b) may be formed simultaneously with the p-type regions constituting the MOSFET of the active region 1 formed by ion implantation.

[0085] For example, the first to third regions (partial FLRs) 21 to 23 that are adjacent to each other in the depth direction Z and that constitute one p-type FLR region 24 are the second p + 62, the p-type base region 34 and the p ++ The partial FLRs may be formed simultaneously with the p-type contact region 36 (see FIG. 2). In addition, the partial FLRs adjacent to each other in the depth direction Z and constituting one p-type FLR region 24 may be formed at a timing different from the formation of the p-type region constituting the MOSFET of the active region 1. The p-type FLR region 24 may terminate inside the peripheral n-type current diffusion region 33a (not shown).

[0086] The depth of p-type FLR region 24 can be adjusted by the number of stacked partial FLRs constituting p-type FLR region 24. For example, FLR 20a may be configured with p-type FLR region 24a having a two-layer structure of second and third regions 22 and 23 in the upper layers (FIG. 3), or FLR 20b may be configured with p-type FLR region 24b having a single-layer structure of only the uppermost third region 23 (FIG. 4). + By terminating at a position shallower than the depth of the mold regions 61 and 62, an electric field can be concentrated in the active region 1 when an overload is applied.

[0087] For example, among the first regions 21-23 constituting the p-type FLR region 24, when the impurity concentration of the second region 22 at the center in the depth direction Z is made lower than the impurity concentrations of the other first and third regions 21 and 23 (see FIG. 2), the edge termination region 2 is less susceptible to adverse effects of charges accumulated in the polyimide film (first protective film 50) on the front surface of the semiconductor substrate 10. This prevents the first protective film 50 from expanding outward or shrinking inward due to the charges accumulated in the first protective film 50, stabilizing the breakdown voltage characteristics of the FLR 20.

[0088] The adverse effect of the charge in the first protective film 50 is, for example, when the first protective film 50 is positively charged, the positive charge in the first protective film 50 causes the n - The expansion of the depletion layer in the n-type drift region 32 is suppressed. In addition, when the first protective film 50 is negatively charged, the n-type - The potential in the n-type drift region 32 is pulled outward by the negative charges in the first protective film 50, + The problem is that it tends to extend to the vicinity of the die stopper region 25.

[0089] As described above, since the step 291 (see FIG. 20) as in the conventional structure is not formed on the front surface of the semiconductor substrate 10, the depth of the FLR 20 from the front surface of the semiconductor substrate 10 (the depth of the p-type FLR region 24) is compared with the depth of the FLR 220 from the second surface 210b of the front surface of the semiconductor substrate 210 of the conventional structure when compared at the same breakdown voltage class. - Type region 221 and p -- The depth of the edge termination region 222 can be made deeper than the depth of the mold region 222. Therefore, the length (width in the normal direction) of the edge termination region 2 can be made narrower than in the conventional structure.

[0090] Furthermore, in the conventional structure, if the breakdown voltage is set to 10 kV or more, it becomes even more susceptible to the effects of electric charges, and a field plate (FP), which is a floating metal electrode in contact with the FLR, is required, which further increases the length of edge termination region 202. On the other hand, in the first embodiment, by configuring FLR 20 with p-type FLR region 24, it is no longer necessary to provide an FP even when the breakdown voltage is set to 10 kV or more, so that the length of edge termination region 2 can be made shorter than in the conventional structure, resulting in a voltage-resistant structure that is stable against electric charges.

[0091] In the surface region of the front surface of the semiconductor substrate 10, there are n + A die stopper area 25 is optionally provided. + The stopper region 25 is formed by ion implantation into a 2n-th - The first, second, and third epitaxial layers 73 are formed in the first, second, and third epitaxial layers 73 and exposed on the front surface and edge of the semiconductor substrate 10. - The p-type FLR region 24 and the n-type epitaxial layers 72 and 73 + The part excluding the mold stopper region 25 is n - The drift region 32 is a type.

[0092] Between adjacent p-type FLR regions 24 and between the outermost p-type FLR region 24 and n + Between the die stopper region 25, the first, second, and third - The n-type epitaxial layers 72 and 73 - The n-type drift region 32 reaches the front surface of the semiconductor substrate 10 and is exposed. + On the starting substrate 71, - Type epitaxial layer (1st, 2nd - By epitaxially growing only the n-type epitaxial layers 72, 73), - The FLR 20 can be formed by simply ion-implanting a p-type impurity into the p-type epitaxial layer.

[0093] 5 and 6, the impurity concentration and thickness of the second region 22 of the p-type FLR region 24 may be adjusted by adjusting the impurity concentration and thickness of the p-type base region 34 of the active regions 1a and 1b. In this case, the configuration of the p-type FLR region 24 in the edge termination region 2 in the depth direction Z is the same as that of the p-type FLR region 24 in FIG. ++ 5, the configuration of the second region 22 in FIG. 2 is the same as the configuration of the second region 22 in the depth direction Z of the contact region 36. - 6. The configuration of the intermediate region 3 may be the same as that of the intermediate region 3 in Fig. 2, or the configuration of the peripheral p-type base region 34c in Fig. 2 may be the same as that of the p-type base region 34 in Fig. 5 and 6.

[0094] 2nd n - When the p-type base region 34 is formed by ion implantation into the p-type epitaxial layer 73, for example, the p-type base region 34 is formed to a predetermined thickness penetrating in the depth direction Z, - Alternatively, the n-type epitaxial layer 73 may be deposited in one stage (see FIG. 6 for example). - The p-type epitaxial layer 73 may be deposited in multiple stages (two stages, reference numerals 73a and 73b, in this case) until it reaches a predetermined thickness t3, and the p-type base regions 34a and 34b formed by ion implantation may be linked in the depth direction Z to form the p-type base region 34 (see FIGS. 12 and 13).

[0095] 2nd n - When the type epitaxial layer 73 (73a, 73b) is deposited in a plurality of stages, the 2n - The p-type epitaxial layers 73a and 73b are formed with p-type impurity layers having different concentrations. - The n-type base region 34d and the p-type base region 34b may be connected in the depth direction Z to form the p-type base region 34 (FIG. 5). - p type drift region 32 side -The gate threshold voltage can be controlled by the p-type impurity concentration of the base region 34d (for example, by making the p-type impurity concentration relatively low).

[0096] 2nd n - When the type epitaxial layer 73 is deposited in one step, for example, the 2n - The deposition of the 2n-type epitaxial layer 73a is omitted. - Only the 2n-type epitaxial layer 73b is deposited (FIG. 6). - The thickness of the p-type epitaxial layer 73b is set to a thickness that allows the p-type base region 34 formed by ion implantation to penetrate in the depth direction Z. For example, - The thickness of the epitaxial layer 73b is set to p ++ The depth of the contact region 36 is set to the same as that of the contact region 36, and the depth direction Z is set to p ++ The second contact region 36 and the second + The mold area 62 may be contacted.

[0097] The drain electrode (second electrode) 52 is disposed on the rear surface (n + The drain electrode 52 is in ohmic contact with the entire surface of the insulating substrate 71 (the back surface of the mold starting substrate 71). On the drain electrode 52, a drain pad (electrode pad: not shown) is provided, for example, with a laminated structure in which a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in this order. The drain pad is soldered to a metal base plate (not shown) of the insulating substrate, for example, made of copper (Cu) foil, and at least a portion of the drain pad is in contact with the base of a cooling fin (not shown) via the metal base plate.

[0098] As described above, by bonding the terminal pin 49 to the Al electrode film 47 on the front surface of the semiconductor substrate 10 and bonding the drain pad on the back surface to the metal base plate of the insulating substrate, the semiconductor substrate 10 has a double-sided cooling structure with cooling structures on both main surfaces. Heat generated in the semiconductor substrate 10 is dissipated from the fins of the cooling fins via the metal base plate bonded to the drain pad on the back surface of the semiconductor substrate 10, and is also dissipated from the metal bar to which the terminal pin 49 on the front surface of the semiconductor substrate 10 is bonded.

[0099] The operation of the semiconductor device 30 according to the first embodiment will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 39 while a positive voltage (forward voltage) is applied to the drain electrode 52 with respect to the source electrode (Al electrode film 47), a channel (n-type inversion layer) is formed in the portion of the p-type base region 34 along the gate trench 37. + The n-type drain region 31 is connected through the channel + A current flows toward the source region 35, turning on the MOSFET (semiconductor device 30).

[0100] On the other hand, when a forward voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 39, the first and second p + The p-type regions 61 and 62 and the p-type base region 34, and the n-type current diffusion region 33 and the n - The MOSFET is maintained in the off state by reverse-biasing the pn junction between the pn junction and the type drift region 32. At this time, a depletion layer spreads from the pn junction, and the electric field applied to the bottom surface of the gate trench 37 located closer to the source electrode than the pn junction is relaxed.

[0101] Furthermore, when the MOSFET is turned off, the depletion layer extending from the pn junction in the active region 1 is connected to the p-type FLR region 24 and the n-type - The depletion layer extends laterally outward (toward the chip end) through edge termination region 2 due to the pn junction with p-type drift region 32. The depletion layer extends outward through edge termination region 2, ensuring a predetermined breakdown voltage based on the dielectric breakdown field strength of silicon carbide and the depletion layer width (the width in the direction from active region 1 toward the chip end (the normal direction of annular p-type FLR region 24)).

[0102] When the MOSFET is turned off, a negative voltage is applied to the drain electrode 52 with respect to the source electrode (Al electrode film 47). + The p-type regions 61 and 62 and the p-type base region 34, and the n-type current diffusion region 33 and the n -A forward current can flow through a parasitic diode formed by a pn junction between the semiconductor substrate 10 and the pn-type drift region 32. For example, when the MOSFET is an inverter device, the parasitic diode built into the semiconductor substrate 10 can be used as a freewheeling diode for protecting the MOSFET itself.

[0103] Next, a method for manufacturing the semiconductor device 30 according to the first embodiment will be described. Figures 7 to 16 are cross-sectional views showing the semiconductor device according to the first embodiment in the middle of its manufacture. Figures 7 to 15 show the active region 1 (see Figure 2). Figure 16 shows only one p-type FLR region 24 constituting the FLR 20 (see Figure 2), but as described above, the FLR 20 is composed of multiple p-type FLR regions 24 of the same configuration. Each part of the edge termination region 2 and intermediate region 3 in Figures 1 and 2 is formed simultaneously with each part having the same impurity concentration and depth as each part formed in the active region 1.

[0104] First, as shown in FIG. 7, a silicon carbide n + As a starting substrate (semiconductor wafer) 71, for example, a nitrogen (N)-doped silicon carbide single crystal substrate is prepared. + On the front surface of the starting mold substrate 71, n + The first n-type starting substrate 71 is doped with nitrogen at a lower concentration. - A first epitaxial layer 72 is epitaxially grown. - The thickness t1 of the type epitaxial layer 72 is, for example, about 30 μm in the case of a breakdown voltage of 3300V class, and is, for example, about 10 μm in the case of a breakdown voltage of 1200V class.

[0105] Next, as shown in FIG. 8, a first n-type impurity layer is formed in the active region 1 by photolithography and ion implantation of a p-type impurity such as Al. - The surface region of the first p-type epitaxial layer 72 is + A mold region 61 and a second p + p that is part of type domain 62 + At this time, the 1nth mold region 91 is formed. - The surface region of the first p-type epitaxial layer 72 is +At the same time as the mold region 61, the outer periphery p of the intermediate region 3 + The p-type region 62a and each of the first regions 21 of the plurality of p-type FLR regions 24 constituting the FLR 20 of the edge termination region 2 are each a part of + A mold region 91 is formed.

[0106] Next, a first n-type impurity is formed in the active region 1 by photolithography and ion implantation of an n-type impurity, for example nitrogen. - An n-type region 92 that will become a part of the n-type current diffusion region 33 is formed in the surface region of the epitaxial layer 72. At this time, the first n-type region 92 is formed in the intermediate region 3 and the edge termination region 2. - An n-type region 92 that will become a part of the n-type current diffusion region 33a is formed in the surface region of the p-type epitaxial layer 72. + The order of forming the mold regions 61 and 91 may be reversed.

[0107] Between adjacent first regions 21 in edge termination region 2, n-type regions 92 are formed as part of peripheral n-type current diffusion region 33a. + The distance d2 between the mold regions 61 and 91 is, for example, about 1.5 μm. + The mold regions 61 and 91 have a depth d1 of about 0.5 μm and an impurity concentration of 3.0×10 18 / cm 3 Above 7.0×10 18 / cm 3 The depth d3 and impurity concentration of the n-type region 92 are, for example, about 0.4 μm and 5.0×10 16 / cm 3 Above 1.0×10 17 / cm 3 It is about the following.

[0108] 1st n - The portion of the epitaxial layer 72 that is not implanted with ions is n -In the edge termination region 2, an n-type drift region 32 is formed between the outer end (chip end side) of the n-type region 92 that is to become a part of the peripheral n-type current diffusion region 33a and the end of the chip region (the region that will become the semiconductor chip after the semiconductor wafer is diced). - Type drift region 32 (1n - The ion-implanted portion of the first epitaxial layer 72 remains. - The surface of the epitaxial layer 72 is exposed.

[0109] Next, as shown in FIG. - The n-type epitaxial layer 72 is doped with an n-type impurity such as nitrogen. - The first n-type epitaxial layer is epitaxially grown to a thickness t2 of, for example, about 0.5 μm. - The first epitaxial layer 72 is then grown to a predetermined thickness. - The impurity concentration of the thickened portion 72a of the epitaxial layer 72 is, for example, 3×10 15 / cm 3 The n of the edge termination region 2 may be - The drift region 32 has a first n-th region in the depth direction Z. - 4. The epitaxial layer 72 is connected to the thickened portion 72 a of the epitaxial layer 72 .

[0110] Next, as shown in FIG. 10, a first n-type impurity layer is formed in the active region 1 by photolithography and ion implantation of p-type impurities such as Al. - The thickened portion 72a of the epitaxial layer 72 is provided with a second p + p that is part of type domain 62 + A mold region 93 is formed. - The p-type epitaxial layer 72 has a thickened portion 72a. + At the same time as the mold region 93, the outer periphery p of the intermediate region 3 + The p-type region 62a and each of the first regions 21 of the plurality of p-type FLR regions 24 constituting the FLR 20 of the edge termination region 2 are each a part of + A mold region 93 is formed.

[0111] Next, a first n-type impurity is formed in the active region 1 by photolithography and ion implantation of an n-type impurity, for example nitrogen. - In the thickened portion 72a of the epitaxial layer 72, an n-type region 94 that will become a part of the n-type current spreading region 33 is formed. - In the thickened portion 72a of the epitaxial layer 72, an n-type region 94 that will become part of the n-type current diffusion region 33 and an n-type region 94 that will become part of the peripheral n-type current diffusion region 33a are simultaneously formed.

[0112] 1st n - The portion 72a of the thickened portion of the n-type epitaxial layer 72 that is not implanted with ions is - In the edge termination region 2, an n-type drift region 32 is formed between the outer end (chip end side) of the n-type region 94 that is a part of the peripheral n-type current diffusion region 33a and the end of the chip region. - Type drift region 32 (1n - The thickened portion 72a of the epitaxial layer 72 (the portion not implanted with ions) remains, and the first n - The thickened portion 72a of the epitaxial layer 72 is exposed at its surface.

[0113] p adjacent to the depth direction Z + The mold regions 91 and 93 are connected to each other to form a second p + The mold region 62 and the outer periphery p + In the p-type FLR region 24, the first regions 21 of the p-type FLR regions 24 are formed. The n-type regions 92, 94 adjacent to each other in the depth direction Z are connected to each other to form the n-type current diffusion region 33 and the peripheral n-type current diffusion region 33a. + The conditions of the impurity concentration of the n-type region 93 and the n-type region 94 are, for example, p + The p-type region 91 and the n-type region 92 are similar. + The order of forming the n-type region 93 and the n-type region 94 may be reversed.

[0114] Next, as shown in FIG. -A second n-type epitaxial layer 72 is formed on the n-type epitaxial layer 72 by doping with an n-type impurity such as nitrogen. - 12, a second n-type epitaxial layer 73 (73a) is epitaxially grown in the active region 1 by photolithography and ion implantation of p-type impurities such as Al. - The epitaxial layer 73a has a second n-type - A p-type region 95 that will become a part of the p-type base region 34 (p-type base region 34a) is formed so as to penetrate the p-type epitaxial layer 73a. The impurity concentration of the p-type region 95 is, for example, 1.0×10 17 / cm 3 Above 8.0×10 18 / cm 3 It is about the following.

[0115] At this time, the 2nth - In the epitaxial layer 73 (73a), a p-type region 95 that will become the p-type base region 34a is formed, and at the same time, each of the p-type regions 95 that will become the peripheral p-type base region 34c in the intermediate region 3 and each of the second regions 22 of the plurality of p-type FLR regions 24 that make up the FLR 20 in the edge termination region 2 is formed. - The second n-type epitaxial layer 73a is doped with an n-type impurity such as nitrogen. - The second n-type epitaxial layer 73b is epitaxially grown. - The type epitaxial layer 73 (73a, 73b) is formed to a predetermined thickness t3.

[0116] Next, a second n-type GaN layer is formed in the active region 1 by photolithography and ion implantation of p-type impurities such as Al. - A p-type region 96 that will become a part of the p-type base region 34 (p-type base region 34b) is formed in the p-type epitaxial layer 73 (73b). - In the epitaxial layer 73b, p-type regions 96 that will become the p-type base region 34b, as well as p-type regions 96 that will become part of the peripheral p-type base region 34c in the intermediate region 3 and part of each of the second regions 22 of the plurality of p-type FLR regions 24 that make up the FLR 20 in the edge termination region 2 are formed at the same time.

[0117] 2nd n - The impurity concentrations of the epitaxial layers 73a and 73b are, for example, 4.0×10 17 / cm 3 The second n - The second n-type epitaxial layers 73a and 73b are laminated to a predetermined thickness t3. - A 2n-type epitaxial layer 73 is formed. - The thickness t3 of the p-type epitaxial layer 73 is, for example, about 1.1 μm or less. The p-type regions 95, 96 adjacent to each other in the depth direction Z are connected to each other to form the p-type base region 34, the peripheral p-type base region 34c, and each of the second regions 22 of the multiple p-type FLR regions 24.

[0118] 2nd n - The thickness of each of the epitaxial layers 73a and 73b is 2n - The thickness of the p-type epitaxial layers 73a and 73b is the thickness through which the p-type regions 95 and 96 formed by ion implantation penetrate in the depth direction Z. - When the predetermined thickness t3 of the type epitaxial layer 73 is a thickness that penetrates the p-type base region 34 formed by ion implantation, - The epitaxial layer 73 is a 2n - Instead of depositing (epitaxially growing) the type epitaxial layers 73a and 73b in two stages, they may be deposited in one stage to a predetermined thickness t3.

[0119] The reason is as follows. In the conventional structure (see FIG. 20), when the p-type epitaxial layer 273 that becomes the p-type base region 234 is epitaxially grown, the p-type base region 234 and the n - The second p-type epitaxial layer 272 is formed by ion implantation. + In the first embodiment, for example, the 2nth layer deposited in one step is in contact with the mold region 262 in the depth direction Z. - The thickness t3 of the epitaxial layer 73, or the thickness of the second n - Assume that the thicknesses of the type epitaxial layers 73a and 73b are each too thick.

[0120] In this case, the 2nth - The p-type base region 34 formed by ion implantation inside the p-type epitaxial layer 73, the peripheral p-type base region 34c, and each of the second regions 22 of the plurality of p-type FLR regions 24 form a 2n-th order. - The depth of the n-type epitaxial layer 73 is not large enough to penetrate the n-type epitaxial layer 73. - p-type regions 95 and 96 are formed in the n-type epitaxial layers 73a and 73b by ion implantation, respectively. - The depth does not penetrate through the type epitaxial layers 73a and 73b.

[0121] A p-type base region 34 and a first n - The second p-type epitaxial layer 72 + The n remaining between the mold region 62 and - type area(n - The p-type drift region 32 is connected to the p-type base region 34 and the second p + As a result, the 2nth mold region 62 is disconnected. - When the p-type epitaxial layer 73 is deposited in one step, its thickness t3 is set to 1 / 2 the thickness of the p-type base region 34 formed by ion implantation. - It is preferable that the thickness of the n-type epitaxial layer 73 is set to a thickness necessary for the channel (n-type inversion layer) (for example, about 0.5 μm) or more and about 0.8 μm or less.

[0122] Therefore, the 2nth - The thickness t3 of the epitaxial layer 73, or the thickness of the second n - The thicknesses of the p-type epitaxial layers 73a and 73b are thinner than the thickness t201 (see FIG. 20) of the p-type epitaxial layer 273 that becomes the p-type base region 234 in the conventional structure. + On the starting substrate 71 - Type epitaxial layer (1st, 2nd - In this way, an n-type semiconductor substrate 10 (semiconductor wafer) is produced in which only n-type epitaxial layers 72, 73) are stacked in order.

[0123] Edge termination region 2 n- The drift region 32 has a 2n-th junction at its portion facing the depth direction Z. - The n-th epitaxial layer 73 is connected to the n-th epitaxial layer 74. - The portion of the epitaxial layer 73 that is not implanted with ions is n - In the edge termination region 2, n-type p-type base regions 34c are formed between the outer peripheral p-type base region 34c and the innermost second region 22, between adjacent second regions 22, and between the outermost second region 22 and the chip edge. - The n-th type drift region 32 remains. - The surface of the epitaxial layer 73 is exposed.

[0124] 13, a set of steps of photolithography and ion implantation is repeated under different conditions. - The surface region of the n-type epitaxial layer 73 is + type source region 35 and p ++ A second n-type contact region 36 is formed in the edge termination region 2. - The surface region of the n-type epitaxial layer 73 is + Form a mold stopper region 25. + Type source region 35, p ++ Type contact region 36 and n + The order in which the mold stopper regions 25 are formed can be changed.

[0125] At this time, the 2nth - The surface region of the p-type epitaxial layer 73 is ++ The outer periphery p of the intermediate region 3 is ++ The p-type contact region 36a and the third regions 23 of the p-type FLR regions 24 that constitute the FLR 20 of the edge termination region 2 + The impurity concentration of the third region 23 is, for example, 1.0×10 17 / cm 3 Above 5.0×10 20 / cm 3 As mentioned above, the first, second and third -The first to third regions 21 to 23 formed in the p-type epitaxial layers 72 (72a) and 73 (73a, 73b), respectively, and adjacent to each other in the depth direction Z are all connected to form the p-type FLR regions 24.

[0126] The first to third regions 21-23 adjacent to each other in the depth direction Z are inevitably misaligned by about 0.1 μm in the normal direction (horizontal direction in FIG. 16) due to the alignment accuracy of the ion implantation mask used to form the first to third regions 21-23. This makes it possible to substantially shorten the interval between the adjacent p-type FLR regions 24. The magnitude of the misalignment between the first to third regions 21-23 adjacent to each other in the depth direction Z is, for example, about 0.05 μm or more and 0.3 μm or less. The first to third regions 21-23 have approximately the same width (the width in the normal direction of the ring-shaped p-type FLR region 24). "Approximately the same width" means that the width is the same within a range including an allowable error due to process variation.

[0127] FIG. 16 shows the 1n - The first region 21 (p) is formed in two separate steps by implanting ions into the first deposited portion (see FIG. 8) of the epitaxial layer 72 and then implanting ions into the thickened portion 72a (see FIG. 9). + The positional deviation in the normal direction between the mold regions 91 and 93 is omitted in the illustration. - The positional deviation in the normal direction between second regions 22 (between p-type regions 95, 96) formed in two separate steps by ion implantation into p-type epitaxial layers 73a, 73b (see FIGS. 12 and 13), respectively, is omitted in the drawing.

[0128] If there is a positional deviation in the normal direction between the partial FLRs (first to third regions 21 to 23) adjacent to each other in the depth direction Z, the electric field becomes high locally at the position of the positional deviation. For this reason, for example, when the FLR 20 of the first embodiment is applied to a semiconductor device using silicon as a semiconductor material, the partial FLR and the n - Avalanche breakdown occurs at the pn junction with the type drift region, and the device is easily destroyed by the electron current (hereafter referred to as avalanche current) that flows from the point where avalanche breakdown occurs toward the source electrode.

[0129] One of the causes of destruction by avalanche current is that the built-in voltage of the pn junction surface of silicon is small at 0.6V, making it prone to parasitic operation. When the semiconductor device using silicon as a semiconductor material is a MOSFET, the avalanche current flows as a forward current of the MOSFET's parasitic diode, and the parasitic diode operation causes deterioration over time, making the device prone to destruction. When the semiconductor device using silicon as a semiconductor material is an IGBT, the IGBT's parasitic thyristor is turned on by the avalanche current, making the device prone to destruction.

[0130] Furthermore, when the FLR 20 of the first embodiment is applied to a semiconductor device using silicon as a semiconductor material, during high temperature (e.g., 200° C. or higher) operation, the adverse effects of leakage current become greater at locations where there is a normal misalignment between partial FLRs adjacent in the depth direction Z, making the device more susceptible to destruction. Specifically, during high temperature operation at 200° C., the leakage current increases to 10 mA or more, immediately leading to destruction. On the other hand, since silicon carbide has a wider band gap than silicon as described above, a semiconductor device using silicon carbide as a semiconductor material has a small leakage current even during high temperature operation.

[0131] In the first embodiment, even if there are locations where the electric field is locally high due to misalignment in the normal direction between the partial FLRs adjacent in the depth direction Z, the wide band gap of silicon carbide prevents an increase in leakage current. In addition, the built-in voltage of the pn junction surface of silicon carbide is high at about 3V to 5V, so parasitic operation is unlikely to occur and breakdown is unlikely to occur. Therefore, the impurity concentration and the number of stacked layers of the partial FLRs constituting the p-type FLR region 24 may be set in consideration of the amount of misalignment in the normal direction between the partial FLRs adjacent in the depth direction Z.

[0132] For example, by increasing the number of stacked partial FLRs constituting p-type FLR region 24, p-type FLR region 24 becomes deeper, so that it is less susceptible to adverse effects due to electric charges and is less likely to be destroyed even if there is a positional shift in the normal direction between partial FLRs adjacent in depth direction Z. In addition, because it is less susceptible to adverse effects due to electric charges, it is also possible to thin the thickness of first protective film 50 in edge termination region 2 to about 5 μm (the thickness of protective film 250 in edge termination region 202 of the conventional structure is about 10 μm), or to provide a nitride film (SiN film) instead of first protective film 50.

[0133] The impurity concentration of the partial FLR constituting the p-type FLR region 24 is, for example, 1×10 16 / cm 3 The impurity concentration may be approximately equal to or greater than the p-type region of any of the MOSFETs in the active region 1 and may be substantially the same as that of the p-type region, or may be set for the FLR 20. The impurity concentrations of the multiple partial FLRs constituting the p-type FLR region 24 may all be substantially the same, or may differ from one another. "Substantially the same impurity concentration" means that the impurity concentrations are the same within a range that includes the allowable error due to process variations.

[0134] For example, as described above, the first to third regions 21 to 23 of the p-type FLR region 24 are each + 62, the p-type base region 34 and the p ++ When the first to third regions 21 to 23 are formed simultaneously with the contact region 36, the impurity concentrations of the first to third regions 21 to 23 are, for example, 5×10 18 cm / 3 About 4×10 17 cm / 3 degree and 3×10 20 cm / 3 The first to third regions 21 to 23 may have substantially the same thickness. "Substantially the same thickness" means that the thickness is the same within a range including an allowable error due to process variation.

[0135] Further reducing the thickness, multiple n layers were deposited in multiple stages. -Alternatively, the number of partial FLRs constituting the p-type FLR region 24 may be increased by forming partial FLRs in the p-type epitaxial layers by ion implantation. - The thinner the epitaxial layer, the smaller the n - The partial FLR formed by ion implantation into the p-type epitaxial layer can have a uniform p-type impurity concentration (BOX profile) in the depth direction Z. A uniform impurity concentration means that the impurity concentration is approximately the same within a range including tolerances due to process variations.

[0136] Next, all the diffusion regions (first and second p + 3, n-type regions 61 and 62, n-type current diffusion region 33, p-type base region 34, + Type source region 35, p ++ a peripheral n-type contact region 36; a peripheral n-type current diffusion region 33a; a peripheral p-type base region 34c; ++ the p-type contact region 36a, the p-type FLR region 24 and the n + The impurity activation of the mold stopper region 25) is performed by heat treatment for about 2 minutes at a temperature of about 1700° C. The impurity activation of all the diffusion regions may be performed in one heat treatment, or heat treatment may be performed for each ion implantation.

[0137] Next, as shown in FIG. 14, n-type semiconductor substrate 10 is removed from the front surface thereof by photolithography and etching. + A first p-type source region 35, a p-type base region 34 and an n-type current diffusion region 33 are formed. + A gate trench 37 is formed so as to reach the gate region 61. Next, as shown in FIG. + Type source region 35, p ++ The contact region 36 and the outer periphery p ++ A gate insulating film 38 is formed along the surface of the contact region 36a and the inner walls (side walls and bottom surface) of the gate trench 37.

[0138] The gate insulating film 38 may be, for example, a thermal oxide film formed by thermally oxidizing the semiconductor surface at a temperature of about 1000° C. in an oxygen (O2) atmosphere, or may be a deposited film by high temperature oxidation (HTO: High Temperature Oxide). Next, for example, a phosphorus (P) doped polysilicon layer is deposited (formed) on the front surface of the semiconductor substrate 10 so as to fill the inside of the gate trench 37, and then selectively removed, leaving only the portion that will become the gate electrode 39 inside the gate trench 37.

[0139] Also, a part of the polysilicon layer may be left as the gate electrode 39, and at the same time, a part of the polysilicon layer may be left as the gate polysilicon wiring layer 82. In this case, after the formation of the gate insulating film 38 and before the deposition of the phosphorus-doped polysilicon layer, a field oxide film 81 is formed on the front surface of the semiconductor substrate 10 in the intermediate region 3 and the edge termination region 2. Although not shown in FIG. 2, the gate insulating film 38 may remain between the front surface of the semiconductor substrate 10 and the field oxide film 81.

[0140] Next, an interlayer insulating film 40 made of, for example, BPSG (Boro Phospho Silicate Glass) or PSG is formed to a thickness of, for example, 1 μm over the entire front surface of the semiconductor substrate 10 to cover the gate electrode 39 and the gate polysilicon wiring layer 82. Next, contact holes 40a and 40b are formed by photolithography and etching in the active region 1, penetrating the interlayer insulating film 40 and the gate insulating film 38 in the depth direction Z. In the intermediate region 3, a contact hole 40c is formed, penetrating the interlayer insulating film 40 in the depth direction Z.

[0141] The contact hole 40a is connected to the n + type source region 35 and p ++ The contact region 36 is exposed. ++The gate contact region 36a is exposed. The gate polysilicon wiring layer 82 is exposed in the contact hole 40c. Next, the interlayer insulating film 40 is planarized (reflowed) by heat treatment. Next, a first TiN film 42 is formed to cover only the interlayer insulating film 40 in the active region 1. Next, a NiSi film 41 is formed on the portion of the front surface of the semiconductor substrate 10 exposed in the contact hole 40a. In addition, a NiSi film is formed as a drain electrode 52 in ohmic contact with the rear surface of the semiconductor substrate 10.

[0142] Next, a first Ti film 43, a second TiN film 44, and a second Ti film 45 are laminated in this order so as to cover the NiSi film 41 and the first TiN film 42, and a barrier metal 46 is formed so as to cover almost the entire surface of the active region 1. Next, an Al electrode film 47 is deposited on the second Ti film 45. Simultaneously with the Al electrode film 47, a gate pad (not shown) is formed on the interlayer insulating film 40 apart from the Al electrode film 47, and a gate metal wiring layer 83 is formed on the gate polysilicon wiring layer 82 inside the contact hole 40c.

[0143] Next, a drain pad (not shown) is formed by sequentially stacking, for example, a Ti film, a Ni film, and a gold (Au) film on the surface of the drain electrode 52. Next, a first protective film 50 made of polyimide is formed on the entire front surface of the semiconductor substrate 10, and the Al electrode film 47, the gate pad, and the gate metal wiring layer 83 are covered with the first protective film 50.

[0144] Next, the first protective film 50 is selectively removed to expose the Al electrode film 47 and the gate pad at different openings in the first protective film 50. Next, after a general plating pretreatment, a plating film 48 is formed on the portion (source pad) of the Al electrode film 47 exposed at the opening of the first protective film 50 by a general plating treatment. Next, the plating film 48 is dried by a heat treatment (bake). Next, a second protective film 51 made of polyimide is formed to cover the boundary between the plating film 48 and the first protective film 50.

[0145] Next, the strength of the polyimide films (first and second protective films 50, 51) is improved by heat treatment (curing). Next, terminal pins 49 are bonded onto the plating film 48 with a solder layer. On the gate pad, a first protective film, a plating film, and a second protective film are formed in this order at the same time as the wiring structure on the Al electrode film 47, and a wiring structure is formed in which the terminal pins are bonded with a solder layer. Thereafter, the semiconductor substrate 10 (semiconductor wafer) is diced (cut) to separate the individual chip regions, thereby completing the MOSFET (semiconductor device 30) shown in FIGS. 1 and 2.

[0146] As described above, according to the first embodiment, the semiconductor substrate is - By depositing only the n-type epitaxial layer, the main part of the MOSFET in the active region (near the channel) is n-type. - This allows the formation of a channel with good crystallinity and low impurity concentration, which reduces the electric field applied to the bottom surface of the gate trench. + The JFET resistance between the die regions is reduced, and the conduction loss can be reduced.

[0147] According to the first embodiment, the semiconductor substrate is - By depositing only the n-type epitaxial layer, - The FLR can be formed by arranging multiple p-type FLR regions concentrically around the active region by ion implantation into the p-type epitaxial layer. Therefore, unlike the conventional structure (see FIG. 20), the front surface of the semiconductor substrate is not exposed to the n-type FLR region in the edge termination region. - There is no need to form a step to expose the type epitaxial layer, and the entire front surface of the semiconductor substrate becomes a continuous flat surface from the active region to the chip edge.

[0148] In addition, in the conventional structure, when the FLR 220 is a spatial modulation type, the p - Type region 221 and p --The overlap of the ion implantation for forming the mold region 222 becomes complicated, and the alignment of the ion implantation mask becomes difficult. - By forming partial FLRs with different impurity concentrations each time a p-type epitaxial layer is deposited and forming a p-type FLR region by arranging multiple partial FLRs adjacent to each other in the depth direction, the impurity concentration distribution in the depth direction of the p-type FLR region can be easily adjusted.

[0149] Moreover, according to the first embodiment, the number of stacked partial FLRs constituting the p-type FLR region can be easily increased or decreased, and the depth of the p-type FLR region from the front surface of the semiconductor substrate can be easily adjusted by increasing or decreasing the number of stacked partial FLRs constituting the p-type FLR region. For example, the length (width in the normal direction) of the edge termination region can be narrowed while maintaining the breakdown voltage by increasing the number of stacked partial FLRs constituting the p-type FLR region and deepening the depth of the p-type FLR region from the front surface of the semiconductor substrate.

[0150] On the other hand, the number of stacked partial FLRs constituting the p-type FLR region is reduced, and the p-type FLR region is formed from the front surface of the semiconductor substrate to the first and second p-type FLR layers that relax the electric field applied to the bottom surface of the gate trench in the active region. + By terminating the bias at a position shallower than the die region, the electric field can be concentrated in the active region when the semiconductor element is overloaded, thereby ensuring the safe operating area (RBSOA) of the semiconductor element.

[0151] Thus, according to the first embodiment, the impurity concentration and depth of the p-type FLR region can be easily adjusted, and a highly complete breakdown voltage structure (FLR) can be easily formed. The high degree of completion of the breakdown voltage structure can improve the reliability of the semiconductor device. In addition, since there is no etching process for forming a step on the front surface of the semiconductor substrate as in the conventional structure, and no material is discarded by the etching (a part of the p-type epitaxial layer that becomes the p-type base region), an economically excellent and stable breakdown voltage structure can be ensured.

[0152] (Embodiment 2) Next, the structure of the semiconductor device according to the second embodiment will be described. Figures 17 to 19 are cross-sectional views showing an example of a voltage-resistant structure of the semiconductor device according to the second embodiment. Figures 17 to 19 show one each of p-type FLR regions 102a to 102c constituting the FLRs 101a to 101c in the edge termination regions of the semiconductor devices 100a to 100c according to the second embodiment, but the FLRs 101a to 101c of the second embodiment are also composed of a plurality of p-type FLR regions 102a to 102c of the same configuration concentrically surrounding the active region, similar to the FLR 20 of the first embodiment (see Figure 2).

[0153] 17-19 according to the second embodiment differ from semiconductor device 30 (FIGS. 2 and 16) according to the first embodiment in that at least one of a plurality of partial FLRs (p-type regions) adjacent to each other in the depth direction Z to form a p-type FLR region has a relatively wide width (width in the normal direction). For example, an FLR 101a may be formed by concentrically arranging a plurality of p-type FLR regions 102a having a three-layer structure in which first to third regions (partial FLRs) 21a-23a, the width of which increases as the region is positioned deeper from the front surface of semiconductor substrate 10, are adjacent to each other in the depth direction Z (FIG. 17).

[0154] Alternatively, FLR 101b may be formed by concentrically arranging a plurality of p-type FLR regions 102b having a three-layer structure in which first to third regions (partial FLR) 21b to 23b are adjacent in the depth direction Z, the narrower the width the deeper the region from the front surface of semiconductor substrate 10 (FIG. 18). FLR 101c may be formed by concentrically arranging a plurality of p-type FLR regions 102c having a three-layer structure in which first and third regions (partial FLR) 21c and 23c are adjacent, the wider the region the deeper and shallower the region from the front surface of semiconductor substrate 10 in the depth direction Z, the wider the region the deeper and shallower the region the central second region (partial FLR) 22c is (FIG. 19).

[0155] By varying the widths of the multiple partial FLRs, it becomes easier to adjust the impurity concentrations of the p-type FLR regions 102a-102c. In the FLRs 101a-101c in the above-described second embodiment, the partial FLR with the widest width is configured to protrude further than the other partial FLRs at both ends in the in-plane direction of the semiconductor substrate 10 from the active region 1 to the edge termination structure 2. In this case, since the partial FLR with the widest width determines the interval between the adjacent p-type FLR regions 102a-102c, a high breakdown voltage can be obtained stably even if the alignment of each layer of the partial FLR is shifted.

[0156] Regarding the position in the normal direction between the partial FLRs adjacent in the depth direction Z (horizontal direction in Figs. 17 to 19), it is preferable to form the widest partial FLR so as to protrude inward and outward in the normal direction by at least 0.05 µm or more from the other partial FLRs. The difference in the position in the normal direction between the partial FLRs adjacent in the depth direction Z is changed variously depending on the required withstand voltage. Furthermore, when a plurality of widest partial FLRs are provided as in Fig. 19, the same effect as in the first embodiment can be obtained in the first and third regions (partial FLRs) 21c and 23c, and the effect shown in the second embodiment can be obtained in the second region (partial FLR) 22c.

[0157] As described above, according to the second embodiment, the width of at least one of the partial FLRs that are adjacent to each other in the depth direction to form one p-type FLR region is made relatively wide. As a result, even if one or more of the partial FLRs that are adjacent to each other in the depth direction to form one p-type FLR region are formed shifted from a predetermined position in the normal direction of the p-type FLR region, the relatively wide partial FLR can ensure that all the partial FLRs are adjacent to each other in the depth direction. This further improves the completeness of the FLRs, and thus the same effect as in the first embodiment can be obtained.

[0158] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can be applied to a case where a wide band gap semiconductor other than silicon carbide is used instead of silicon carbide as a semiconductor material. The present invention also applies when the conductivity type (n-type, p-type) is reversed. [Industrial Applicability]

[0159] INDUSTRIAL APPLICABILITY As described above, the semiconductor device and the method of manufacturing the semiconductor device according to the present invention are useful for power semiconductor devices that control high voltages and large currents. [Explanation of symbols]

[0160] 1,1a,1b active area 2 Edge Termination Area 3 Intermediate area 10. Semiconductor Substrate 20, 20a, 20b, 101a~101c FLR 21 The first region at the bottom of the p-type FLR region 22 The second region in the center of the p-type FLR region 23 The third region on top of the p-type FLR region 24,24a,24b,102a~102c p-type FLR region 25 n + Mold stopper area 30, 100a-100c Semiconductor device 31 n + Type drain region 32n - Mold Drift Region 33 n-type current diffusion region 33a Peripheral n-type current diffusion region 34, 34a, 34b p-type base region 34c Peripheral p-type base region 34d p - Type-based regions 35 n + Type Source Area 36 pages ++ Mold Contact Area 36a outer circumference p ++Mold Contact Area 37 Gate Trench 38 Gate insulating film 39 Gate electrode 40 Interlayer insulating film 40a~40c Contact holes 41 NiSi film 42 1st TiN film 43 1st Ti film 44 2nd TiN film 45 2nd Ti film 46 Barrier Metal 47 Al electrode film 48 Plating Film 49 Terminal Pins 50 1st protective film 51 Second protective film 52 Drain electrode 61,62,91,93 p + type area 62a outer circumference p + type area 71 n + Starting substrate 72 No. 1n - Type epitaxial layer 72a 1stn - The part where the epitaxial layer is thickened 73, 73a, 73b 2nd - Type epitaxial layer 81 Field oxide 82 Gate polysilicon wiring layer 83 Gate metal wiring layer 92,94 n-type region 95,96 p-type region d1 p + Type area depth d2 adjacent p + Distance between mold regions d3 Depth of n-type region t1 n - of the n-type epitaxial layer + The thickness of the first layer to be laminated on the starting substrate t2n - The thickness of the thickened portion of the epitaxial layer t3 Thickness of p-type epitaxial layer X: A first direction parallel to the front surface of the semiconductor substrate Y: A second direction that is parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z depth direction

Claims

1. A semiconductor device having an active region through which a main current flows and a termination region surrounding the active region, a semiconductor substrate made of a semiconductor having a band gap wider than that of silicon; a first semiconductor region of a first conductivity type provided within the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region in the active region; a predetermined element structure formed by a pn junction between the second semiconductor region and the first semiconductor region in the active region; A first electrode electrically connected to the second semiconductor region; a second electrode provided on a second main surface of the semiconductor substrate; a second conductivity type breakdown voltage region provided in the termination region between the first main surface of the semiconductor substrate and the first semiconductor region, the second conductivity type breakdown voltage region being spaced apart from the element structure and concentrically arranged around the active region; Equipped with the first main surface of the semiconductor substrate is a flat surface extending from the active region to the termination region; a first conductivity type epitaxial layer forming a first main surface of the semiconductor substrate; the second semiconductor region and the second conductivity type breakdown voltage region are selectively provided within the first conductivity type epitaxial layer, the first semiconductor region is a portion of the first conductive type epitaxial layer excluding the second semiconductor region and the second conductive type breakdown voltage region, and reaches a first main surface of the semiconductor substrate between adjacent second conductive type breakdown voltage regions; Each of the second conductivity type withstand voltage regions has a plurality of second conductivity type regions adjacent to each other in a depth direction, three or more second conductivity type regions are provided adjacent to each other in a depth direction in the termination region, A semiconductor device characterized in that, among three or more second conductivity type regions adjacent in a depth direction, the impurity concentration of the second conductivity type region at the center of the depth direction of the second conductivity type withstand voltage region is lower than the impurity concentrations of the other second conductivity type regions.

2. A semiconductor device having an active region through which a main current flows and a termination region surrounding the active region, a semiconductor substrate made of a semiconductor having a band gap wider than that of silicon; a first semiconductor region of a first conductivity type provided within the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region in the active region; a predetermined element structure formed by a pn junction between the second semiconductor region and the first semiconductor region in the active region; A first electrode electrically connected to the second semiconductor region; a second electrode provided on a second main surface of the semiconductor substrate; a second conductivity type breakdown voltage region provided in the termination region between the first main surface of the semiconductor substrate and the first semiconductor region, the second conductivity type breakdown voltage region being spaced apart from the element structure and concentrically arranged around the active region; Equipped with the first main surface of the semiconductor substrate is a flat surface extending from the active region to the termination region; a first conductivity type epitaxial layer forming a first main surface of the semiconductor substrate; the second semiconductor region and the second conductivity type breakdown voltage region are selectively provided within the first conductivity type epitaxial layer, the first semiconductor region is a portion of the first conductive type epitaxial layer excluding the second semiconductor region and the second conductive type breakdown voltage region, and reaches a first main surface of the semiconductor substrate between adjacent second conductive type breakdown voltage regions; Each of the second conductivity type withstand voltage regions has a plurality of second conductivity type regions adjacent to each other in a depth direction, The element structure includes: a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a trench penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region; a gate electrode provided inside the trench via a gate insulating film; a fourth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region at a position farther from the trench than the third semiconductor region, the fourth semiconductor region having a higher impurity concentration than the second semiconductor region; a second conductivity type high concentration region having an impurity concentration higher than that of the second semiconductor region, the second conductivity type high concentration region being selectively provided within the first semiconductor region and located closer to the second main surface of the semiconductor substrate than a bottom surface of the trench; any one of the plurality of second conductivity type regions is located at the same depth as the second semiconductor region and has the same impurity concentration as the second semiconductor region; a second semiconductor region that is formed on the second conductive type region and has a different impurity concentration from the second semiconductor region;

3. 3. The semiconductor device according to claim 1, further comprising a first conductivity type region having a higher impurity concentration than the first semiconductor region, the first conductivity type region being provided inside the first semiconductor region and in contact with the plurality of second conductivity type breakdown voltage regions in the termination region.

4. 3. The semiconductor device according to claim 1, wherein the positions of the second conductive type regions adjacent to each other in the depth direction in the normal direction are shifted from each other by 0.05 [mu]m to 0.3 [mu]m.

5. A semiconductor device according to any one of claims 1 to 4, characterized in that, among the plurality of second conductivity type regions adjacent in the depth direction, the normal width of at least one of the second conductivity type regions is different from the normal width of the other second conductivity type regions.

6. 5. A semiconductor device according to claim 1, wherein the impurity concentration of at least one of the second conductivity type regions adjacent in the depth direction is different from the impurity concentrations of the other second conductivity type regions.

7. three or more second conductivity type regions are provided adjacent to each other in a depth direction in the termination region, 3. The semiconductor device according to claim 2, wherein, among the three or more second conductivity type regions adjacent in the depth direction, the impurity concentration of the second conductivity type region at the center in the depth direction of the second conductivity type withstand voltage region is lower than the impurity concentrations of the other second conductivity type regions.

8. The element structure includes: a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a trench penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region; a gate electrode provided inside the trench via a gate insulating film; a fourth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region at a position farther from the trench than the third semiconductor region, the fourth semiconductor region having a higher impurity concentration than the second semiconductor region; a second conductivity type high concentration region having an impurity concentration higher than that of the second semiconductor region, the second conductivity type high concentration region being selectively provided within the first semiconductor region and located closer to the second main surface of the semiconductor substrate than a bottom surface of the trench; The termination region includes three second conductivity type regions adjacent to each other in a depth direction, Among the three second conductivity type regions adjacent in the depth direction, the second conductivity type region closest to the first main surface of the semiconductor substrate has the same impurity concentration as the fourth semiconductor region; the second conductivity type region farthest from the first main surface of the semiconductor substrate has the same impurity concentration as the second conductivity type high concentration region; 2. The semiconductor device according to claim 1, wherein the remaining second conductive type region has the same impurity concentration as that of the second semiconductor region.

9. The termination region includes three second conductivity type regions adjacent to each other in a depth direction, Among the three second conductivity type regions adjacent in the depth direction, the second conductivity type region closest to the first main surface of the semiconductor substrate has the same impurity concentration as the fourth semiconductor region; the second conductivity type region farthest from the first main surface of the semiconductor substrate has the same impurity concentration as the second conductivity type high concentration region; 3. The semiconductor device according to claim 2, wherein the remaining second conductive type region has the same impurity concentration as that of the second semiconductor region.

10. The element structure includes: a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a trench penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region; a gate electrode provided inside the trench via a gate insulating film; a second conductivity type high concentration region having an impurity concentration higher than that of the second semiconductor region, the second conductivity type high concentration region being selectively provided within the first semiconductor region and located closer to the second main surface of the semiconductor substrate than a bottom surface of the trench; 2. The semiconductor device according to claim 1, wherein the second conductivity type voltage withstanding region terminates at a position shallower from the first main surface of the semiconductor substrate than the second conductivity type high concentration region.

11. 3. The semiconductor device according to claim 2, wherein the second conductivity type voltage withstanding region terminates at a position shallower from the first main surface of the semiconductor substrate than the second conductivity type high concentration region.

12. The second conductivity type high concentration region is a first high concentration region facing a bottom surface of the trench in a depth direction; 12. The semiconductor device according to claim 10, further comprising: a second high concentration region separated from the first high concentration region and the trench and in contact with the second semiconductor region.

13. A method for manufacturing a semiconductor device comprising: an active region in which a predetermined element structure formed by a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type is provided in a semiconductor substrate made of a semiconductor having a band gap wider than that of silicon; and a termination region surrounding the active region, a first step of epitaxially growing a first conductivity type epitaxial layer forming a first main surface of the semiconductor substrate; a second step of forming a diffusion region which becomes at least the second semiconductor region by introducing a predetermined impurity into a surface region of the first conductive type epitaxial layer in the active region, and forming the element structure including the pn junction between the second semiconductor region and the first semiconductor region which is a portion of the first conductive type epitaxial layer in the active region excluding the diffusion region; a third step of forming a plurality of second conductivity type breakdown voltage regions concentrically spaced apart from one another in a surface region of the first conductivity type epitaxial layer in the termination region, away from the element structure and surrounding a periphery of the active region, and leaving the first conductivity type epitaxial layer to become the first semiconductor region between adjacent second conductivity type breakdown voltage regions; Including, In the first step, a laminated structure is formed by stacking a plurality of the first conductive type epitaxial layers in multiple stages, and a first main surface of the semiconductor substrate is formed flat from the active region to the termination region; In the second step, the element structure is forming the second semiconductor region in any one of the first conductivity type epitaxial layers; selectively forming a third semiconductor region of a first conductivity type between the first main surface of the semiconductor substrate and the second semiconductor region; forming a trench penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region; forming a gate electrode within the trench via a gate insulating film; selectively forming a fourth semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor region at a position between the first main surface of the semiconductor substrate and the second semiconductor region and farther from the trench than the third semiconductor region; selectively forming a second conductivity type high concentration region having an impurity concentration higher than that of the second semiconductor region at a position deeper than a bottom surface of the trench within the first semiconductor region; In the third step, forming a second conductivity type region in each of the first conductivity type epitaxial layers, and forming the second conductivity type breakdown voltage region by adjacently forming the second conductivity type regions in a depth direction; forming any one of the plurality of second conductivity type regions at the same depth position as the second semiconductor region and with the same impurity concentration as the second semiconductor region; a second semiconductor region formed on the second conductive type region and having an impurity concentration different from that of the second semiconductor region;

14. In the second step, the second semiconductor region is formed in one of the first conductive type epitaxial layers; 14. The method for manufacturing a semiconductor device according to claim 13, wherein in the third step, the second conductivity type region is formed simultaneously with the second semiconductor region in the first conductivity type epitaxial layer among the plurality of first conductivity type epitaxial layers in which the second semiconductor region is to be formed.

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