Information processing system, information processing method, and information processing device

Abstract

The present technology relates to an information processing system, an information processing method, and an information processing device which enable a load of an information processing unit to be reduced, when data is shared between a plurality of information processing devices. The present invention is provided with: a first information processing device which performs a DMA control on the basis of transfer parameters used for a transfer control of data; and a second information processing device which communicates with the first information processing device and performs a DMA control on the basis of the transfer parameters, wherein the first information processing device generates the transfer parameters to be used for a reception control of transfer data and transmits the transfer parameters to the second information processing device, and the second information processing device controls reception of the transfer data from the first information processing device on the basis of the transfer parameters received from the first information processing device. The present technology can be applied to, for example, an apparatus provided with a multiprocessor system.

Description

[Technical field]

[0001] The present technology relates to an information processing system, an information processing method, and an information processing device, and in particular to an information processing system, an information processing method, and an information processing device that are suitable for use when data is shared among a plurality of information processing devices. [Background technology]

[0002] Generally, when data is shared between processors in a multiprocessor system, a method of providing a shared memory shared between the processors or a method of sharing the address space of the memory of each processor is used (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-63442 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the former method requires a shared memory, which increases the hardware cost and is not very suitable for, for example, an embedded system.

[0005] In addition, the latter method requires constant data transfer between processors so that the same data is stored in an area that shares the address space of the memory of each processor, which increases the load on the CPU (Central Processing Unit) built into the processor, for example.

[0006] The present technology has been made in consideration of such circumstances, and is intended to reduce the load on an information processing unit such as a CPU when data is shared among multiple information processing devices such as processors. [Means for solving the problem]

[0007] An information processing system according to a first aspect of the present technology includes a first information processing device and a second information processing device, wherein the first information processing device includes a first information processing unit that generates transfer parameters used for controlling data transfer, a first DMA control unit that controls DMA (Direct Memory Access) based on the transfer parameters, and a first communication unit, and the second information processing device includes a second information processing unit that generates the transfer parameters, a second DMA control unit that controls DMA based on the transfer parameters, and a second communication unit that communicates with the first communication unit, wherein the first information processing unit generates first transfer parameters used for controlling reception of first transfer data, the first DMA control unit controls transmission of the first transfer parameters to the second information processing device, and the second DMA control unit controls reception of the first transfer data from the first information processing device based on the first transfer parameters.

[0008] An information processing method according to a second aspect of the present technology includes a first information processing device that controls DMA (Direct Memory Access) based on transfer parameters used to control data transfer, and a second information processing device that communicates with the first information processing device and controls DMA based on the transfer parameters, wherein the first information processing device generates the transfer parameters used to control reception of transferred data and transmits them to the second information processing device, and the second information processing device controls reception of the transferred data from the first information processing device based on the transfer parameters received from the first information processing device.

[0009] An information processing device according to a third aspect of the present technology includes an information processing unit that generates transfer parameters used to control the transfer of data, a DMA control unit that controls DMA (Direct Memory Access) based on the transfer parameters, and a communication unit that communicates with other information processing devices, wherein the information processing unit generates the transfer parameters used to control the reception of the transferred data, and the DMA control unit controls the transmission of the transfer parameters used to control the reception of the transferred data to the other information processing devices.

[0010] An information processing device according to a fourth aspect of the present technology includes a DMA control unit that controls DMA (Direct Memory Access) based on transfer parameters used to control the transfer of data, and a communication unit that communicates with other information processing devices, wherein the communication unit receives the transfer parameters used to control the reception of the transferred data from the other information processing devices, and the DMA control unit controls the reception of the transferred data from the other information processing devices based on the transfer parameters received from the other information processing devices.

[0011] In a first or second aspect of the present technology, a first information processing device generates transfer parameters used to control reception of transfer data, controls transmission of the transfer parameters to a second information processing device, and the second information processing device controls reception of the transfer data from the first information processing device based on the transfer parameters.

[0012] In a third aspect of the present technology, a transfer parameter used for controlling reception of transfer data is generated, and transmission of the transfer parameter used for controlling reception of the transfer data to the other information processing device is controlled.

[0013] In a fourth aspect of the present technology, reception of transfer data from another information processing device is controlled based on the transfer parameters received from the other information processing device. [Brief description of the drawings]

[0014] [Figure 1]1 is a block diagram showing a configuration example of an information processing system to which the present technology is applied. [Diagram 2] 1 is a block diagram showing an example configuration of a CPU and a RAM of an information processing system to which the present technology is applied. [Diagram 3] 13 is a flowchart for explaining processing by a CPU of a transmitting-side processor. [Figure 4] FIG. 1 is a diagram illustrating an example of the configuration of an LLI. [Diagram 5] FIG. 11 is a diagram for explaining a transmission process of status data. [Figure 6] FIG. 11 is a diagram for explaining a transmission process of BBS data. [Figure 7] FIG. 11 is a diagram for explaining a message transmission process. [Figure 8] 11 is a flowchart for explaining a process of the DMAC of a transmitting processor. [Figure 9] 13 is a flowchart for explaining an initial process of a CPU of a receiving-side processor. [Figure 10] 11 is a flowchart for explaining a process of the DMAC of a receiving processor. [Figure 11] 13 is a flowchart illustrating a transfer data reception process of a CPU of a receiving processor. [Figure 12] FIG. 11 is a sequence diagram showing a specific example of a data transfer process. [Figure 13] FIG. 1 is a block diagram showing an example of the configuration of a camera system. [Figure 14] FIG. 2 is a block diagram showing an example of the software configuration of the interchangeable lens unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present technology will be described in the following order. 1. Embodiment 2. Application Examples 3. Variations 4.Other

[0016] <<1. Preferred embodiment>> An embodiment of the present technology will be described with reference to FIGS.

[0017] <Configuration example of information processing system 100> FIG. 1 is a block diagram showing an embodiment of an information processing system 100 to which the present technology is applied.

[0018] The information processing system 100 is a multiprocessor system having multiple processors, and is incorporated in, for example, various devices to perform predetermined processes.

[0019] The information processing system 100 includes a processor 101a and a processor 101b that are information processing devices having the same configuration. Note that the reference numerals of the components of the processor 101a are followed by the letter "a," and the reference numerals of the components of the processor 101b are followed by the letter "b."

[0020] The processor 101a and the processor 101b can perform predetermined processing independently. Furthermore, the processor 101a and the processor 101b support full-duplex serial communication, and can perform bidirectional communication simultaneously and asynchronously. In other words, data transfer from the processor 101a to the processor 101b and data transfer from the processor 101b to the processor 101a can be performed asynchronously and in parallel. Furthermore, the processor 101a and the processor 101b share a part of the data.

[0021] The configuration of the processor 101a will be described below. As described above, the processor 101b has the same configuration as the processor 101a, and the description thereof will be omitted.

[0022] The processor 101a includes a CPU 111a, a DMAC (Direct Memory Access Controller) 112a, a flash ROM 113a, a RAM 114a, a SPI (Serial Peripheral Interface) 115a, and a system bus 116a. The CPU 111a, the DMAC 112a, the flash ROM 113a, the RAM 114a, and the SPI 115a are connected to each other via the system bus 116a.

[0023] The CPU 111a is an information processing unit that performs various processes and controls each unit of the processor 101a. The CPU 111a also generates transfer parameters used for controlling data transfer by DMA (Direct Memory Access) and stores the parameters in an LLI (Linked List Item) area 151a of the RAM 114a, thereby setting the transfer parameters.

[0024] The transfer parameters are stored in the LLI area 151a in the form of an LLI. Each LLI includes a set of transfer parameters. The LLI is data with a linked list structure, and each LLI can be connected to other LLIs in a linked manner.

[0025] Each LLI includes, for example, a source address, a destination address, a transfer attribute, and a link address.

[0026] The source address indicates the source of the data to be transferred. Specifically, the source address indicates the address (position) of the area where the data to be transferred is stored in the address space of the processor 101a or the processor 101b before the data is transferred.

[0027] The destination address indicates the destination of the data to be transferred. Specifically, the destination address indicates the address (position) of the area where the data to be transferred is stored in the address space of the processor 101a or the processor 101b after the data is transferred.

[0028] The transfer attributes include attributes and control information relating to the data transfer, such as the size of the data, addressing, and whether or not an interrupt notification is issued when the transfer is completed.

[0029] The link address indicates the address (position) of the area in the address space of the processor 101a or 101b where the LLI of the link destination, that is, the LLI to be referenced next, is stored. The link address can be dynamically rewritten, and the LLI to be referenced next is changed by rewriting the link address.

[0030] The DMAC 112a controls DMA. For example, the DMAC 112a sets transfer parameters by reading transfer parameters from the LLI area 151a of the RAM 114a and storing the parameters in an internal register. Then, for example, the DMAC 112a controls the transmission of data to the processor 101b by transferring data stored in the RAM 114a to the SPI 115a via the system bus 116a based on the set transfer parameters. Also, for example, the DMAC 112a controls the reception of data from the processor 101b by storing data received by the SPI 115a in the RAM 114a or the like via the system bus 116a based on the set transfer parameters.

[0031] The flash ROM 113a stores programs and data necessary for the processing of the processor 101a.

[0032] The RAM 114a temporarily stores programs and data necessary for the processing of the processor 101a. The RAM 114a also includes the shared memory area 161a described above, as shown in FIG.

[0033] The shared memory area 161a shares an address space with the shared memory area 161b of the processor 101b, and is an area used for sharing data. That is, the shared memory area 161a and the shared memory area 161b have the same address configuration, and are controlled by the DMAC 112a and the DMAC 112b so that the same data is stored in the corresponding areas. Note that the areas in which the same data is stored between the shared memory area 161a and the shared memory area 161b are basically areas with the same address, but as long as there is a correspondence, they do not necessarily have to be areas with the same address.

[0034] In addition, the shared memory area 161a is provided with a status data area 171a, a BBS (Bulletin Board System) area 172a, and a message area 173a.

[0035] The status data area 171a is an area for storing status data. The status data is data including status values ​​indicating various statuses of the processors 101a and 101b. The processors 101a and 101b can grasp each other's status in real time by sharing the status data in real time.

[0036] Although not shown in the figure, the status data area 171a is provided with a sender area and a referrer area. The sender area stores status data indicating the status of the processor 101a. As described later, the status data stored in the sender area is transmitted to the processor 101b and shared with the processor 101b. The referrer area stores status data received from the processor 101b and indicating the status of the processor 101b. For example, the sender area of ​​the status data area 171a of the processor 101a and the referrer area of ​​the status data area 171b of the processor 101b are provided in areas with the same address. Also, the referrer area of ​​the status data area 171a of the processor 101a and the sender area of ​​the status data area 171b of the processor 101b are provided in areas with the same address.

[0037] The BBS area 172a is an area for storing BBS data. The BBS data is data shared in the BBS function, and includes information (e.g., processing results) output from each task executed in the processor 101a and the processor 101b. The BBS function is a function for publishing the BBS data so that it can be referenced by other tasks.

[0038] Although not shown in the figure, the BBS area 172a is provided with a source area and a reference area. The source area stores BBS data published by a task of the processor 101a. As described later, the BBS data stored in the source area is transmitted to the processor 101b and shared with the processor 101b. The reference area stores BBS data published by a task of the processor 101b and received from the processor 101b. For example, the source area of ​​the BBS area 172a of the processor 101a and the reference area of ​​the BBS area 172b of the processor 101b are provided in areas with the same address. Also, the reference area of ​​the BBS area 172a of the processor 101a and the source area of ​​the BBS area 172b of the processor 101b are provided in areas with the same address.

[0039] The message area 173a is an area for storing messages. A message is data that is transmitted and received between tasks executed by the processor 101a and the processor 101b by specifying a destination. For example, a message may be a message that requests processing by a task at a destination, or a message that responds to a received message.

[0040] Although not shown in the figure, the message area 173a is provided with a sending side area and a receiving side area. The sending side area stores messages sent by a task of the processor 101a. As described later, the messages stored in the sending side area are sent to the processor 101b and shared with the processor 101b. The receiving side area stores messages received from a task of the processor 101b. For example, the sending side area of ​​the message area 173a of the processor 101a and the receiving side area of ​​the message area 173b of the processor 101b are provided in areas with the same address. Also, the receiving side area of ​​the message area 173a of the processor 101a and the sending side area of ​​the message area 173b of the processor 101b are provided in areas with the same address.

[0041] The SPI 115a can simultaneously perform bidirectional serial communication with the SPI 115b of the processor 101b through full-duplex communication. For example, the SPI 115a transmits data transferred from the RAM 114a by the DMAC 112a to the SPI 115b, and receives data transmitted from the SPI 115b.

[0042] In the following description of the processing of the processor 101a, the system bus 116a will be omitted. For example, when the DMAC 112a transfers data stored in the RAM 114a to the SPI 115a via the system bus 116a, it will be described that the DMAC 112a transfers the data stored in the RAM 114a to the SPI 115a.

[0043] Similarly, in the following description of the processing of the processor 101b, the description of the system bus 116b will be omitted.

[0044] <Data transfer process> Next, an example of a data transfer process executed by the information processing system 100 will be described with reference to FIGS.

[0045] Hereinafter, an example of transferring data from the processor 101a to the processor 101b with the processor 101a as the transmission side and the processor 101b as the reception side will be described.

[0046] Further, hereinafter, an example of a case where the processor 101a repeatedly transmits status data to the processor 101b and transmits BBS data and messages to the processor 101b as necessary will be described.

[0047] <Processing of the transmitting-side processor 101a> First, with reference to FIGS. 3 to 8, the processing of the transmitting-side processor 101a will be described.

[0048] <Processing of the CPU 111a> First, with reference to the flowchart of FIG. 3, the processing of the CPU 111a of the transmitting-side processor 101a will be described.

[0049] This processing is started, for example, when the power of the device in which the information processing system 100 is incorporated is turned on, and ends when the power is turned off.

[0050] In step S1, the CPU 111a sets transfer parameters for transmitting status data.

[0051] Specifically, the CPU 111a generates status data including the status value of the processor 101a and stores it in the transmission-side area of the status data area 171a.

[0052] Also, as shown in FIG. 2, the CPU 111a generates LLI-SA1 to LLI-SC1 and stores them in the LLI areas 151a-1 to 151a-3, respectively.

[0053] The 1 at the end of LLI-SA1 is a serial number used to distinguish between LLI-SAs of the same type based on the order of their creation. Hereinafter, unless there is a need to distinguish between LLI-SAs of the same type, the suffix will be omitted and the name will simply be LLI-SA. The same applies to LLI-SB and LLI-SC.

[0054] FIG. 4 shows an example of the configuration of LLI-SA1 to LLI-SC1.

[0055] The LLI-SA1 includes transfer parameters used for transmission control of the LLI-SB1. The source address is set to the address of the LLI area 151a-2 in which the LLI-SB1 is stored. The destination address is set to the address of the transmission channel TX, which is the area in the SPI 115a in which data to be transmitted is stored. The link address is set to the address of the LLI area 151a-3 in which the LLI-SC1 is stored. That is, the LLI-SC1 is set as the link destination of the LLI-SA1.

[0056] The LLI-SB1 includes transfer parameters used by the receiving processor 101b to control the reception of status data. The source address is set to the address of the receiving channel RX, which is the area in the SPI 115b of the processor 101b where the received data is stored. The destination address is set to the address of the reference side area in the status data area 171b of the receiving processor 101b, which corresponds to the originating side area in the status data area 171a of the transmitting processor 101a. The link address is set to the address of the LLI area 151b-1 in which the LLI-R1 of the processor 101b is stored. That is, the LLI-R1 is set as the link destination of the LLI-SB1.

[0057] The 1 at the end of LLI-R1 is a serial number used to distinguish LLI-Rs of the same type based on the order of generation, etc. Hereinafter, unless there is a need to distinguish between LLI-Rs of the same type, the final number will be omitted and the name will simply be referred to as LLI-R.

[0058] LLI-SC1 includes transfer parameters used for controlling the transmission of status data. The source address is set to the address of the sender area of ​​the status data area 171a of the sending processor 101a. The destination address is set to the address of the transmission channel TX of the SPI 115a. The link address is set to the address of the LLI area 151a-1 in which the LLI-SA1 is stored. That is, the LLI-SA1 is set as the link destination of the LLI-SC1. Therefore, the LLI-SA1 and the LLI-SC1 are linked to each other.

[0059] In step S2, the CPU 111a determines whether or not to update the state data. For example, if the state of the processor 101a has been updated, the CPU 111a determines to update the state data, and the process proceeds to step S3.

[0060] In step S3, the CPU 111a updates the status data. Specifically, the CPU 111a generates status data including the updated status value of the processor 101a, and stores the data in the sender side area of ​​the status data area 171a.

[0061] The process then proceeds to step S4.

[0062] On the other hand, in step S2, if the state of the processor 101a has not been updated, the CPU 111a determines not to update the state data, skips the process of step S3, and proceeds to step S4.

[0063] In step S4, the CPU 111a determines whether or not to share the BBS data If it is determined that the BBS data is not to be shared, the process proceeds to step S5.

[0064] In step S5, the CPU 111a determines whether or not to transmit a message. If it is determined that a message is not to be transmitted, the process returns to step S2.

[0065] Thereafter, the process returns to step S2, and steps S2 to S5 are repeatedly executed until it is determined in step S4 that the BBS data is to be shared, or until it is determined in step S5 that a message is to be transmitted.

[0066] As a result, based on the LLI-SA1 to LLI-SC1 set in the LLI area 151a, the transmission control of the LLI-SB1 from the processor 101a to the processor 101b and the transmission control of the status data are alternately repeated. Then, as shown in Fig. 5, the status data (Status) is repeatedly transmitted from the processor 101a to the processor 101b.

[0067] On the other hand, in step S4, for example, as shown in FIG. 6, if the CPU 111a determines that the task 201a being executed shares BBS data, the process proceeds to step S6.

[0068] In step S6, the CPU 111a sets transfer parameters for transmitting BBS data.

[0069] For example, the CPU 111a stores the shared BBS data in the sender's area of ​​the BBS area 172a.

[0070] Furthermore, as shown in FIG. 6, the CPU 111a executes a communication control task 202a called from the task 201a to generate LLI-BA1 to LLI-BC1, and stores them in the LLI areas 151a-4 to 151a-6.

[0071] The 1 at the end of LLI-BA1 is a serial number used to distinguish between LLI-BAs of the same type based on the order of their creation. Hereinafter, unless there is a need to distinguish between LLI-BAs of the same type, the digit at the end will be omitted and the name will simply be referred to as LLI-BA. The same applies to LLI-BB and LLI-BC.

[0072] LLI-BA1 includes transfer parameters used for transmission control of LLI-BB1. The source address is set to the address of the LLI area 151a-5 in which LLI-BB1 is stored. The destination address is set to the address of the transmission channel TX of the SPI 115a. The link address is set to the address of the LLI area 151a-6 in which LLI-BC1 is stored. That is, LLI-BC1 is set as the link destination of LLI-BA1.

[0073] LLI-BB1 includes transfer parameters used by the receiving processor 101b for controlling reception of BBS data. Specifically, the address of the receiving channel RX of the SPI 115b of the processor 101b is set as the transfer source address. The address of the reference side area of ​​the BBS area 172b of the receiving processor 101b is set as the transfer destination address. The address of the LLI area 151b-1 in which the LLI-R1 of the processor 101b is stored is set as the link address. That is, LLI-R1 is set as the link destination of LLI-BB1.

[0074] The LLI-BC1 includes transfer parameters used for controlling the transmission of BBS data. Specifically, the address of the sender area of ​​the BBS area 172a of the sending processor 101a is set as the transfer source address. The address of the transmission channel TX of the SPI 115a is set as the transfer destination address. The address of the LLI area 151a-7 next to the LLI area 151a-6 in which the LLI-BC1 is stored is set as the link address.

[0075] In step S7, the CPU 111a sets transfer parameters for transmitting status data. That is, the CPU 111a sets transfer parameters for transmitting status data after transmitting BBS data. For example, the CPU 111a generates LLI-SA2 to LLI-SC2 similar to LLI-SA1 to LLI-SC1 as shown in FIG. 6, and stores them in the LLI areas 151a-7 to 151a-9.

[0076] In step S8, the CPU 111a changes the link destination of the transfer parameters to the BBS data. Specifically, the CPU 111a rewrites the link address of the LLI-SC1 stored in the LLI area 151a-3 from the address of the LLI area 151a-1 to the address of the LLI area 151a-4. This changes the link destination of the LLI-SC1 from LLI-SA1 to LLI-BA1.

[0077] Thereafter, the process returns to step S2, and the processes from step S2 onwards are executed, whereby the setting for sending BBS data is completed, and the updating of the status data is resumed.

[0078] On the other hand, in step S5, for example, as shown in FIG. 7, if the task 201a being executed by the CPU 111a determines to transmit a message to another task being executed by the processor 101b, the process proceeds to step S9.

[0079] In step S9, the CPU 111a sets transfer parameters for message transmission.

[0080] For example, the CPU 111a stores the message to be sent in the sending side area of ​​the message area 173a.

[0081] Also, for example, the CPU 111a executes a communication control task 202a called from the task 201a as shown in FIG. 7 to generate LLI-MA1 to LLI-MC1 and store them in the LLI areas 151a-4 to 151a-6.

[0082] The 1 at the end of LLI-MA1 is a serial number for distinguishing the same type of LLI-MA based on the order of generation, etc. Hereinafter, when there is no need to distinguish between LLI-MAs of the same type, the suffix will be omitted and the name will simply be referred to as LLI-MA. This also applies to LLI-MB and LLI-MC.

[0083] The LLI-MA1 includes transfer parameters used for transmission control of the LLI-MB1. The source address is set to the address of the LLI area 151a-5 in which the LLI-MB1 is stored. The destination address is set to the address of the transmission channel TX of the SPI 115a. The link address is set to the address of the LLI area 151a-6 in which the LLI-MC1 is stored. That is, the LLI-MC1 is set as the link destination of the LLI-MA1.

[0084] The LLI-MB1 includes transfer parameters used by the receiving processor 101b for message reception control. The source address is set to the address of the receiving channel RX of the SPI 115b of the processor 101b. The destination address is set to the address of the receiving side area of ​​the message area 173b of the receiving processor 101b. The link address is set to the address of the LLI area 151b-1 in which the LLI-R1 of the processor 101b is stored. That is, the LLI-R1 is set as the link destination of the LLI-MB1. The attribute is set to transfer completion notification control information for performing an interrupt notification when transfer of data (message) based on the LLI-MB1 is completed.

[0085] The LLI-MC1 includes transfer parameters used for message transmission control. The source address is set to the address of the sender area in the message area 173a of the sending processor 101a. The destination address is set to the address of the transmission channel TX of the SPI 115a. The link address is set to the address of the LLI area 151a-7 next to the LLI area 151a-6 in which the LLI-MC1 is stored.

[0086] In step S10, transfer parameters for transmitting status data are set in the same manner as in the process of step S7. That is, transfer parameters for transmitting status data after transmitting a message are set. For example, as shown in FIG. 7, the CPU 111a generates LLI-SA2 to LLI-SC2 similar to LLI-SA1 to LLI-SC1, and stores them in the LLI areas 151a-7 to 151a-9.

[0087] In step S11, the CPU 111a changes the link destination of the transfer parameter to a message. Specifically, the CPU 111a rewrites the link address of LLI-SC1 stored in the LLI area 151a-3 from the address of the LLI area 151a-1 to the address of the LLI area 151a-4. Thereby, the link destination of LLI-SC1 is changed from LLI-SA1 to LLI-MA1.

[0088] Thereafter, the process returns to step S2, and the processes after step S2 are executed. Thereby, for example, after the setting of message transmission is performed, the update of the state data is resumed.

[0089] <Processing of DMAC 112a> Next, with reference to the flowchart of FIG. 8, the processing of DMAC 112a of the transmission-side processor 101a will be described.

[0090] This process starts, for example, when the power of the device in which the information processing system 100 is incorporated is turned on, and ends when the power is turned off.

[0091] In step S31, DMAC 112a reads out the transfer parameter for transfer parameter transmission.

[0092] For example, in the process of the first step S31, DMAC 112a reads out LLI-SA1 from the LLI area 151a-1 and stores it in the built-in register.

[0093] In step S32, DMAC 112a transmits the transfer parameter for transfer parameter reception.

[0094] For example, in the process of the first step S32, DMAC 112a reads out LLI-SB1 from the LLI area 151a-1 based on LLI-SA1 and stores it in the transmission channel TX of SPI 115a.

[0095] The SPI 115a transmits the LLI-SB1 stored in the transmission channel TX to the processor 101b.

[0096] In response to this, the receiving side processor 101b receives the LLI-SB1 in step S121 of FIG. 10, which will be described later.

[0097] In step S33, the DMAC 112a reads out transfer parameters for transmitting the transfer data.

[0098] For example, in the first process of step S33, the DMAC 112a reads out the LLI-SC1 from the LLI area 151a-3 based on the link address of the LLI-SA1, and stores it in the built-in register.

[0099] In step S34, the DMAC 112a transmits the transfer data.

[0100] For example, in the first process of step S34, the DMAC 112a reads out status data from the sender area of ​​the status data area 171a based on the LLI-SC1, and stores it in the transmission channel TX of the SPI 115a.

[0101] The SPI 115a transmits the status data stored on the transmission channel TX to the processor 101b.

[0102] In response to this, the receiving processor 101b receives the status data in step S123 of FIG. 10, which will be described later.

[0103] After that, the process returns to step S31, and the processes of steps S31 to S34 are repeatedly executed. As a result, for example, if the link destination of the transfer parameter has not been changed in step S8 or step S11 of Fig. 3 described above, the status data (Status) is repeatedly transmitted from the processor 101a to the processor 101b by the above-mentioned process, as shown in Fig. 5.

[0104] On the other hand, if the link destination of the transfer parameters is changed to BBS data in step S8 described above, the BBS data is transmitted.

[0105] Specifically, in step S31, the DMAC 112a reads out the LLI-BA1 from the LLI area 151a-4 based on the link address of the LLI-SC1, and stores it in an internal register.

[0106] In step S32, the DMAC 112a reads out the LLI-BB1 from the LLI area 151a-5 based on the LLI-BA1, and stores it in the transmission channel TX of the SPI 115a.

[0107] The SPI 115a transmits the LLI-BB1 stored in the transmission channel TX to the processor 101b.

[0108] In response to this, the receiving side processor 101b receives the LLI-BB1 in step S122 of FIG. 10, which will be described later.

[0109] In step S33, the DMAC 112a reads out the LLI-BC1 from the LLI area 151a-6 based on the link address of the LLI-BA1, and stores it in an internal register.

[0110] In step S34, the DMAC 112a reads the BBS data from the source area of ​​the BBS area 172a based on the LLI-BC1, and stores it in the transmission channel TX of the SPI 115a.

[0111] The SPI 115a transmits the BBS data stored in the transmission channel TX to the processor 101b.

[0112] As a result, as shown in FIG. 6, the transmission of status data (Status) from the processor 101a to the processor 101b is interrupted, and the BBS data is transmitted.

[0113] In response to this, the receiving processor 101b receives the BBS data in step S123 of FIG. 10, which will be described later.

[0114] Thereafter, the process returns to step S31, the processes from step S31 onwards are executed, and the transmission of status data is resumed based on LLI-SA2 to LLI-SC2.

[0115] On the other hand, if the link destination of the transfer parameters is changed to a message in step S11 described above, the message is sent.

[0116] Specifically, in step S31, the DMAC 112a reads out the LLI-MA1 from the LLI area 151a-4 based on the link address of the LLI-SC1, and stores it in an internal register.

[0117] In step S32, the DMAC 112a reads out the LLI-MB1 from the LLI area 151a-4 based on the LLI-MA1, and stores it in the transmission channel TX of the SPI 115a.

[0118] The SPI 115a transmits the LLI-MB1 stored in the transmission channel TX to the processor 101b.

[0119] In response to this, the receiving side processor 101b receives the LLI-MB1 in step S122 of FIG. 10, which will be described later.

[0120] In step S33, the DMAC 112a reads out the LLI-MC1 from the LLI area 151a-6 based on the link address of the LLI-MA1, and stores it in an internal register.

[0121] In step S34, the DMAC 112a reads the message from the sending side area of ​​the message area 173a based on the LLI-MC1, and stores it in the sending channel TX of the SPI 115a.

[0122] SPI115a transmits the message stored in the transmission channel TX to the processor 101b.

[0123] As a result, as shown in FIG. 7, the transmission of the status data from the processor 101a to the processor 101b is interrupted and the message is transmitted.

[0124] On the other hand, the receiving processor 101b receives the message in step S123 of FIG. 10 described later.

[0125] Thereafter, the process returns to step S31, the processes after step S31 are executed, and the transmission of the status data is resumed based on LLI-SA2 to LLI-SC2.

[0126] <Processing of the receiving processor 101b> Next, with reference to FIGS. 9 to 11, the processing executed by the receiving processor 101b corresponding to the processing of the transmitting processor 101a in FIGS. 3 to 8 will be described.

[0127] <Initial processing of CPU111b> First, with reference to the flowchart of FIG. 9, the initial processing executed by the CPU111b of the receiving processor 101b will be described.

[0128] This process starts, for example, when the power of the device in which the information processing system 100 is incorporated is turned on.

[0129] In step S101, the processor 101b sets transfer parameters for receiving transfer parameters. Specifically, as shown in FIG. 2, the CPU111b generates LLI-R1 and stores it in the LLI area 151b-1.

[0130] LLI-R1 includes transfer parameters used for receiving control of transfer parameters. Specifically, as shown in FIG. 4, the address of the reception channel RX of SPI115b is set as the source address for transfer. The address of the next LLI area 151b-2 of the LLI area 151b-1 in which LLI-R1 is stored is set as the destination address for transfer. The address of the LLI area 151b-2 is set as the link address. That is, the LLI stored in the LLI area 151b-2 is set as the link destination of LLI-R1.

[0131] After that, the process ends.

[0132] <Processing of DMAC112b> Next, with reference to the flowchart of FIG. 10, the processing executed by DMAC112b of the receiving-side processor 101b will be described.

[0133] This processing is started, for example, when the power of the device in which the information processing system 100 is incorporated is turned on, and ends when the power is turned off.

[0134] In step S121, DMAC112b receives transfer parameters for receiving transfer data.

[0135] DMAC112b reads LLI-R1 from the LLI area 151b-1 and sets it in an internal register. Thereby, DMAC112b enters a reception waiting state. That is, DMAC112b waits for LLI-SB1, LLI-BB1, or LLI-MB1 to be transmitted to the reception channel RX of SPI115b.

[0136] SPI115b receives LLI-SB1, LLI-BB1, or LLI-MB1 transmitted in the process of step S32 of FIG. 8 from the processor 101a and stores it in the reception channel RX.

[0137] In step S122, the processor 101b sets transfer parameters for receiving transfer data.

[0138] Specifically, the DMAC 112b reads out the LLI-SB1, LLI-BB1, or LLI-MB1 from the receiving channel RX of the SPI 115b based on the LLI-R1, and stores it in the LLI area 151b-2.

[0139] 2 and 4 show an example in which LLI-SB1 is stored in the LLI area 151b-2.

[0140] As described above, the link address of LLI-R1 is set to the address of the LLI region 151b-2. Also, as described above, the link addresses of LLI-SB1, LLI-BB1, and LLI-MB1 are set to the address of the LLI region 151b-1. Therefore, LLI-R1 and LLI-SB1, LLI-BB1, or LLI-MB1 are linked to each other.

[0141] In step S123, the processor 101b receives the transfer data.

[0142] Specifically, the DMAC 112b reads out the LLI-SB1, LLI-BB1, or LLI-MB1 from the LLI area 151b-2 and stores it in an internal register. This puts the DMAC 112b into a receive standby state. That is, the DMAC 112b waits for status data, BBS data, or a message to be sent to the receive channel RX of the SPI 115b.

[0143] The SPI 115b receives the status data, BBS data, or message sent in the process of step S34 in FIG. 8 from the processor 101a, and stores it in the receiving channel RX.

[0144] The transfer data stored in the receiving channel RX is transferred to the shared memory area 161b by the DMAC 112b.

[0145] For example, when status data is received, the DMAC 112b reads the transfer data from the receiving channel RX of the SPI 115b based on the LLI-SB1, and stores it in the reference side area of ​​the status data area 171b of the shared memory area 161b.

[0146] When BBS data is received, the DMAC 112b reads the BBS data from the receiving channel RX of the SPI 115b based on the LLI-BB1, and stores the BBS data in the reference side area of ​​the BBS area 172b of the shared memory area 161b.

[0147] When a message is received, the DMAC 112b reads the message from the receiving channel RX of the SPI 115b based on the LLI-MB1, and stores the message in the receiving side area of ​​the message area 173b of the shared memory area 161b.

[0148] In step S124, the DMAC 112b determines whether or not to perform a transfer completion notification. When the DMAC 112b transfers a message from the SPI 115b to the message area 173b based on the LLI-MB1, the DMAC 112b determines to perform a transfer completion notification based on the transfer completion notification control information set in the attribute of the LLI-MB1, and the process proceeds to step S125.

[0149] In step S125, the DAMC 112b notifies the CPU 111b of the completion of the transfer of the message by an interrupt.

[0150] Thereafter, the process returns to step S121, and the processes of steps S121 to S125 are repeatedly executed. That is, the process of receiving transfer parameters for receiving any one of status data, BBS data, or messages from the transmitting processor 101a, receiving status data, BBS data, or messages using the received transfer parameters, and storing the data in a predetermined area of ​​the shared memory area 161b is repeatedly executed.

[0151] On the other hand, in step S124, when the DMAC 112b transfers status data from the SPI 115b to the status data area 171a based on the LLI-SB1, the transfer completion notification control information is not set in the attribute of the LLI-SB1, so the DMAC 112b determines not to perform a transfer completion notification, and the process returns to step S121. Similarly, when the DMAC 112b transfers BBS data from the SPI 115b to the BBS area 172b based on the LLI-BB1, the transfer completion notification control information is not set in the attribute of the LLI-BB1, so the DMAC 112b determines not to perform a transfer completion notification, and the process returns to step S121.

[0152] Thereafter, the processes of steps S121 to S125 are repeatedly executed.

[0153] <Interrupt processing> Next, a transfer data reception process executed by the CPU 111b in correspondence with the process of the DMAC 112b in FIG. 10 will be described with reference to a flowchart in FIG.

[0154] This process starts when the DAMC 112b issues an interrupt notification of the completion of message transfer to the CPU 111b in step S125 of FIG.

[0155] In step S141, the CPU 111b analyzes the transfer data. Specifically, the CPU 111b analyzes the message, which is the transfer data stored in the receiving side area of ​​the message area 173b, to identify the destination task of the message and generate a task message to be transmitted to the destination task.

[0156] In step S142, the CPU 111b transmits a task message to the destination task.

[0157] After that, the transfer data receiving process ends.

[0158] In this manner, status data, BBS data, and messages can be transferred from the processor 101a to the processor 101b.

[0159] In addition, the shared memory area 161a of the processor 101a and the shared memory area 161b of the processor 101b share the address space by a communication control algorithm. Therefore, the load on the sending side and the receiving side is reduced compared to the case where a mechanism for sending and receiving data by protocol communication is used.

[0160] For example, the CPU 111a of the processor 101a on the transmitting side only needs to set the LLI and rewrite the link address of the LLI, and does not need to perform device control such as starting and ending transfers on the DMAC 112a and SPI 115a. This reduces the processing load of the CPU 111a.

[0161] For example, the CPU 111b of the receiving processor 101b only needs to set the LLI-R1 in the LLI area 151b, and does not need to set any other LLI. Also, the CPU 111b does not need to perform device control such as starting and ending transfers on the DMAC 112b and SPI 115b. This reduces the processing load of the CPU 111b.

[0162] Furthermore, since the transfer parameters are realized by a linked list structure, for example, it becomes possible to repeatedly transfer the status data stored in the status data area 171a without the intervention of the CPU 111a. It also becomes possible to continuously transfer two or more types of data among the status data, BBS data, and messages stored in the shared memory area 161a. It also becomes possible for the CPU 111a to change the content of the data to be transferred simply by changing the link destination of the LLI.

[0163] In the above description, the process of data transfer from the processor 101a to the processor 101b has been described, but data transfer from the processor 101b to the processor 101a can also be achieved by a similar process.

[0164] In addition, since the SPI 115a and SPI 115b are capable of full-duplex communication, data transfer from the processor 101a to the processor 101b and data transfer from the processor 101b to the processor 101a can be executed asynchronously in parallel.

[0165] <Example of data transfer process> Next, a specific example of the above-mentioned data transfer process will be described with reference to the sequence diagram of FIG.

[0166] FIG. 12 shows a sequence diagram in which a task 201a of a processor 101a sends a processing request message to a task 201b of a processor 101b, the processing result of the task 201b is shared on the BBS, and the task 201b returns a processing response message to the task 201a.

[0167] It is assumed that, through the above-mentioned processing, the processor 101a transmits constant status data to the processor 101b, and the processor 101b transmits constant status data to the processor 101a.

[0168] A task 201a of the processor 101a generates a processing request message for a task 201b and stores it in the sending side area of ​​the message area 173a of the shared memory area 161a. The task 201a calls a communication control task 202a to request the sending of the processing request message.

[0169] The communication control task 202a generates LLI-MA to LLI-MC used for transmitting a processing request message, and stores them in the LLI area 151a.

[0170] The DMAC 112a of the processor 101a reads the LLI1-MA from the LLI area 151a and stores it in an internal register. The DMAC 112a transmits the LLI-MB via the SPI 115a based on the LLI-MA.

[0171] On the other hand, the DMAC 112b of the processor 101b reads the LLI-R from the LLI area 151b and stores it in an internal register. The DMAC 112b receives the LLI-MB via the SPI 115b based on the LLI-R and stores the LLI-MB in the LLI area 151b.

[0172] The DMAC 112a of the processor 101a reads the LLI-MC from the LLI area 151a and stores it in an internal register. Based on the LLI-MC, the DMAC 112a transmits the processing request message stored in the sending side area of ​​the message area 173a of the shared memory area 161a via the SPI 115a.

[0173] The DMAC 112b of the processor 101b reads the LLI-MB from the LLI area 151b and stores it in an internal register. The DMAC 112b receives a processing request message via the SPI 115b based on the LLI-MB and stores it in the receiving area of ​​the message area 173b of the shared memory area 161b. The DMAC 112b also transmits an interrupt notification to the communication control task 202b based on the transfer completion notification control information set in the attribute of the LLI-MB.

[0174] The communication control task 202b reads the processing request message from the message area 173b of the shared memory area 161b, and transmits it as a task message to the task 201b, which wakes up the task 201b.

[0175] The task 201b performs a predetermined process according to the process request message, and stores BBS data indicating the process result in the sender area of ​​the BBS area 172b in the shared memory area 161b. The task 201b calls the communication control task 202b to request the transmission of the BBS data.

[0176] The communication control task 202b generates LLI-BA to LLI-BC for transmitting BBS data, and stores them in the LLI area 151b.

[0177] The DMAC 112b of the processor 101b reads the LLI-BA from the LLI area 151b and stores it in an internal register. The DMAC 112b transmits the LLI-BB via the SPI 115b based on the LLI-BA.

[0178] The DMAC 112a of the processor 101a reads the LLI-R from the LLI area 151a and stores it in an internal register. The DMAC 112a receives the LLI-BB via the SPI 115a based on the LLI-R and stores it in the LLI area 151a.

[0179] The DMAC 112b of the processor 101b reads the LLI-BC from the LLI area 151b and stores it in an internal register. The DMAC 112b transmits the BBS data stored in the BBS area 172b of the shared memory area 161b via the SPI 115b based on the LLI-BC.

[0180] The DMAC 112a of the processor 101a reads the LLI-BB from the LLI area 151a and stores it in an internal register. The DMAC 112a receives the BBS data via the SPI 115a based on the LLI-BB and stores it in the reference side area of ​​the BBS area 172a of the shared memory area 161a. This allows the BBS data to be shared.

[0181] Furthermore, the task 201b of the processor 101b generates a processing response message to the task 201a and stores it in the sending side area of ​​the message area 173b of the shared memory area 161b. The task 201b calls the communication control task 202b to request the sending of the processing response message.

[0182] The communication control task 202b generates LLI-MA to LLI-MC for transmitting a processing response message, and stores them in the LLI area 151b.

[0183] The DMAC 112b of the processor 101b reads the LLI-MA from the LLI area 151b and stores it in an internal register. The DMAC 112b transmits the LLI-MB via the SPI 115b based on the LLI-MA.

[0184] The DMAC 112a of the processor 101a reads the LLI-R from the LLI area 151a and stores it in an internal register. The DMAC 112a receives the LLI-MB via the SPI 115a based on the LLI-R and stores it in the LLI area 151a.

[0185] The DMAC 112b of the processor 101b reads the LLI-MC from the LLI area 151b and stores it in an internal register. The DMAC 112b transmits the message stored in the message area 173b of the shared memory area 161b via the SPI 115b based on the LLI-MC.

[0186] The DMAC 112a of the processor 101a reads the LLI-MB from the LLI area 151a and stores it in an internal register. The DMAC 112a receives a processing response message via the SPI 115a based on the LLI-MB and stores it in the receiving side area of ​​the message area 173a of the shared memory area 161a. The DMAC 112a also transmits an interrupt notification to the communication control task 202a based on the transfer completion notification control information set in the attribute of the LLI-MB.

[0187] The communication control task 202a reads the processing response message from the message area 173a of the shared memory area 161a, and transmits it as a task message to the task 201a, which wakes up the task 201a and checks the processing response message.

[0188] In this manner, BBS data and messages can be transferred between the processor 101a and the processor 101b while sharing state data.

[0189] <<2. Application Examples>> Next, a specific application example of the present technology will be described with reference to Fig. 13 and Fig. 14. Specifically, an example in which the present technology is applied to a camera system 400 will be described.

[0190] FIG. 13 is a block diagram illustrating a schematic configuration example of a camera system 400. As shown in FIG.

[0191] The camera system 400 includes a camera body 401 and an interchangeable lens unit 402. The interchangeable lens unit 402 is attachable to and detachable from the camera body 401.

[0192] 1 is applied to a lens control system of an interchangeable lens unit 402. The lens control system is a system that drives an aperture 423 and a focus lens 425 in response to instructions from a camera body 401.

[0193] The lens control system includes a processor 421a, a processor 421b, a driving unit 422, an aperture 423, a driving unit 424, and a focus lens 425. The processors 421a and 421b correspond to the processors 101a and 101b of the information processing system 100 in FIG.

[0194] The processor 421a includes an inter-processor communication unit 441a, a driver 442a, and a camera-lens communication unit 443.

[0195] The processor 421b includes an inter-processor communication unit 441b and a driver 442b.

[0196] A driver 442a of the processor 421a controls the size of the opening of the diaphragm 423 by controlling a drive unit 422 that includes an actuator and the like.

[0197] A driver 442b of the processor 421b controls a driving unit 424 including an actuator and the like, thereby controlling the position of a focus lens 425 and the like.

[0198] Furthermore, the processor 421a receives instructions from the camera body 401 via the camera-lens communication unit 443. The processor 421a transmits instructions from the camera body 401 to the processor 421b via the inter-processor communication unit 441a as necessary.

[0199] Furthermore, the processor 421a and the processor 421b transmit and receive transfer parameters, status data, BBS data, messages, etc., via the inter-processor communication unit 441a and the inter-processor communication unit 441b, thereby allowing the processor 421a and the processor 421b to share information with each other and transmit and receive various instructions.

[0200] FIG. 14 is a block diagram showing an example of the software configuration of the processor 421a.

[0201] The software configuration of the processor 421b is basically the same as that of the processor 421a, and the description thereof will be omitted as appropriate. Also, the reference numerals of the components of the processor 421a are followed by the letter "a", and the reference numerals of the components of the processor 421b are followed by the letter "b".

[0202] The processor 421a includes a driver 442a, a communication control task 501a, a drive control task 502a, a communication control module 503a, a DMAC 504a, and an SPI 505a. The DMAC 504a and the SPI 505a correspond to the DMAC 112a and the SPI 115a of the processor 101a in FIG. 1, and configure the inter-processor communication unit 441a in FIG.

[0203] The drive control task 502a includes a BBS module 521a and a message module 522a.

[0204] The communication control module 503a includes a state data sharing control unit 541a, a BBS control unit 542a, a message control unit 543a, a communication control unit 544a, and a shared memory area 545a. The shared memory area 545a corresponds to the shared memory area 161a of the processor 101a in FIG.

[0205] The shared memory area 545a is provided with a status data area 561a, a BBS area 562a, and a message area 563a. The status data area 561a, the BBS area 562a, and the message area 563a correspond to the status data area 171a, the BBS area 172a, and the message area 173a of the processor 101a in Fig. 2. The status data area 561a is provided with a sender area and a referrer area. The BBS area 562a is provided with a sender area and a referrer area. The message area 563a is provided with a sender area and a receiver area.

[0206] The communication control task 501a issues instructions to a state data sharing control unit 541a, and controls the sharing of state data with the processor 421b.

[0207] The drive control task 502a issues a drive instruction to the driver 442a, and controls the size of the opening of the diaphragm 423, etc., by controlling the drive unit 422 via the driver 442a.

[0208] The BBS module 521a generates BBS data to be shared with other tasks, and supplies it to the BBS control unit 542a.

[0209] The message module 522 a generates messages to be sent to other tasks, and supplies them to a message control unit 543 .

[0210] The communication control module 503a is a module that controls communication with the processor 421b. For example, the communication control module 503a controls the transmission and reception of status data, BBS data, and messages with the processor 421b.

[0211] The status data sharing control unit 541a stores the status data to be shared with the processor 421b in the sending side area of ​​the status data area 561a of the shared memory area 545a, and instructs the communication control unit 544a to transmit the status data.

[0212] The BBS control unit 542a stores the BBS data shared with the processor 421b in the sender's area of ​​the BBS area 562a in the shared memory area 545a, and instructs the communication control unit 544a to transmit the BBS data.

[0213] When the message control unit 543a transmits a message to a task of the processor 421b, the message control unit 543a stores the message to be transmitted in the transmitting side area of ​​the message area 563a of the shared memory area 545a, and instructs the communication control unit 544a to transmit the message.

[0214] When an instruction to transmit status data, BBS data, or a message is given, the communication control unit 544a generates a transfer control LLI and stores it in an LLI area of ​​a RAM (not shown). The transfer control LLI is composed of, for example, the above-mentioned LLI-SA to LLI-SC, LLI-BA to LLI-BC, or LLI-MA to LLI-MC.

[0215] The status data area 561a of the shared memory area 545a stores status data shared with the processor 421b. The sending side area stores status data sent by the processor 421a. The referencing side area stores status data sent by the processor 421b and received from the processor 421b.

[0216] By carrying out the above-mentioned status data transfer process, the status data stored in the sender area of ​​the status data area 561a of the processor 421a is transferred to the referee area of ​​the status data area 561b of the processor 421b in almost real time, and the same data is stored in both. Also, the status data stored in the sender area of ​​the status data area 561b of the processor 421b is transferred to the referee area of ​​the status data area 561a of the processor 421a in almost real time, and the same data is stored in both.

[0217] The BBS area 562a of the shared memory area 545a stores BBS data shared with the processor 421b. The sending side area stores BBS data sent by the processor 421a. The reading side area stores BBS data sent by the processor 421b and received from the processor 421b.

[0218] By carrying out the above-mentioned BBS data transfer process, the BBS data stored in the originating area of ​​BBS area 562a of processor 421a is transferred to the referencing area of ​​BBS area 562b of processor 421b in substantially real time, and the same data is stored in both. Also, the BBS data stored in the originating area of ​​BBS area 562b of processor 421b is transferred to the referencing area of ​​BBS area 562a of processor 421a in substantially real time, and the same data is stored in both.

[0219] For example, the BBS is used when each task shares processing results with other tasks. For example, the drive control task 502a can share the processing results with other tasks in the processors 421a and 421b by generating BBS data indicating the processing results and storing the data in the sending side area of ​​the BBS area 562a. Also, for example, the drive control task 502a can know the processing results of other tasks by referring to the BBS data stored in the sending side area and the reference side area of ​​the BBS area 562a. For example, the drive control task 502a can collect information on the driving states of the aperture 423 and the focus lens 425 in order to analyze the driving instructions from the camera body 401 by referring to the BBS data.

[0220] The message area 563a of the shared memory area 545a stores messages sent to and received from the processor 421b. The sending side area stores messages sent to the processor 421b. The receiving side area stores messages received from the processor 421b.

[0221] By carrying out the above-mentioned message transfer process, a message stored in the sending side area of ​​message area 563a of processor 421a is transferred to the receiving side area of ​​message area 563b of processor 421b in almost real time, and the same data is stored in both. Also, a message stored in the sending side area of ​​message area 563b of processor 421b is transferred to the receiving side area of ​​message area 563a of processor 421a in almost real time, and the same data is stored in both.

[0222] For example, messages are used to send and receive instructions between tasks of the processor 421a and the processor 421b. For example, when the drive control task 502a gives instructions to the driver 442a in the processor 421a, an internal message is used. On the other hand, for example, the drive control task 502a can give instructions such as driving the focus lens 425 to a task in the processor 421b by generating a message indicating a drive instruction and storing the message in the sending side area of ​​the message area 563a. Also, for example, the drive control task 502a can receive instructions such as driving the aperture 423 from a task in the processor 421b by reading out a message stored in the receiving side area of ​​the message area 563a.

[0223] The DMAC 504a controls DMA in the processor 421a. For example, the DMAC 504a obtains a transfer control LLI from an LLI area of ​​a RAM (not shown), and transfers an LLI for data reception to the SPI 505a based on the transfer control LLI, or reads status data, BBS data, and messages from the shared memory area 545a and transfers them to the SPI 505a.

[0224] The DMAC 504a also stores the status data, BBS data, and messages that the SPI 505a receives from the processor 421b in the shared memory area 545a. Furthermore, the DMAC 504a stores the transfer control LLI that the SPI 505a receives from the processor 421b in the LLI area of ​​the RAM.

[0225] The SPI 505a performs full-duplex serial communication with the SPI 505b of the processor 421b.

[0226] As described above, the processor 421a and the processor 421b can seamlessly and closely share various pieces of information with little load, and can control the aperture 423 and the focus lens 425 independently.

[0227] <<3. Modifications>> Below, a modification of the above-described embodiment of the present technology will be described.

[0228] For example, it is possible to use a communication device other than SPI, such as a universal asynchronous receiver / transmitter (UART), a serial input / output (SIO), an inter-integrated circuit (I2C), a universal serial bus (USB), or Ethernet. It is also possible to use a communication device that performs parallel communication, for example.

[0229] Furthermore, for example, the present technology can also be applied to cases where communication between processors is half-duplex communication or unidirectional communication.

[0230] Furthermore, for example, instead of the DMAC, it is possible to use devices such as a DSP (Digital Signal Processor) or a PLD (Programmable Logic Device) that have a DMA control function.

[0231] Furthermore, it is not necessary for each processor to have a built-in memory that shares the address space, and each processor may be provided with an external memory.

[0232] Furthermore, as the information processing section built into each processor, it is possible to use a device such as a GPU (Graphics Processing Unit) or a PLD instead of a CPU.

[0233] The present technology can also be applied to the case where data is shared among information processing devices such as three or more processors.

[0234] Furthermore, the present technology can be applied to multiprocessor systems other than camera systems.

[0235] <<4.Other>> The above-mentioned series of processes can be executed by hardware or software. When the series of processes is executed by software, the programs constituting the software are installed in a computer. Here, the computer includes a computer built into dedicated hardware, and a general-purpose personal computer, for example, capable of executing various functions by installing various programs.

[0236] The program executed by the computer can be provided by being recorded on a removable medium such as a package medium, etc. Also, the program can be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

[0237] In addition, the program executed by the computer may be a program in which processing is performed chronologically in the order described in this specification, or it may be a program in which processing is performed in parallel or at the required timing, such as when called.

[0238] In this specification, a system refers to a collection of multiple components (devices, modules (parts), etc.), regardless of whether all the components are in the same case. Therefore, multiple devices housed in separate cases and connected via a network, and a single device in which multiple modules are housed in a single case, are both systems.

[0239] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0240] For example, the present technology can be configured as cloud computing, in which a single function is shared and processed collaboratively by multiple devices via a network.

[0241] Furthermore, each step described in the above flow chart can be executed by one device, or can be shared and executed by a plurality of devices.

[0242] Furthermore, when a single step includes multiple processes, the multiple processes included in the single step can be executed by a single device, or can be shared and executed by multiple devices.

[0243] <Examples of configuration combinations> The present technology can also be configured as follows.

[0244] (1) A first information processing device; A second information processing device; Equipped with The first information processing device, a first information processing unit that generates transfer parameters used for controlling the transfer of data; a first DMA control unit that controls a direct memory access (DMA) based on the transfer parameters; The first communication section Equipped with The second information processing device is A second information processing unit that generates the transfer parameters; a second DMA control unit that controls DMA based on the transfer parameters; a second communication unit that communicates with the first communication unit; Equipped with the first information processing unit generates a first transfer parameter used for receiving control of the first transfer data; the first DMA control unit controls transmission of the first transfer parameters to the second information processing device; The second DMA control unit controls reception of the first transfer data from the first information processing device based on the first transfer parameters. Information processing system. (2) the first information processing unit generates a second transfer parameter used for transmission control of the first transfer parameter and a third transfer parameter used for transmission control of the first transfer data; The first DMA control unit controls transmission of the first transfer parameters to the second information processing device based on the second transfer parameters, and controls transmission of the first transfer data to the second information processing device based on the third transfer parameters. The information processing system according to (1) above. (3) the transfer parameters are a linked list structure; The first information processing unit sets the third transfer parameter to a link destination of the second transfer parameter, and sets the second transfer parameter to a link destination of the third transfer parameter. The information processing system according to (2) above. (4) The first DMA control unit alternately repeats a transmission control of the first transfer parameter to the second information processing device and a transmission control of the first transfer data to the second information processing device based on the second transfer parameter and the third transfer parameter. The information processing system according to (3) above. (5) The first transfer data includes status data indicating a status of the first information processing device. The information processing system according to (4) above. (6) the first information processing unit generates a fourth transfer parameter used for control of reception of the second transfer data when transmitting second transfer data stored in a position different from that of the first transfer data in the first storage unit to the second information processing device; the first DMA control unit controls transmission of the fourth transfer parameter to the second information processing device; The second DMA control unit controls reception of the second transfer data from the first information processing device based on the fourth transfer parameter. The information processing system according to any one of (2) to (5). (7) the first information processing unit sets a fifth transfer parameter used for transmission control of the second transfer parameter and a sixth transfer parameter used for transmission control of the second transfer data; The first DMA control unit controls the transmission of the second transfer parameters to the second information processing device based on the fifth transfer parameters, and controls the transmission of the second transfer data to the second information processing device based on the sixth transfer parameters. The information processing system according to (6) above. (8) the transfer parameters are a linked list structure; The first information processing unit sets a link destination of the second transfer parameter to the third transfer parameter, sets a link destination of the third transfer parameter to the second transfer parameter, and changes a link destination of the third transfer parameter to the fifth transfer parameter when transmitting the second transfer data to the second information processing device. The information processing system according to (7) above. (9) The first information processing unit sets, in the first transfer parameters, control information for generating an interrupt notification of a transfer completion of the first transfer data when the first transfer data includes a message between tasks. The information processing system according to any one of (1) to (8). (10) When the control information is set in the first transfer parameters, the second DMA control unit performs an interrupt notification to the second information processing unit after controlling reception of the first transfer data. The information processing system according to (9) above. (11) the first information processing unit sets, in the first transfer parameters, a location in the second storage unit corresponding to a location in the first storage unit where the first transfer data is stored, as a transfer destination of the first transfer data; The second DMA control unit stores the first transfer data at a location in the second storage unit that is set as a transfer destination in the first transfer parameters. The information processing system according to any one of (1) to (10). (12) At least a part of the area of ​​the first storage unit and at least a part of the area of ​​the second storage unit share an address space. The information processing system according to (11) above. (13) the second information processing unit generates seventh transfer parameters used for receiving control of the first transfer parameters; The second DMA control unit controls reception of the first transfer parameter based on the seventh transfer parameter. The information processing system according to any one of (1) to (12). (14) the transfer parameters are a linked list structure; the first information processing unit sets the seventh transfer parameter to a link destination of the first transfer parameter; The second information processing unit sets the first transfer parameter to a link destination of the seventh transfer parameter. The information processing system according to (13) above. (15) The first transfer data includes status data indicating a status of the first information processing device, data for sharing information output from a task of the first information processing device, or a message from a task of the first information processing device to a task of the second information processing device. The information processing system according to any one of (1) to (14). (16) The first communication unit and the second communication unit perform full-duplex communication. The information processing system according to any one of (1) to (15). (17) The transfer parameters are a linked list structure, and include the source and destination of the data, as well as the link destination. The information processing system according to any one of (1) to (16). (18) A first information processing device that controls a direct memory access (DMA) based on a transfer parameter used for controlling the transfer of data; a second information processing device that communicates with the first information processing device and controls DMA based on the transfer parameters; Equipped with the first information processing device generates the transfer parameters used for controlling reception of the transfer data, and transmits the transfer parameters to the second information processing device; The second information processing device controls reception of the transfer data from the first information processing device based on the transfer parameters received from the first information processing device. Information processing methods. (19) an information processing unit that generates transfer parameters used for controlling the transfer of data; a DMA control unit that controls DMA (Direct Memory Access) based on the transfer parameters; a communication unit for communicating with other information processing devices; Equipped with the information processing unit generates the transfer parameters used for control of reception of the transfer data; The DMA control unit controls transmission of the transfer parameters used for controlling reception of the transfer data to the other information processing device. Information processing device. (20) a DMA control unit that controls DMA (Direct Memory Access) based on transfer parameters used for controlling data transfer; a communication unit for communicating with other information processing devices; Equipped with The communication unit receives the transfer parameters used for controlling reception of the transfer data from another information processing device, The DMA control unit controls reception of the transfer data from the other information processing device based on the transfer parameters received from the other information processing device. Information processing device.

[0245] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained. [Explanation of symbols]

[0246] 100 information processing system, 101a, 101b processor, 111a, 111b CPU, 112a, 112b DMAC, 115a, 115b SPI, 151a, 151b LLI area, 161a, 161b shared memory area, 171a, 171b status data area, 172a, 172b BBS area, 173a, 173b message area, 400 camera system, 401 camera body, 402 interchangeable lens unit, 421a, 421b processor, 441a, 441b inter-processor communication unit, 442a, 442b driver, 501a communication control task, 502a drive control task, 503a communication control module, 504a, 504b DMAC, 505a, 505b SPI, 541a status data sharing control section, 542a BBS control section, 543a message control section, 544a communication control section, 545a shared memory area, 561a status data area, 562a BBS area, 563a message area

Claims

1. A first information processing device; A second information processing device; Equipped with The first information processing device, a first information processing unit that generates transfer parameters used for controlling the transfer of data; a first DMA control unit that controls a direct memory access (DMA) based on the transfer parameters; A first communication unit; Equipped with The second information processing device is A second information processing unit that generates the transfer parameters; a second DMA control unit that controls DMA based on the transfer parameters; a second communication unit that communicates with the first communication unit; Equipped with the first information processing unit generates a first transfer parameter used for receiving control of the first transfer data; the first DMA control unit controls transmission of the first transfer parameters to the second information processing device; The second DMA control unit controls reception of the first transfer data from the first information processing device based on the first transfer parameters. Information processing system.

2. the first information processing unit generates a second transfer parameter used for transmission control of the first transfer parameter and a third transfer parameter used for transmission control of the first transfer data; The first DMA control unit controls transmission of the first transfer parameters to the second information processing device based on the second transfer parameters, and controls transmission of the first transfer data to the second information processing device based on the third transfer parameters. The information processing system according to claim 1 .

3. the transfer parameters are a linked list structure; The first information processing unit sets the third transfer parameter to a link destination of the second transfer parameter, and sets the second transfer parameter to a link destination of the third transfer parameter. The information processing system according to claim 2 .

4. The first DMA control unit alternately repeats the transmission control of the first transfer parameters to the second information processing device and the transmission control of the first transfer data to the second information processing device based on the second transfer parameters and the third transfer parameters. The information processing system according to claim 3 .

5. The first transfer data includes status data indicating a status of the first information processing device.

5. The information processing system according to claim 4.

6. the first information processing unit generates a fourth transfer parameter used for control of reception of the second transfer data when transmitting second transfer data stored in a position different from that of the first transfer data in the first storage unit to the second information processing device; the first DMA control unit controls transmission of the fourth transfer parameter to the second information processing device; The second DMA control unit controls reception of the second transfer data from the first information processing device based on the fourth transfer parameter. The information processing system according to claim 2 .

7. the first information processing unit sets a fifth transfer parameter used for transmission control of the fourth transfer parameter and a sixth transfer parameter used for transmission control of the second transfer data; The first DMA control unit controls the transmission of the fourth transfer parameter to the second information processing device based on the fifth transfer parameter, and controls the transmission of the second transfer data to the second information processing device based on the sixth transfer parameter.

7. The information processing system according to claim 6.

8. the transfer parameters are a linked list structure; The first information processing unit sets a link destination of the second transfer parameter to the third transfer parameter, sets a link destination of the third transfer parameter to the second transfer parameter, and changes a link destination of the third transfer parameter to the fifth transfer parameter when transmitting the second transfer data to the second information processing device. The information processing system according to claim 7.

9. The first information processing unit sets, in the first transfer parameters, control information for generating an interrupt notification of a transfer completion of the first transfer data when the first transfer data includes an inter-task message. The information processing system according to claim 1 .

10. When the control information is set in the first transfer parameters, the second DMA control unit performs an interrupt notification to the second information processing unit after performing reception control of the first transfer data. The information processing system according to claim 9.

11. the first information processing unit sets, in the first transfer parameters, a location in the second storage unit corresponding to a location in the first storage unit where the first transfer data is stored, as a transfer destination of the first transfer data; The second DMA control unit stores the first transfer data at a location in the second storage unit that is set as a transfer destination in the first transfer parameters. The information processing system according to claim 1 .

12. At least a part of the first storage area and at least a part of the second storage area share an address space. The information processing system according to claim 11.

13. the second information processing unit generates second transfer parameters used for receiving control of the first transfer parameters; The second DMA control unit controls reception of the first transfer parameters based on the second transfer parameters. The information processing system according to claim 1 .

14. the transfer parameters are a linked list structure; the first information processing unit sets the second transfer parameter to a link destination of the first transfer parameter; The second information processing unit sets the first transfer parameter to a link destination of the second transfer parameter. The information processing system according to claim 13.

15. The first transfer data includes status data indicating a status of the first information processing device, data for sharing information output from a task of the first information processing device, or a message from a task of the first information processing device to a task of the second information processing device. The information processing system according to claim 1 .

16. The first communication unit and the second communication unit perform full-duplex communication. The information processing system according to claim 1 .

17. The transfer parameters are a linked list structure, and include the source and destination of the data, as well as the link destination. The information processing system according to claim 1 .

18. A first information processing device that controls a direct memory access (DMA) based on a transfer parameter used for controlling the transfer of data; a second information processing device that communicates with the first information processing device and controls DMA based on the transfer parameters; Equipped with the first information processing device generates the transfer parameters used for controlling reception of the transfer data, and transmits the transfer parameters to the second information processing device; The second information processing apparatus controls reception of the transfer data from the first information processing apparatus based on the transfer parameters received from the first information processing apparatus. Information processing methods.

19. an information processing unit that generates transfer parameters used for controlling the transfer of data; a DMA control unit that controls a DMA (Direct Memory Access) based on the transfer parameters; a communication unit for communicating with other information processing devices; Equipped with the information processing unit generates the transfer parameters used for control of reception of the transfer data; The DMA control unit controls transmission of the transfer parameters used for controlling reception of the transfer data to the other information processing device. Information processing device.

20. a DMA control unit that controls DMA (Direct Memory Access) based on transfer parameters used for controlling data transfer; a communication unit for communicating with other information processing devices; Equipped with The communication unit receives the transfer parameters used for controlling reception of the transfer data from another information processing device, The DMA control unit controls reception of the transfer data from the other information processing device based on the transfer parameters received from the other information processing device. Information processing device.

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