Light-emitting package and display device

Abstract

a first LED subunit, a second LED subunit disposed on the first LED subunit, a third LED subunit disposed on the second LED subunit, a first bonding layer disposed between the first and second LED subunits, a second bonding layer disposed between the second and third LED subunits, and a first connection electrode electrically connected to and overlapping at least one of the first, second, and third LED subunits, the first connection electrode having opposing first and second side surfaces, the first side surface having a first length, and the second side surface having a second length, wherein a difference between the length of the first side surface and the length of the second side surface of the first connection electrode is greater than a thickness of at least one of the LED subunits.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Exemplary embodiments of the present invention relate to a light-emitting chip for a display and a manufacturing method thereof, and more particularly to a micro light-emitting chip having a stacked structure and a manufacturing method thereof. [Background technology]

[0002] Light-emitting diodes (LEDs), which are inorganic light sources, are used in a variety of technical fields, including displays, automotive lamps, general lighting, etc. Light-emitting diodes have features such as long life, low power consumption, and high responsiveness, and are rapidly becoming more and more popular as replacements for existing light sources.

[0003] Light-emitting diodes have been used primarily as a backlight source for display devices, but recently micro-LED displays that can directly display images using light-emitting diodes have been developed.

[0004] Generally, a display device realizes various colors by mixing blue, green, and red light. The display device includes pixels having sub-pixels corresponding to the colors blue, green, and red, and the color of a pixel is determined based on the color of the sub-pixel, and an image can be displayed by combining the pixels.

[0005] Since LEDs can emit various colors depending on the material they are made of, displays can usually have individual LED chips that emit blue, green, and red light arranged on a two-dimensional plane. However, if one LED chip is provided for each subpixel, the number of LED chips required to form a display device can be very large, for example, hundreds of thousands or even millions, and the mounting work can be very time-consuming and labor-intensive. Furthermore, since the subpixels are arranged on a two-dimensional plane of the display device, a relatively large area is required for one pixel, including the subpixels for blue, green, and red light, and there is a problem that the brightness of the subpixels deteriorates if the light-emitting area of ​​each subpixel is reduced.

[0006] In addition, micro LEDs are very small, typically with a surface area of ​​around 10,000 square micrometers or less, which presents various technical challenges. For example, an array of micro LEDs may be formed on a substrate, and the substrate may be cut to singulate the micro LEDs into individual micro LED chips. The micro LED chips may then be mounted on another substrate, such as a printed circuit board, using various transfer techniques. However, during these transfer steps, each micro LED chip is typically difficult to handle due to its small size and fragile structure.

[0007] The above information disclosed in this Background is intended solely to provide an understanding of the background of the inventive concept, and may therefore contain information that is not prior art. Summary of the Invention [Problem to be solved by the invention]

[0008] A light emitting chip constructed in accordance with the principles of the present invention and some exemplary embodiments can protect the light emitting stack during various transfer processes.

[0009] A light emitting chip, such as a micro LED, constructed according to the principles of the present invention and some exemplary embodiments thereof, and a display using the same, have a simplified structure and can shorten the mounting process time during manufacturing.

[0010] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the inventive concepts. [Means for solving the problem]

[0011] A light emitting chip according to an exemplary embodiment includes a first LED subunit, a second LED subunit disposed on the first LED subunit, a third LED subunit disposed on the second LED subunit, a first bonding layer disposed between the first and second LED subunits, a second bonding layer disposed between the second and third LED subunits, and a first connection electrode electrically connected to and overlapping at least one of the first, second and third LED subunits, the first connection electrode having opposing first and second side surfaces, the first side surface having a first length and the second side surface having a second length, wherein a difference between a length of the first side surface and a length of the second side surface of the first connection electrode is greater than a thickness of at least one of the LED subunits.

[0012] The light emitting chip may further include a substrate on which the first LED subunit is disposed, and a passivation layer that at least partially surrounds the first connection electrode and exposes a side surface of the substrate.

[0013] The first side surface may face an outer side of the light emitting chip, and the second side surface may face a center of the light emitting chip.

[0014] The passivation layer may expose a side surface of the first LED subunit and cover at least one side surface of the second and third LED subunits.

[0015] The passivation layer may include at least one of an epoxy molding compound and a polyimide film, and the passivation layer may cover a top surface of the third LED subunit.

[0016] The passivation layer may be transparent to light emitted from the first, second and third LED subunits.

[0017] The portion of the passivation layer overlapping the third LED subunit may have a thickness of about 100 μm or less.

[0018] The light-emitting chip may further include a second connection electrode electrically connected to the first LED subunit, a third connection electrode electrically connected to the second LED subunit, and a fourth connection electrode electrically connected to the third LED subunit, wherein the first connection electrode is electrically connected to each of the first, second, and third LED subunits, and each of the first, second, third, and fourth connection electrodes may have an elongated shape protruding in a direction away from the substrate so that an upper surface of each is positioned higher than an upper surface of the third LED subunit.

[0019] At least one of the first, second, third and fourth connection electrodes may have a lower surface having a larger area than an upper surface thereof.

[0020] At least one of the first, second, third and fourth connection electrodes may overlap a side surface of each of the first, second and third LED subunits.

[0021] The first connection electrode may be electrically connected to each of the first, second and third LED subunits via first, second and third lower contact electrodes, respectively, and the first, second and third lower contact electrodes may be arranged on different planes.

[0022] The third LED subunit may include a first-type semiconductor layer, an active layer, a second-type semiconductor layer, and an upper contact electrode in ohmic contact with the first-type semiconductor layer, the first-type semiconductor layer may include a recess, and the upper contact electrode may be formed in the recess of the first-type semiconductor layer.

[0023] The light emitting chip may further include a substrate, the first LED subunit may include a first LED light emitting stack, the second LED subunit may include a second LED light emitting stack, and the third LED subunit may include a third LED light emitting stack, the first, second and third LED light emitting stacks may have successively smaller areas overlapping with the substrate, and at least one of the light emitting stacks may include a micro LED having a surface area of ​​about 10,000 square microns or less.

[0024] The difference in length between the first side and the second side of the first connecting electrode may be in the range of about 3 μm to about 16 μm.

[0025] A light-emitting package according to another exemplary embodiment includes a light-emitting chip including a first LED subunit, a second LED subunit arranged on the first LED subunit, a third LED subunit arranged on the second LED subunit, a plurality of connection electrodes arranged on each of the first, second and third LED subunits, a circuit board having a first surface facing the light-emitting chip and a plurality of upper electrodes respectively connected to the connection electrodes, and a molding layer covering substantially all of an outer surface of the light-emitting chip.

[0026] The light emitting chip may further include a passivation layer disposed between the plurality of connecting electrodes, and the passivation layer and the molding layer may include the same material.

[0027] The light emitting chip may further include a passivation layer disposed between the plurality of connecting electrodes, and the passivation layer and the molding layer may include different materials.

[0028] The portion of the molding layer disposed on the light emitting chip may have a thickness of less than about 100 μm.

[0029] At least one of the plurality of connecting electrodes may have opposing first and second sides having first and second lengths, respectively, and a difference between the first length and the second length may be at least about 3 μm.

[0030] At least one of the plurality of connection electrodes may overlap a side surface of each of the first, second and third LED subunits.

[0031] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. [Brief description of the drawings]

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and, together with the description, serve to explain the concepts of the invention.

[0033] [Figure 1A] 1 is a schematic perspective view of a light-emitting chip configured in accordance with an exemplary embodiment of the present invention; [Figure 1B] 1B is a plan view showing the underlying structure of the light emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 1C] 2A-2C are cross-sectional views of the light-emitting chip of FIG. 1B taken along line AA', respectively, according to an exemplary embodiment. [Figure 1D] 1C are cross-sectional views of the light-emitting chip of FIG. 1B taken along line BB', respectively, according to an exemplary embodiment. [Figure 1E] 1B is a SEM image of the light-emitting chip of FIG. 1A according to an exemplary embodiment. [Diagram 2] 1 is a schematic cross-sectional view of a light emitting stack constructed in accordance with an illustrative embodiment. [Figure 3A] 1B is a plan view illustrating a manufacturing process of the light emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 3B]3B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 3A in accordance with an exemplary embodiment. [Figure 4A] 1B is a plan view illustrating a manufacturing process of the light emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 4B] 4B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 4A in accordance with an exemplary embodiment. [Figure 5A] 1B is a plan view illustrating a manufacturing process of the light emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 5B] 5B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 5A in accordance with an exemplary embodiment. [Figure 6A] 1B is a plan view illustrating a manufacturing process of the light emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 6B] 6B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 6A in accordance with an exemplary embodiment. [Figure 7A] 1B is a plan view illustrating a manufacturing process of the light emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 7B] 7B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 7A in accordance with an exemplary embodiment. [Figure 8A] 1B is a plan view illustrating a manufacturing process of the light emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 8B] 8B is a cross-sectional view taken along line AA' of the corresponding plan view shown in FIG. 8A in accordance with an exemplary embodiment. [Figure 9] 1B is a schematic cross-sectional view of the light-emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 10] 1B is a cross-sectional view illustrating a manufacturing process of the light-emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 11] 1B is a cross-sectional view illustrating a manufacturing process of the light-emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 12] 1B is a cross-sectional view illustrating a manufacturing process of the light-emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 13]1B is a cross-sectional view illustrating a manufacturing process of the light-emitting chip of FIG. 1A according to an exemplary embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating a manufacturing process of a light emitting package according to an exemplary embodiment. [Figure 15] 1A to 1C are cross-sectional views illustrating a manufacturing process of a light emitting package according to an exemplary embodiment. [Figure 16A] 1A to 1C are cross-sectional views illustrating a manufacturing process of a light emitting package according to an exemplary embodiment. [Figure 16B] 16B is a schematic plan view of the light emitting package of FIG. 16A according to an exemplary embodiment. [Figure 17] 1 is a schematic cross-sectional view of a light emitting package attached to a target device in accordance with an exemplary embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable terms that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or in one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring various exemplary embodiments. Furthermore, various exemplary embodiments may differ, but are not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the concept of the present invention.

[0035] Unless otherwise stated, the illustrated exemplary embodiments should be understood as providing illustrative features of various details of some of the ways in which the concepts of the present invention may be practically practiced. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments can be combined, separated, interchanged and / or rearranged in other manners without departing from the concepts of the present invention.

[0036] The use of cross-hatching and / or shading in the accompanying drawings is generally for clarifying boundaries between adjacent elements. As such, the use of cross-hatching or shading, whether or not present, is not intended to convey or indicate preferences or requirements for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements and / or other properties, attributes, characteristics, etc. of the elements, unless otherwise specified. Additionally, in the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or explanation purposes. When the exemplary embodiments may be implemented differently, certain processing sequences may be performed differently than described. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order of the described order. Additionally, like reference numerals refer to like elements.

[0037] When an element, such as a layer, is described as being "on" or "connected" to another element or layer, it may be directly on, connected to, or connected to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is described as being "directly on" or "directly connected" to or directly connected to another element or layer, there are no intervening elements or layers. Thus, the term "connected" may refer to a physical, electrical, and / or fluid connection, with or without intervening elements. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system, such as the x-, y-, and z-axes, but may be interpreted in a broader sense. For example, the D1, D2, and D3 axes may be orthogonal to each other, or may represent different directions that are not orthogonal to each other. For purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] In this specification, terms such as "first" and "second" may be used to describe various types of elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element described below can be called a second element without departing from the teachings of the present disclosure.

[0039] For purposes of explanation, spatially relative terms such as below, below, under, lower, above, upper, over, higher, side (e.g., as in sidewall) may be used herein to describe the relationship of an element to other elements shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), in which case the spatially relative descriptors used herein are interpreted accordingly.

[0040] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. Furthermore, as used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that the terms "substantially," "about," and other similar terms are used herein as terms of approximation, not degree, and are utilized to account for inherent deviations in measurements, calculations, and provided values ​​that would be recognized by one of ordinary skill in the art.

[0041] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments disclosed herein should not be construed as necessarily limited to the shape of a particular illustrated region, which may include, for example, deviations in shape that result from manufacturing. As such, the regions illustrated in the drawings are schematic in nature and the shapes of these regions may not reflect the actual shape of a region of a device, and as such are not necessarily intended to be limiting.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure is a part. Terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning in the context of the relevant art, unless expressly so defined herein, and should not be interpreted in an idealized or overly formal sense.

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As used herein, a light emitting stack structure, a light emitting chip, or a light emitting package according to exemplary embodiments may include a micro LED having a surface area of ​​less than about 10,000 μm2, as known in the art. In other exemplary embodiments, the micro LED may have a surface area of ​​less than about 4,000 μm2 or a surface area of ​​less than about 2,500 μm2, depending on the particular application.

[0044] Fig. 1A is a schematic diagram of a light-emitting chip configured according to an exemplary embodiment of the present invention, Fig. 1B is a perspective plan view of the light-emitting chip of Fig. 1A according to an exemplary embodiment, Fig. 1C and Fig. 1D are cross-sectional views taken along lines A-A' and B-B', respectively, of the light-emitting chip of Fig. 1B according to an exemplary embodiment, and Fig. 1E is an SEM image of the light-emitting chip of Fig. 1A according to an exemplary embodiment.

[0045] 1A and 1B, the light emitting chip 100 according to the exemplary embodiment includes a light emitting stack structure, a first connection electrode 20ce, a second connection electrode 30ce, a third connection electrode 40ce, and a fourth connection electrode 50ce formed on the light emitting stack structure, and a passivation layer 90 surrounding the connection electrodes 20ce, 30ce, 40ce, and 50ce. An array of the light emitting chips 100 may be formed on a substrate 11, and the light emitting chip 100 shown in FIG. 1A is illustratively shown as a singularized version of the array, which will be described in more detail below. In some exemplary embodiments, the light emitting chip 100 including the light emitting stack structure may be further processed to form a light emitting package, which will be described in more detail below.

[0046] 1A-1D, the light emitting chip 100 according to the illustrated exemplary embodiment includes a light emitting stack structure, which may include a first LED subunit, a second LED subunit, and a third LED subunit disposed on a substrate 11. The first LED subunit may include a first LED light emitting stack (hereinafter referred to as a first light emitting stack) 20, the second LED subunit may include a second LED light emitting stack (hereinafter referred to as a second light emitting stack) 30, and the third LED subunit may include a third LED light emitting stack (hereinafter referred to as a third light emitting stack) 40. Although the drawings show a light emitting stack structure including three light emitting stacks 20, 30, and 40, the concept of the present invention is not limited to a particular number of light emitting stacks formed in the light emitting stack structure. For example, in some exemplary embodiments, the light emitting stack structure may include two or more light emitting stacks therein. Hereinafter, the light emitting chip 100 will be described with reference to a light emitting stack structure including three light emitting stacks 20, 30, and 40 according to an exemplary embodiment.

[0047] The substrate 11 may include a light-transmitting insulating material for transmitting light. However, in some exemplary embodiments, the substrate 11 may be formed to be semi-transparent, transmitting only light having a specific wavelength, or partially transparent, transmitting only a portion of light having a specific wavelength. The substrate 11 may also be a growth substrate on which the third light-emitting stack 40 can be epitaxially grown, such as a sapphire substrate. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the substrate 11 may include various other transparent insulating materials. For example, the substrate 11 may include glass, quartz, silicon, an organic polymer, or an organic-inorganic composite material, such as silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium oxide (Ga2O3), or a silicon substrate. As another example, substrate 11 in some illustrative embodiments may be a printed circuit board or composite substrate that includes electrical wiring therein to provide light emitting signals and a common voltage to each of the light emitting stacks formed thereon.

[0048] Each of the first, second and third light emitting stacks 20, 30 and 40 is configured to emit light toward the substrate 11. Thus, for example, light emitted from the first light emitting stack 20 may pass through the second and third light emitting stacks 30 and 40. According to an exemplary embodiment, the light emitted from each of the first, second and third light emitting stacks 20, 30 and 40 may have different wavelength bands, and the light emitting stacks located further away from the substrate 11 may emit light having a longer wavelength band. For example, the first, second and third light emitting stacks 20, 30 and 40 may emit red light, green light and blue light, respectively. However, the concept of the present invention is not limited thereto. As another example, the first, second and third light emitting stacks 20, 30 and 40 may emit red light, blue light and green light, respectively. As yet another example, in another exemplary embodiment, one or more light emitting stacks may emit light having substantially the same wavelength band. As yet another example, when the light emitting stack structure includes micro LEDs having a surface area of ​​less than about 10,000 μm2 as known in the art, or in other exemplary embodiments, less than about 4,000 μm2 or 2,500 μm2, the small form factor of the micro LEDs allows light emitting stacks located farther from the substrate 11 to emit light having a shorter wavelength band than light emitted from those located closer to the substrate 11 without adversely affecting operation. In this case, it may not be necessary to provide a separate color filter between the light emitting stacks because the micro LEDs can be operated at a lower operating voltage. Hereinafter, the first, second and third light emitting stacks 20, 30 and 40 are illustratively described as emitting red light, green light and blue light, respectively, according to an exemplary embodiment.

[0049] The first light emitting stack 20 includes a first type semiconductor layer 21, an active layer 23, and a second type semiconductor layer 25. According to an exemplary embodiment, the first light emitting stack 20 may include red light emitting semiconductor materials such as, but not limited to, aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), and gallium phosphide (GaP).

[0050] The first upper contact electrode 21n may be disposed on the first-type semiconductor layer 21 and form an ohmic contact with the first-type semiconductor layer 21, and the first lower contact electrode 25p may be disposed under the second-type semiconductor layer 25 of the first light emitting stack 20. According to an exemplary embodiment, a portion of the first-type semiconductor layer 21 may be patterned, and the first upper contact electrode 21n may be disposed in the patterned region of the first-type semiconductor layer 21 to enhance the level of ohmic contact therebetween. The first upper contact electrode 21n may have a single-layer structure or a multi-layer structure, and may include, but is not limited to, Al, Ti, Cr, Ni, Au, Ag, Sn, W, Cu, or alloys thereof, such as Au-Te alloy and Au-Ge alloy. In an exemplary embodiment, the first upper contact electrode 21n has a thickness of about 100 nm and may include a metal with high reflectivity to enhance the light emitting efficiency in the downward direction toward the substrate 11.

[0051] The second light emitting stack 30 includes a first-type semiconductor layer 31, an active layer 33, and a second-type semiconductor layer 35. According to an exemplary embodiment, the second light emitting stack 30 may include a semiconductor material that emits green light, such as, but not limited to, indium gallium nitride (InGaN), gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP), aluminum gallium phosphide (AlGaP). A second bottom contact electrode 35p is disposed below the second-type semiconductor layer 35 of the second light emitting stack 30.

[0052] The third light emitting stack 40 includes a first type semiconductor layer 41, an active layer 43, and a second type semiconductor layer 45. According to an exemplary embodiment, the third light emitting stack 40 may include a semiconductor material that emits blue light, such as, but not limited to, gallium nitride (GaN), indium gallium nitride (InGaN), zinc selenide (ZnSe), etc. A third bottom contact electrode 45p is disposed on the second type semiconductor layer 45 of the third light emitting stack 40.

[0053] According to exemplary embodiments, the first-type semiconductor layers 21, 31, and 41, respectively, and the second-type semiconductor layers 25, 35, and 45, respectively, of the first, second, and third light emitting stacks 20, 30, and 40 may have a single layer structure or a multi-layer structure, and in some exemplary embodiments may include a superlattice layer. Furthermore, the active layers 23, 33, and 43 of the first, second, and third light emitting stacks 20, 30, and 40 may have a single quantum well structure or a multiple quantum well structure.

[0054] Each of the first, second and third lower contact electrodes 25p, 35p and 45p may include a transparent conductive material for transmitting light. For example, the lower contact electrodes 25p, 35p and 45p may include a transparent conductive oxide (TCO) such as, but not limited to, tin oxide (SnO), indium oxide (InO2), zinc oxide (ZnO), indium tin oxide (ITO) or indium tin zinc oxide (ITZO).

[0055] A first adhesive layer 61 is disposed between the first light emitting stack 20 and the second light emitting stack 30, and a second adhesive layer 63 is disposed between the second light emitting stack 30 and the third light emitting stack 40. The first adhesive layer 61 and the second adhesive layer 63 may contain a non-conductive material that transmits light. For example, the first adhesive layer 61 and the second adhesive layer 63 may each contain OCA (Optical Clear Adhesive), and may contain, without being limited thereto, epoxy, polyimide, SU8, SOG (Spin-on Glass), BCB (Benzocyclobutene), or the like.

[0056] According to the illustrated exemplary embodiment, a first insulating layer 81 and a second insulating layer 83 are disposed on at least a portion of the side surfaces of the first, second, and third light emitting stacks 20, 30, and 40. At least one of the first insulating layer 81 and the second insulating layer 83 may include various organic or inorganic insulating materials, such as polyimide, SiO2, SiNx, and Al2O3. For example, at least one of the first insulating layer 81 and the second insulating layer 83 may include a distributed Bragg reflector (DBR). As another example, at least one of the first and second insulating layers 81 and 83 may include an organic polymer that is colored black. In some exemplary embodiments, an electrically floating metal reflective layer may be further disposed on the first and second insulating layers 81, 83 to reflect the light emitted from the light emitting stacks 20, 30, and 40 toward the substrate 11. In some exemplary embodiments, at least one of the first and second insulating layers 81, 83 may have a single-layer structure or a multi-layer structure formed of two or more insulating layers having different refractive indices from each other.

[0057] According to an exemplary embodiment, each of the first, second, and third light emitting stacks 20, 30, and 40 may be driven independently. More specifically, a common voltage may be applied to one of the first and second type semiconductor layers of each light emitting stack, and a respective light emitting signal may be applied to the other of the first and second type semiconductor layers of each light emitting stack. For example, according to the illustrated exemplary embodiment, the first type semiconductor layers 21, 31, and 41 of each light emitting stack may be n-type, and the second type semiconductor layers 25, 35, and 45 of each light emitting stack may be p-type. In this case, the third light emitting stack 40 may have a stacking order reversed compared to the first light emitting stack 20 and the second light emitting stack 30, such that the p-type semiconductor layer 45 is disposed on the active layer 43, in order to simplify the manufacturing process. Hereinafter, according to the illustrated exemplary embodiment, the first type semiconductor layer and the second type semiconductor layer may be interchangeably referred to as p-type and n-type, respectively.

[0058] Also, the first, second, and third lower contact electrodes 25p, 35p, and 45p connected to the p-type semiconductor layers 25, 35, and 45 of the light-emitting stack, respectively, may be connected to the fourth contact portion 50C, and the fourth contact portion 50C may be connected to the fourth connection electrode 50ce to receive a common voltage from the outside. Meanwhile, the n-type semiconductor layers 21, 31, and 41 of the light-emitting stack may be connected to the first contact portion 20c, the second contact portion 30c, and the third contact portion 40c, respectively, to receive corresponding light-emitting signals via the first, second, and third connection electrodes 20ce, 30ce, and 40ce, respectively. In this way, the first, second, and third light-emitting stacks 20, 30, and 40 can be driven independently while having a common p-type light-emitting stack structure.

[0059] Although the light emitting chip 100 according to the illustrated exemplary embodiment has a common p-type structure, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the first type semiconductor layers 21, 31 and 41 of each light emitting stack may be p-type, and the second type semiconductor layers 25, 35 and 45 of each light emitting stack may be n-type to form a common n-type light emitting stack structure. Furthermore, in some exemplary embodiments, the stacking order of each light emitting stack may be variously changed without being limited to that shown in the drawings. Hereinafter, the light emitting chip 100 according to the illustrated exemplary embodiment will be described with reference to the common p-type light emitting stack structure.

[0060] According to the illustrated exemplary embodiment, the first contact portion 20c includes a first pad 20pd and a first bump electrode 20bp electrically connected to the first pad 20pd. The first pad 20pd is disposed on the first upper contact electrode 21n of the first light-emitting stack 20, and is connected to the first upper contact electrode 21n through a first contact hole 20CH defined by penetrating the first insulating layer 81. At least a part of the first bump electrode 20bp may overlap the first pad 20pd, and the first bump electrode 20bp is connected to the first pad 20pd through a first through hole 20ct in the overlapping portion between the first bump electrode 20bp and the first pad 20pd, with the second insulating layer 83 interposed therebetween. In this case, the first pad 20pd and the first bump electrode 20bp may have substantially the same shape so as to overlap each other, without being limited thereto.

[0061] The second contact portion 30c includes a second pad 30pd and a second bump electrode 30bp electrically connected to the second pad 30pd. The second pad 30pd is disposed on the first-type semiconductor layer 31 of the second light-emitting stack 30, and is connected to the first-type semiconductor layer 31 through a second contact hole 30CH defined by penetrating the first insulating layer 81. At least a part of the second bump electrode 30bp may overlap the second pad 30pd. The second bump electrode 30bp may be connected to the second pad 30pd through a second through hole 30ct in an overlapping portion between the second bump electrode 30bp and the second pad 30pd, with the second insulating layer 83 interposed therebetween.

[0062] The third contact portion 40C includes a third pad 40pd and a third bump electrode 40bp electrically connected to the third pad 40pd. The third pad 40pd is disposed on the first-type semiconductor layer 41 of the third light-emitting stack 40, and is connected to the first-type semiconductor layer 41 through a third contact hole 40CH defined by penetrating the first insulating layer 81. At least a part of the third bump electrode 40bp may overlap the third pad 40pd. The third bump electrode 40bp may be connected to the third pad 40pd through a third through-hole 40ct in an overlapping portion between the third bump electrode 40bp and the third pad 40pd, with the second insulating layer 83 interposed therebetween.

[0063] The fourth contact portion 50c includes a fourth pad 50pd and a fourth bump electrode 50bp electrically connected to the fourth pad 50pd. The fourth pad 50pd is connected to the second-type semiconductor layers 25, 35, and 45 of the first, second, and third light-emitting stacks 20, 30, and 40 through a first sub-contact hole 50CHa and a second sub-contact hole 50CHb defined in the first, second, and third lower contact electrodes 25p, 35p, and 45p of the first, second, and third light-emitting stacks 20, 30, and 40. In particular, the fourth pad 50pd is connected to the first lower contact electrode 25p through the second sub-contact hole 50CHb, and is connected to the second and third lower contact electrodes 35p and 45p through the first sub-contact hole 50CHa. In this way, since the fourth pad 50pd is connected to the second and third lower contact electrodes 35p and 45p through one first sub-contact hole 50CHa, the manufacturing process of the light emitting chip 100 is simplified, and the area occupied by the contact holes of the light emitting chip 100 can be reduced. In addition, at least a part of the fourth bump electrode 50bp may overlap with the fourth pad 50pd. The fourth bump electrode 50bp may be connected to the fourth pad 50pd through the fourth through hole 50ct in the overlapping portion between the fourth bump electrode 50bp and the fourth pad 50pd, with the second insulating layer 83 interposed therebetween.

[0064] The concept of the present invention is limited to a specific structure of the contact portions 20C, 30C, 40C, and 50C. For example, in some exemplary embodiments, the bump electrodes 20bp, 30bp, 40bp, or 50bp may be omitted from at least one of the contact portions 20C, 30C, 40C, and 50C. In this case, the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C may be connected to the respective connection electrodes 20ce, 30ce, 40ce, and 50ce. In some exemplary embodiments, bump electrodes 20bp, 30bp, 40bp and 50bp may be omitted from contact portions 20C, 30C, 40C and 50C, respectively, and pads 20pd, 30pd, 40pd and 50pd of contact portions 20C, 30C, 40C and 50C may be directly connected to respective connection electrodes 20ce, 30ce, 40ce and 50ce.

[0065] According to an exemplary embodiment, the first, second, third and fourth contact portions 20C, 30C, 40C and 50C may be formed at various positions. For example, if the light emitting chip 100 has a substantially rectangular shape as shown in the drawings, the first, second, third and fourth contact portions 20C, 30C, 40C and 50C may be arranged to surround each corner of the substantially rectangular shape. However, the concept of the present invention is not limited thereto, and in some exemplary embodiments, the light emitting chip 100 may be formed to have various shapes, and the first, second, third and fourth contact portions 20C, 30C, 40C and 50C may be formed at other positions depending on the shape of the light emitting device.

[0066] The first, second, third and fourth pads 20pd, 30pd, 40pd and 50pd are insulated from each other by spacing them apart. Furthermore, the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp are insulated from each other by spacing them apart. According to an exemplary embodiment, the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp may cover at least a part of the side surface of the first, second and third light emitting stacks 20, 30 and 40, respectively, which facilitates in situ dissipation of heat generated from the first, second and third light emitting stacks 20, 30 and 40.

[0067] According to the illustrated exemplary embodiment, each of the connecting electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially elongated shape that protrudes away from the substrate 11, and the top surface of each of the connecting electrodes 20ce, 30ce, 40ce, and 50ce is disposed on the top surface of the first light emitting stack 20. The connecting electrodes 20ce, 30ce, 40ce, and 50ce may include a metal such as, but not limited to, Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof. For example, each of the connecting electrodes 20ce, 30ce, 40ce, and 50ce may include two or more metals or multiple different metal layers to relieve stress thereon from the elongated shape of the connecting electrodes 20ce, 30ce, 40ce, and 50ce. In another exemplary embodiment, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include Cu, an additional metal may be deposited or plated thereon to inhibit oxidation of Cu. In some exemplary embodiments, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include Cu / Ni / Sn, the Cu may prevent Sn from penetrating into the light emitting stack. In some exemplary embodiments, the connecting electrodes 20ce, 30ce, 40ce, and 50ce may include a seed layer for forming a metal layer during a plating process, which will be described in more detail below.

[0068] As shown in the drawings, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially flat upper surface to facilitate electrical connection between the light emitting stack and external wiring or electrodes, which will be described later. According to an exemplary embodiment, when the light emitting chip 100 includes a micro LED having a surface area of ​​less than about 10,000 μm2 as known in the art, or less than about 4,000 μm2 or 2,500 μm2 in other exemplary embodiments, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one portion of the first, second, and third light emitting stacks 20, 30, and 40, as shown in the drawings. More specifically, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on a side surface of the light emitting stack. In this way, a larger contact area can be formed between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light emitting stack, since the area of ​​the lower surface of the connection electrodes is larger than that of the upper surface thereof. Therefore, the connection electrodes 20ce, 30ce, 40ce, and 50ce can be formed more stably on the light-emitting stack structure. For example, the side surfaces L1, L2, L3, and L4 of the connection electrodes 20ce, 30ce, 40ce, and 50ce facing outward and the other side surfaces L1', L2', L3', and L4' facing the center of the light-emitting chip 100 may have different lengths (or heights). More specifically, the length of one side surface facing outward of the connection electrodes may be greater than the length of the other side surface facing the center of the light-emitting chip 100. For example, the difference in length between the two opposing surfaces L, L' of the connection electrodes may be greater than the thickness (or height) of at least one of the light-emitting stacks 20, 30, and 40. In this way, the contact area between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light-emitting stack structure can be increased, and the structure of the light-emitting chip 100 can be strengthened. Furthermore, the connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least two steps formed on the side surfaces of the light-emitting stacked structure, so that heat generated from the light-emitting stacked structure can be dissipated to the outside more efficiently.

[0069] According to an exemplary embodiment, the difference in length between one side L1, L2, L3 or L4 of the connection electrode facing outward and the other side L1', L2', L3', L4' facing the center of the light emitting chip 100 may be about 3 μm. In this case, the light emitting stack structure may be formed thin, in particular, the first light emitting stack 20 may have a thickness of about 1 μm, the second light emitting stack 30 may have a thickness of about 0.7 μm, the third light emitting stack 40 may have a thickness of about 0.7 μm, and the first and second adhesive layers may each have a thickness of about 0.2 μm to about 0.3 μm, but is not limited thereto. According to another exemplary embodiment, the difference in length between one side L1, L2, L3 or L4 of the connection electrode facing outward and the other side L1', L2', L3', L4' facing the center of the light emitting chip 100 may be about 10 μm to 16 μm. In this case, the light emitting stack structure may be formed relatively thick to have a more stable structure, in particular, the first light emitting stack 20 may have a thickness of about 4 μm to 5 μm, the second light emitting stack 30 may have a thickness of about 3 μm, the third light emitting stack 40 may have a thickness of about 3 μm, and the first adhesive layer and the second adhesive layer may each have a thickness of about 3 μm, but are not limited thereto. According to yet another exemplary embodiment, the difference in length between one side L1, L2, L3 or L4 facing the outside of the connecting electrode and the other side L1', L2', L3', L4' facing the center of the light emitting chip 100 may be about 25% of the length of the longest side. However, the concept of the present invention is not limited to a specific difference in length between the opposing surfaces of the connecting electrodes, and the difference in length between the opposing surfaces of the connecting electrodes may be various.

[0070] In some exemplary embodiments, at least one of the connecting electrodes 20ce, 30ce, 40ce, and 50ce may overlap with each side of the light-emitting stacks 20, 30, and 40, thereby balancing the temperature between the light-emitting stacks 20, 30, and 40, and efficiently dissipating heat generated inside to the outside. In addition, when the connecting electrodes 20ce, 30ce, 40ce, and 50ce include a reflective material such as a metal, the connecting electrodes 20ce, 30ce, 40ce, and 50ce can reflect light emitted from at least one or more of the light-emitting stacks 20, 30, and 40 to improve the effectiveness of the light.

[0071] Typically, during manufacturing, an array of multiple light-emitting chips is formed on a substrate. The substrate is then cut along scribe lines to singulate (separate) each light-emitting chip, and various transfer techniques may be used to transfer the light-emitting chips to another substrate or tape for further processing of the light-emitting chips, such as packaging. In this case, if the light-emitting chip includes connection electrodes such as metal bumps or pillars that protrude from the light-emitting structure to the outside, various problems may occur in subsequent steps, such as the transfer step, due to the structure of the bare light-emitting chip exposing the connection electrodes to the outside. Furthermore, if the light-emitting chip includes a microLED with a surface area of ​​less than about 10,000 square micrometers, less than about 4,000 square micrometers, or less than about 2,500 square micrometers depending on the application, the light-emitting chip may be difficult to handle due to its small form factor.

[0072] For example, when the connection electrode has a substantially elongated shape such as a rod shape, the protruding structure of the connection electrode may not ensure a sufficient adsorption area for the light emitting chip, making it difficult to transport the light emitting chip using a conventional vacuum method. Furthermore, the exposed connection electrode may be directly subjected to various stresses in subsequent processes, such as when the connection electrode comes into contact with a manufacturing device, which may damage the structure of the light emitting chip. As another example, when the light emitting chip is transferred by attaching an adhesive tape to the upper surface (e.g., the surface facing the substrate) of the light emitting chip, the contact area between the light emitting chip and the adhesive tape may be limited to the upper surface of the connection electrode. In this case, unlike when the adhesive tape is attached to the lower surface of the chip (e.g., the substrate), the adhesive force between the light emitting chip and the adhesive tape may be weak, and the light emitting chip may unintentionally peel off from the adhesive tape during transfer. As another example, when the light emitting chip is transported using a conventional pick-and-place method, an ejection pin may directly come into contact with a part of the light emitting chip arranged between the connection electrodes, damaging the upper structure of the light emitting structure. In particular, the ejection pin may strike the center of the light emitting chip, causing physical damage to the light emitting stack on top of the light emitting chip. Such an impact of the ejection pin on the light emitting chip is shown in FIG. 1E, where the center of the light emitting chip 100 is dented by the ejection pin.

[0073] According to an exemplary embodiment, the passivation layer 90 may be formed on the light emitting stack structure. The thickness of the portion of the passivation layer 90 overlapping with the first light emitting stack 20 may be 100 μm or less. More specifically, as shown in FIG. 1A, the passivation layer 90 may be formed between the connection electrodes 20ce, 30ce, 40ce, and 50ce and cover at least the side of the light emitting stack structure. For example, the passivation layer 90 may also cover the top surface of the first light emitting stack 20. According to the illustrated exemplary embodiment, the passivation layer 90 may expose the side surfaces of the substrate 11, the first and second insulating layers 81, 83, and the third light emitting stack 40. The passivation layer 90 may be formed to be substantially flush with the top surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce, and may include an epoxy molding compound (EMC) formed in various colors such as black and transparent. However, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, the passivation layer 90 may include polyimide (PID), in which case the PID may be provided as a dry film rather than a liquid type to enhance the level of flatness when applied to the light-emitting stack structure. In some exemplary embodiments, the passivation layer 90 may include a material having photosensitivity. In this way, the passivation layer 90 can protect the light-emitting structure from external impacts that may be applied in subsequent steps, and provide a sufficient contact area for the light-emitting chip 100 to facilitate handling in the subsequent transfer step. In addition, the passivation layer 90 can prevent light from leaking toward the side of the light-emitting chip 100, and prevent or at least suppress interference of light emitted from adjacent light-emitting chips 100.

[0074] 2 is a schematic cross-sectional view of a light-emitting stack structure according to an exemplary embodiment. The light-emitting stack structure according to the illustrated exemplary embodiment is substantially the same as that included in the light-emitting chip 100 described above, so that the substantially same elements forming the light-emitting stack structure are not repeatedly described to avoid redundancy.

[0075] Referring to FIG. 2, the first, second and third lower contact electrodes 25p, 35p and 45p according to the exemplary embodiment may be connected to a common line to which a common voltage Sc is applied. The light-emitting signal lines SR, SG and SB may be connected to the first-type semiconductor layers 21, 31 and 41 of the first, second and third light-emitting stacks 20, 30 and 40, respectively. In this case, the light-emitting signal line is connected to the first-type semiconductor layer 21 of the first light-emitting stack 20 via the first upper contact electrode 21n. In addition, in the illustrated exemplary embodiment, a common voltage Sc is applied to the first, second and third lower contact electrodes 25p, 35p and 45p via a common line, and light-emitting signals are applied to the first-type semiconductor layers 21, 31 and 41 of the first, second and third light-emitting stacks 20, 30 and 40, respectively, via the light-emitting signal line. In this way, the first, second and third light-emitting stacks 20, 30 and 40 can be individually controlled to selectively emit light.

[0076] 2 shows a light emitting stack having a p-common structure, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, a common voltage Sc may be applied to the first type (or n-type) semiconductor layers 21, 31, 41 of the first, second, and third light emitting stacks 20, 30, and 40, and a light emitting signal may be applied to the second type (or p-type) semiconductor layers 25, 35, 45 of the first, second, and third light emitting stacks 20, 30, and 40.

[0077] The light-emitting stack structure according to the exemplary embodiment can display various colors of light depending on the operating state of each light-emitting stack 20, 30, and 40, whereas the conventional light-emitting device can display various colors by a combination of multiple light-emitting cells that emit light of a single color. More specifically, the conventional light-emitting device generally includes light-emitting cells that emit different colors of light, for example, red, green, and blue, spaced apart from each other along a two-dimensional plane to achieve a full-color display. Therefore, the conventional light-emitting cells may occupy a relatively large area. However, the light-emitting stack structure according to the exemplary embodiment can emit different colors of light by stacking multiple light-emitting stacks 20, 30, and 40, thereby providing a high level of integration and implementing full color through a much smaller area than that in the conventional light-emitting device.

[0078] In addition, when the light emitting chip 100 is mounted on another substrate to manufacture a display device, the number of chips to be mounted can be significantly reduced compared to conventional light emitting devices, for example, due to the stacked structure. In this way, the manufacture of a display device employing the light emitting chip 100 can be substantially simplified, especially when hundreds of thousands or millions of pixels are formed on one display device.

[0079] According to exemplary embodiments, the light-emitting stack structure may further include various additional components to improve the purity and efficiency of the light emitted therefrom. For example, in some exemplary embodiments, a wavelength pass filter may be formed between adjacent light-emitting stacks to prevent or at least inhibit light having a shorter wavelength from moving toward a light-emitting stack emitting a longer wavelength. Furthermore, in some exemplary embodiments, a roughness may be formed on the light-emitting surface of at least one light-emitting stack to balance the brightness of the light between the light-emitting stacks. For example, since green light is generally more visible than red light or blue light, in some exemplary embodiments, a roughness may be formed on the light-emitting stack emitting red light or blue light to improve its light efficiency and balance the visibility between the lights emitted from the light-emitting stacks.

[0080] Hereinafter, based on an exemplary embodiment, a method for forming the light emitting chip 100 will be described with reference to the drawings.

[0081] 3A, 4A, 5A, 6A, 7A, and 8A are plan views showing the manufacturing process of the light-emitting chip of FIG. 1A according to an exemplary embodiment. 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional views taken along line A-A' of the corresponding plan views shown in FIG. 3A, 4A, 5A, 6A, 7A, and 8A according to an exemplary embodiment. FIG. 9 is a schematic cross-sectional view of the light-emitting chip of FIG. 1A according to an exemplary embodiment. 10, 11, 12, and 13 are cross-sectional views showing the manufacturing process of the light-emitting chip of FIG. 1A according to an exemplary embodiment.

[0082] 2, the first-type semiconductor layer 41, the third active layer 43, and the second-type semiconductor layer 45 of the third light-emitting stack 40 may be sequentially grown on the substrate 11 by, for example, a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. The third lower contact electrode 45p may be formed on the third p-type semiconductor layer 45 by, for example, a physical vapor deposition method or a chemical vapor deposition method, and may include a transparent conductive oxide (TCO) such as tin oxide (SnO), indium oxide (InO2), zinc oxide (ZnO), indium tin oxide (ITO), or indium tin zinc oxide (ITZO). In the case where the third light emitting stack 40 emits blue light according to an exemplary embodiment, the substrate 11 may include Al2O3 (e.g., a sapphire substrate), and the third bottom contact electrode 45p may include a transparent conductive oxide (TCO) such as tin oxide (SnO), indium oxide (InO2), zinc oxide (ZnO), indium tin oxide (ITO), or indium tin zinc oxide (ITZO). Similarly, the first light emitting stack 20 and the second light emitting stack 30 may be formed by sequentially growing a first-type semiconductor layer, an active layer, and a second-type semiconductor layer on a temporary substrate, and a bottom contact electrode including a transparent conductive oxide (TCO) may be formed on the second-type semiconductor layer by, for example, chemical vapor deposition.

[0083] According to an exemplary embodiment, the first and second light emitting stacks 20 and 30 may be adjacent to each other with the first adhesive layer 61 therebetween, and at least one of the temporary substrates of the first and second light emitting stacks 20 and 30 may be removed, for example, by a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, a concave-convex portion may be formed on the exposed light emitting stack to improve light extraction efficiency. Thereafter, the first and second light emitting stacks 20 and 30 may be adjacent to the third light emitting stack 40 with the second adhesive layer 63 therebetween, and the remaining one of the temporary substrates of the first and second light emitting stacks 20 and 30 may be removed, for example, by a laser lift-off process, a chemical process, a mechanical process, or the like. In this case, in some exemplary embodiments, a concave-convex portion may be formed on the remaining exposed light emitting stack to improve light extraction efficiency. In this manner, a light emitting stack structure as shown in FIG. 2 may be formed.

[0084] In another exemplary embodiment, the second adhesive layer 63 may be formed on the third light emitting stack 40. The second light emitting stack 30 may then be adjacent to the third light emitting stack 40 with the second adhesive layer 63 interposed therebetween, and the temporary substrate of the second light emitting stack 30 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like. The first adhesive layer 61 may then be formed on the second light emitting stack 30. The first light emitting stack 20 may then be adjacent to the second light emitting stack 30 with the first adhesive layer 61 interposed therebetween. When the first light emitting stack 20 is bonded to the second light emitting stack 30 bonded to the third light emitting stack 40, the temporary substrate of the first light emitting stack 20 may be removed by a laser lift-off process, a chemical process, a mechanical process, or the like. In some exemplary embodiments, one or more surfaces of one light emitting stack may be textured before or after being bonded to another light emitting stack to improve light extraction efficiency.

[0085] 3A and 3B, various portions of each of the first, second and third light emitting stacks 20, 30 and 40 may be patterned, such as via an etching process, to expose portions of the first-type semiconductor layer 21, the first bottom contact electrode 25p, the first-type semiconductor layer 31, the second bottom contact electrode 35p, the third bottom contact electrode 45p and the first-type semiconductor layer 41. According to the illustrated exemplary embodiment, the first light emitting stack 20 has the smallest area among the light emitting stacks 20, 30 and 40. However, the concept of the present invention is not limited to the relative sizes of the light emitting stacks 20, 30 and 40.

[0086] 4A and 4B, a portion of the upper surface of the first-type semiconductor layer 21 of the first light-emitting stack 20 may be patterned, for example, via wet etching, and a first upper contact electrode 21n may be formed thereon. As described above, the first upper contact electrode 21n may be formed in the patterned region of the first-type semiconductor layer 21 with a thickness of, for example, about 100 nm in order to improve ohmic contact therebetween.

[0087] 5A and 5B, a first insulating layer 81 may be formed to cover the light emitting stacks 20, 30, and 40, and a portion of the first insulating layer 81 may be removed to form the first, second, third, and fourth contact holes 20CH, 30CH, 40CH, and 50CH. The first contact hole 20CH is defined on the first n-type contact electrode 21n so as to expose a portion of the first n-type contact electrode 21n.

[0088] The second contact hole 30CH may also expose a portion of the first-type semiconductor layer 31 of the second light-emitting stack 30. The third contact hole 40CH may also expose a portion of the first-type semiconductor layer 41 of the third light-emitting stack 40. The fourth contact hole 50CH may also expose a portion of the first, second and third lower contact electrodes 25p, 35p and 45p. The fourth contact hole 50CH may include a second sub-contact hole 50CHb exposing a portion of the first lower contact electrode 25p and a first sub-contact hole 50CHa exposing the second and third lower contact electrodes 35p and 45p. However, in some exemplary embodiments, a single first sub-contact hole 50CH may also expose each of the first, second and third lower contact electrodes 25p, 35p and 45p.

[0089] 6A and 6B, the first, second, third and fourth pads 20pd, 30pd, 40pd and 50pd are formed on a first insulating layer 81 in which the first, second, third and fourth contact holes 20CH, 30CH, 40CH and 50CH are formed. The first, second, third and fourth pads 20pd, 30pd, 40pd and 50pd can be formed, for example, by forming a conductive layer on substantially the entire surface of the substrate 11 and patterning the conductive layer using a photolithography process or the like.

[0090] The first pad 20pd is formed so as to overlap the region where the first contact hole 20CH is formed, so that the first pad 20pd can be connected to the first upper contact electrode 21n of the first light-emitting stack 20 through the first contact hole 20CH. The second pad 30pd is formed so as to overlap the region where the second contact hole 30CH is formed, so that the second pad 30pd can be connected to the first-type semiconductor layer 31 of the second light-emitting stack 30 through the second contact hole 30CH. The third pad 40pd is formed so as to overlap the region where the third contact hole 40CH is formed, so that the third pad 40pd can be connected to the first-type semiconductor layer 41 of the third light-emitting stack 40 through the third contact hole 40CH. In addition, the fourth pad 50pd is formed so as to overlap the region in which the fourth contact hole 50CH is formed, more specifically, the region in which the first sub-contact hole 50CHa and the second sub-contact hole 50CHb are formed, and the fourth pad 50pd may be connected to the first, second and third lower contact electrodes 25p, 35p, 45p of the first, second and third light-emitting stacks 20, 30 and 40 via the first sub-contact hole 50CHa and the second sub-contact hole 50CHb.

[0091] 7A and 7B, a second insulating layer 83 may be formed on the first insulating layer 81. The second insulating layer 83 may include silicon oxide and / or silicon nitride. However, the concept of the present invention is not so limited, and in some exemplary embodiments, the first insulating layer 81 and the second insulating layer 83 may include an inorganic material. Next, the second insulating layer 83 is patterned to form first, second, third and fourth through holes 20ct, 30ct, 40ct and 50ct therein.

[0092] The first through hole 20ct formed in the first pad 20pd exposes a part of the first pad 20pd. The second through hole 30ct formed in the second pad 30pd exposes a part of the second pad 30pd. The third through hole 40ct formed in the third pad 40pd exposes a part of the third pad 40pd. The fourth through hole 50ct formed in the fourth pad 50pd exposes a part of the fourth pad 50pd. In the illustrated exemplary embodiment, the first, second, third and fourth through holes 20ct, 30ct, 40ct and 50ct may be defined in the areas where the first, second, third and fourth pads 20pd, 30pd, 40pd and 50pd are formed, respectively.

[0093] 8A and 8B, the first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp are formed on the second insulating layer 83 in which the first, second, third and fourth through holes 20ct, 30ct, 40ct and 50ct are formed. The first bump electrode 20bp is formed so as to overlap the area in which the first through hole 20ct is formed, and the first bump electrode 20bp is connected to the first pad 20pd through the first through hole 20ct. The second bump electrode 30bp may be formed so as to overlap the area in which the second through hole 30ct is formed, and the second bump electrode 30bp may be connected to the second pad 30pd through the second through hole 30ct. The third bump electrode 40bp may be formed so as to overlap the region where the third through hole 40ct is formed, and the third bump electrode 40bp may be connected to the third pad 40pd through the third through hole 40ct. The fourth bump electrode 50bp may be formed so as to overlap the region where the fourth through hole 50ct is formed, and the fourth bump electrode 50bp may be connected to the fourth pad 50pd through the fourth through hole 50ct. The first, second, third and fourth bump electrodes 20bp, 30bp, 40bp and 50bp may be formed by forming a conductive layer containing at least one of Ni, Ag, Au, Pt, Ti, Al, Cr, Wi, TiW, Mo, Cu, TiCu and the like on the substrate 11 and patterning the conductive layer.

[0094] Returning to FIG. 1B to FIG. 1D, the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce are formed on the light-emitting stack structure with a space between them. The first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce may be electrically connected to the first, second, third, and fourth bump electrodes 20bp, 30bp, 40bp, and 50bp, respectively, to transmit external signals to the light-emitting stacks 20, 30, and 40, respectively. More specifically, according to the illustrated exemplary embodiment, the first connection electrode 20ce may be connected to the first bump electrode 20bp connected to the first upper contact electrode 21n via the first pad 20pd, and electrically connected to the first-type semiconductor layer 21 of the first light-emitting stack 20. The second connection electrode 30ce may be connected to the second bump electrode 30bp via the second pad 30pd and electrically connected to the first-type semiconductor layer 31 of the second light-emitting stack 30. The third connection electrode 40ce may be connected to the third bump electrode 40bp connected to the third pad 40pd and electrically connected to the first-type semiconductor layer 41 of the third light-emitting stack 40. The fourth connection electrode 50ce may be connected to the fourth bump electrode 50bp connected to the fourth pad 50pd and electrically connected to the second-type semiconductor layers 25, 35, 45 of the light-emitting stacks 20, 30, and 40 via the first, second, and third lower contact electrodes 25p, 35p, 45p, respectively.

[0095] The method of forming the first, second, third and fourth connecting electrodes 20ce, 30ce, 40ce and 50ce is not particularly limited. For example, according to an exemplary embodiment, a seed layer may be deposited as a conductive surface on the light emitting stack structure, and the seed layer may be patterned using photolithography or the like so that the seed layer is located at a desired position where the connecting electrode is to be formed. According to an exemplary embodiment, the seed layer may be deposited to have a thickness of about 1000 Å, without being limited thereto. The seed layer may then be plated with a metal, such as Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag or an alloy thereof, and the seed layer may be removed. In some exemplary embodiments, additional metal may be deposited or plated on the plated metal (e.g., the connecting electrodes), such as by electroless nickel immersion gold (ENIG), to prevent or at least inhibit oxidation of the plated metal. In some exemplary embodiments, the seed layer may remain on each connecting electrode.

[0096] According to an exemplary embodiment, when the bump electrodes 20bp, 30bp, 40bp, and 50bp are omitted from the contact portions 20C, 30C, 40C, and 50C, the pads 20pd, 30pd, 40pd, and 50pd may be connected to the respective connection electrodes 20ce, 30ce, 40ce, and 50ce. For example, after forming the through holes 20ct, 30ct, 40ct, and 50ct that partially expose the pads 20pd, 30pd, 40pd, and 50pd of the contact portions 20C, 30C, 40C, and 50C, a seed layer may be formed as a conductive surface on the light-emitting stacked structure, and the seed layer may be patterned using photolithography or the like so that the seed layer is disposed at a desired position where the connection electrode is to be formed. In this case, the seed layer may overlap at least a portion of each of the pads 20pd, 30pd, 40pd, and 50pd. According to exemplary embodiments, the seed layer may be deposited to a thickness of about 1000 Å, and then the seed layer may be plated with a metal, such as, but not limited to, Cu, Ni, Ti, Sb, Zn, Mo, Co, Sn, Ag, or alloys thereof, and the seed layer may be removed. In some exemplary embodiments, additional metal may be deposited or plated onto the plated metal (e.g., the connection electrodes), such as with electroless nickel immersion gold (ENIG), to prevent or at least inhibit oxidation of the plated metal. In some exemplary embodiments, the seed layer may remain on each connection electrode.

[0097] According to the illustrated exemplary embodiment, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially elongated shape that protrudes away from the substrate 11. In another exemplary embodiment, the connection electrodes 20ce, 30ce, 40ce, and 50ce may include two or more metals or multiple different metal layers to reduce stress on the connection electrodes 20ce, 30ce, 40ce, and 50ce from their elongated shape. However, the concept of the present invention is not limited to a particular shape of the connection electrodes 20ce, 30ce, 40ce, and 50ce, and in some exemplary embodiments, the connection electrodes may have various shapes.

[0098] As shown in the drawings, each of the connection electrodes 20ce, 30ce, 40ce, and 50ce may have a substantially flat upper surface to facilitate electrical connection between the light-emitting stack structure and external wiring or electrodes. The connection electrodes 20ce, 30ce, 40ce, and 50ce may overlap at least one step formed on the side of the light-emitting stack structure. In this manner, the lower surface of the connection electrode may have a width larger than that of its upper surface, providing a larger contact area between the connection electrodes 20ce, 30ce, 40ce, and 50ce and the light-emitting stack structure, so that the light-emitting chip 100 has a more stable structure that can withstand various subsequent processes together with the passivation layer 90. In this case, one side L of the connection electrodes 20ce, 30ce, 40ce, and 50ce facing the outside and the other side L' facing the center of the light-emitting chip 100 may have different lengths. For example, the difference in length between the two opposing sides of the connection electrodes may be in the range of about 3 μm to about 16 μm, without being limited thereto.

[0099] Then, the passivation layer 90 is disposed between the connection electrodes 20ce, 30ce, 40ce, and 50ce. The passivation layer 90 may be formed to be substantially flush with the upper surfaces of the connection electrodes 20ce, 30ce, 40ce, and 50ce by a polishing process or the like. According to an exemplary embodiment, the passivation layer 90 may include, but is not limited to, a black epoxy molding compound (EMC). For example, in some exemplary embodiments, the passivation layer 90 may include a photosensitive polyimide dry film (PID). In this manner, the passivation layer 90 can protect the light emitting structure from external impacts that may be applied in a subsequent process, and can provide a sufficient contact area for the light emitting chip 100 to facilitate handling in a subsequent transfer process. Furthermore, the passivation layer 90 can prevent light from leaking toward the side surface of the light emitting chip 100, and can prevent or at least suppress interference of light emitted from adjacent light emitting chips 100.

[0100] FIG. 10 illustrates a state in which a plurality of light-emitting chips 100 arranged on a substrate 11 are subjected to a singulation process for separating each of the light-emitting chips 100. Referring to FIG. 11, according to an exemplary embodiment, a laser beam Laser may be emitted between the light-emitting stacked structures to form a separation path that partially separates the light-emitting stacked structures from each other. Referring to FIG. 12, the first bonding layer 95 is attached to the substrate 11, and the substrate 11 may be cut or broken using various known methods in the art to singulate each of the light-emitting chips 100 while attached to the first bonding layer 95. For example, the substrate 11 may be cut by dicing through a scribing line formed thereon, or may be cut by applying a mechanical force to break the substrate 11 along the separation path formed during the laser irradiation process. The first bonding layer 95 may be a tape, but the concept of the present invention is not limited thereto as long as the first bonding layer 95 can stably attach the light-emitting chips 100 while allowing the light-emitting chips 100 to be peeled off in a subsequent process. Also, although the above describes the first bonding layer 95 as being attached to the substrate 11 after the laser irradiation step, in some exemplary embodiments, the first bonding layer 95 may be attached to the substrate 11 before the laser irradiation step.

[0101] 14, 15, 16A, and 17 are cross-sectional views that are schematic diagrams illustrating the manufacturing process of the light-emitting package according to an exemplary embodiment. FIG. 16B is a schematic plan view of the light-emitting package of FIG. 16A according to an exemplary embodiment. The light-emitting chip 100 according to the exemplary embodiment may be transferred and packaged by various methods known in the art. In the following, the light-emitting chip 100 is exemplarily described as being transferred by attaching the second adhesive layer 13 onto the substrate 11 using a carrier substrate 11c, but the concept of the present invention is not limited to a specific transfer method.

[0102] Referring to FIG. 14, according to an exemplary embodiment, the singulated light-emitting chip 100 may be transferred and placed on the carrier substrate 11c with the second adhesive layer 13 interposed therebetween. In this case, if the light-emitting chip includes a connection electrode protruding outward from the light-emitting stack structure, the uneven structure as described above may cause various problems in subsequent processes, especially in the transfer process. Furthermore, if the light-emitting chip includes a micro LED, its surface area is less than about 10,000 μm2, less than about 4,000 μm2, or less than about 2,500 μm2, so that the light-emitting chip may be difficult to handle due to its small form factor in some applications. However, by providing the light-emitting chip 100 according to the exemplary embodiment with the passivation layer 90 disposed between the connection electrodes 20ce, 30ce, 40ce, and 50ce, it is not only easier to handle the light-emitting chip 100 in subsequent processes such as transfer and packaging, but also protect the light-emitting structure from external impact and prevent light interference between adjacent light-emitting chips 100.

[0103] The carrier substrate 11c is not particularly limited as long as the light emitting chip 100 can be stably mounted thereon with the second adhesive layer 13. The second adhesive layer 13 may be a tape, but the concept of the present invention is not limited thereto as long as the second adhesive layer 13 can stably attach the light emitting chip 100 to the carrier substrate 11c while peeling off the light emitting chip 100 in a subsequent process. In some exemplary embodiments, the light emitting chip 100 in FIG. 13 may be directly transferred to the circuit substrate 11p without being transferred to another carrier substrate 11c. In this case, the carrier substrate 11c shown in FIG. 14 may be the substrate 11, and the second adhesive layer 13 shown in FIG. 14 may be the first adhesive layer 95 shown in FIG. 13.

[0104] The light emitting chip 100 may be mounted on a circuit board 11p. According to an exemplary embodiment, the circuit board 11p may include an upper circuit electrode 11pa, a lower circuit electrode 11pc, and an intermediate circuit electrode 11pb disposed therebetween, which are electrically connected to each other. The upper circuit electrode 11pa may correspond to the first, second, third, and fourth connection electrodes 20ce, 30ce, 40ce, and 50ce, respectively. In some exemplary embodiments, the upper circuit electrode 11pa may be surface-treated with ENIG to facilitate electrical connection with the connection electrodes of the light emitting chip 100 by being partially melted at high temperature.

[0105] According to the illustrated exemplary embodiment, the light emitting chips 100 may be spaced apart from one another on the carrier substrate 11c at a desired pitch, preferably taking into account the pitch P (see FIG. 16B) of the upper circuit electrodes 11pa of the circuit substrate 11p, which will be mounted in a final target device such as a display device.

[0106] According to an exemplary embodiment, the first, second, third and fourth connection electrodes 20ce, 30ce, 40ce and 50ce of the light emitting chip 100 may be respectively bonded to the upper circuit electrode 11pa of the circuit board 11p by, for example, anisotropic conductive film (ACF) bonding. When the light emitting chip 100 is bonded to the circuit board by ACF bonding, which can be performed at a lower temperature compared to other bonding methods, the light emitting chip 100 can be prevented from being exposed to high temperatures during bonding. However, the concept of the present invention is not limited to a specific bonding method. For example, in some exemplary embodiments, the light emitting chip 100 may be bonded to the circuit board 11p by using anisotropic conductive paste (ACP), solder, ball grid area (BGA), or microbumps including at least one of Cu and Sn. In this case, since the upper surfaces of the connection electrodes 20ce, 30ce, 40ce and 50ce are substantially flush with the passivation layer 90 due to a polishing process or the like, the adhesion of the light-emitting chip 100 to the anisotropic conductive film is improved, and a more stable structure can be formed when the light-emitting chip 100 is joined to the circuit board 11p.

[0107] Referring to FIG. 15 , a molding layer 91 is formed between the light emitting chips 100. According to an exemplary embodiment, the molding layer 91 may transmit a part of the light emitted from the light emitting chips 100, and may also reflect, diffract and / or absorb a part of the external light to prevent the external light from being reflected by the light emitting chips 100 toward a direction that may be viewed by a user. The molding layer 91 may also cover at least a part of the light emitting chips 100 to protect the light emitting chips 100 from external moisture and stress. In addition, together with the passivation layer 90 formed on the light emitting chips 100, the molding layer 91 provides additional protection to the light emitting package by strengthening the structure of the light emitting package.

[0108] According to an exemplary embodiment, when the molding layer 91 covers the top surface of the substrate 11 facing away from the circuit board 11p, the molding layer 91 may have a thickness of less than about 100 μm to transmit at least 50% of the light emitted from the light emitting chip 100. In an exemplary embodiment, the molding layer 91 may include an organic polymer or an inorganic polymer. In some exemplary embodiments, the molding layer 91 may further include pillars such as silica or alumina. In some exemplary embodiments, the molding layer 91 may include the same material as the passivation layer 90. The molding layer 91 may be formed by various methods known in the art, such as lamination, plating, and / or printing. For example, the molding layer 91 may be formed by a vacuum lamination process in which an organic polymer sheet is placed on the light emitting chip 100 and high temperature and pressure are applied in a vacuum to improve light uniformity by providing a substantially planar top surface of the light emitting package.

[0109] In some exemplary embodiments, the substrate 11 may be removed from the light emitting chip 100 before the molding layer 91 is formed thereon. If the substrate 11 is a patterned sapphire substrate, a textured portion may be formed in the first-type semiconductor layer 41 of the third light emitting stack 40 in contact with the substrate 11 to improve light efficiency. In another exemplary embodiment, a textured portion may be formed in the first-type semiconductor layer 41 of the third light emitting stack 40 by etching or patterning, as known in the art.

[0110] 16A and 16B, the light-emitting chips 100 arranged on the circuit board 11p may be cut into a desired shape to form a light-emitting package 110. For example, the light-emitting package 110 shown in FIG. 16B includes four light-emitting chips 100 (2×2) arranged on the circuit board 11p. However, the concept of the present invention is not limited to a specific number of light-emitting chips formed in the light-emitting package 110. For example, in some exemplary embodiments, the light-emitting package 110 may include one or more light-emitting chips 100 formed on the circuit board 11p. Also, the concept of the present invention is not limited to a specific arrangement of the one or more light-emitting chips 100 in the light-emitting package 110. For example, the one or more light-emitting chips 100 in the light-emitting package 110 may be an n×m array, where n and m are natural numbers greater than zero. According to an exemplary embodiment, the circuit board 11p may include scan lines and data lines for independently driving each of the light-emitting chips 100 included in the light-emitting package 110.

[0111] Referring to FIG. 17, the light-emitting package 110 may be mounted on a target substrate 11b of a final device such as a display device. The target substrate 11b may include target electrodes 11s corresponding to the lower circuit electrodes 11pc of the light-emitting package 110. According to an exemplary embodiment, the display device may include a plurality of pixels, and each of the light-emitting chips 100 may be arranged to correspond to each pixel. More specifically, each of the light-emitting stacks of the light-emitting chip 100 according to the exemplary embodiment may correspond to each subpixel of one pixel. Since the light-emitting chip 100 includes the light-emitting stacks 20, 30, and 40 stacked vertically, the number of chips that need to be transferred for each subpixel may be significantly reduced compared to that in a conventional light-emitting device. In addition, since the lengths of the opposing surfaces of the connection electrodes are different, the connection electrodes can be stably formed on the light-emitting stack structure, and the internal structure can be strengthened. Furthermore, since the light-emitting chip 100 according to some exemplary embodiments includes a passivation layer 90 between the connection electrodes, the light-emitting chip 100 can be protected from external impact.

[0112] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description, and therefore, the inventive concept is not intended to be limited to such embodiments, but rather is intended to cover the broader scope of the appended claims and various obvious modifications and equivalents that will be apparent to those skilled in the art.

Claims

1. A light emitting package including a light emitting chip, A first LED subunit; A second LED subunit disposed on the first LED subunit; a third LED subunit disposed on the second LED subunit; the light emitting chip including a plurality of connection electrodes electrically connected to the first, second and third LED subunits, respectively; a circuit board having a plurality of upper electrodes disposed on a first surface of the circuit board facing the light emitting chip and connected to the connection electrodes respectively; a molding layer covering substantially all of the outer surface of the light emitting chip; Including, At least one of the plurality of connection electrodes is arranged to cover a plurality of steps formed on a side surface of a light-emitting stacked structure including each of the first, second, and third LED subunits.

2. The light emitting chip further includes a passivation layer disposed between the plurality of connecting electrodes; The luminescent package of claim 1 , wherein the passivation layer and the molding layer comprise the same material.

3. The light emitting chip further includes a passivation layer disposed between the plurality of connecting electrodes; The light emitting package of claim 1 , wherein the passivation layer and the molding layer comprise different materials.

4. The light emitting package of claim 1 , wherein the portion of the molding layer disposed on the light emitting chip has a thickness of less than about 100 μm.

5. At least one of the plurality of connection electrodes has opposing first and second side surfaces having first and second lengths, respectively; 10. The luminescent package of claim 1, wherein the difference between the first length and the second length is at least about 3 [mu]m.

6. A display device comprising a substrate and a plurality of pixels on the substrate, The pixel includes at least one light emitting package having a light emitting chip; The light emitting package includes: A first LED subunit; A second LED subunit disposed on the first LED subunit; a third LED subunit disposed on the second LED subunit; the light emitting chip including a plurality of connection electrodes electrically connected to the first, second and third LED subunits, respectively; a circuit board having a plurality of upper electrodes disposed on a first surface of the circuit board facing the light emitting chip and connected to the connection electrodes respectively; a molding layer covering substantially all of the outer surface of the light emitting chip; Including, At least one of the plurality of connection electrodes is disposed so as to cover a step formed on a side surface of a light-emitting stacked structure including each of the first, second, and third LED subunits.

7. The display device according to claim 6 , wherein the light emitting chip further includes a passivation layer disposed between the plurality of connection electrodes.

8. The display device of claim 6 , wherein the portion of the molding layer disposed on the light emitting chip has a thickness of less than about 100 μm.

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